Accelerating the next technology revolution

Copyright ©2010 SEMATECH, Inc. SEMATECH, and the SEMATECH logo are registered servicemarks of SEMATECH, Inc. International SEMATECH Manufacturing Initiative, ISMI, Advanced Materials Research Center and AMRC are servicemarks of SEMATECH, Inc. All other servicemarks and trademarks are the property of their respective owners.

More Moore or More Than Moore?

Raj Jammy PhDVP, Materials and Emerging TechnologiesSEMATECH

SEMATECH Symposium TaiwanSeptember 7, 2010

Contents

•

Overview

•

Industry trends

•

CMOS (More Moore) options

•

Beyond CMOS (More than Moore) options

•

Conclusions

2

Overview•

More Moore: Scaling as per Moore’s Law–

Double number of transistors every ~two years–

Challenges: •

Unsustainable power dissipation•

Atomic scale dimensions-

physical limits•

Process and device variability•

No real performance increase with scaling•

Expensive R&D and manufacturing costs

•

More than Moore: Application driven components–

Analog, RF, M(N)EMS, sensors, opto, power devices,..–

Challenges:•

Bulky•

Incompatible with CMOS•

Often unsuitable for mobile platforms

3

• To get More from Moore, More than Moore is a must!

How is the industry changing? 1) Mobile trend –

performance AND power critical

• Mobile products have increased share of the Semiconductor TAM• IMPACT: Need low power device, sensing(analog), storage, display solutions

4

How is the industry changing? 2) Data center trend; performance AND power critical

http://www.emerson.com/neverbeendone/EnergyLogic.aspx

Dat

a ce

nter

s in

the

Uni

ted

Sta

tes

alon

e so

aked

up

abou

t 61

billi

on k

ilow

att-h

ours

(k

Wh)

, or $

4.5

billi

on w

orth

of e

lect

ricity

in 2

006.

If c

urre

nt e

nerg

y us

age

trend

s co

ntin

ue, a

U.S

. Env

ironm

enta

l Pro

tect

ion

Age

ncy

pred

icts

U.S

. dat

a ce

nter

s w

ill u

se

mor

e th

an 1

00 b

illio

n kW

h by

201

1, re

pres

entin

g $7

.4 b

illio

n in

ann

ual e

lect

ricity

cos

ts

and

2.5

perc

ent o

f the

nat

ion’

s to

tal e

lect

ricity

.

0

20

40

60

80

100

120

140

Power

 Use

 (Billion kW

‐hr)

Chem

ical

Meta

lDa

ta Ce

nterFo

odPa

per

Auto

Plasti

cs

Source: EIA, NREL May 2009

2011$7.4B Power Bill

• Cloud computing growing –

logic & memory for data centers important!• IMPACT: Dedicated power stations for data center ops and cooling (?)• IMPACT: Data centers need Both

Low Power & High Performance

Cloud Computing Growth

2006 Data

5

• SOC requires combining digital, analog, passives and lots of memory•

IMPACT: Mainstream chips are no longer restricted to discrete memory or logic• IMPACT: Memory needs to be low power too

Sou

rce:

Mar

k B

ohr,

Inte

l Dev

elop

er F

orum

200

9. a

vaila

ble

on w

ww

.inte

l.com

Source: Y. Nishi, S.M. Sze, EE319 Lecture Stanford 2009

6

How is the industry changing? 3) SOC trend; performance AND power critical

• Most “digital”

consumer systems have significant • Analog and Communication components• Memory

• Significant need for low power operation

SenseCompute

StoreTransmit

7

How is the industry changing? 4) It is not just a digital world!; performance AND power critical

Industry “must solve”

challenges

TODAY GOAL TODAY GOAL

Energy

(per OP or bit)1000pJ 10pJ 2pJ 0.06pJ

Power Cost $1B $1M $1B $1M

Enterprise Logic Enterprise Memory

Source: DARPA and Kryder, et. al. IEEE TRANS ON MAGNETICS, VOL. 45,, OCT 09

New materials, processes, tools, devices for next generation low power

technologies

Chip makers/design houses will drive multi-core designs,

circuit power optimization

• Must Solve: Power-Performance Trend

• Must Solve: ExaFLOP

/ Terabit Power, $$$

Adapted from: Y. Nishi, S.M. Sze, EE319 Stanford 2009

8

Common theme

• GOAL: Device with low power AND high performance • Avoid cost, complexity of dozens of devices on a chip

Universal, Single Device?

9

How to address “must solve”

challenges? Pareto analysis of power issue

Sour

ce: N

EC (w

ww. N

ec.c

o.jp

) and

T. B

. Hoo

k et

al I

EDM

p 2

7.6

2006

#3: Gate LeakageHK/MG

#2: Subthreshold

LeakageJunctions, damage, TFET

20%

30%

10%

40%

Best Efficiency Vdd

~0.3V

For Vdd

Scaling, Transistors Need:• Good mobility [strain , Ge, III-V, etc…]• Robust electrostatics [scaled HK/MG, USJ, finFETs, nanowire

FETs, …]• Controlled stochastics

/variability [tsi

in SOI, low Rcon

materials , fin LER …]

Today

~1V#1: Dynamic “leakage”Vdd

Scaling (Vdd=0.3-0.6V)

10

Power performance trade-offs More Moore opportunities

12

Drive

Curr

ent

I d,s

at

Gate Voltage

On state currentMaximize for performance

Off-state currentMinimize for power

11

•

High Mobility materials•

SiGe, Ge, InGaAs

•

Better electrostatic control•

Multiple gates + more channel area

•

FinFETs, nanowire

FET•

Low Tinv: Scaled HKMG•

USJ•

Parasitics

(Rco, Cp..)

Gate stack plays critical role in roadmap

HK

MG MG

GeSi

HK

MG

Si

MG

InGaAs

•

Zero Interface Layer HK reduces Jg

by 107X•

2nd and 3rd generation HKMG will also require ZIL

0

20

40

60

80

100

120

140

2000 2002 2004 2006 2008 2010 2012 2014 2016Year of Introduction by Leading Edge Companies

Tech

nolo

gy S

calin

g

SiON/poly-Si

300 mm200 mm

1st Gen Hi-k/MGSiON/poly-Si LP

130nm

90nm

65nm

45nm32nm

22nm16nm2nd Gen Hi-k/metal

Multi-gate FETs

HOT, FDSOI, Novel Materials

12nm3rd Gen Hi-k/metalOn high channels

Tunable Vt

SEMATECH Confidential0

20

40

60

80

100

120

140

2000 2002 2004 2006 2008 2010 2012 2014 2016Year of Introduction by Leading Edge Companies

Tech

nolo

gy S

calin

g

SiON/poly-Si

300 mm200 mm

1st Gen Hi-k/MGSiON/poly-Si LP

130nm

90nm

65nm

45nm32nm

22nm16nm2nd Gen Hi-k/metal

Multi-gate FETs

HOT, FDSOI, Novel Materials

12nm3rd Gen Hi-k/metalOn high channels

Tunable Vt

SEMATECH Confidential

Zero InterfaceInterface

12

0.0 0.2 0.4 0.6 0.8 1.0 1.210-4

10-2

100

102

104

106

108

EOTIL=0.8nmSiOx/HfSiON

J g@V fb

-1 (-

A/c

m2 )

EOT (nm)

SiO2/poly-Si

ZIL/HfO2

EOTIL=0.45nmSiON/HfSiON

16nmHP

ZrO2

1020 C-1070°C spike

12nm HP

Ultra shallow junctions Scaled USJ: conventional and damage-free

•Standard implantation•Flash anneal•Rs~1050-1100/sq

Xj

~7.5nm

•“Monolayer”

doping•Low Rs

& damage free•Suitable for group IV & III-V 4 nmSiO2

InAs

S doped region

50 nm

Epoxy

SiO2

InAs

[110] Zone

111220

(a) (b)

13

Contacts: Key scaling challenge Schottky

Barrier height engineering to lower Rc

•

600 –

800 meV

tuning of Schottky

Barrier Height•

N and P-Si contact engineering for conventional Ni based dual silicides•

Potential dual silicide

solution for nodes well beyond 16nm•

Simple and manufacturable

approaches –

help low power operation

10 100

0

20

40

60

80

100

Cum

ulat

ive

Freq

uenc

y

Rcont()

W/TiN/Ti on NiSi

ControlNiSi

N-implantNiSi

Interface Engineered NiSi

NiSix

based

Target

Interface Engineering Co-

implantation

Dipole mediated

Rc

Reduction in NiSi: Three Methods

0 5 10 15 20 25-0.8

-0.6

-0.4

-0.2

0.0

0.2

0.4

0.6

Reverse Bias IV Measurement Depletion CV Measurement

B(e

V)

tHigh- (A)

Si Bandgap

B.Coss

et al VLSI 2009 5BWY Loh

et al VLSI 2009 5B

14

15

•

24% enhancement in drive current for doped NiSi

DSS-nFETs

0.0 0.2 0.4 0.6 0.8 1.00

-100

-200

-300

-400

-500

-600

-700 Control N(3.5E15)

I s (

A/

m)

Vds

(V)

Vg-V

T = 1.0VDSS nFET 20%

B.Coss

et al VLSI 2009 5BWY Loh

et al VLSI 2009 5B

Transistor performance improvement Lower Rext

16

LDD

Deep Source/Drain

Silicide

IL

High‐K

MG

(Si)Ge

Si

High mobility channels: Quantum-well MOSFETs Short channel Planar Si/SiGe/Si QW pFETs

•

Best reported short Lg

pFET

(Ion/Ioff

~ 5X104

!) devices with high Ge%•

Defect-free thin SiGe, Ge

PMOS for high performance application •

Better than state-of-art Si on power / performance metric •

No uniaxial

strain in this work –

further boost possible•

Demonstrated concept in scaled non-planar scheme as well as in III-V SH

Lee

et a

l VLS

I 200

9JW

Oh

et a

l VLS

I 200

9

(Si)Ge

QW channelLow defect thin filmSelective

~3xSi

Value of III-V Performance @ Power

III-V demonstrated as superior to state-

of-art Si in :- Fundamental Energy to Switch - Energy Speed Benefits- Energy*Delay Benefit w/ scaling- Many issues to be resolved

17

S. Datta

[PennState]

Property/Material

Si Ge GaAs In0.53

Ga0.47

As InAs Graphene

Eg

(eV) 1.1 0.66 1.4 0.75 0.35 0*n

(cm2/v-sec) 1,350 3,900 4,600 >8,000 40,000 >100,000p

(cm2/v-sec) 480 1,900 500 350 <500 >100,000m*/mo 0.165 0.12 0.067 0.041 0.024 <0.01Lattice mismatch to Si

0 4% 4% 8% 12% n.A

Properties of promising high mobility materials [electrons and holes]

pMOSFET nMOSFET

2

,

)(2 tdd

invox

odsat VV

LW

TAI

* Tunable but at cost of degradation

18

III-V directly on Si

•

1st ever demonstrated flow for III-V on Si FETs

using industry standard tool set•

Systematic materials evaluation/process development for industry infrastructure

III-V on 200 mm Si wafer

III-V on 200 mm Si waferFully processed transistor flow

19

III-V/Si for VLSI using 200 mm line

20

SOI2 Gates

Tall Fins

Stacked wires

High Mobility Channel

Heterogeneous Fin Channel

High Mobility Channel

Platform

Heterogeneous Wire Channel

Single wire

3 Gates

Bulk

SOI2 Gates

Tall Fins

Stacked wires

High Mobility Channel

Heterogeneous Fin Channel

High Mobility Channel

Platform

Heterogeneous Wire Channel

Single wire

3 Gates

Bulk

FinF

ETs

Nan

owire

sW

afer

s

0 .0 0 .2 0 .4 0 .6 0 .8 1 .0 1 .20 .0

0 .2

0 .4

0 .6

0 .8

1 .0

1 .2

V(s)

[V]

V (S B ) [V ]

SNM of 300mV-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5

1E-71E-61E-51E-41E-30.010.1

110

1001000

10000

Lg~30nmVTH=-0.52VDIBL=60mV/VSS=67mV/decEOT~1nm

ID (

A/

m)

Vg (V)

open: Vds=|1V|closed: Vds=|0.05V|

Lg~30nmVTH=0.26VDIBL=49mV/VSS=70mV/decEOT~1nm

• 6-8 nm Fins

SEMATECH Si Nanowire

SiGeSi

SRAM

Nanowire

FETs

Dual Channel Fin FETFin FETs

Non-planar devices: FinFETS

and nanowires

21

Non-planar device scaling

•

Model based understanding using simulation + experimental data.

High w and w/o 3rd

gate ?

High Bulk vs

SOI

OR

OR

Scaling Pathways

Hom

gene

ous

Het

erog

eneo

us

Nanowire

10nm*10nmTrigate

40nm*10nm

InGaAs

QW Volume Inversion

45%

FinFET

with Heterogenous

Channel

FinFETs

with SiGe

and SiGe/Si Fins

22

20 nm20 nm

{110

}{100}

20 nm20 nm

{100

}

{100}

BOX

MGHK

BOX

Img: 'E1918 080622001 6081002 22 L86 SiGe FINS s dm3' MAG: 115kX

20 nm20 nm

{110

}

{100}

Img: 'E2092 080625015 6081002 22 2ndTry Fins SiGe 45deg s dm3' MAG: 115kX

20 nm20 nm

{100

}

{100}

SiGe SiGe

SiGeSi

SiGeSi

(110)

<110>

(110) fin sidewall surface.

Current in <110> direction.

(100)

<100>

(100) fin sidewall surface.

Current in <100> direction.

Si nanowire

arrays/stacks

450 nm

450 nmsource

drain

suspended wires

Single Si NW FETs

23

Stacked NWs

Si Nanowire

SiGeSi Si/SiGe

High

Nanowire

24

S. Datta

Voltage scaling

Pathways for low power CMOS & beyond…

Contact throughILD

Spacer

Si fin (~10nm

wide)

Img: ' E0985 080516013_ U T_ Tr ansi s tor _ 200_ TaN _ Zr O_InGaAs.Ed_r ot_ s.dm3' M AG: 590kX

5 nm5 nm5 nm

In0.53

GaAs

T

i

NZrO2

Gate-First nMOSFET700 0C anneal

Img: 'E2092 080625015_6081002_22 2ndTry_Fins SiGe 45deg_s.dm3' MAG: 115kX

20 nm20 nm

Si

SiGe

HKMG

10 nm10 nm

Gate

DrainSourceDamage-freeJunctions

High Channel Materials

Channel Structures

Low R Contacts

Disruptive Gate Stacks andDual WF Metal Gates for LP/HP

Numerous Options …breakthroughs needed, but exciting possibilities

HfOx

Si

TaNGraphene

Gate

N+ Drain P+ Source

BOX

TFETs

Metal

Si

Driving Electrode A

Driving Electrode B

SensingElectrode B

SensingElectrode A

Width = 90nmGap = <100nm

NEMS

25

Power performance trade-offs More than Moore opportunities

•

High Mobility materials•

SiGe, Ge, InGaAs•

Graphene

[e

~15000 cm2/V-s at RT]

•

Better electrostatic control•

Multiple gates + more channel area•

FinFETs, nanowire

FET

•

Improve on-off ratio •

Tunnel FET•

Very steep ΔSS

<< 60 mV/dec•

Low bias voltages (<< 1V) •

Nano

Electro Mechanical switch (NEMS)

•

Hybrid: Ion

by CMOS + Ioff

by NEMS

•

Zero Leakage Power

12

3Drive

Curr

ent

I d,s

at

Gate Voltage

On state currentMaximize for performance

Off-state currentMinimize for power

26

Schottky-source tunneling FET Sub-60mV/dec subthreshold

swing Conventional Si CMOS limit: 62mV/dec

•

New device concept: Schottky

Source TFET with SS ~ 46mV/dec

With UC Berkeley

NEMS: Nano

Electro-Mechanical Switch

MEMS NEMS GainFrequency kHz GHz Ultra low power

Power mWW pW Faster operationQuality factor 107 104 Challenge

Sensitivity High Highest High sensitivity

Dadgour

et al, Session 1.1.1, ISLPED 2010

M. Hussain

et al, NATO Nano

DSA, 2009

Gate

Cantilever

28

MEMS/NEMS “zero leakage”

devices Disruptive memory/logic switch

[1] W

. Y. C

hoi,

and

T.-J

. Kin

g Li

u IE

DM

p. 6

03 (2

007)

.[2

] A. D

riski

ll-S

mith

, Y. H

uaiF

utur

e Fa

bp.

28

(200

7).

SEMATECH sub 100nm NEMS

0 10 20 30 40 50100

101

102

103

104

105

DRAM

PCRAMFeRAM

NEMS SRAMMRAM

NOR

low power mid power hi power

Log

Spee

d (r

ead+

writ

e) [n

s]

Density AF2

NAND

SSTRAM

• NEMS may get to 6F2 [1,2]

Why NEMS Memory?

Drive A

Drive B DrainB

BeamDrain

A

Source

0 2 4 6 80.00

0.04

0.08

0.12

Cur

rent

(A

)

Voltage (V)

Vpi = 4.25V

Hysteresiswindow ~5V

gap g width w

sacrificial thicknessdevice thickness t

29

NEMS NANDflo

atin

g e

lect

rode

out = AB

A

VDD

VDD

GN

D

B

out = 1

A = 1

VDD

VDD

GN

D

B = 0

out = 0

A = 1

VDD

VDD

GN

D

B = 1

Bef

ore

initi

aliz

atio

n

VGS

1

32

0VpiVpo

VDD

0

Once the beam is pulled-in, VDD

> Vpi

is no more needed to hold the beam, VDD

> Vpo

is sufficientComparison for the same delay

(10.5 ns) and realistic dimensions

Time (ns)

Nor

mal

ized

Bea

m P

ositi

on

Conventional

Energy-Reversible

VDD = 2.24 V

VDD = 0.59 V

Drive A

Drive B Drain B

Beam

Drain A

Source

30

NEM switch fabrication

•

CMOS Compatible NEMS•

Can be integrated easily with conventional CMOS for logic/memory/sensing

Beam thickness = 25nm

Air gap = 60nm

Amorphous metalDriving

Electrode ADriving

Electrode B

SensingElectrode B

SensingElectrode ALength =

2~10m

Width = 90nmGap = <100nm

Source

Sacrificial layer

Cantilever

Metallic contact

0 1 0 2 0 3 0 4 0

-1 .0 x 1 0 -1

-5 .0 x 1 0 -2

0 .0

5 .0 x 1 0 -2

1 .0 x 1 0 -1

Cur

rent

(mA

)

V o lta g e (v o lts )

C o lle c tio n T e rm in a l C a n tile v e r

Z e ro Io ff

In fin ite Io n /Io ff

Lswitch = 2m Wswitch = 130nmGelectrode = 120nm Gcollection = 110nm

31

0 2 4 6 80.00

0.04

0.08

0.12

Cur

rent

(A

)

Voltage (V)

Vpi = 4.25V

Hysteresiswindow ~5V

NEMS-based logic circuitsInverter Gate

GN

DVD

D

XOR/XNOR Gates

Alternative implementations of XOR/XNOR gates

BAA B

BAA B

Gat

e A

Gat

e B

Pull-

up

NEM

SPu

ll-do

wn

NEM

S

VDD

GND

A B

VDD

GND

A B

XNOR (Design #2)XNOR (Design #1)

AND Gates

The implementation of a two-input AND gate

• NEMS relay outperforms conventional relay in terms of energy, voltage and reliability

VDrive

Vpull-in

t1 t2

Vhold

t3 t4

Vhold

t5 t6

Vhold

Hamed

Dadgour

et al, ISLPED 2010

100mV switching is possiblewith few nanometers gap

NEMS: Robust, CMOS compatible, nanoscale

switch

•

Potential on-the fly impedance matching for analog/mixed signal applications

•

Versatile device platform: the “transistor” of the MEMS world

Capacitance SensorDielectric coating

To power harvester

To transmitter

Temperature Sensor

To power harvester

Bimetallic strip

To transmitter

Resistance SensorMetallic coating

To power harvester

To transmitter

Pressure Sensor

To power harvester

To transmitter

tBeam

Substrate

Sacrificial Material

Beam

tGap

LBeamwBeam tBeam

Substrate

Sacrificial Material

Beam

tGap

LBeamwBeam

+ Well studied + Highly manufacturable

+ Extremely versatile + Scaling friendly higher sensitivity, lower cost, powerful arrays

Basic Building Block

CMOS

Analog

Z!NEMS NEMS

Example: in-situ process monitoring

33

34

-2 -1 0 1 24.0

4.5

5.0

5.5

6.0

6.5

7.0

7.5

40

45

Single ZrO2 (6 nm) Single SiO2 (6 nm) ZrO2(6 nm)/SiO2(3 nm)/ZrO2(6 nm)

Cap

acita

nce

Den

sity

(fF

/um

2 )

Voltage (V)

-6 -4 -2 0 2 4 610-11

10-9

10-7

10-5

10-3

10-1

101

Cur

rent

Den

sity

(A

/cm

2 )Voltage (V)

Single ZrO2 (6 nm) Single SiO2 (6 nm) ZrO2(6 nm)/SiO2(3 nm)/ZrO2(6 nm)

VCC=25ppm/V2

VCC=25ppm/V2SEMATECH Stack (6 nm)

SEMATECH Stack (6 nm)

Optimized low VCC MIM stack for Analog/MS

•

Meets ITRS specs to 2013 for analog and mixed signal needs•

Robust manufacturing ready process

Varactor Resistor Inductor CapacitorStructure

Issue(s)

•Linearity•Area scaling(cap/um2)

•Linearity•Heat Dissipation•FINFET, MG

•

Linearity•

Area Scaling(induct/µm2)

•

Capacitive coupling

•

Linearity•

Area scaling(cap/um2)

Approach

•Abrupt Junction•Barrier Height Reduction @ M-S contact•

Parasitic R

•Thin metal•Materials screening for TCR•

Parasitic R

•

3-D/ serpentine coils

•

Remove Si between coils

•

Parasitic R

•

SEMATECH solution to 2013

•

Higher k

SEMATECH Contribution

• Dipole tuning SBH•N Implant tuning SBH•

Damage free monolayer doping • Plasma doping •

Anneal: ms (flash, laser, spike

• Tune Rco

NiSi-Si• O, Si, N implant • TaN

optimization(C, N, O) for TCR• W system• I-V measurements

•

3-D test structure

•

Series Resistance

•

High freq capability to 40GHz

•

VCC<<100•

Vg<10-7

A/cm2

•

Cap den=7fF/um2

•

Work with tool supplier

•

Etch / etch stop development.

•

Conformal process

Analog mixed signal Passive components development

35

Moore’s Law & MoreMore than Moore: Diversification

Mor

e M

oore

: M

inia

turiz

atio

nM

ore

Moo

re:

Min

iatu

rizat

ion

Combining SoC and SiP: Higher Value SystemsBas

elin

e C

MO

S: C

PU, M

emor

y, L

ogic

BiochipsSensorsActuators

HVPowerAnalog/RF Passives

130nm

90nm

65nm

45nm

32nm

22nm...V

130nm

90nm

65nm

45nm

32nm

22nm...V

Information Processing

Digital contentSystem-on-chip

(SoC)

Interacting with people and environment

Non-digital contentSystem-in-package

(SiP)

Beyond CMOS

Traditional Models

[Geo

met

rical

& E

quiv

alen

t sca

ling]

Scal

ing

(Mor

e M

oore

)Functional Diversification (More than Moore)

HVPower Passives

SIP “White Paper”A&P ITWGwww.itrs.net/papers.html

Continuing SoC and SiP: Higher Value Systems

36

2009 ITRS: Overview of scaling trends

Logic and memory roadmap Technologies converge for higher value solutions

2009

Advanced Materials Advanced Structures

2010 2011 2012 2013 2014

Bulk/SOI Si Bulk/SOI SiHigh

(b)

r ans i stor _200_TaN _Zr O_InGaAs .Ed_r ot_s .dm3' M AG:

MetalHigh-k

InGaAs

SEMATECH Si Nanowire

HfOx

Si

50nm

WOx

TiN

W

TiN

W

WOx

TiN

W

TiN

W

CT Flash ReRAM1T DRAM

SiG

eSi

2009 2011 2013 2015 2017 2019

Logic

Memory

Beyond CMOS Materials/Structures

Driving Electrode A

Driving Electrode B

SensingElectrode B

SensingElectrode A

Width = 90nmGap = <100nm

Bit Line

Word Line

Common

Drain

Source

Gate Dielectric

GateElectrode

Bit Line

Word Line

Common

Drain

Source

Gate Dielectric

GateElectrode

STTRAM

ReRAM/Nanowire

3DArray

I d,s

at

Vg

ControlSTEEP

NEMS

TFET

Graphene

High mobilityFins/Nanowires

BoxGate-2 (substrate)

N+ N+

N+ Poly-SiGate Ox

Ge (SiGe)Box

Gate-2 (substrate)

N+ N+

N+ Poly-SiGate Ox

Ge (SiGe)Box

Gate-2 (substrate)

N+ N+

N+ Poly-SiGate Ox

Ge (SiGe)

<20nm ReRAM

Semi-conducting filament

BE

MOx

TESemi-conducting filament

BE

MOx

TE

Gate stack Channels, contacts, USJ

High Fin/NW

SiSi

20 nm20 nm

{100

}

{100}

SiGe

37

Summary

•

More Moore or More than Moore is NOT

the question–

Sense, compute, store, transmit: Integrated functionality

•

Convergence of technologies is the future–

System level power reduction with performance gain is key

•

Functional diversity vs

device density–

Focus of miniaturization shifts to adding diverse components–

CMOS+ : Hybrid integration of beyond-CMOS with CMOS–

Challenge: How can we fabricate them and make them work seamlessly

•

Fundamental shift in memory to non-charge-based memory–

Embedded memory for level 3/4 cache –

Reconfigurable memory-logic devices in the horizon

•

3D Interconnects is a game changer•

Process-Integration-Design co-optimization is a must

38

Vision of Future

Source: Brian Cristie

Design

Accelerating the next technology revolution

Research Development Manufacturing