Monolithic VR demonstration board for chipset and DDR2/3 ...€¦ · Monolithic VR demonstration...
Transcript of Monolithic VR demonstration board for chipset and DDR2/3 ...€¦ · Monolithic VR demonstration...
September 2008 Rev 1 1/37
AN2787Application note
Monolithic VR demonstration board for chipsetand DDR2/3 supply for ultramobile PC (UMPC) applications
IntroductionPM6641 demonstration board order code: STEVAL-ISA050V1 (previously coded as PM6641EVAL).
The PM6641 demonstration board is a monolithic voltage regulator (VR) module with internal power MOSFETs, specifically designed to supply DDR2/3 memory and chipset in ultramobile PC and real estate constrained portable systems.
It integrates three independent, adjustable, constant frequency buck converters, a ±2 Apk low dropout (LDO) linear regulator, and a ±15 mA low-noise buffered reference.
Each regulator is provided with basic undervoltage (UV) and overvoltage (OV) protections, programmable soft-start and current limit, active soft-end, and pulse skipping at light loads.
This document describes all features of the PM6641 demonstration board.
Figure 1. PM6641 demonstration board
www.st.com
Contents AN2787
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Contents
1 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Demonstration kit schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3 Bill of material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4 Component assembly and layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5 I/O interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6 Recommended equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7.1 JP1 VDDQ output discharge (DSCG pin) . . . . . . . . . . . . . . . . . . . . . . . . . 15
7.2 JP3 switching regulator phase control (SET_PH1 pin) . . . . . . . . . . . . . . 15
7.3 JP4 1.8 V (VDDQ) external/internal divider (VFB_1S8 pin) . . . . . . . . . . . 16
7.4 JP5 1.5 V external/internal divider (VFB_1S5 pin) . . . . . . . . . . . . . . . . . . 17
7.5 JP6 1.05 V external/internal divider (VFB_1S05 pin) . . . . . . . . . . . . . . . . 17
7.6 JP7 current limit (CSNS pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
8 Test setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
9 Getting started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
10 STEVAL-ISA050V1 evaluation tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
10.1 SW regulators turn-on (soft-start) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
10.2 SW regulator - working mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
10.3 Load regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
10.4 Load transient responses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
10.5 Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
10.6 Phase management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
10.7 Fault management (OVP, UVP, UVLO, thermal) . . . . . . . . . . . . . . . . . . . 30
10.8 SW regulators current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
10.9 Soft-end . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
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10.10 Thermal behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
List of figures AN2787
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List of figures
Figure 1. PM6641 demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Figure 2. PM6641 demonstration board schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Figure 3. Top side component placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Figure 4. Top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Figure 5. Layer 2 view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Figure 6. Layer 3 view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Figure 7. Bottom view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Figure 8. Bottom side component placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Figure 9. JP1 DSCG pin setting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Figure 10. JP3 phase control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Figure 11. JP4 1.8 V divider selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Figure 12. JP5 1.5 V divider selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Figure 13. JP6 1.05 V divider selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Figure 14. PM6641 demonstration board programmed current limit vs. CSNS resistor . . . . . . . . . . . 18Figure 15. JP8 setting switching frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18Figure 16. PM6641 demonstration board test setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Figure 17. VDDQ turn-on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21Figure 18. VDDQ, VTT and VTTREF turn-on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22Figure 19. PWM mode: VDDQ output voltage, phase voltage and inductor current, current
load = 2.3 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23Figure 20. Pulse skip mode: VDDQ output voltage, phase voltage and inductor current, current
load = 0 A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24Figure 21. Forced PWM mode (soft OV): VDDQ output voltage, phase voltage, inductor current
and Power Good signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24Figure 22. VDDQ (1.8 V) load regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25Figure 23. 1.5 V load regulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25Figure 24. 1.05 V load regulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26Figure 25. VTT load regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26Figure 26. VTTREF load regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26Figure 27. VDDQ, VTT and VTTREF, VDDQ load transient response, IVDDQ = 0 to
2.3 A at 2.5 A/µs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27Figure 28. 1.5 V output voltage and inductor current, 1.5 V rail load transient response,
1.5 V = 0 to 1.25 A at 2.5 A/µs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27Figure 29. 1.05 V output voltage and inductor current, 1.05 V rail load transient response.
I1.05 V = 0 to 1.75 A at 2.5 A/µs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28Figure 30. VDDQ, VTTREF, VTT and VTT output current, VTT rail load transient response,
IVTT = –1 A to +1 A at 2.5 A/µs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28Figure 31. SW regulators efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29Figure 32. SW regulators phases, 120 deg phase shift. SETPH1 pin tied to AGND . . . . . . . . . . . . . . 29Figure 33. SW regulators phases, no phase shift - synchronous clock, SETPH1 pin tied to AVCC . . 30Figure 34. VDDQ, VTT, VTTREF output voltage, VDDQ temporarily shorted to 3.3 V, output
overvoltage protection triggered . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30Figure 35. VDDQ, VTT, VTTREF output voltage and VDDQ inductor current, VDDQ feedback pin
temporarily shorted to GND, output undervoltage protection triggered . . . . . . . . . . . . . . . 31Figure 36. VDDQ (1.8 V), 1.5 V, 1.05 V output voltage and AVCC input power supply, input
undervoltage lockout triggered . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32Figure 37. VDDQ (1.8 V), 1.5 V, 1.05 V and VTT rails output voltage, thermal shutdown triggered . . 32Figure 38. 1.5 V rail output voltage, 1.5 V inductor current and output current, peak current limit
AN2787 List of figures
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reached. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33Figure 39. VDDQ(1.8 V), VTT and VTTREF rail output voltage, EN_1S8 and EN_VTT tied to
AGND - soft off with tracking discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34Figure 40. VDDQ(1.8 V), VTT and VTTREF rail output voltage. EN_1S8 and EN_VTT tied to
AGND - soft off without tracking discharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34Figure 41. PM6641 demonstration board surface temperature when loaded with typical currents,
Tamb = 23 °C, VIN = 3.3 V, FSW = 660 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Main features AN2787
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1 Main features
Switching section
0.8 V ±1% voltage reference
2.7 V to 5.5 V input voltage range
Fast response, constant frequency, current mode control
Three independent, adjustable, SMPS for DDR2/3 (VDDQ) and chipset supply
S3-S5 states compliant with DDR2/3 section
Active soft-end for all outputs
Selectable tracking discharge for VDDQ
Separate Power Good signals
Pulse skipping at light load
Programmable current limit and soft-start for all outputs
Latched OVP, UVP protection
Thermal protection
Reference and termination voltages (VTTREF and VTT)
±2 Apk LDO for DDR2/3 termination (VTT) with foldback
Remote VTT output sensing
High-Z VTT output in S3
±15 mA low-noise DDR2/3 buffered reference (VTTREF)
AN2787 Demonstration kit schematic
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2 Demonstration kit schematic
Figure 2. PM6641 demonstration board schematic
C26 06
03-1
00p
C4
0805
-10u
C16 06
03-1
00n
C27 06
03-1
00p
R10
0603
-180
k
TP8
GN
D 1
R20
0603
-68k
TP6
AGN
D
1
C28 06
03-1
00p
R2
0603
-4R
3
VIN
TP16
AGN
D
1
C18 06
03-3
3n
VCC
TP15
LDO
IN
1
C30 06
03-1
00p
VCC
AVCC
C19
0603
-22n
C7
B C
ase
- 220
u
TP4
PG_1
S05
1
C31 06
03-1
00p
+C
13EL
SM
D C
-10u
1 2
R33
0603
-join
AVC
C
TP12
VOU
T_1S
05
1
C2
0805
-10u
AVCC
R12
0603
-47k
R3
0603
-100
k
TP14
VTT 1
R4
0603
-68k
C6
B C
ase
- 220
u
C17
0603
-100
n
TP5
VCC 1
R11
0603
-100
k
+C
5EL
SM
D C
-10u
1 2
C21
0603
-22n
R17
0603
-68k
C25 06
03-1
00p
TP1
VTTR
EF
1
C32 06
03-1
5p
JP1
STR
IP 3
13
2
R31
0603
-join
C11
1206
-22u
1
2
TP13
GN
D1
JP3
STR
IP 3
13
2
R34
0603
-join
U1
PM66
41_Q
FPN
AGN
D_1
1
SET_
SWF
2
VOU
T_1S
83
CSN
S4
SGN
D_1
S8_1
5
SGN
D_1
S8_2
6
VSW
_1S8
_17
VSW
_1S8
_28
VIN
_1S8
_19
VIN
_1S8
_210
VFB_
1S8
11
CO
MP_
1S8
12
SS_1S813
SS_1S05 14
COMP_1S05 15
VFB_1S05 16
SGND_1S05_117
VSW_1S05_119
VSW_1S05_2 20
VIN_1S05_2 22
PG_1S0523
PG_1S824
EN_V
TT36
EN_1
S535
EN_1
S05
34
VIN
_1S5
33
VSW
_1S5
_232
VSW
_1S5
_131
SGN
D_1
S5_2
30
SGN
D_1
S5_1
29
VFB_
1S5
28
CO
MP_
1S5
27
SS_1
S526
PG_1
S525
SGND_1S05_218
VIN_1S05_1 21
VCC48
VTT_FB47
DSCG46
VTTREF45
LDO_IN44
VTT43
VTT_GND42
AVCC41
AGND_240
SET_PH139
AGND_338
EN_1S837
THER
MAL
49
AVC
C
L2
2839
-1u5
12
C23
0603
-470
p
L328
39-1
u
12
R19
0603
-68k
+C
8EL
SM
D C
-10u
1 2
TP18
AUX 1
C33 06
03-1
5p
C12
0805
-10u
TP2
PG_1
S8 1
AVC
C
TP7
VIN
1
C15
B C
ase
- 220
u
C22
0603
-330
p
C20
0603
-22n
C1 06
03-1
u
JP4
STR
IP 3
13
2
L1
2839
-1u
12
R5
0603
-150
k
JP5
STR
IP 3
13
2
R7
0603
-100
k
R8
0603
-120
k
R32
0603
-join
+
C14
EL S
MD
C-1
0u
12
AVC
C
TP10
VOU
T_1S
5
1
TP3
PG_1
S5 1
C34
0603
-15p
AUX
AUX
TP9
VOU
T_1S
8
1
R21
0603
-68k
R6
0603
-120
k
R22
0603
-68k
JP7
STR
IP 21 2
R30
0603
-join
R13
0603
-68k
AUX
TP17
GN
D
1
C3
0805
-10u
R23
0603
-68k
JP8
STR
IP 21 2
SW1
SW D
IP-4
1 2 3 45678
VIN
C24
0603
-330
p
C9
B C
ase
- 220
u
R18
0603
-68k
C10
B C
ase
- 220
u
R1
0603
-4R
3
TP11
GN
D 1
VIN
C29 06
03-1
00p
JP6
STR
IP 3
13
2
R9
0603
-56k
Bill of material AN2787
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3 Bill of material
Table 1. PM6641 demonstration board list of components
Qty Component Description Package Part number MFR Value Note
1 C1Ceramic, 10 V,
X5R, 20%SMD 0603 Standard 1 µ
4C2, C3, C4,
C12Ceramic, 10 V,
X5R, 20%SMD 0805 GRM21BR61A106KE19 Murata 10 µ
4C5, C8, C13,
C14SMD C case n.m.
5C6, C7, C9, C10, C15
Ceramic, 4 V, X5R, 20%
SMD 1206 AMK316BJ107ML Taiyo Yuden 100 µ
1 C11Ceramic, 6.3 V,
X5R, 10%SMD 1206 GRM31CR60J226KE19 Murata 22 µ
2 C16, C17Ceramic, 16 V,
X7R, 10%SMD 0603 Standard 100 n
1 C18Ceramic, 25 V,
X7R, 10%SMD 0603 GRM188R71E333KA01 Murata 33 n
3C19, C20,
C21Ceramic, 16 V,
X7R, 10%SMD 0603 Standard 22 n
2 C22, C24Ceramic, 50 V,
C0G, 5%SMD 0603 Standard 330 pF
1 C23Ceramic, 50 V,
C0G, 5%SMD 0603 Standard 470 pF
4C25, C26, C27, C28
Ceramic, 50 V, C0G, 5%
SMD 0603 Standard 100 pF
3C29, C30,
C31Ceramic, 50 V,
C0G, 5%SMD 0603 n.m.
3C32, C33,
C34Ceramic, 50 V,
C0G, 5%SMD 0603 n.m.
2 R1, R2Chip resistor,
0.1 W, 1%SMD 0603 Standard 3R3
1 R3Chip resistor,
0.1 W, 1%SMD 0603 Standard 100 kΩ
9
R4, R13 R17, R18, R19, R20, R21, R22,
R23
Chip resistor, 0.1 W, 1%
SMD 0603 Standard 68 kΩ
1 R16Chip resistor,
0.1 W, 1%SMD 0603 n.m.
1 R5Chip resistor,
0.1 W, 1%SMD 0603 Standard 150 kΩ
AN2787 Bill of material
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2 R6, R8Chip resistor,
0.1 W, 1%SMD 0603 Standard 120 kΩ
1 R7Chip resistor,
0.1 W, 1%SMD 0603 Standard 100 kΩ
1 R9Chip resistor,
0.1 W, 1%SMD 0603 Standard 56 kΩ
1 R10Chip resistor,
0.1 W, 1%SMD 0603 Standard 180 kΩ
1 R11Chip resistor,
0.1 W, 1%SMD 0603 Standard 100 kΩ
1 R12Chip resistor,
0.1 W, 1%SMD 0603 Standard 47 kΩ
3R32, R33,
R34Chip resistor,
0.1 W, 1%SMD 0603 Standard 0 Ω short
2 R30, R31Chip resistor,
0.1 W, 1%SMD 0603 n.m.
2 L1, L3SMT 11Arms,
9.5 mΩ SMD 2827 744312100 /LF Würth 1.0 µH
1 L2SMT 9 Arms,
10.5 mΩ SMD 2827 744312150 /LF Würth 1.5 µH
1 U1 IC VR - 48-pin VFQFPN 7x7 PM6641 STMicroelectronics
5JP1, JP3, JP4, JP5,
JP6Header, 3-pin SIP3
2 JP7, JP8 Header, 2-pin SIP2
5TP1, TP2, TP3, TP4,
TP18
Header, single pin
13
TP5, TP6, TP7, TP8, TP9, TP10,
TP11, TP12, TP13, TP14, TP15, TP16,
TP17
Test point
1 SW1 Switch 4-SPST DIP-8 Standard
Table 1. PM6641 demonstration board list of components (continued)
Qty Component Description Package Part number MFR Value Note
Component assembly and layout AN2787
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4 Component assembly and layout
Figure 3. Top side component placement
Figure 4. Top view
AN2787 Component assembly and layout
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Figure 5. Layer 2 view
Figure 6. Layer 3 view
Component assembly and layout AN2787
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Figure 7. Bottom view
Figure 8. Bottom side component placement
AN2787 I/O interface
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5 I/O interface
The PM6641 demonstration board has the following test points given in Table 2.
Table 2. PM6641 demonstration board input/output interface
Test point Description
VCC (TP5) +5 V IC supply, positive terminal
LDOIN (TP15) LDO (VTT) linear regulator input power supply
AUX (TP18) Auxiliary 3.3 V for pull-up (not required)
AGND (TP6, TP16) VCC, LDO, VTT and VTTREF common return
VIN (TP7) Power supply input voltage positive terminal
GND (TP8, TP11, TP13, TP17) Power supply and switching regulator outputs common return
V1S8 (TP9) 1.8 V (VDDQ) switching regulator output
V1S5 (TP10) 1.5 V switching regulator output
V1S05 (TP12) 1.05 V switching regulator output
VTT (TP14) LDO (VTT) linear regulator output
VTTREF (TP1) Voltage reference (VTTREF) buffer output
PG1S8 (TP2) 1.8 V (VDDQ) switching regulator Power Good signal
PG1S5 (TP3) 1.5 V switching regulator Power Good signal
PG1S05 (TP4) 1.05 V switching regulator Power Good signal
Recommended equipment AN2787
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6 Recommended equipment
5 V power supply
3.3 V, 20 W power supply
Active loads
Digital multimeters
500 MHz four-trace oscilloscope
AN2787 Configuration
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7 Configuration
The PM6641 demonstration board allows the user to test all the main features of the VR PM6641, acting on 7 different jumpers and 4 switches. SW1 (4 SPST switches) lets the user enable the switching regulators and the VTT linear regulator.
In the following sections each jumper is analyzed.
7.1 JP1 VDDQ output discharge (DSCG pin)The JP1 jumper is used to choose between the tracking discharge or nontracking discharge of the 1.8 V rail (VDDQ) output.
When the 1.8 V rail is deactivated (EN_1S8 goes low) and the DSCG is set high, tracking discharge takes place:
The 1.8 V rail regulator is discharged by the internal MOSFETs
The 0.9 V LDO and VTTREF work tracking with half of the 1.8 V rail
When the 0.9 V LDO and VTTREF reach a voltage threshold of about 300 mV, the nontracking discharge mode is performed by closing the internal discharge MOSFETs.
If the nontracking discharge mode is chosen, when EN_1S8 goes low, the 1.8 V and 0.9 V rails and the VTTREF buffer are independently discharged by internal MOSFETs.
Figure 9. JP1 DSCG pin setting
7.2 JP3 switching regulator phase control (SET_PH1 pin)The JP3 jumper allows selecting two different oscillator settings in order to change the delay between the pulses that start the control cycle. The inner clock is divided in order to obtain three slower clocks with a fixed delay of 120 deg. By setting JP3 as depicted in Figure 10, it is possible to synchronize the 1.8 V, 1.5 V and 1.05 V switching regulator clocks or to select 120 deg delay in order to decrease the total RMS input current.
Non Tracking Discharge
Tracking Discharge
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Figure 10. JP3 phase control
The 120 deg phase shifting is the default configuration in which the inner clock is divided and three pulses delayed by 120 deg are obtained to trigger the switching regulator loops.
The synchronous clocking allows all the regulators to start at the same pulse, avoiding the jitter due to simultaneous turn-on and off of different sections, but increasing the overall RMS input current.
7.3 JP4 1.8 V (VDDQ) external/internal divider (VFB_1S8 pin)The JP4 jumper allows selecting the internal divider or the external divider for the 1.8 V switching regulator. When the VFB_1S8 pin is connected directly to the output capacitor, the internal divider is enabled and this section provides 1.8 V output voltage. When the multifunction pin VFB_1S8 is tied to the central tap of an external divider, the switching regulator becomes adjustable, with the following output voltage:
Equation 1
Figure 11. JP4 1.8 V divider selection
120deg Phase Shifting
Synchronous
JP3
V8.01R
RVout
6
5 ⋅⎟⎟⎠
⎞⎜⎜⎝
⎛+=
Internal Divider Enabled
External Divider Enabled
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7.4 JP5 1.5 V external/internal divider (VFB_1S5 pin)The JP5 jumper allows selecting the internal divider or the external divider for the 1.5 V switching regulator. When the VFB_1S5 pin is connected directly to the output capacitor, the internal divider is enabled and this section provides 1.5 V output voltage. When the multifunction pin VFB_1S5 is tied to the central tap of an external divider, the switching regulator becomes adjustable, with the following output voltage:
Equation 2
Figure 12. JP5 1.5 V divider selection
7.5 JP6 1.05 V external/internal divider (VFB_1S05 pin)The JP6 jumper allows selecting the internal divider or the external divider for the 1.05 V switching regulator. When the VFB_1S05 pin is connected directly to the output capacitor, the internal divider is enabled and this section provides 1.05 V output voltage. When the multifunction pin VFB_1S5 is tied to the central tap of an external divider, the switching regulator becomes adjustable, with the following output voltage:
Equation 3
Figure 13. JP6 1.05 V divider selection
V8.01RR
Vout8
7 ⋅⎟⎟⎠
⎞⎜⎜⎝
⎛+=
External Divider Enabled
Internal Divider Enabled
V8.01R
RVout
10
9 ⋅⎟⎟⎠
⎞⎜⎜⎝
⎛+=
Internal Divider Enabled
External Divider Enabled
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7.6 JP7 current limit (CSNS pin)Each switching regulator current limit is set by inserting a resistor between the CSNS pin and AGND. By changing this resistor value, all the current limits change, as shown in Figure 14.
Figure 14. PM6641 demonstration board programmed current limit vs. CSNS resistor
If the CSNS pin is tied to AVCC, the current limit is set through the inner reference resistor (equal to 50 kΩ).
Figure 15. JP8 setting switching frequency
Peak Current Limit
0,00
1,00
2,00
3,00
4,00
5,00
6,00
7,00
50 70 90 110 130 150 170
Rcsns [kOhm]
Cur
rent
Lim
it [A
]
CL_1V8
CL_1V5
CL_1V05
Adjusted Switching Frequency
Default Switching Frequency
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8 Test setup
Figure 16 shows the suggested setup connections between the PM6641 demonstration board, the loads, and the external supply.
Figure 16. PM6641 demonstration board test setup
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9 Getting started
The following step-by-step power-up and power-down sequences are provided in order to correctly evaluate the PM6641 demonstration board performance.
Power-up sequence
Connect power supplies as shown in the PM6641 demonstration board test setup (Figure 16) and insert the meters in order to perform the desired performance evaluation. Connect the scope-probes as desired
Set the JP1 through JP8 jumpers in order to properly configure the PM6641 demonstration board. Set the SW1 switches (EN_1S8, EN_VTT, EN_1S5, EN_1S05) to the ON position. Do not change jumper settings when the board is powered
Set the VCC supply to 5 V ±5% and the current limit to 100 mA
Set the VIN supply to a voltage in the range 2.7 V to 3.6 V
Set all active loads to 0 A
Turn-on the VIN supply
Turn-on the VCC supply
Vary the 1.8 V (VDDQ) load from 0 A to 4 A
Vary the 1.5 V load from 0A to 2.5 A
Vary the 1.05 V load from 0A to 3.5 A
Vary the 0.9 V (VTT) load from 0 A to 2 A to test source capability. To test sink capability use the alternative VTT load connection shown in Figure 16
Vary VTTREF load to test source capabilty.
Power-down sequence
Decrease VTTREF and VTT loads to 0 A
Turn-off the 1.8 V (VDDQ), 1.5 V, 1.05 V loads
Decrease VCC supply from 5 V to 3.8 V in order to test the input undervoltage lockout (UVLO)
Increase VCC supply from 3.8 V to 5 V to restart the device
Use the EN_1S8 and En_VTT switches to enter/exit the S0-S3-S5 states
Turn-off the VCC supply
Turn-off the VIN supply.
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10 STEVAL-ISA050V1 evaluation tests
10.1 SW regulators turn-on (soft-start)When the EN_xx pin is toggled high, the correspondent SW regulator performs the soft-start as programmed through the external soft-start capacitor. Figure 17 depicts VDDQ (1.8 V) turn-on with CSS = 22 nF.
Figure 17. VDDQ turn-on
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Figure 18. VDDQ, VTT and VTTREF turn-on
10.2 SW regulator - working modeEach switching regulator changes working mode with the appropriate load. When the load is heavy, the SW enters PWM mode, but when the load is light, pulse skip mode is entered. Each SW regulator is also able to sink current from the output (forced PWM mode when a soft overvoltage occurs).
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Figure 19. PWM mode: VDDQ output voltage, phase voltage and inductor current, current load = 2.3 A
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Figure 20. Pulse skip mode: VDDQ output voltage, phase voltage and inductor current, current load = 0 A
Figure 21. Forced PWM mode (soft OV): VDDQ output voltage, phase voltage, inductor current and Power Good signal
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10.3 Load regulation
Figure 22. VDDQ (1.8 V) load regulation
Figure 23. 1.5 V load regulation
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Figure 24. 1.05 V load regulation
Figure 25. VTT load regulation
Figure 26. VTTREF load regulation
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10.4 Load transient responses
Figure 27. VDDQ, VTT and VTTREF, VDDQ load transient response, IVDDQ = 0 to 2.3 A at 2.5 A/µs
Figure 28. 1.5 V output voltage and inductor current, 1.5 V rail load transient response, 1.5 V = 0 to 1.25 A at 2.5 A/µs
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Figure 29. 1.05 V output voltage and inductor current, 1.05 V rail load transient response. I1.05 V = 0 to 1.75 A at 2.5 A/µs
Figure 30. VDDQ, VTTREF, VTT and VTT output current, VTT rail load transient response, IVTT = –1 A to +1 A at 2.5 A/µs
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10.5 Efficiency
Figure 31. SW regulators efficiency
10.6 Phase managementFigure 32 and 33 show the SW regulators loaded with 1.3 A (VDDQ rail), 1.25 A (1.5 V rail) and 1.75 A (1.05 V rail). By connecting the SETPH1 pin to AGND or to AVCC the following two different phase shifts are allowed.
Figure 32. SW regulators phases, 120 deg phase shift. SETPH1 pin tied to AGND
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Figure 33. SW regulators phases, no phase shift - synchronous clock, SETPH1 pin tied to AVCC
10.7 Fault management (OVP, UVP, UVLO, thermal)Each switching regulator is able to detect the output overvoltage and undervoltage. When the OV is detected the high-side MOSFET is turned off and the low-side MOSFET is turned on. When the UV is detected, the power MOSFETs are both turned off and the discharge MOSFET is turned on (soft-end). The soft-end is also performed when the junction temperature is higher than 150 °C.
Figure 34. VDDQ, VTT, VTTREF output voltage, VDDQ temporarily shorted to 3.3 V, output overvoltage protection triggered
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Figure 35. VDDQ, VTT, VTTREF output voltage and VDDQ inductor current, VDDQ feedback pin temporarily shorted to GND, output undervoltage protection triggered
When the input undervoltage is detected, the VDDQ (1.8 V) rail performs the output voltage soft-end. The 1.5 V and 1.05 V rails turn-off the high-side power MOSFET and turn-on the low-side one.
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Figure 36. VDDQ (1.8 V), 1.5 V, 1.05 V output voltage and AVCC input power supply, input undervoltage lockout triggered
Figure 37. VDDQ (1.8 V), 1.5 V, 1.05 V and VTT rails output voltage, thermal shutdown triggered
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10.8 SW regulators current limitCycle-by-cycle the high-side MOSFET current is monitored and if it's higher than the programmed current limit, the high-side MOSFET is immediately turned off.
Figure 38. 1.5 V rail output voltage, 1.5 V inductor current and output current, peak current limit reached
10.9 Soft-endEach SW regulator, when turned off, performs the output voltage soft-end by turning off the power MOSFET and turning on the discharge MOSFET. When the output voltage is lower than about 300 mV, the low-side power MOSFET is turned on. VTTREF and VTT can track half of VDDQ also during the soft off.
These rails are allowed two different modes of discharge: tracking and nontracking discharge.
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Figure 39. VDDQ(1.8 V), VTT and VTTREF rail output voltage, EN_1S8 and EN_VTT tied to AGND - soft off with tracking discharge
Figure 40. VDDQ(1.8 V), VTT and VTTREF rail output voltage. EN_1S8 and EN_VTT tied to AGND - soft off without tracking discharge
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10.10 Thermal behaviorThe device temperature is mainly influenced by LDO VTT current. The typical working currents are shown in Table 3.
VTT is supplied by VDDQ and the device (average) temperature is 54.5 °C.
Figure 41. PM6641 demonstration board surface temperature when loaded with typical currents, Tamb = 23 °C, VIN = 3.3 V, FSW = 660 kHz
Table 3. Average working currents for each rail
Rail Current [A]
VDDQ (1.8 V) 1.35
1.5 V 1.25
1.05 V 1.75
VTT (0.9 V) 0.3
Revision history AN2787
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11 Revision history
Table 4. Document revision history
Date Revision Changes
05-Sep-2008 1 Initial release
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