MONDAY€¦ · MONDAY September 8, 2:00 p.m. 1.2 2:00 p.m. "ATest Generator IC for Testing Large...

INTERNATIONAL TEST CONFERENCEMONDAY

September 8, 1:30 p.m.

1.1 1:30 p.m. "An Efficient Self-Test Structure forSequential Machines"S.Z. Hassan - Rolm Mil-Spec Computers

In this paper, a BIST structure for sequential machines ispresented. The approach requires augmentation of themachine by the addition of an extra input and some logic.The test sequence is independent of the functionimplemented and depends only on the number of inputcombinations and the number of states. The approachlends itself to being automated as part of a designsynthesis system.

INTERNATIONAL TEST CONFERENCE

MONDAYSeptember 8, 2:00 p.m.

1.2 2:00 p.m. "A Test Generator IC for Testing LargeCMOS-RAMs"W. Daehn and J. Gross - University of Hannover

Described in this paper is a test procedure for largeCMOS-RAMs, which can achieve excellent fault coveragewhen applied at the chip or board levels. The procedurerequires that the RAM be organized as a quadratic array ofcells with arbitrary ordering of rows and columns. Aself-testing 256K RAM requires an additional overhead ofless than 5% in silicon area. For the test of 256K x 8 bitmemory boards, a 2.5 micron CMOS chip was designed.

2.1 1:30 p.m. "Manufacturing Process Control System: 2.2 2:00 p.m. "A Burn-In Monitor and Error ReportingA Solution to Test Data Acquisition and Management" System for PBX Systems Test"D. Mancl, M. Sullivan - AT&T Engineering W. W. Bust, C. Darst, G. Krysl - AT&T InformationResearch Center Systems

Testing of assembled circuit packs is one of the most This paper describes production shop processes that areimportant steps on many manufacturing lines. Closely tied controlled by a computerized system using processto the automation of circuit pack testing is the automation of emulation for control functions, and direct interrogation oftest data collection and analysis. This paper will briefly test targets for data collection. A local area network allowsreview the need for circuit pack test area data collection, a porting of data to a host machine for analysis.system used to meet this need, and one example of theapplication of this system.

3.1 1:30 p.m. "A Multi-level Test Pattern Generation 3.2 2:00 p.m. "Structured Functional Level Testand Validation Environment" Generation Using Binary Decision Diagrams"I. Stamelos, M. Melgara, M. Paolini - CSELT H. P. Chang, W. A. Rogers, J. A. Abraham - Univ.S. Morpurgo, C. Segre - Olivetti of Illinois

This paper describes a highly interactive, integrated While functional test generation is used for memories, PLAs,environment for test generation and validation for VLSI & microprocessors, application to general functional modulescircuits. Although the primary logic description is at the has not been successful. This paper describes the problemsregister transfer level, modeling links are provided to associated with functional test generation from binary decisionlayout-derived functional models. The system comprises diagrams & proposes extensions which provide improved testprograms for fault extraction/definition, testability analysis, fault quality. Experimental results are presented which demonstratecollapsing, test pattem generation, and fault simulation. reduced test length and increased test coverage.

4.1 1:30 p.m. "Two CMOS Metastability Sensors" 4.2 2:00 p.m. "Testing Barrel Shifters inG. Freeman, D. Liu, B. Wooley, E. McCluskey - Microprocessors"Stanford University W. Bruce, C. Hunter, L. Basto- Motorola Inc.

To predict the reliability of a synchronizer, the designer This paper discusses several approaches and considerationsneeds certain parameters that are dependent on the latch for testing barrel shifters embedded in microprocessoror flip-flop being used. This paper introduces two sensing execution units. Both functional and structural testing of thesecircuits applicable to CMOS VLSI that can be used to logic elements will be analyzed with respect to results anddetermine these parameters. chip area impact.

5.1 1:30 p.m. "ASIC Verification - Second GenerationSystems and Solutions"B. Baril, Integrated Measurement Systems

Verification systems are gaining widespread attention as asolution for debug of custom and semicustom IC's. Thispaper will review the capabilities of these verfication toolsas they enter the second generation, and look at the rangeof verification problems solved and those that remain to besolved for the ASIC user.

5.2 2:00 p.m. "Memory Chip Test Economics"A. Tuszynski, San Diego State University

Exceptionally low prices of DRAM parts ($0.35 for a 64Kdevice) on one hand, and numerous malfunctioncontingencies on the other, add up to policy questions thatare unique to memory test. Since memory chips claim moresockets than all other parts taken together, it is important tolook at the end application of chips and develop teststrategies aimed at minimum cost per specified confidencelevel.

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1.3 2:30 p.m. "Circuits for Pseudo-Exhaustive Test PattemGeneratlon"L-T. Wang and E. J. McCluskey - StanfordUniversity

Discussion of a design technique for LFSRs that generatestest patterns for pseudo-exhaustive testing. The techniqueuses cyclic codes for any combinational network in whichnone of the outputs depends on all inputs. It is shown thatdesigns for in-circuit test generation using cyclic codes areeasier to implement and have less hardware overhead thantechniques using linear codes. Break: 3:00 p.m.

2.3 2:30 p.m. "Using a Relational Database to Developa Statistical Quality Control System for ATE"M. Winkel- Hewlett-Packard

This paper addresses the problems of developing aStatistical Quality Control (SQC) system from a RelationalDatabase Management System (RDBMS) by examining thefollowing: the requirements Automatic Test Equipment(ATE) makes of SQOC, the design of the database scheme,tradeoffs between performance and functionality, andproblems that complicate analysis of the data.Break: 3:00 p.m.

3.3 2:30 p.m. "Test Pattern Generation for Circults withThree-State Modules by Improved Z-Aigorithm"N. Itazaki, K. Kinoshita - Hiroshima University

Bocause of the extensive use of bus-structured logic in theVLSI environment, it has become necessary to generatetests for three-state devices. This paper describes analgorithm, based on PODEM, which generates a completeset of tests, while avoiding problems with orthogonal busvalues. Results are presented.Break: 3:00 p.m.

4.3 2:30 p.m. "Performance Assurance of MemoriesEmbedded In VLSI Chips"K. E. Torku, J. Monzel, C. E. Radke - IBM Corp.

Two diverse methods are proposed to assure performancecharacteristics of memories buried in random logic on thesame chip. One is achieved by design and analysis, whilethe other uses memory testers.Break: 3:00 p.m.

INTERNATIONAL TEST CONFERENCE1986 PUBLICATION EXHIBITORS

Design and TestEDN

Electronic BusinessElectronic Component News

Electronic Packaging and ProductionElectronic Test

Evaluation EngineeringMicroelectronic Manufacturing and Test

Semiconductor InternationalSolid State Technology

Test and Measurement WorldVLSI Systems DesignIEEE Computer Society

5.3 2:30 p.m. "Financial Impact of Tester ReliabilityImprovements"J. Dayhoff, R. W. Atherton, In-Motion Technology

The financial impact of tester reliability improvements isassessed with the use of a simulation model. Productionflow is increased as reliability improves; the extent of thisincrease can be found accurately through modelingsporadic tester downtime and queueing effects, a financialanalysis that shows the actual financial advantage of capitalinvestments that increase tester reliability.Break: 3:00 p.m.

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1.4 3:30 p.m. "An Optimal Design of Maximum-Length 1.5 4:00 p.m. "A Parity Bit Signature for Exhaustive

Sequence Generators" Testing"L-T. Wang and E.J. McCluskey - Stanford SB. Akers-University of Massachusetts

University In this paper the author describes and analyzes a signature

This ALFSR-based generator is devised to minimize the which is based solely on parity bits of a given function and

number of exclusive-OR gates required for the feedback which is well suited for exhaustive testing techniques. It is

function. It is shown that an n-stage maximum-length shown that this type of signature not only possesses such

sequence generator, which uses m modulo-2 adders and is desirable properties as uniformity and ease of

capable of cycling through (2**n) - 1 nonzero states, can be implementation, but that it is particularly amenable to

redesigned to employ at most (m + 1)/2 modulo-2 adders, if efficient fault coverage evaluation.its characteristic polynomial meets certain requirements.

2.4 3:30 p.m. "Systematic Yield Improvement in Board Testing 2.5 4:00 p.m. "A Case History of Networking a Wafer

Practice" E. Dalton, S. Denker, W. Ahern, K. Sweltzer, T. Sort Area"Kelly, B. Cooper, S. Smith - GenRad C. Cohoon, J. Sheridan - Signetics Corp.

This paper describes some of the motivations, procedures, This paper is a case study of implementing an ATE network

and continual attention to detail required by electronics on a wafer E-sort floor. The network ties together different

manufacturers to improve the quality of board brands of testers, as well as including a simple interface to

manufacturing and the effectiveness of an automatic board the wafer probers. It has led to major changes in testing

test facility. Goals are achieved by measuring and philosophy and practice, and delivers the capability to

systematically increasing first-pass board-test yields and monitor the fabrication process based on wafer-sort test

pass-after-repair rates. results.

3.4 3:30 p.m. "Informed Test Generation Guidance 3.5 4:00 p.m. "New Front-end and Line Justification AlgorithmUsing Partially Specified Fanout Constraints" for Automatic Test Generation"K. S. Hwang, M. R. Mercer - University of Texas

This paper presents a new ATPG algorithm for R-S. Wel, A. Sanglovanni-Vincenteill - University of

combinational circuits. A preprocessing step, which California, Berkeley

operates in linear time, traverses a logic circuit twice and Two acceleration techniques for test generation of

generates the partially specified functions "fanout combinational logic circuits are discussed: a heuristic test

constraints for controllability" and "fanout constraints for generator based on the testability analysis program

observability" for each link in the circuit. This information VICTOR-Il and an efficient line justification algorithm which

provides an efficient "fault grading" scheme which is used significantly reduces the number of backtracks.by the algorithm.4.4 3:30 p.m. "Timing Measurements on CMOS VLSI 4.5 4:00 p.m. "Accurate, Cost Effective Performance

Devices Designed to Drive TTL Loads" Screening of VLSI Circuit Designs"M. R. Barber, W. I. Satre - AT&T Bell Laboratories J. Van Horn - IBM Corp.

High speed MOS VLSI circuits are presenting serious This paper will describe a test technique for

problems when output timing measurements are made screening/sorting VLSI chips using the period measurement

using modern VLSI test systems. Transmission line of an oscillator as a predictor of circuit performance. Major

problems at the tester interface are analyzed and topics covered will include test methodology development,

suggestions are given to avoid major measurement errors. correlation studies, present applications and futureapplications.

6- .:UU p.m._ ANL_ uJu Q1f%U" - "inainn ATF"5.4 3:30 p.m. "Reducing Test Costs Through Strategic

Changes In Maintenance and Service"J. Perone - IBM Corporation

The operation of a test facility, in the manufacturing ofsemiconductors, or boards, is very costly. Examination of therelevant costs resulting from this process will convince thecasual analyst that the maintenance, service, and support ofproduction test equipment represents possibly the singlelargest recurrent annual expense. This paper will propose astrategy for the maintenance of automatic test equipmentwhich should significantly reduce this expense.

5.5 4:00 p.m. PANEL Ul15GUb:bIUN ---MUnugin MI|C* SPREAD SHEETS?* MATRIX? * GUTS?* BLACK MAGIC? * CYA?

Come and meet representatives of the six major VLSI-ATEcompanies and participate in the discussion of themethodologies used for selection of large, expensive ATE.

Panelists: J. Perone, IBM (Chairperson); R. Leckie,Megatest; R. Huston, Trillium; J. Wilbur, Teradyne; G. Griggs,Sentry-Schlumberger; T. Maruyama, Advantest.

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September 8, 8:00 p.m.-10:00 p.m.

1.6 4:30 p.m. "Built-In Checking of the CorrectSelf-Test Signature"W.H. McAnney and J. Savir - IBM Corporation

This paper describes a procedure for finding the initial valueof a single or multiple input signature register used tocompress responses in built-in self-testing so the finalgood-machine signature is always unique, say all zeros. Thus,it is possible to determine if a fault has been detected byOR-ing the outputs of the register stages. Since the ORoperation can be built-in, a single observation of the output ofthe OR gate will determine if the circuit has passed the test.

3.6 4:30 p.m. "Testability Measures: What Do They Dofor ATPG?:"A. Ivanov, V. K. Agarwal - McGill University

This paper discusses the use of testability measures in thePODEM and FAN test generation algorithms. It introducesthe concept of dynamic testability measures. Results ofseveral experiments are reported, as is a new testgeneration strategy devised to exploit the advantages ofboth static and dynamic testability measures in realizingbetter fault coverage in a given amount of CPU time.

4.6 4:30 p.m. "Requirements and Trends for HighSpeed Testing"G. Chlu, J. Halbout - IBM Corp.

This paper reviews the performance of micron andsubmicron devices and chips for the coming decade andthe challenges and problems for test they create.Methodology to meet these challenges and problems isdiscussed.

MONDAY, SESSION 6September 8, 8:00 p.m.-10:00 p.m.

POSTER SESSIONR. Kirkpatrick - Micro Switch/Honeywell(Chairperson/Organizer)SUMMARY: Six posters will be presented to afford theopportunity for authors and attendees to have one-on-one discussions.6.1 Vernier Method for Calibration of High Speed

Sampling SystemW. Damm, P. Janowitz, M. Hagen, Y. Shih, G. Widener-Tektronix, Inc.

6.2 Quickly Developing Effective CODEC Tests on anIn-Circuit Board Test SystemJ. Kirschling - Hewlett-Packard Co.

6.3 A Method of Flexible Catch RAM Display for MemoryTestingMark Rich - Teradyne, Inc.

6.4 Test to Eliminate TestKemon Taschiogiou - The Kemon Company

6.5 The DASS Needs Youl - An Update on the Activities of

the DASSRon Short - Sperry Corp.

6.6 Test System Architecture for Testing AdvancedMixed-Signal DevicesRick Nohelty - Teradyne, Inc.

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September 8, 8:00 p.m.- 0:00 p.m.

MONDAY, SESSION 7September 8, 8:00 p.m.-10:00 p.m.PANEL SESSION: ADVANCED BURN-IN AND LIFE TESTTECHNIQUESG. R. Hnatek - Honeywell (Chairperson)W. Hecirick - Emerson, Brooks Inst. Div. (Organizer)This panel session offers a wide range of timely informationon the important subjects of bum-in and life testing. Thefollowing topics are covered:* Technology advances as related to infant mortality failures* Bum-in and life test in the ASIC environment* Considerations for GaAs digital IC burn-in* Impact of die temperature on reliability extrapolations* Bum-in board considerations for high speed ICsThe panelists will provide a short presentation of their area ofexpertise followed by interaction with attendees. This sessionshould be of great interest to everyone interested in qualityand reliability in military and aerospace electronics.Panelists: G. Hnatek, Honeywell (Chair); J. Huljev, NationalSemiconductor; R. Venkataramin, Gigabit Logic; D. Mank,VLSI Technology; G. Spirakis, Intel; H. Haill, Reliability, Inc.

MONDAY, SESSION 8September 8, 8:00 p.m.-10:00 p.m.PANEL SESSION: ISDN - A CHALLENGE TO THE TESTCOMMUNITYR. Davidson - General Data Communications(Chalrperson)R. Davidson - General Data Communications(Organizer)Integrated Services Data Networks (ISDN) have beencharacterized as:* "I Sure Don't Know"* "Integrated Services That Do Nothing"In short, the technology is here, but where's the market?But there's also a great deal of money that's betting on itssuccess. Most of the telephone companies are activelyengaged in testing this service and most of the majorsemiconductor companies-Intel, TI, Motorola- aredeveloping LSI circuits for the ISDN Interfaces. Earlyservices could be available by 1988.It is important that the test community prepare for thismultibillion market-opportunities for new test equipmentand new test methods exist.This workshop will discuss:* The semiconductor vendors' strategy for ISDN.* How soon will the VLSI chip sets be available?* Software architectures.* In which products will ISDN be implemented and how?* Impact on electronics test industry.Panelists:L. T. Burke - Travis Associates Inc.Thomas J. Innes - Intel Corp.Richard Mullen - TeradyneAdditional panelists to be announced

INTERNATIONAL TEST CONFERENCETUESDAY

September 9, 8:30 a.m.-12:00 noon

TUESDAY, SESSION 9September 9, 8:30 a.m.-12:00 noonANALYSIS TECHNIQUES FOR BUILT-IN SELF-TESTR. Sedmak - Self-Test Services (Chairperson)R. Sedmak - Self-Test Services (Organizer)SUMMARY: In this second of two sessions on built-inself-test, methodologies and tools are described which areuseful for the design and analysis of BIST capabilities.

TUESDAY, SESSION 10September 9, 8:30 a.m.-12:00 noonADVANCES IN BOARD TEST TECHNOLOGYK. Parker - Hewlett-Packard (Chairperson)K. Parker- Hewlett-Packard (Organizer)SUMMARY: Advancing technology is providing challenges forBoard Test. This session addresses board test for GaAsdevices, surface mount technology, more work on backdrivingdamage, and the renewed interest in functional testing.

TUESDAY, SESSION 11September 9, 8:30 a.m.-12:00 noonMODELING, SIMULATION, AND DESIGN VERIFICATIONJ. G. Tellier - Digital EquIpment Corp. (Chairman)J. G. Tellier - Digital Equipment Corp. (Organizer)SUMMARY: The papers of this session treat a variety ofrelated subjects, including design verification, fault modeling(at both circuit and functional levels), multiple fault coveragefrom single fault patterns, fault simulators, and systems.

TUESDAY, SESSION 12September 9, 8:30 a.m.-12:00 noonTESTING THE NEWEST GENERATION OFMICROPROCESSORSR. Patrie - MIPS Computer Systems (Chairperson)K. Mandl- Sperry (Organizer)SUMMARY: This session addresses the testability and testof the newest generation of microprocessor families.

TUESDAY, SESSION 13September 9, 8:30 a.m.-12:00 noonQUALITY AND RELIABILITYD. Haggan -Bell Labs (Chairperson)W. Hedrck -Emerson, Brooks Inst. Dlv. (Organizer)SUMMARY: Topics include parametric test data as feedbackfor SPC, failure analysis of complex IC's, transient thermalcharacteristics & backdriving of high speed IC technologies,intermittent & latent failure which test methods may overlook.

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September 9, 8:30 a.m.

9.1 8:30 a.m. "Economically Viable Automatic Insertionof Self-Test Features for Custom VLSI"A.P. Ambler, I.D.Dear-Brunel UniversityM. Paraskeva, D.F. Burrows, W.L. Knight-Plessey ESR Ltd.

This session provides an overview of BIST designmethodology that is suitable for automatic insertion of BISTfeatures in circuits designed with a minimum of design rules.Also described is an enhanced economic model developed toproduce accurate figures for the costs of incorporating BISTusing the design methodology. Economic analyses arepresented that confirm the role of BIST as a production aid.

10.1 8:30 a.m. "Testing GaAs Devices with a DigitalIn-Circuit Test System"J. Klrschling - Hewlett Packard Co.

The use of high speed GaAs devices is posing newchallenges to digital in-circuit board test.



9.2 9:00 a.m. "Improved Techniques for EstimatingSignal Probabilities"B. Krishnamurthy - Tektronixl.G. Tollis - University of Illinois

The authors of this paper offer an improved algorithm forestimating signal probabilities for random pattern testabilityanalysis. The algorithm, which attempts to take into accountthe first-order effects of reconvergent input leads, is linear inthe product of the network size and number of inputs.Empirical evidence is offered indicating improvedperformance over conventional probability computations.

10.2 9:00 a.m. "Thermal Analysis of Backdriven OutputTransistors"R. L. Swent, M. J. Ward - Schiumberger Palo AltoResearch

Durational limits for backdriving devices during in-circuittesting can be computed using a new, empirically validatedthermal model which establishes time-dependenttemperature distributions.

11.1 8:30 a.m. "The Difference Fault Model - Using 11.2 9:00 a.m. "Automatic Modeling of MOS TransistorFunctional Fault Simulation to Obtain Networks for Automatic Test Pattern Generation"Implementation Fault Coverage" C. Vivier, G. Fournie - Bull, FranceG. Silberman, I. Spillinger - Technion and IBM This paper describes an automatic method of modelingIsrael MOS transistor networks, which leads to a functional

Presented here is an approach to predicting the coverage, representation of the network and accurate modeling ofin faults occurring at the VLSI implementation level, from MOS technology-specific faults.fault simulation results obtained at the functional level. Afault model which constitutes a formal abstraction of thefaults in the implementation level is described.

12.1 8:30 a.m. "An MC68020 Users Test Program" 12.2 9:00 a.m. "Tabular Mechanization for FlexibleB. Henshaw - NCR Corp. Testing of Microprocessors"

The Motorola MC68020 32-bit microprocessor has some P. Seetharamalah, V. R. Murthy - Andhrafeatures not found in earlier versions of the 68000 family or Universityother earlier microprocessors. This paper will describe a Classical fault detection methods based on the gate level oruser's test program for the 68020 and present test results. state diagram level description are not always suitable for

test generation of microprocessors. This paper presents ageneral and global model at the microoperation level andindicates a test procedure based on the model.

13.1 8:30 a.m. "Statistical Process Control Using the 13.2 9:00 a.m. "Transient Thermal Characteristics ofParametric Tester"A. D. Flowers, K. Mathur - Case Western ReserveUniversityJ. lsakson - Kelthley Instruments, Inc.

Implementing statistical process control (SPC) using theparametric tester for rapid identification of out-of-controlconditions, so that diagnosis and corrective action follow.Needed capabilities and examples of their use are in thispaper.

VLSI Devices - Evaluation and Application"M. Klrschner, M. Aghazadeh - Intel Corp.

Thermal characterization of VLSI circuits within the firstseveral seconds after power is applied has been performed.Environment, package type, and power dissipation arevaried and the resulting data analyzed and explained. Theapplication of this type of information to test temperaturecalculation of these components is reviewed.

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9.3 9:30 a.m. "On the Computation of Detection 9.4 10:30 a.m. "Random Pattern Testability of DelayProbability for Multiple Faults" Faults"S. Chakravarty, H.B. Hunt III - State University of J. Savir, W.H. McAnney - IBM CorporationNew York In a computer system, the maximum allowable propagation

This paper presents a new and improved algorithm for delay of the combinational logic networks between latchesdetermining if the detection probability of a fault in a is equal to the interval between the system clocks. Thecombinational circuit is above a given threshold value and objective of delay testing is to guarantee that the delay offor calculating the exact value of the detection probability. the manufactured network falls within specifications. In thisUnlike previous approaches, this algorithm is applicable to paper, the authors analyze the capability of randommultiple functional gate faults, not just single stuck-at faults. patterns to detect slow paths in combinational logic.Break: 10:00 a.m.

10.3 9:30 a.m. "Integrating Guided Probe and Fault 10.4 10:30 a.m. "A Strategy for Enhancing FaultDictionary: an Enhanced Diagnostic Approach" Coverage on VLSI Circuit Boards UsingV. Rafford, P. Keating - Teradyne, Inc. Performance In-Circuit Test Techniques"

An approach is described which integrates guided probe M. Fabish - Teradyne Inc.analysis and the fault dictionary in a closed feedback loop Higher fault detection in high performance in-circuit test iswhich improves overall diagnostic efficiency. realized in exchange for an acceptable amount of testBreak: 10:00 a.m. programming time. Case studies demonstrate the

practicality of achieving 95-99% fault coverage on VLSIboards.

11.3 9:30 a.m. "A Logic Verification System for 11.4 10:30 a.m. "PROSPECT: A Production System forCombinational Circuits" Partitioning and Evaluating Chip Testability"R-S. Wel, A. Sanglovanni-Vincentell - Univ. of G. Chen-Ellis, D. Lahtl- Hughes Aircraft Co.California, Berkeley A new system is described which performs testability

In this paper, several new algorithms for logic verification of guideline checking on a new logic design and whichlarge scale circuits are presented. These offer performance performs partitioning of the design to make it amenable toadvantages over previous approaches. efficient ATG.Break: 10:00 a.m.

12.3 9:30 a.m. "Testability Features of MC68851 12.4 10:30 a.m. "Testability Design for Micro-370, APMMU" System/370 Single Chip Microprocessor"G. Giles, K. Scheuer - Motorola Inc. F. W. Shih, H. H. Chao, S. Ong, J. Y. F. Tang, C. A.

This paper discusses the testability features of the Trempel, A. L. Diamond - IBM Corp.MC68851 Paged Memory Management Unit. These This paper details testability design for Micro-370, a 32-bitfeatures include a control store readout, injectable single chip microprocessor that directly implements &microcode, memory test modes, and scan based PLA test emulates the entire System/370 instruction set. Practicalmodes. testability design problems & the associated solutions areBreak: 10:00 a.m. discussed.

13.3 9:30 a.m. "An Experiment on Intermittent-FailureMechanisms"M. L. Cortes, E. J. McCluskey - Stanford University

Intermittent failures can be studied by stressing good parts.The behavior of the chips under stress is similar to that of amarginal chip under normal operating conditions. Theexperiments show that most intermittent failures arepattern-sensitive for both sequential and combinationalcircuits. A stress-strength analysis is presented to explainthe experimental results.Break: 10:00 a.m.

13.4 10:30 a.m. "Reliability and Electrical Properties ofGate Oxide Shorts In CMOS ICs"J. M. Soden - Sandia National LaboratoriesC. F. Hawkins - The University of New Mexico

Gate oxide shorts are the dominant defect in most MOSFETprocesses. This defect was shown in many cases to betransparent to a functional or stuck-at test model. Adverseimplications for battery operated and high reliability IC'sprovide motivation for further investigation of the long-termreliability and electrical properties of gate oxide shorts.

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9.5 11:00 a.m. "Random Pattern Testability by FastFault Simulation"A.J. Brlers, K.A.E. Totton - British TelecomResearch Laboratories

A BIST analysis tool is described which makes use of fastfault simulation, a parallel implementation of the single faultpropagation technique. The tool identifies those faults in acircuit which are random pattern resistant. Also described isadditional software which will automatically introduce extratest hardware to ensure detection of such faults, thusensuring high test quality.10.5 11:00 a.m. "Testing a Board Loaded with Leaded

and Surface Mounted Components"H. Bleeker and D. van de Lagemaat, Philips, Tele.and Data Systems, The Netherlands

The testability of a board loaded with leaded and surfacemounted components is treated, with an overview of testmethodology and test results.

11.5 11:00 a.m. "Multiple Stuck-At Fault Coverage ofSingle Stuck-At Fault Test Sets"J. Hughes, E. McCluskey - Palo Alto ResearchAssoc.

The results reported here demonstrate significantly highermultiple stuck-at coverage than that predicted by previousstudies. A new fault-masking property, 'self-masking," isidentified, and a procedure is defined for identifyingpotentially self-masking faults.



9.6 11:30 a.m. "Comparison of Allasing Errors forPrlmItIve and Non-Primitive Polynomials"T.W. Williams, C.W. Starke - IBM CorporationW. Daehn, M. Gruetzner - Univ. of Hannover

In this paper, the authors employ a Markov process toinvestigate aliasing during signature analysis, when theprobability of an error occurring for any random vector isvery small or very large. Both cases of primitive andnon-primitive polynomials implemented in the signatureregister are examined. Conclusions from the analysis areverified using simulation.

10.6 11:30 a.m. "A Method of Improving In-Circuit TestEffectiveness"R. Russell, Honeywell Information Systems

Apparent intermittent rejection of good parts preventsin-circuit test from reaching its full potential. A programmingtechnique is offered to alleviate this problem.

11.6 11:30 a.m. "ESIM/AFS - A ConcurrentArchitectural Level Fault Simulator"S. Davidson, J. Lewandowskl - AT&T Eng. Res.Center

The authors describe a concurrent fault simulator whichsupports internal faults, as well as pin faults, usinghigh-level simulation models to achieve high throughput.

12.5 11:00 a.m. PANEL DISCUSSION ONMICROPROCESSOR TESTINGSession speakers plus:P. Gelsinger- Intel Corp.J. Crane - Sperry Corp.

13.5 11:00 a.m. "The Effects of Back-drive StressingFast IC Technologies"B. Schneider, G. Jorgensen, M. B. Christensen -ElektronIkcentralen

A study of back-drive stressing of fast bipolar and CMOSIC's and the related impact on device reliability has beencarried out. A population of back-driven samples and asimilar virgin population have been exposed to extendedlifetest under accelerated conditions and results of the twopopulations are compared.

13.6 11:30 a.m. "Towards Automatic Failure Analysisof Complex ICs through E-Beam Testing"L. Bergher, J. Laurent, B. Courtols - IMAGJ.P. Collin - IBM

The paper will describe a new strategy for failure analysisin random logic devices such as microprocessors and otherVLSI chips when the electrical scheme is not known. Thisstrategy is based upon the use of a test tool composed of aScanning Electron Microscope (SEM) allied to voltagecontrast, an exerciser, an image processing system and acontrol and data processing system.

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September 9, 1:30 p.m.-5:00 p.m.

TUESDAY, SESSION 14September 9, 1:30 p.m.-5:00 p.m.DESIGN FOR TESTABILITY-METHODS ANDMEASUREST. W. Williams - IBM (Chairperson)R. Mercer - University of Texas (Organizer)SUMMARY: This session suggests new approaches to designof testable digital circuits. Both new methods evaluatetestability of a design & ways to make design more testable.

TUESDAY, SESSION 15A/BSeptember 9, A. 1:30 p.m.-3:00 p.m.; B. 3:30 p.m.-5:00 p.m.15A: CMOS MODELING, TEST GENERATION, ANDFAULT SIMULATIONM. A. Kearney - Digital Equip. Corp. (Chairman)J. G. Tellier - Digital Equip. Corp. (Organizer)SUMMARY: Devoted to CMOS logic tests: detection of multi-ple stuck faults in CMOS VLSI, efficient CMOS circuit stuckfault simulation, modeling & simulation of CMOS delay faults.

TUESDAY, SESSION 16A/BSeptember 9, A. 1:30 p.m.-3:00 p.m.; B. 3:30 p.m.-5:00 p.m.16A. INEXPENSIVE TESTING TECHNIQUESE. Millham - IBM Corp. (Chairperson)A. Hoover - NCR Corp. (Organizer)SUMMARY: VLSI device testing does not always requirethe purchase of an expensive tester. Three examples ofeconomical test approaches are reviewed in this session.

TUESDAY, SESSION 17September 9, 1:30 p.m.-5:00 p.m.CAE AND WORKSTATION

R. Apte - Valid Logic Systems (Chairperson)R. Apte - Valid Logic Systems (Organizer)SUMMARY: Session on CAE & Workstation, a new field ofthe links between CAE workstations and test engineering isrecognized. Six papers address issues from rapidly changingCAE software to friendly interaction with a workstation.

TUESDAY, SESSION 18September 9, 1:30 p.m.-5:00 p.m.ADVANCED TESTING OF ANALOG-DIGITAL DEVICESAND SYSTEMSC. Evans - Analogic (Chairperson)S. Denker - GenRad (Organizer)SUMMARY: Advanced theoretical methods are applied inpractical ways to real-world testing of complex analogdevices and systems.



14.1 1:30 p.m. "TRIM: Testability Range by Ignoringthe Memory"L. Carter, L. Huisman, and T.W. Williams - IBM

The testability by random test patterns of faults in the logicsurrounding embedded two port RAM's is studied. Upperand lower bounds on the probability of detecting faults areobtained by analyzing a modified, purely combinationalcircuit without the RAM.

15A.1 1:30 p.m. "Detecting Multiple Faults in CMOSCircuits"N. Jha - Univ. of Michigan

The author describes the effect of tests, designed to coversingle stuck-open faults in complex CMOS gates, but whichresults in coverage of all multiple stuck-opens in suchgates. He derives conditions in which a multiple faultconsisting of both stuck-open and stuck-on faults can beguaranteed to be detectable.

16A.1 1:30 p.m. "Functional Testing of the NS 32332Microprocessor"S. Shalem - National Semiconductor (Israel)

This paper describes the functional test of a 32-bitmicroprocessor on a custom functional tester. A briefoverview of the hardware and software utilized to producean easy to use tester is presented.

17.1 1:30 p.m. "An Automated, Menu ScreenGeneration Software Tool for VLSI ATEProgramming and Operation"N. Morgan - GenRad, Inc.

This paper describes the capabilities of an automated screenmenu generation facility for use on VLSI test systems. Anhistorical perspective as well as a comparison betweentraditional techniques and a more modem approach ispresented. The design goals and requirements of this systemare discussed in detail. Methods of exploiting the advantagesand disadvantages of this system are discussed as well.

18.1 1:30 p.m. "Video DAC/ADC Dynamic Testing"T. Tamamura - Yokogawa Hewlett-Packard

This paper presents a new analog IC tester architecture totest very-high-frequency DAC's and ADC's. Measurementresolution of greater than 10 bits can be achieved.

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14.2 2:00 p.m. "Approaches to Circuit Level Design for 14.3 2:30 p.m. "Designing Testable Control Paths withTestability" Multiple and Feedback Scan-Paths"R. Fulil and J. Abraham - University of Ilinois R. Makki and C. Tiansheng - University of North

Design approaches to overcome testing problems such as Carolinalogic race conditions, stuck open faults, and long counter A technique for designing testable control paths and anchains - which can occur in functional logic blocks - are associated test process called branch testing arepresented. These approaches are derived based on fault presented. This work attempts to extend common methodscharacterization and fault analysis, and they are of software testing to hardware designs.implemented within the functional blocks. Break: 3:00 p.m.

15A.2 2:00 p.m. "Efficient Fault Simulation of CMOS 15A.3 2:30 p.m. "Modeling and Simulation of DelayCircuits with Accurate Models" Faults In CMOS Logic Circuits"V. iyengar, Z. Barzilai, B. Rosen, J. L. Carter, I. S. Koeppe - Siemens AGNair, J. Rutledge - IBM Corporation A technique is presented here by which single delay faultsG. Silberman - Technicon and IBM Israel in static CMOS logic gates can be fault-simulated at the

This paper describes a method of deriving gate-level logic gate level. Implementation of this simulation technique in anmodels equivalent to CMOS circuits, such thai transistor existing fast fault simulation program is described.stuck-conducting and stuck-nonconducting faults can be Break: 3:00 p.m.represented by stuck-at faults in those models and fault-simulated efficiently.

16A.2 2:00 p.m. "Inexpensive Microprocessor Testing 16A.3 2:30 p.m. "ATE Test Head Requirements forof Custom ICs on Wafers, Packages, and Boards" Low-Cost VLSI Testing"T.J. Muirooney - AT&T Bell Labs J.D. Bray - GenRad, Inc.

In many cases the application or volume of new VLSI A remote test head can be designed that will deliver morecircuits does not warrant the use of expensive test than adequate performance at a reasonable cost for testinghardware and software. This paper describes a set-up VLSI devices. The system covers the testing requirementswhich allows complete testing from wafers to boards of a for a wide variety of devices.very small volume, high speed VLSI circuit. Break: 3:00 p.m.

17.2 2:00 p.m. "VIVED- A Vlsual Vector Editor" 17.3 2:30 p.m. "Improved Workstation/Tester InterfaceR. S. Chomiczewski - AT&T Engineerlng Is the Key to the Quality of Test-ProgramResearch Center Generation"

VIVED is a special-purpose, display oriented editor J. Telsher - Tektronix, Inc.especially designed for entering and updating test vectors. The paper describes the current method of test generationUsing the terminal screen as a window to the vectors and a- and its inherent problems. It then describes Testlink, apowerful command set, VIVED has increased productivity in major project aimed at solving these problems. The detailstest vector generation. of how Testlink functions and solves the problem of test

generation are described in the paper.Break: 3:00 p.m.

18.2 2:00 p.m. "Testing Ten-Bit A/D Converter with aDigital VLSI Tester"S. Mcintyre - Intel Corporation

Single-chip microcontrollers such as Intel's 8022 andMotorola's 68HC1 1, have incorporated eight bit A/Dconverters for some years. Now, newer microcontrollersincorporate ten bit A/D converters that demand greatermeasurement accuracy. This paper discusses the testingtechniques used for production testing of an on-board 10 bitA/D converter using a 12-bit VLSI tester.

18.3 2:30 p.m. "ISDN: Analog or Digital Test?"D. Orrecchlo - LTX

The industry is establishing standards for an IntegratedServices Digital Network (ISDN). Paper examines mostappropriate methods for testing, transmitting, & receivingcircuits for this standard. Worst-case waveform templaterequirements, as well as the signal degradation expected inreal applications are considered. Parts designed to meet therequirements of the physical layer of the ISDN must be testedas analog (not digital) devices.Break: 3:00 p.m.

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14.4 3:30 p.m. "Logic Elements for Universally 14.5 4:00 p.m. "Calculation of Greatest Lower BoundsTestable Circuits" Obtainable by the Cutting Algorithm"M.R. Mercer - University of Texas at Austin R. Gaede, M.R. Mercer- University of Texas at Austin

A new approach to design for testability is introduced based B. Underwood - MCCon the properties of universally testable logic elements. Any The cutting algorithm calculates bounds on the probabilitycombinational or sequential circuit constructed using these of detecting faults with random patterns. This paperelements can be tested for all stuck-at data faults with just investigates the best possible data which the cuttingfour test patterns. algorithm can generate based on analysis of several

example circuits.

15B: AC TESTING TECHNIQUES 15B.2 4:00 p.m. "Transition Fault Simulation byM. A. Kearney - Digital Equip. Corp. (Chairman) Parallel Pattern Single Fault Propagation"J. P. Barlow - IBM Corporation (Coordinator) J. Waicukauski, E. Lindbloom - IBM15B.1 3:30 p.m. "Statistical AC Test Coverage" Corporation

D. Wu, C. Radke - IBM Corporation B. Rosen, V. Iyengar - IBM ResearchJ. Roth - IBM Research In this paper, the authors describe an efficient method of

The authors here describe an algorithm which calculates "transition fault" simulation, for use in evaluating the ACthe effectiveness of a test set in providing test coverage for test coverage of test pattern sets for combinational or LSSDAC (delay) faults. The coverage rating obtained will logic designs. Several interesting cases of "AC faultconsider the statistical impact of process random defects. redundancy" wore observed and will be discussed.

16B: ADVANCED TEST APPROACHES AND METHODS 16B.2 4:00 p.m. "Electron Beam Tester with 10 psE. Miliham - IBM Corp. (Chairman) Time Resolution"A. Hoover - NCR Corp. (Coordinator) H. Todokoro, S. Yoneda, S. Seltou, S. Hosoki-16B.1 3:30 p.m. "A Prober/Handler Interface for High Hitachi LTD Central Research Laboratory

Pin-Count ASIC Devices" An Electron Beam Tester capable of examining the internalB. Wells - Teradyne, Inc. functioning of high-speed LSI's with a 10 ps resolution has

This paper reviews interface requirements for high accuracy been developed. This tester has successfully been used todevice testing, and describes a new 576 pin handler/prober measure the internal waveforms of a GaAs ring oscillator.interface to a VLSI module tester with an 80 MHz data rate.

17.4 3:30 p.m. "Visual Programming for Analog/Hybrid 17.5 4:00 p.m. "Instability - A CAD Dilemma"ATE" M. Mannan - Nat. Semiconductor Corp.L. Konneker, F. Cox, D. Moreland - Georgia Inst. Computer Aided Design is a relatively new field and theof Tech. problems and complexities involved in designing a system

This paper describes a current research project into visual are immense and need a greater knowledge base thanprogramming for analog/hybrid ATE. Arguments are made designing a pure hardware or a pure software system. Awhy programming ATE is a prime candidate for visual CAD engineer must be well conversant with theprogramming. The architecture of the proposed system is fundamentals of the system for which the computer aid isdescribed. The way an ATE programmer interacts with the being designed and, of course, must have an extensivesystem is described. knowledge of the software tools that are being used.

18.4 3:30 p.m. "ISDN Device Testing Demands a New 18.5 4:00 p.m. "Testing a Solid-State Color ImageLevel of Performance From Automatic TestEquipment"R. Kramer - Teradyne, Inc.

Devices designed for the Integrated Services Digital Network(ISDN) have created new technological challenges forautomatic test equipment. This paper analyzes the tests thatwill be required by these new devices; and the testtechniques, test system hardware, and software toolsnecessary to perform them. It concludes with a description ofone test solution.

Sensor"T. Noguchl, A. Murakami, M. Kawal, and Y. Hayasaka- Mitsubishi Electric Corporation

When testing solid-state image sensors, it is important todetect different classes of picture-quality defects. They includenot only grey-level pixel data, but also the spatial distributionof bad pixels included in the defect. Paper presents a digitalmethod for automatic detection and measurement of imagesensor defects.

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14.6 4:30 p.m. "A New Testability Measure for DigitalCircuits"J.C. Wang, D-Z. Wei - Institute of ComputingTechnology, People's Republic of China

An improvement on the SCOAP testability measure calledRFOTM is presented based on reconvergent fanoutconcepts. A type of fanout which behaves like a fanout-freeline is described.

INTERNATIONAL TEST CONFERENCEWEDNESDAY

September 10, 8:30 a.m.-12:00 noon

WEDNESDAY, SESSION 19ASeptember 10, 8:30 a.m.-1 1:00 a.m.DESIGN FOR TESTABILITY-PLA's, SCAN PATHS, ANDVERIFICATION TECHNIQUESV. D. Agrawal - AT&T Bell Labs (Chairperson)M.R. Mercer - University of Texas (Organizer)SUMMARY: New ways to use scan paths to test for faults &design methods to make PLA's more testable. Also a contri-bution on design verification techniques at the system level.

16B.3 4:30 p.m. "Tests of Hermetically Sealed LSINLSIDevices by Laser/Photoexcitation Logic WEDNESDAY, SESSION 20Analysis"Setme 0830am1130..F. J. Henley - Dataprobe Corporation September 10, 8:30 am-11:30 am.

Successful use of laser photoexcitation logic analysis on ARTIFICIAL INTELLIGENCE APPLICATIONS TO TEST -hermetically sealed CMOS devices with transparent lids has PART Iestablished the feasibility of its use on production parts. A H. K. Reghbati-Simon Fraser Univ. (Chairperson)significant simplification was achieved in the electrical test A. Miczo - Sentry Schiumberger (Organizer)pattern program. SUMMARY: The first session on the application of Artificial

Intelligence to test concentrates on its use in the areas oftest pattern generation, built-in self-test, and fault location.

17.6 4:30 p.m. "Software Integration In aWorkstation-Based Electron-Beam Tester" W S 21S. Concina, L. Lattanzi, G. Liu, S. Reyfman, N.Richardson - Sentry/Schiumberger September 10, 8:30 a.m.-11:30 a.m.

This paper introduces a novel electron-beam probing ACCURACY & PERFORMANCE - THEY'LL GET YOUsystem for VLSI engineering. It will describe a software EVERY TIME!environment that tightly integrates several application B. West - Sentry/Schiumberger (Chairperson)specific tools. These tools cooperate to provide A. Hoover-NCR Corp. (Organizer)unprecedented functionality for electron-beam probing SUMMARY: As technology surges on, tester speeds aretechniques. required to keep up with new device speeds. This session

explores accuracy and performance from different viewpoints.

WEDNESDAY, SESSION 22September 10, 8:30 a.m.-12:00 noonMEMORY TEST - FROM FIFO TO VIDEOJ. Katz - AMD (Chairperson)D. J. Graham - inTest (Organizer)SUMMARY: The increasing size, speed and functionalcomplexity of today's memory devices are changing the roleof memory test. Papers address testing of large memories,FIFOs, video RAMs and other non-classic types of memories.

WEDNESDAY, SESSION 23September 10, 8:30 a.m.-12:00 noonSOFTWARE SOLUTIONS TO TESTING CHALLENGESD. L. Denburg - AT&T Bell Laboratories (Chairperson)D. L. Denburg - AT&T Bell Laboratories (Organizer)SUMMARY: Software pervades every aspect of testing. Thepapers in this session cover a broad range of topics from testgeneration to test program debugging and design verification.

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INTERNATIONAL TEST CONFERENCEWEDNESDAYSeptember 10, 8:30 a.m.

19A.1 8:30 a.m. "On the Design of Random PatternTestable PLAs"D. S. Ha, S. Reddy - University of Iowa

Programmable logic arrays provide a cost effective methodto realize multiple input, multiple output combinational logiccircuits. In this paper, a method for the design of randompattern testable PLA s is presented.

20.1 8:30 a.m. "Concurrent Test Generation Using AlTechniques"C. W. Yau - AT&T Engineering Research Center

A concurrent test generation algorithm for combinationalcircuits referred to as the C-algorithm, is described. It aimsat generating a test vector that detects the most, asopposed to a single, undetected fault by using an AND-ORgraph in conjunction with efficient Al-styled heuristic searchtechniques.

21.1 8:30 a.m. "Fundamental Limits to TimingAccuracy"M. Keating - GenRad, Inc.

As VLSI devices move to higher and higher speeds, andtest systems start pushing accuracy well below thenanosecond region, it is reasonable to ask what thefundamental limits are for timing accuracy using today'stechnology. This paper explores some of the issues whichlimit timing performance in today's VLSI test systems andoffers some ways of overcoming these limitations.

22.1 8:30 a.m. "Innovative Video RAM Testing"A. Teleda, G. Conner - Teradyne

This paper introduces an innovative philosophy for testingvideo RAMs: simultaneously test the DRAM and serial portto check the interaction within the device using thecapabilities of an advanced memory test systemarchitecture.

23.1 8:30 a.m. "Test Data Quality Assurance"M. Kawal, T. Shimono, S. Funatsu - NECCorporation

This paper examines the possible sources of error in testdata generation and proposes countermeasures. A testdata quality assurance system is also discussed.


19A.2 9:00 a.m. "Scan Path with Look Ahead Shifting(SPLASH)"M. Abadir, M. Breuer - University of SouthernCalifornia

A new testing scheme for circuits with scan paths isdescribed. Both deterministic and random testing arecombined without any additional circuit modifications insuch a way that fewer test vectors generate higher faultcoverage.

20.2 9:00 a.m. "An Artificial Intelligence BasedImplementation of the P-Algorithm for TestGeneration"A. S. Wojcik, N. Srinivas, Y. Levendel- AT&T BellLaboratories

The P-Algorithm is implemented for combinational circuitsusing the Interactive Theorem Prover (ITP). The test set isobtained by expressing the circuit connectivity as a set ofinput clauses and by employing the demodulation andhyper-resolution inference mechanisms provided by ITP.

21.2 9:00 a.m. "A New Pin Electronics Architecture ForHigh Performance Functional Module Testing"S. Cohen - Teradyne, Inc.

As the speed and accuracy requirements of the moduletesters approach those traditionally associated with devicetesting, the interplay of drive rise-time, output impedanceand fixture technique are increasingly critical to testaccuracy. A new pin electronics architecture that permitsselectable output impedance and on-the-fly detectortermination will be described in this paper.

22.2 9:00 a.m. "Transmission Problems EncounteredWhen Testing Memory Devices In Parallel onMemory ATE"A. Mostacciuolo - Sentry Schiumberger

Testing memory devices in parallel with modem Memory ATEis different than testing individual memories. Methodologiestoday are not ideal for parallel testing because of problems inthe transmission of the DUT output to the Comparator/Loadcircuitry of the ATE equipment. Paper will analyze thetransmission problem, propose interface configurations, andrecommend one solution that provides the best performance.

23.2 9:00 a.m. "A Group Probing Strategy for TestingLarge Numbers of Chips"V. S. Cherkassky, L. L. Kinney - University ofMinnesota

An approach to optimally testing a large number of identicalchips in parallel is presented. The method is useful fordesign verification and production testing.

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19A.3 9:30 a.m. "A Concurrent Testing Strategy forPLAs"D. L. Tao, P. K. Lala, C. R. P. Hartmann -Syracuse University

A new concurrent testing technique for PLAs is proposed.Any single fault, and a majority of multiple faults can beautomatically detected in PLAs which are designed usingthe proposed technique.Break: 10:00 a.m.

20.3 9:30 a.m. "ARNOLD: Applying an Al Workstationto Production Test Code Generation"R. Smoody - Tektronix

An expert system called Arnold, which possesses testerspecific knowledge, receives a test described in the testengineer's domain and generates test suites optimized for aparticular tester. This permits the test engineer toconcentrate on what must be done and not concern himselfwith how it is to be done by a particular tester.Break: 10:00 a.m.

21.3 9:30 a.m. "Testing FMAX In a ProductionEnvironment"D. Simpkins - MCT, Inc.

Current definitions for FMAX can be confusing, and industryspecifications are often inadequate. This paper definesFMAX and presents the critical parameters that influenceset-up and testing criteria. It will also address testing IC's inan ATE environment.Break 10:00 a.m.

22.3 9:30 a.m. "FIFO Test Program Development"A. Kanadjlan, D. Rodgers & M. Shepherd - Xerox

This paper presents methods for developing ATE testprograms for First-In-First-Out memory ICs. Results includinganalysis of failure modes found in available devices will bepresented. FIFO memories are becoming popular as bufferstorage between subsystems operating at different test rates.Memory test engineers familiar with addressable synchronousmemory must be aware of test techniques for testing thesenon-addressable, asynchronous serial memories.Break: 10:00 a.m.

23.3 9:30 a.m. "An Automated E-Beam Tester with CADInterface, "FINDER": A Powerful Tool for FaultDiagnosis of ASICs"N. Kuil, T. Tamama - NTT ElectricalCommunications Laboratories

A previously reported E-Beam test system has beenextended to handle ASIC devices. It is interfaced to acommercially available CAD system for net-list extractionand can measure the logic state of metal patterns beneathan insulating layer.Break: 10:00 a.m.


19A.4 10:30 a.m. "DVTS: Design VerificationTechniques for Functional Simulation"K. Fukuoka, S. Takemura, K. Ohga, A. Suglyama -Hitachi

This paper describes a methodology for applying testprograms to the verification of design for very large scalecomputers. Examples show that 97% of the design faultscan be detected through this system function simulationbefore the start of hardware testing.

20.4 10:30 a.m. "An Intelligent Knowledge-BasedSystem Tool for High-Level BIST Design"N. A. Jones, K. Baker - GEC Research

This paper describes a knowledge based CAD tool to planBIST applications in VLSI design. Implementation is basedon a multi-paradigm methodology using the LOOPSenvironment and knowledge from a DFT experts group.

21.4 10:30 a.m. "Timing Accuracy and YieldEstimation"J.S. Pabst - Trillium Test Systems

The purpose of this paper is to demonstrate how testerTiming Accuracy affects product yield. Using elementarystatistical tools, a method which compares the timingaccuracy of different testers and estimates their resultantyields will be shown.

22.4 10:30 a.m. "Redundancy Test for 1 Mbit DRAMUsing Multi-Bit Test Mode"Y. Nishimura, H. Hamada, H. Hidaka, H. Ozaki, K.Fujlishima, Y. Hayasaka - Mitsubishi

This paper describes the wafer test for redundancy of 1 MBx 1 DRAMs with Multi-Bit Test (MBT) mode. To realize aneffective redundancy test using the MBT mode, simpleredundancy flags have been introduced in the tester and aneffective redundancy architecture is used on chip.

23.4 10:30 a.m. "A Functional Test Program Generator"E. Sarkany, J. Muhr, J. Feeney- IBM Corporation

This paper discusses a system for reducing the effortneeded to manually generate tests for devices for whichfully automatic test generation tools cannot be used.

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INTERNATIONAL TEST CONFERENCEWEDNESDAYSeptember 10, 1 1:00 a.m.

WEDNESDAY, SESSION 19B 11:00 a.m.-12:00 noonPANEL: Deterministic Versus Random TestingV.D. Agrawal -AT&T Bell Labs (Chalrperson)M.R. Mercer - University of Texas (Organizer)SUMMARY: Two fundamentally different methods for testpattern generation currently are used in order to test digitallogic. Deterministic patterns are usually produced byassuming a structural fault set and finding patterns whichwill detect a large fraction of those faults - as verified byfault simulation. Test pattern generation in this approach

(continued)

20.5 11:00 a.m. "The Role of Pattern Recognition InVLSI Testing"S. D. Bedrosian - Univ. of Pennsylvania

The focus in this paper is on concurrent developments suchas fiber optics and optical techniques, including the Hopfieldneural net model, and their application to the needs of VLSItesting. Critical developments are brought together whichwill permit feasibility study of an automatic test systembased on artificial intelligence ingredients. An objective is todevelop smart sensing to extract features from chips orfrom mask sets.


September 10, 11:00 a.m.-12 noon

SESSION 19B (continued)can be computationally expensive for large circuits withlarge fault sets, but the confidence in the ability of thepatterns to detect the faults is high. In contrast, random testpatterns are very inexpensive to generate. This panel willdiscuss the relative merits and probable future utilization ofthese two test pattern generation methods.Panelists:E. J. McCluskey - Stanford; R. Sedmak - Self-TestServices; T. J. Snethen, R. Walther - IBMPlus authors of papers in Session 19A.

20.6 11:30 a.m. "Artificial Intelligence Mini PanelH. Reghbati- Simon Fraser University

PANELISTS:C. Yau - AT&T Engineering Research CenterN. Srinivas - AT&T Bell LabsR. Smoody - Tektronix, Inc.N. A. Jones - GEC ResearchS. Bedrosian - University of PennsylvaniaR. Hartley - New Mexico State University

21.5 11:00 a.m. "Accuracy and Repeatability in DSPTest Methods"E. Rosenfeld - LTX Corporation

As analog semiconductor device test becomes more heavilybased on DSP measurement techniques, the test engineeris confronted with evaluating software and hardwareperformance. This paper draws on concepts from bothsignal processing and statistics and provides a usefulcombination of concepts.

22.5 11:00 a.m. "A Novel Approach for Testing 22.6 11:30 a.m. "Designing Characterization Tests forMemories Using a Built-In Self Testing Technique" Bipolar Array Performance Verification"K. T. Le - Sydney University D. J. Malone, T. J. Knips - IBMK. Saluja - University of Wisconsin Characterization of high performance bipolar memory array

A method to reduce test time which accesses many cells products has become increasingly difficult in recent yearssimultaneously while in test mode is presented. Based on due to both product densities and increasing complexity ofsimulation studies, new test algorithms are proposed. system dedicated memory architectures. One of the moreThese are simple to implement, and the necessary pressing problems deals with verification of switchinghardware overhead to implement them is discussed. performance specifications. This paper presents a strategy

for defining tests of high performance arrays.

23.5 11:00 a.m. "Test Program DebuggingEnvironment for Linear IC Testers"T. Hidal, T. Matsumoto, F. Tsuruda - YokogawaHewlett-Packard Co.

One approach to minimizing the cost of developing testprograms for linear IC testers is discussed. It utilizes virtualpanels and virtual scopes to increase the productivity of testprogrammers.

23.6 11:30 a.m. "Issues That Arise In Translating VLSITest Programs Between Testers"C. Havener - GenRad, Inc.

This paper discusses the issues which make the translationof test programs between VLSI testers difficult, andrecommends program design practices that enhanceportability.

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September 10, 1:30 p.m.-5:00 p.m.

WEDNESDAY, SESSION 24September 10, 1:30 p.m.-5:00 p.m.SYSTEMS TESTD. Ringleb - DEC (Chairperson)V. Spiros - DEC (Organizer)SUMMARY: The session covers test techniques for memorysystems of hexagonally-connected systolic arrays, concurrenttesting for microprogrammed control units, and failure analysisof fault-tolerant clock systems.

WEDNESDAY, SESSION 25September 10, 1:30 p.m.-5:00 p.m.ARTIFICIAL INTELLIGENCE APPLICATIONS TO TEST-PART IIR. Hartley - New Mexico State Univ. (Chairperson)A. Miczo - Sentry Schiumberger (Organizer)SUMMARY: This session on the application of ArtificialIntelligence focuses on applications to fault and processdiagnosis in ATE systems and semiconductor manufacturng.

WEDNESDAY, SESSION 26September 10, 1:30 p.m.-4:30 p.m.SEARCH TECHNIQUES THAT YOU CAN USE!P. Burilson - Megatest Corp. (Chairperson)A. Hoover - NCR Corp. (Organizer)SUMMARY: Traditional search algorithms have severeperformance limitations. The authors present alternatives totraditional methods and outline performance improvements,improved efficiency and speed techniques.

INTERNATIONAL TEST CONFERENCEWEDNESDAYSeptember 10, 1:30 p.m.

24.1 1:30 p.m. "Techniques for TestingHexagonally-Connected Systolic Arrays"H. Elhunl, L. Kinney - University of Minnesota

Two sets of conditions for testing hexagonally-connectedsystolic arrays are presented. The first one gives generaltestability conditions for such arrays. The second test setgives stronger conditions and a simpler test procedure.Under these conditions, the arrays can be tested with aconstant number of distinct test vectors independent of thearray size.

25.1 1:30 p.m. "A Knowledge Based DiagnosticSystem for Automatic Test Equipment"B. L. Havilcsek - Westinghouse

This paper describes a knowledge based diagnostic systemthat combines both shallow and deep knowledge reasoning.The overall diagnostic system concept is described and adetailed description of the deep knowledge (causalreasoning) system is presented.

26.1 1:30 p.m. "Automated Effective-BitCharacterization of Waveform Digitizers"Y.C. Jenq - Tektronix, Inc.

This paper presents a new approach to characterize theeffective bits of a waveform digitizer. This proposedalgorithm is simple and accurate. Furthermore, the newapproach can achieve a speed up to a factor of 30 to 80times for the effective bits characterization as compared tothe old approach.

WEDNESDAY, SESSION 27September 10, 1:30 p.m.-3:00 p.m.PANEL SESSION: HOW HARDWARE MODELING ANDENGINEERING PROTOTYPE TESTING FIT INTO THETEST ENVIRONMENTM. S. Glenn - Valid Logic Systems (Chairperson)R. Apte- Valid Logic Systems (Organizer)Hardware modeling from the leading CAE vendors is beingused today for functional verification of both ICs andmodules in the engineering department. At the same time,"Engineering Prototype" testers, a new form of test system,are also being used. What are the advantages anddisadvantages of each of these methods, and when is itbest to use one approach over the other? This panel willpresent the issues and merits of each approach, followedby open discussion of questions from the audience.Panelists:

M. Glenn - Valid Logic SystemsK. Fetterly - TektronixK. Lindsay - Integrated Measurement SystemsWayne Heideman - AT&T Bell Labs

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24.2 2:00 p.m. "On Concurrently TestableMicroprogrammed Control Units"C. H. Tung, J. Robinson - University of Iowa

A new architecture for concurrent testing of amicroprogrammed control unit is presented. This approachdetects a larger class of failures with lower overhead thanearlier work. In this paper, a new scheme for the design ofconcurrently testable microprogrammed control units ispresented. A specific modified routine signature isassociated with each microroutine.

25.2 2:00 p.m. "Artificial Intelligence In SemiconductorManufacturing for Process Development, FunctionalDiagnostics, and Yield Crash Prevention"M. C. Murphy Hoye - Sentry/Schlumberger

Several aspects of semiconductor manufacturing and testcan be controlled and enhanced through the use of anintelligent system, including determination of productcharacteristics, development of reliable manufacturingtechniques, and minimization of yield crash and recoveryepisodes. An expert system called SMART is used toachieve these ends.26.2 2:00 p.m. "DSP Measurement of Frequency"

E. Rosenfeld - LTX CorporationTraditional techniques for measuring amplitude andfrequency require dedicated hardware. A new,computationally efficient technique for accurately measuringthe amplitude and frequency of each of the components ofa composite signal is presented. This technique uses onlyan antialias filter, digitizer and DSP analysis.


24.3 2:30 p.m. "Testing of Fauft-Tolerant Clock Systems"P. Marinos, N. Vasanthavada - Duke UniversityG. Mersten - Lockheed Electronics Co.

The failures of mutually synchronized fault-tolerant clocks areextremely complex to analyze due to the hybrid nature of thesystem and its mutual-feedback structure. The purpose of thispaper is twofold: (1) to present a combination of simulationand analysis of mutually synchronized fault-tolerant clocks;and (2) to describe the experimental results of tests on suchsystems and how those results might be used in the overalldesign process. Break: 3:00 p.m.

25.3 2:30 p.m. "Improving In-Circuit Diagnosis ofAnalog Networks with Expert SystemsTechniques"L. Apfelbaum - Teradyne

Complex analog circuits are difficult to test and diagnoseaccurately. Failed measurements are recorded, but skilledanalysis is frequently required to determine why the testfailed, and how to correct the problem. The expert systemdescribed in this paper employs a comprehensive knowledgebase and diagnostic rules to automate failure analysis andgenerate repair-oriented diagnostics. Break: 3:00 p.m.

26.3 2:30 p.m. "An Improved Search Algorithm"M. Keating - GenRad, Inc.

Searching for the transition from a passing state to a failingstate is a problem that occurs frequently in VLSI testing,especially when characterizing a new part. The traditionalalgorithms used to perform such a search are the binarysearch and the linear search. Both of these algorithms,however, have severe performance penalties under certaintest conditions. This paper describes a new algorithm whichovercomes these limitations, resulting in optimalperformance under all test conditions. Break: 3:00 p.m.

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24.4 3:30 p.m. "Proposed Test Method to ProveSoftware Having a Vector Space Behavior"P. Veronneau - University of QuebecP. Robillard - Ecole Polytech of Montreal

A test method is proposed where the program to be testedis first separated into testable software logical states. Theseare obtained by grouping together all action statementshaving the same global conditional predicate. When thelogical states are vector spaces, it is possible to prove theprogram correct using a finite number of tests.

25.4 3:30 p.m. "Explanation Capabilities in DEFT-A Designfor Testability Expert System"M. Arif Samad, J.A.B. Fortes - Purdue Univ.

The Design for Testability Expert System (DEFT) is capableof modifying circuits that have been designed without anyconsideration for testability to make them testable. Inaddition, it is able to provide meaningful explanations forits reasoning process.


24.5 4:00 p.m. "Functional Testing ofMicroprocessor-Like Architectures"G. Kildiran, P. MarInos - Duke University

A fully automated test generation procedure isdescribed for the functional testing of microprocessor-likearchitectures. It assumes knowledge of the instruction setand a register-level description of the system in order togenerate the optimal test-pattern set.

25.5 4:00 p.m. "Benchmarking an Expert DiagnosticSystem for ATE"A. J. Wilkinson - Teradyne

The goal of the expert system MIND (Machine forINtelligent Diagnosis) is to reduce mean time to repair of acomplex VLSI test system. This paper proposes abenchmarking process for evaluating how well MIND andsimilar diagnostic expert systems meet that goal.

26.4 3:30 p.m. "A Test System For High Density and 26.5 4:00 p.m. "A Divide and Conquer Testing StrategyHigh Speed Digital Board" for Detection of Multiple Faults by SFDTS"K. Moriwakl, S. Ishlyama, K. Takizawa, S. Sekine, J.S.R. Subrahmanyam and P.P. ChaudhuriY. Hinataze, F. Kobayashi - Hitachi Ltd. Indian Institute of Technology

This paper presents the new in-circuit test technique used Due to increased circuit density on a chip, the problem offor high density and high speed all ECL-LSI boards. The test generation is becoming harder. Multiple stuck faultsauthors' approach realizes an excellent diagnostic add a new dimension to the problem. This paper utilizes acharacteristic with a very small amount of overhead divide and conquer strategy to search out the problem ofhardware. multiple stuck faults and presents a new approach.

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24.6 4:30 p.m. "Self-Diagnostics on System Level byDesign"Y. Baron - Varian Associates

In a microprocessor based product, it is feasible to createtesting processes that solely rely upon the product'shardware. This paper presents software design which iscapable of performing failure analysis for system leveltesting and removing service incorporating principles ofartificial intelligence. Also discussed is a description of thebasic hardware required in order to execute test software.

25.6 4:30 p.m. "Making a System Diagnostic Usable"0. Grillmeyer - Teradyne

A practical test system diagnostic must perform with speedand accuracy. In addition, it must have the capability toadapt to a variety of specific customer requirements. Thispaper addresses these needs as applied to MIND, a VLSItest system diagnostic.

INTERNATIONAL TEST CONFERENCE1986 EXHIBITORS LIST

Adcotech CorporationAdvantest America, Inc.Aehr Test SystemsAlessi, Inc.Analog DevicesAndo CorporationAseco CorporationAttain IncorporatedAutomated Electronic

Technology, Inc.Autotest CompanyAxiom Technology

CorporationBiddle InstrumentsCadic, Inc.CerProbe CorporationComputer AutomationComputype, Inc.CTX InternationalDaymarc CorporationDelta Design, Inc.Eagle Test Systems, Inc.Eaton CorporationEG&G WakefieldSystems

ElectroglasElectro-MechanicalSystems, Inc.

Epro CorporationESH, Inc.ExatronJohn Fluke Mfg. Co., Inc.GatanGenRad, Inc.GHI, Inc.Hewlett PackardHHB SystemsHiLevel TechnologyIdea, Inc.Integrated MeasurementSystems, Inc.

Interface TechnologyInternational ElectronicsKarl Suss America, Inc.Keithley Instruments, Inc.KLA InstrumentsKMEGA TechnologyLehighton Electronics,

Inc.Logical Solutions

Technology, Inc.

LOMAC, Div. of ReedholmInstr.

LTX CorporationMac Panel Co.Marconi InstrumentsMastechMegatest CorporationMicro Control CompanyMicro Component

Technology,Inc. (MCT)

Mitsui & Co., USAMosaid Systems, Inc.NCR-CETCNH Research, Inc.Oneac Corp.Pacific Western SystemsProbe Technology

CorporationAugat/PYLON Co., Inc.Reid-Ashman, Inc.Reliabiliity IncorporatedSiemens Energy and

Automation, Inc.Semiconductor Test

SolutionsSentry Schlumberger TestSystems

Support Technologies,Inc.

Sym-Tek Systems, Inc.Temptronic CorporationTektronix, Inc.Teledyne TACTeradyne, Inc.TestronicsTestsystems, Inc.Thermonics, Inc.Thermotron Industries,

Inc.3H IndustriesTrigon IndustriesTrue Diagnostic SystemsTTI TestronWandel & Goltermann,

Inc.Wentworth LabsXCATZehntel, Inc.Zycad Corporation

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MONDAY€¦ · MONDAY September 8, 2:00 p.m. 1.2 2:00 p.m. "ATest Generator IC for Testing Large...

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