Modulation and Demodulation Techniques for FPGAs
Transcript of Modulation and Demodulation Techniques for FPGAs
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1copyright 1998,1999,2000 Andraka Consulting Group, Inc. All Rights reserved
Modulation and DemodulationTechniques for FPGAs
Ray Andraka P.E., president,
Andraka Consulting Group, Inc.the
16 Arcadia Drive • North Kingstown, RI 02852-1666 • USA401/884-7930 FAX 401/884-7950
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2copyright 1998,1999,2000 Andraka Consulting Group, Inc. All Rights reserved
You can do Mathin them things???
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3copyright 1998,1999,2000 Andraka Consulting Group, Inc. All Rights reserved
Overview
• Introduction
• Digital demodulation for FPGAs
• Filtering in FPGAs
• Comparison to other technologies
• Summary
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Digital Communications• Historically only base-band processing• High sample rates for down-converters• Down-conversion traditionally analog• Digital down-conversion with specialty chips• FPGAs can compete
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Why Digital?• Frequency agility• Repeatability• Cost
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Digital Challenges
• A to D converter• High sample rates• Arithmetic intensive
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7copyright 1998,1999,2000 Andraka Consulting Group, Inc. All Rights reserved
e-jωct =cos(ωct)-jsin(ωct)
Decimateby R
VideoBandpass
Filter2f(t) cos(ωct)
PhaseSplit
ωc-ωc -ωc ωc -2ωc0 0 0
√2f(t)ejωct
Conventional Demodulator
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8copyright 1998,1999,2000 Andraka Consulting Group, Inc. All Rights reserved
-jsin(ωct)
cos (ωct)
Lowpass Filter√2 f(t)
Lowpass Filter√2 f(t)
I
Q
Decimateby R
ωc-ωc -2ωc0 0-2ωc 0
e-jωct
Re-arranged Demodulator
*
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Complex Mixer
Re[Ak]
Im[Ak]
ComplexBaseband
Signal(Passband forDemodulator)
ComplexPassband
Signal(Baseband forDemodulator)
NumericallyControlledOscillator
sin(ωct) cos(ωct)
Re[Sk]
Im[Sk]
ωcPhase or
frequencyinput
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FrequencySynthesizer
Phase Angleto WaveShape
Conversion
WaveformOut
Phase AngleModulation
Waveform Synthesis (NCOs)• Various Methods
– Look up table (LUT)– Partial products– Interpolation– Algorithmic
• Most methods use afrequency synthesizer
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∆ Phase(phase increment)
Sample Clock
Phase Accumulator Design
• “Direct Digital Synthesis”
• Essentially integrates phase increment
• Increment value may be modulated
– Frequency and PSK modulation
• Binary Angular Measure (BAMs)
– Most significant bit = π
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Addr
Data
Phase Angle(BAMs)
WaveformOut
Read OnlyMemory
Waveform Synthesis by LUT• Phase resolution limited• Arbitrary waveshapes• Sampled waveshape must be
band-limited• Complex requires 2 lookups• fosc= fs /4 special case
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Using Symmetry to ExtendLUT Phase Resolution
00 N N 00 N N0 N0 N 0N0N
- -++
00 01 10 11
--++
Q1 SinLUT
Q1 SinLUT
Q
MSB
MSB-1
remainingbits I
Phase MSB’sCount
sequence
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Waveform Synthesizer plus Multiplier• Obvious Solution
• Separate into functionalparts
• Treat each partindependently
NumericallyControlled Oscillator
sin(ωct) cos(ωct)
Re[Sk]
Im[Sk]
ωc
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a Cos(φ) phasesignal 000 001 010 011 100 101 110 111
-4 -4 -2.8 0 2.8 -4 2.8 0 -2.8-3 -3 -2.1 0 2.1 3 2.1 0 -2.1-2 -2 -1.4 0 1.4 2 1.4 0 -1.4-1 -1 -0.7 0 0.7 1 0.7 0 -0.70 0 0 0 0 0 0 0 01 1 0.7 0 -0.7 -1 -0.7 0 0.72 2 1.4 0 -1.4 -2 -1.4 0 1.43 3 2.1 0 -2.1 -3 -2.1 0 2.1
Look Up Table Modulator
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6-LUTA[1:0]
6-LUTA[3:2]
6-LUTA[5:4]
6-LUTA[7:6]
<<2
<<2
<<4
Phase[3:0]
n+8
Partial Products Modulator
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6-LUTI[0]
6-LUTI[1]
6-LUTI[2]
6-LUTI[3]
<<1
<<1
<<2
Phase[3:0]
n+8
Q[1]
Q[2]
Q[3]
Q[0]
Distributed Arithmetic Modulator
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n+8
<<1serialinputs
6-LUT
Phase[3:0]
Q[3], Q[2], Q[1], Q[0]I[3], I[2], I[1], I[0]
Distributed Arithmetic Modulator(Serial Form)
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CORDICRotator
Iin
Qin
PhaseAccumulator
Iout
QoutSignal In Modulated
Signal Out
CORDIC Modulator
Iout = Iin cosφ - Qin sinφQout = Qin* cosφ + Iin sinφ
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CORDIC Algorithm Explained
• Coordinate rotation in a plane:x’ = xcos(φ) - ysin(φ)y’ = ycos(φ) + xsin(φ)
• Rearranges to:x’ = cos(φ) [x - ytan(φ)]y’ = cos(φ) [y + xtan(φ)]
cosφ
sinφφ
I
Q
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>>3
x0 y0 z0
xn yn zn
±± ±
>>3 constsign
>>2
±± ±
>>2 constsign
>>1
±± ±
>>1 constsign
>>0
±± ±
>>0 constsign
>>4
±± ±
>>4 constsign
CORDIC Structure
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Digital Filtering
y[k]=Σx[k-i]•Ci
Z-1 Z-1
C0 C1 Ci-2 Ci-1
Z-1x[k]
• Many ConstantMultipliers
• Delay Queues• Products Summed• Advantages
– No tolerance drift– Low cost– precise characteristic
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Distributed Arithmetic FilterShift Reg
Shift Reg
Shift Reg
Shift Reg
C0
C1
C2
C3
<<1Scaling Accum
Addr Data0000 00001 C 00010 C 10011 C 0 + C 1
1110 C 1+ C 2+ C 31111 C 0 + C 1+ C 2+ C 3
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Take Advantage of Symmetry
SREG
X[k]
SREG
SREG
• Real filters aresymmetric
• Add bits withlike coef’s beforefiltering
• Uses SerialAdders
• Halves taps
SREG
SREG
SREG
SREG
x[k]+x[k-6]
x[k-1]+x[k-5]
x[k-2]+x[k-4]
x[k-3]
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Decimating FIR Filters
• Low pass filter then discard samples
• Keep only every 4th outputYn+0=akC0 +ak-1C1 +ak-2C2 + ak-3C3 +ak-4C4 +…Yn+4= ak+4C0 +ak+3C1 +ak+2C2 +ak+1C3 +akC4 +…Yn+8=ak+8C0 +ak+7C1 +ak+6C2 +ak+5C3 +ak + 4C4 +…
• reduces to n parallel filters fed every nth sample
• sub-filter results summed to get result
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16 Tap FIR (c1,c9…)
16 Tap FIR (c2,c10…)
16 Tap FIR (c0,c8…)
16 Tap FIR (c3,c11…)
16 Tap FIR (c5,c13…)
16 Tap FIR (c6,c14…)
16 Tap FIR (c4,c12…)
16 Tap FIR (c7,c15…)
40 MHzInput 5 MHz
Output
128 tap 8:1 Decimating FIR Filtera0,a8,a16...
a1,a9,a17...
a2,a10,a18...
a7,a15,a23...
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<<1Scaling Accum16 Tap FIR (c1,c9…)
16 Tap FIR (c2,c10…)
16 Tap FIR (c0,c8…)
16 Tap FIR (c3,c11…)
16 Tap FIR (c5,c13…)
16 Tap FIR (c6,c14…)
16 Tap FIR (c4,c12…)
16 Tap FIR (c7,c15…)
40 MHzInput
5 MHzOutput
Decimating FIR Filter Reduction
a0,a8,a16...
a1,a9,a17...
a2,a10,a18...
a7,a15,a23...
5 MHzLoad FIR filters without scaling accumulators
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Multiplier-less Filtering• Boxcar or Moving Average filter• FIR with unity coefficients• Nulls at Fs/N
y[k]=Σ x[k-i]
Z-1 Z-1 Z-1x[k]
-35-30-25-20-15-10
-50
Fs/2 Boxcar response (dB) with N=10 i=1
N
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Z-N
+-
Z-1
++
Z-N
+-
Z-N
+-
R↓
Z-1
++
Z-1
++
M Comb sections (zeros)M Integrator section (poles)
Cascaded Integrator-Comb Filters• Response same as M cascaded N*R boxcar filters• High order multiplier-less interpolation or decimation• Constant response relative to decimated sample rate• Use small FIR to shape response
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Frequency Sampling with CIC
40
35
30
25
20
15
10
-5
0
F0
CIC (M=1, N=1,R=10)
fc
2fc
2*F0 3*F0 4*F0
F0 =FS /R
Output from clean-up filter
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Half Band Filters• Special case of FIR
filter• Nearly half of the
coefficients are zero• Response is anti-
symmetric about Fs/4• 15th order half-band
filter is only 5 taps
Ci = [ -15, 0, 84, 0, -296, 0, 1251, 2048, 1251, 0, -296, 0, 84, 0, -15]
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Comparison to dedicated digitalmodulator chips
• Performance similar to dedicated chips• Can be tailored to exact requirements• Other logic can be integrated into chip• Filtering in dedicated chips sometimes better• Some development required• FPGA generally cheaper than Digital
Modulator Chips
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Comparison to DSP Micros
• Higher performance than DSP micro• Higher integration• Cost is comparable considering performance• Hardware vs. software development
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Design Considerations
• Floorplanning required forperformance and density
• Macro generator tools simplifyingdesign task
• Use instantiation in logic synthesis
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Other Considerations• Transmitter
– filter needed to mimimize ISI– Carrier can be coordinated with symbol rate
• Receiver– filter for noise rejection, correction of channel
distortion– Accurate phase reference for carrier needed– Timing normally recovered from signal– Coordinate IF, sample frequency, symbol frequency
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Summary• Approach depends on performance,
resolution and size• Competes with dedicated digital modulator
chips• Can be tailored to exact requirements• Each design has potential for hardware
shortcuts
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Resources• FPGA Vendor Application Notes
– Xilinx web page http://www.xilinx.com– DSP applications notes
• Tools– DSP toolbox for Xilinx– Vendor DSP Macro Generators
• Consulting services, Training, etc.– Andraka Consulting Group, Inc– 401/884-7930– web page: http://users.ids.net/~randraka
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References• M. Frerking, “Digital Signal Processing in Communication Systems”,
Kluwer Academic Publishers, 1994• R. Andraka, “A survey of CORDIC algorithms for FPGA based
computers”, ACM, 1998• E.B. Hogenauer, “An Economical Class of Digital Filters for
Decimation and Interpolation”, IEEE Trans on ACSSP vol ASSP-29no.2 April 1981
• A. Peled & B. Liu, “A New Hardware Realization of Digital Filters”,IEEE trans on ACSSP, vol. ASSP-22 no. 6, December 1974.
ASSP and other transactions are a goldmine of hardware implementations
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Example:
North AmericanTDMA Digital Cellular
ππππ/4 DQPSK Modem
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Specifications
• Differential phase encoding– ±π/4 or ±3π/4 phase offset
• Non-coherent receiver• 28.6 kbps I
Q
π/4 DQPSK Constellation
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Transmitter
• Differential coding
• Uses 2 bits per symbol
• I and Q take values 0, ±1, ±1/√√√√2• Filter interpolates to upsample
• Similar to QAM modulator example
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Receiver
• Non-coherent differential detection
• Digital demodulation from IF to baseband
• Equalizers left out of example
• Nyquist filter is RRC w/ 35% excess BW
• 48.6 kbps (24.3 kbaud)
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ππππ/4 DQPSK Demodulator
NCO-sin(ωct)cos(ωct)
RRCFilter
RRCFilter
CMULT
I
QSlicer
SymbolTiming
Recovereddata
Modulateddata
Symbol Delay
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Receiver
• Sample baseband at 4x baud rate = 97.2Khz
• Bit serial detection logic– 16 bit baseband I and Q = 16x bit clock
• Sample IF using bit clock then decimate
• IF center frequency = bit clock/4 = 16*B– simplifies mixer
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NCO-sin(ωct)cos(ωct)
Re[Ak]
Im[Ak]
64 TapMatched
FilterModulateddata
Down-Converter and Filters• DAC sampled at bit rate• IF at bit rate/4• NCO sequence is 1,-j,-1,j• Decimate 16:1• Decimating filter reduces
to 16 parallel filters• Use 4 tap filters
– Net filter is 64 taps
64 TapMatched
Filter
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4 Tap FIR (C0,C16,C32,C48)*(1)
Reduced Down-Converter and Filters
4 Tap FIR (C1,C17,C33,C49)*(-j)
4 Tap FIR (C2,C18,C34,C50 )*(-1)
4 Tap FIR (C3,C19,C35,C51)*(j)16 step
sequencer
(drivesload
enables)
4 Tap FIR (C4,C20,C36,C52)*(1)
4 Tap FIR (C5,C21,C37,C53)*(-j)
4 Tap FIR (C6,C22,C384,C54 )*(-1)
4 Tap FIR (C7,C23,C39,C55)*(j)
I Output
To QOutput
SampledIF input
Extended to 16 filters
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Further Filter Reduction
• Each 4 tap filter is 4 LUT and Scaling Acc
• Move SA to end of adder tree– Each filter is a 4 LUT with delay queue
• Mixer and 64 tap filter (I and Q) is 152 CLBs
• Filter bit rate is a low 1.55 MHz
• Present data LSB first– Allows serial LSB first output from filter
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Detector
CMULT
I
QSlicer
SymbolTiming
Recovereddata
Symbol Delay• Differential Detection• x[k] • x*[k-1] yields
sin(φk- φk-1 ),cos(φk- φk-1 )• Implement CMULT with
scaling accumulators• 4 Samples per symbol
– Delay is 64 clocks fixed
• Symbol timing selectswhich sample to output
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Complex Multiply
SREGI
SREG
SREG
SREG
Cos(φk- φk-1) =x∆k
<<1
Q
<<1
Sin(φk- φk-1) = y∆k
SlicerLUTsgn
sgnRecovered
Di-bit
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Symbol Timing• Error statistic controls state machine• e= x∆∆∆∆k
2 + y∆∆∆∆k2
– proportional to magnitude squared– Use larger + 1/2 smaller approx
• Compute for each sample• Compare to previous sample
– if difference is less than a threshold no change to sample point– otherwise if current larger, advance sample point– or if previous larger, retard sample point
• 29 CLBs
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Modem Implementation• 1.55 MHz master clock (slooowww)• Entire design in 3/4 XCS30-3 (or 4013E-4)• Device cost under $10• Performance compares favorably with heavily
loaded TMS320C50– TI DSP can only implement 20 Tap filters,– Tx and Rx not concurrent in TI DSP– TI DSP design in/out is complex baseband, not IF– TI DSP design can’t handle equalizer or viterbi decoder