week12-1Modern VLSI Design 3e: Chapters 1-3

Lecture 30

Scale and Yield

Mar. 24, 2003

week12-2Modern VLSI Design 3e: Chapters 1-3

Scale

In library

week12-3Modern VLSI Design 3e: Chapters 1-3

Yield of fabrication process

1. System Yield: = 0.95

 2. Random Yield:

 A = chip area

D = defective density

 3. Total Yield:

1YADeY 2

21 YYY

week12-4Modern VLSI Design 3e: Chapters 1-3

Example

week12-5Modern VLSI Design 3e: Chapters 1-3

Lectures 31 and 32

Routing and simulation

Mar. 26,28, 2003

week12-6Modern VLSI Design 3e: Chapters 1-3

Topics

Layouts for logic networks.

Channel routing.

Simulation.

week12-7Modern VLSI Design 3e: Chapters 1-3

Standard cell layout

Layout made of small cells: gates, flip-

flops, etc.

Cells are hand-designed.

Assembly of cells is automatic: cells arranged in rows; wires routed between (and through) cells.

week12-8Modern VLSI Design 3e: Chapters 1-3

Standard cell structure

VDD

VSS

n tub

p tub

Intra-cell wiring

pullups

pulldowns

pin

pin

Fee

dthr

ough

are

a

week12-9Modern VLSI Design 3e: Chapters 1-3

Standard cell design

Pitch: height of cell. All cells have same pitch, may have different widths.

VDD, VSS connections are designed to run

through cells.

A feedthrough area may allow wires to be routed

over the cell.

week12-10Modern VLSI Design 3e: Chapters 1-3

Single-row layout design

Routing channel

cell cell cell cell cell

cellcellcellcellcell

wire Horizontal trackVertical track

height

week12-11Modern VLSI Design 3e: Chapters 1-3

Routing channels

Tracks form a grid for routing. Spacing between tracks is center-to-center distance

between wires. Track spacing depends on wire layer used.

Different layers are (generally) used for horizontal

and vertical wires. Horizontal and vertical can be routed relatively

independently.

week12-12Modern VLSI Design 3e: Chapters 1-3

Routing channel design

Placement of cells determines placement of pins.

Pin placement determines difficulty of routing problem.

Density: lower bound on number of horizontal tracks needed to route the channel. Maximum number of nets crossing from one end of channel to the other.

week12-13Modern VLSI Design 3e: Chapters 1-3

Pin placement and routing

before

a b c

b c a

before

a b c

bca

Density = 3 Density = 2

week12-14Modern VLSI Design 3e: Chapters 1-3

Example: full adder layout

Two outputs: sum, carry.

sum

carry

x1

x2

n1

n2

n3

n4

week12-15Modern VLSI Design 3e: Chapters 1-3

Layout methodology

Generate candidates, evaluate area and speed. Can improve candidate without starting from scratch.

To generate a candidate: place gates in a row; draw wires between gates and primary inputs/outputs; measure channel density.

week12-16Modern VLSI Design 3e: Chapters 1-3

A candidate layout

x1 x2 n1 n2 n3 n4

a

b

c

s

cout

Density = 5

week12-17Modern VLSI Design 3e: Chapters 1-3

Improvement strategies

Swap pairs of gates. Doesn’t help here.

Exchange larger groups of cells. Swapping order of sum and carry groups doesn’t help

either.

This seems to be the placement that gives the lowest channel density. Cell sizes are fixed, so channel height determines area.

week12-18Modern VLSI Design 3e: Chapters 1-3

Left-edge algorithm

Basic channel routing algorithm.

Assumes one horizontal segment per net.

Sweep pins from left to right: assign horizontal segment to lowest available track.

week12-19Modern VLSI Design 3e: Chapters 1-3

Example

A B C

A B B C

week12-20Modern VLSI Design 3e: Chapters 1-3

Limitations of left-edge algorithm

Some combinations of nets require more than one

horizontal segment per net.

B A

A B

aligned

?

week12-21Modern VLSI Design 3e: Chapters 1-3

Vertical constraints

Aligned pins form vertical constraints. Wire to lower pin must be on lower track; wire

to upper pin must be above lower pin’s wire.

B A

A B

week12-22Modern VLSI Design 3e: Chapters 1-3

Dogleg wire

A dogleg wire has more than one horizontal segment.

B A

A B

week12-23Modern VLSI Design 3e: Chapters 1-3

Rat’s nest plot

Can be used to judge placement before final

routing.

week12-24Modern VLSI Design 3e: Chapters 1-3

Simulation

Goals of simulation: functional verification; timing; power consumption; testability.

week12-25Modern VLSI Design 3e: Chapters 1-3

Types of simulation

Circuit simulation: analog voltages and currents.

Timing simulation: simple analog models to provide timing but not

detailed waveforms.

Switch simulation: transistors as semi-ideal switches.

week12-26Modern VLSI Design 3e: Chapters 1-3

Types of simulation, cont’d.

Gate simulation: logic gates as primitive elements.

Models for gate simulation: zero delay; unit delay; variable delay.

Fault simulation: models fault propagation (more later).

week12-27Modern VLSI Design 3e: Chapters 1-3

Example: switch simulation

a

+

+

b

cd

c1

0

0

X

X

Xo

0

1

1

week12-28Modern VLSI Design 3e: Chapters 1-3

Example, cont’d.

a

+

+

b

cd

c1

0

0

0

1

1o

0

1

0

0

week12-29Modern VLSI Design 3e: Chapters 1-3

week12-30Modern VLSI Design 3e: Chapters 1-3