Modern VLSI Design 3e: Chapter 2 Partly from 2002 Prentice Hall PTRweek3-1

Lectures 6, 7 and 8

Transistor Function

Jan. 17, 20 and 22, 2003

Modern VLSI Design 3e: Chapter 2 Partly from 2002 Prentice Hall PTRweek3-2

Topics

Previous:– Transistor as switch– Basic fabrication steps.

Basic Transistor function Basic transistor behavior.

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Transistor structure

n-type transistor:

Modern VLSI Design 3e: Chapter 2 Partly from 2002 Prentice Hall PTRweek3-4

Gate voltage and the channel

gate

drainsource

Id

gate

drainsource

Vgs > = Vt

Vgs < Vt

Vt= 0.7 V

Vs=0 V

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Drain current characteristics

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Example 1

V gs keeps 1.5V, 2.5V, 5V V ds changes

Modern VLSI Design 3e: Chapter 2 Partly from 2002 Prentice Hall PTRweek3-7

Drain current

Linear region (Vds < Vgs - Vt): !!!– Id = k’ (W/L)[(Vgs - Vt)Vds - 0.5 Vds

2)]

Saturation region (Vds >= Vgs - Vt):– Id = 0.5k’ (W/L)(Vgs - Vt) 2

Text book is wrong!!!

Modern VLSI Design 3e: Chapter 2 Partly from 2002 Prentice Hall PTRweek3-8

What is related to the characteristics

W/L ratio!!! V between Drain and Source V between Gate and Source Threshold voltage Material

Modern VLSI Design 3e: Chapter 2 Partly from 2002 Prentice Hall PTRweek3-9

Transistor layout

n-type (tubs may vary):

w

L

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0.5 m transconductances

From a MOSIS process: n-type:

– kn’ = 73 A/V2

– Vtn = 0.7 V p-type:

– kp’ = 21 A/V2

– Vtp = -0.8 V

Modern VLSI Design 3e: Chapter 2 Partly from 2002 Prentice Hall PTRweek3-11

Current through a transistor

Use 0.5 m parameters. Let W/L = 3/2. Measure at boundary between linear and saturation regions.

Vgs = 2V:Id = 0.5k’(W/L)(Vgs-Vt)2= 93 A

Vgs = 5V:Id = 1 mA

Modern VLSI Design 3e: Chapter 2 Partly from 2002 Prentice Hall PTRweek3-12

Explanation

When V gs = 2V, can current go beyond 93 uA (when V ds changes)?

Modern VLSI Design 3e: Chapter 2 Partly from 2002 Prentice Hall PTRweek3-13

Example 2

When Vgs = 2 V and V ds = 2 V and 1.2 V respectively, calculate the I ds?– W/L = 8– K’n= 73 uA/V^2

Modern VLSI Design 3e: Chapter 2 Partly from 2002 Prentice Hall PTRweek3-14

Example 3

Inverter: when transition time, what is the current? (important example)– How N and P work?

Inverter: after transition time, what is the current?

Modern VLSI Design 3e: Chapter 2 Partly from 2002 Prentice Hall PTRweek3-15

Questions

What is the real carrier in N transistor?

Modern VLSI Design 3e: Chapter 2 Partly from 2002 Prentice Hall PTRweek3-16

Gate voltage and the channel

gate

drainsource

Id

gate

drainsource

Vgs > = Vt

Vgs < Vt

Vt= -0.8 V

Vs=5 V

Modern VLSI Design 3e: Chapter 2 Partly from 2002 Prentice Hall PTRweek3-17

Questions

What is the real carrier in P transistor?

Modern VLSI Design 3e: Chapter 2 Partly from 2002 Prentice Hall PTRweek3-18

Transistor and digital Logic

Combinational logic– Depend on transistor & inverter

Sequential logic– Depend on transistor & inverter

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Drain current characteristics

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Review

N and P transistors as switches

Fabrication process

Current Characteristics of N and P transistors

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Example 4

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Lecture 9

Transistor Parasitics & Latch Up

Jan. 24, 2003

Modern VLSI Design 3e: Chapter 2 Partly from 2002 Prentice Hall PTRweek3-23

Topics

Transistor and basic fabrication steps. Basic Transistor function Basic transistor behavior. Latch up.

Modern VLSI Design 3e: Chapter 2 Partly from 2002 Prentice Hall PTRweek3-24

Basic transistor parasitics

Gate to substrate, also gate to source/drain. Source/drain capacitance, resistance.

Modern VLSI Design 3e: Chapter 2 Partly from 2002 Prentice Hall PTRweek3-25

Basic transistor capacitance

Gate capacitance Cg. Determined by active area.

Source/drain overlap capacitances Cgs, Cgd. Determined by source/gate and drain/gate overlaps. Independent of transistor L.– Cgs = Col W

Gate/bulk overlap capacitance.

Modern VLSI Design 3e: Chapter 2 Partly from 2002 Prentice Hall PTRweek3-26

Transistor gate capacitance

Gate-source/drain overlap capacitance:

gate

source drain

overlap

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Transistor source/drain parasitics

Source/drain have significant capacitance, resistance.

Measured same way as for wires. Source/drain R, C may be included in Spice

model rather than as separate parasitics.

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Transistor Resistance

R=U/I Future topic

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Latch-up

CMOS ICs have parasitic silicon-controlled rectifiers (SCRs).

When powered up, SCRs can turn on, creating low-resistance path from power to ground. Current can destroy chip.

Early CMOS problem. Can be solved with proper circuit/layout structures.

Modern VLSI Design 3e: Chapter 2 Partly from 2002 Prentice Hall PTRweek3-30

Parasitic SCR

circuit I-V behavior

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Parasitic SCR structure

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Solution to latch-up

Use tub ties to connect tub to power rail. Use enough to create low-voltage connection.

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Tub tie layout

metal (VDD)

p-tub

p+

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Question

Why these tub ties are needed?

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