MODERN Final Review ENIAC-120003 MODERN Ref. Technical Annex MODERN_PartB Rev2 v3.7

MODERN Final Review ENIAC-120003 MODERN Ref. Technical Annex MODERN_PartB Rev2 v3.7

WP1: Giuliana Gangemi WP2: André Juge

WP3: Wilmar Heuvelman WP4: Davide Pandini / Fabio Campi

WP5: Loris Vendrame

Coordinator: Jan van Gerwen

Date: May 3rd, 2012

CONFIDENTIAL 2MODERN Final Review May 3rd, 2012

Agenda (1)Welcome

General information (Jan)– Objectives– Consortium– Resources planned and used– Overview of deliverables and milestones status– Cooperation, dissemination and exploitation– Project management: progress, problems and amendments– Relationship between workpackages– Other issues, Q&A

For WP1 (Giuliana), WP2 (André), WP3 (Wilmar) and WP4 (Davide / Fabio )– Link with other WPs and Tasks– Progress, highlights and lowlights– Technical status and achievements of deliverables (incl. changes)– Cooperation– Dissemination (publications, patents), exploitation– Other issues, Q&A


Agenda (2)

For WP5 (Loris and others)– Link with other WPs and Tasks– Progress, highlights and lowlights– Technical status and achievements of deliverables (incl. changes)– Cooperation– Dissemination (publications, patents), exploitation– Demo’s:

• Thales: Philippe Millet / Simon Heywood• …..

– Other issues, Q&A


Objectives

The objective of the MODERN project is to develop new paradigms in integrated circuit design that will enable the manufacturing of reliable, low cost, low EMI, high-yield complex products using unreliable and variable devices.

Specifically, the main goals of the project are: Advanced, yet accurate, models of process variations for

nanometre devices, circuits and complex architectures. Effective methods for evaluating the impact of process variations

on manufacturability, design reliability and circuit performance. oReliability, noise, EMC/EMI.oTiming, power and yield.

Design methods and tools to mitigate or tolerate the effects of process variations on those quantities applicable at the device, circuit and architectural levels.

Validation of the modelling and design methods and tools on a variety of silicon demonstrators.

1

23 4 5

Layout and strain induced variability (Synopsys)


Consortium

The MODERN Consortium features strong competence and expertise in the field of advanced technologies, with a well-balanced participation between Large Industries, SMEs, Research Centres and Universities from all over Europe.


Resources planned and used

Work

Package

Title

38 1 5 4 6 20 251 3 5 5 6 30 238 1 5 4 6 20 258 5 5 6 6 30 6

381 12 54 46 44 17 26 48 12 39 6 7 12 59566 13 54 48 60 24 25 48 18 48 10 32 12 174381 12 54 46 44 17 26 48 12 39 6 7 12 59639 19 54 84 60 24 42 48 18 48 23 32 12 174619 40 12 24 11 244 46 78 61 20 16 15 5 27 20687 36 12 24 27 204 66 102 108 18 16 15 12 27 20619 40 12 24 11 244 46 78 61 20 16 15 5 27 20695 36 13 24 27 204 66 102 108 18 23 15 12 27 20565 35 24 12 144 31 30 15 22 78 36 79 16 42553 66 36 12 78 31 30 16 36 72 60 58 16 42565 35 24 12 144 31 30 15 22 78 36 79 16 42570 66 36 12 78 36 30 21 36 72 60 58 23 42315 10 75 8 6 75 73 7 0 14 32 16242 14 63 8 3 54 24 10 0 12 38 16315 10 75 8 6 75 73 7 0 14 32 16274 14 63 19 6 54 24 10 18 12 38 16103 1 4 5 2 6 2 2 2 2 48 10 0 2 2 1 3 3 7100 2 6 5 2 6 6 2 2 3 30 12 3 6 2 1 3 3 6103 1 4 5 2 6 2 2 2 2 48 10 0 2 2 1 3 3 7110 5 6 5 2 6 6 2 2 6 30 12 3 6 2 4 3 3 6

2,020 35 24 28 12 125 56 46 150 46 69 56 63 421 80 298 14 40 96 61 20 32 7 33 30 64 30 852,199 66 32 42 12 109 56 48 84 66 77 56 79 342 120 288 23 68 72 108 18 38 32 33 30 186 30 842,020 35 24 28 12 125 56 46 150 46 69 56 63 421 80 298 14 40 96 61 20 32 7 33 30 64 30 852,346 66 43 42 12 109 56 84 84 66 95 56 108 342 120 288 36 90 72 108 18 38 32 50 30 186 30 84

'(*) NOT FUNDED IN ITALY

WP3

2. A

ustr

iaM

icro

syst

ems

AG

3. C

SE

M

4. E

last

ix (

▼pe

r 30

-6-1

1)PERIOD: m1 to m36

Actual total

TO

TA

LS

TOTAL

Actual totalPlan total

Cum. Act. totalCum. Plan total

31. U

nive

rsita

t Pol

itecn

ica

de C

atal

unya

WP4

Architectural to system level:

modeling, analysis, and

Cum.Plan total

Planned total

WP1

Target technologies,

application domains,

WP2

Process/device to compact modeling

Cum. Act. total

Physical/circuit to RT-level: PV-aware and PV-

robust

Actual totalPlanned total

Planned total

Cum. Act. totalCum.Plan total

22. T

IEM

PO

SA

S

21. T

hale

s S

A

28. U

nive

rsity

of C

alab

ria

29. T

he U

nive

rsity

of G

lasg

ow

23. D

elft

Uni

vers

ity

24. E

indh

oven

Uni

vers

ity

25. G

raz

Uni

vers

ity

27. A

lma

Mat

er S

tudi

orum

26. V

ienn

a U

nive

rsity

16. (

Coo

rdin

ator

) N

XP

-NL

18. P

olite

cnic

o di

Tor

ino

19. S

TM

icro

elec

tron

ics

S.r

.l.

20. S

ynop

sys

Sw

itzer

land

LLC

12. C

EA

-LE

TI

13. M

ontp

ellie

r La

bora

tory

15. M

icro

n / N

umon

yx

8. IM

EP

-LA

HC

Lab

orat

ory

TABLE 3. PERSON-MONTH STATUS TABLECONTRACT N°: 120003ACRONYM: MODERN

WP5

Test structures and

demonstrators Cum. Act. total

Cum.Plan total

Actual totalPlanned total

Cum. Act. totalCum.Plan total

Planned total10

. Int

egra

ted

Sys

tem

Dev

elop

men

t SA

Cum.Plan total11

. Con

sorz

io N

azio

nale

version: 3.1 (17-04-2012)

WP6

Management, dissemination

and exploitation

Planned totalCum. Act. total

Partner - Person-month per Workpackage

Cum.Plan total

Actual total

1. S

TM

icro

elec

tron

ics

(Gre

nobl

e2)

SA

S

9. S

TM

icro

elec

tron

ics

SA

S

Actual total

5. T

ekla

tech

Actual total

30. S

apie

nza

Uni

vers

ita d

e R

oma

Cum. Act. total

6. In

tel M

C (

Infin

eon)


Overview of deliverables and milestones status (1)DeliverablesDel. no. Deliverable name WP no. Task

leadNature Dissemin

ationlevel

Delivery date(proj.

month)

Contributors (lead)

Actual / Forecast

delivery date

Delivered

D1.3 Integration Specifications 1 ST-I R PP M18 ST-I, AMS, IFXA, NMX, NXP, THL

09/12/10 Yes

D2.1.1 First version of process simulator including treatment of PV for mainstream CMOS technologies, and Discrete Power Device,SiC,GaN/AlGaN technologies, interfaced to commercial TCAD tools

2 ST-I R CO M15 ST-I, AMS, TUW

15/06/10 yes

D2.2.3 Device simulation analysis of dominant variability sources in state-of-the-art Non-Volatile-Memory technologies

2 UNGL R CO M18 UNET, UNGL, NMX, SNPS

14/10/10 Yes

D2.3.2 Characterization of major sources of PV in SiC technologies/devices, and AlGaN/GaN HEMT devices.Report on 1/f noise dispersion behavior in 45nm bulk CMOS

2 NXP R CO M18 ST-I, NXP 23/11/10 Yes

D2.5.1 PV-aware circuit-level models for standard CMOS technologies (down to 45nm), and Non-Volatile-Memory technologies. State-of-the-art based statistical models, based on hardware and/or TCAD.

2 UNET R CO M18 UNGL, UNET, NXP, POLI, ST-I, STF2, NMX

20/10/10 Yes

D5.1.2 Design of test structures for analog design parameter monitoring

5 AMS R CO M18 TUGI, AMS 28/09/10 Yes

D6.1.6 Semi-annual project progress report 6 NXP R CO M18 NXP, all 02/11/10 Yes

D6.2.3 First report on dissemination activities 6 UNET R CO M18 ST-I, all 10/01/11 Yes

D6.2.4 First update of public part of the project web-site 6 UNET D PU M18 ST-I 11/10/10 Yes

D6.3.1 Dissemination and use plan (first version) 6 NXP R CO M18 UNET, NXP, all

11/10/10 Yes


Overview of deliverables and milestones status (2)Milestones

Milestone number

Milestone name Work package(s)

involved

Expected date (proj.

month)

Actual / Forecast

delivery date

Achieved Means of verification

M2.1 PV aware compact models available for bulk planar CMOS technologies down to 45nm, TCAD/hardware based

2 M18 20/10/10 Yes D2.1.1, D2.2.2, D2.3.1, D2.5.1

M2.2 Identification and description of major PV sources in non-foundry mainstream logic technologies, cross-technology- fertilization

2 M21 23/11/10 Yes D2.2.3D2.3.1/ D2.3.2D2.5.1

M6.2 Second project review by ENIAC all M14 29/06/10 Yes Reviewer’s feedback

Conclusion:

All Deliverables and Milestones due before 31-12-2010 (M22) are ready

M24 Deliverables and Milestones are on schedule


Cooperation, dissemination and exploitation

A Workshop at DATE 2010 with the theme ‘The Fruits of Variability Research in Europe’ was organized. This workshop was a co-operation of the UK EPSRC project, FP7 STREP project REALITY and MODERN

VARI Workshop, 2010 May 26-27, Montpellier, France

Contribution to the Workshop on Simulation and Characterisation of Statistical CMOS Variability and Reliability was presented, Sept. 9th 2010, Bologna, Italy

MODERN participated in the Poster & Demo Session at European Nanoelectronics Forum 2010 in Madrid, Spain

Large number of publications

Main meetings:– General meetings in Catania (Nov. 9&10, 2010) attended by 30+ persons

present and 10+ called in

Due to the travel restrictions that many companies/institutes still face most of the interaction between partners is by phone and email


Project management: progress, funding problems and amendments

Progress: All planned deliverables ready

Most uncertainties in countries causing funding and (national) administrative issues e.g. Italy, Swiss, Spain and Austria are resolved

Amendments:1. The change of project coordinator from ST to NXP and ST-Crolles being

replaced by ST-Grenoble2. The removal of some inconsistencies between some deliverables3. The subcontracting of work by Glasgow to GSS Ltd.4. CSEM withdraws due to lack of national funding as of 29-06-20105. To account for the leaving of some NXP employees and a related change

in direction of the NXP PDM group the deliverables D5.3.2 and D5.3.3 are (slightly) changed

6. To account for some technical difficulties encountered in the research activities within ST-I Tasks 3.1, 3.4 and 5.3 are (slightly) changed

7. Coming: partner #6 Infineon Technologies Austria AG is included in the transaction between Infineon and Intel


Relationship between workpackages


Other issues Q&A

?


WP1 agenda

Link with other WPs and Tasks

Progress, highlights and lowlights

Technical status and achievements of deliverables (incl. changes)

Cooperation

Dissemination (publications, patents), exploitation

Other issues, Q&A


WP2 agenda




Cooperation


Other issues, Q&A

CONFIDENTIAL

WP3 agenda




Cooperation


Other issues, Q&A

17MODERN Final Review May 3rd, 2012

CONFIDENTIAL

WP4: Outline




Cooperation


Other issues, Q&A


CONFIDENTIAL

WP5 agenda




Cooperation


Demo’s:– Thales: Philippe Millet / Simon Heywood– …..

Other issues, Q&A


MODERN Final Review ENIAC-120003 MODERN Ref. Technical Annex MODERN_PartB Rev2 v3.7

Documents

Transcript of MODERN Final Review ENIAC-120003 MODERN Ref. Technical Annex MODERN_PartB Rev2 v3.7