MODELS FOR LARGE INTEGRATED CIRCUITS - Springer978-1-4613-1555-1/1.pdf · 12.1 Appendix 3.1:...
Transcript of MODELS FOR LARGE INTEGRATED CIRCUITS - Springer978-1-4613-1555-1/1.pdf · 12.1 Appendix 3.1:...
THE KLUWER INTERNATIONAL SERIES IN ENGINEERING AND COMPUTER SCIENCE
VLSI, COMPUTER ARCHITECTURE AND DIGITAL SIGNAL PROCESSING
Consulting Editor Jonathan Allen
Otber books In tbe series:
Adaptive Filters: Structures, Algorithms, and Applications. M.L. Honig and D.O. Messerscbmitt. ISBN 0-89838-163-0.
Introduction to VLSI Silicon Devices: Physics, Technology and Characterization. B. EI-Kareh and R.J. Bombard. ISBN 0-89838-210-6.
Latchup in CMOS Technology: The Problem and Its Cure. R.R. Troutman. ISBN 0-89838-215-7. Digital CMOS Circuit Design. M. Annaratone. ISBN 0-89838-224-6. The Bounding Approach to VLSI Circuit Simulation. C.A. Zukowski. ISBN 0-89838-176-2. Multi-Level Simulation for VLSI Design. D.D. Hill and D.R. Coelho. ISBN 0-89838-184-3. Relaxation Techniquesfor the Simulation of VLSI Circuits. J. White and A. Sangiovanni-Vincentelli.
ISBN 0-89838-186-X. VLSI CAD Tools and Applications. W. Fichtner and M. Morf, Editors. ISBN 0-89838-193-2. A VLSI Architecture for Concurrent Data Structures. W.J. Dally. ISBN 0-89838-235-1. Yield Simulation for Integrated Circuits. D.M.H. Walker. ISBN 0-89838-244-0. VLSI Specification, Verification and Synthesis. o. Birtwistle and P.A. Subrahmanyam.
ISBN 0-89838-246-7. Fundamentals of Computer-Aided Circuit Simulation. W.J. McCalla. ISBN 0-89838-248-3. Serial Data Computation. S.O. Smith. P.B. Denyer. ISBN 0-89838-253-X. Phonologic Parsing in Speech Recognition. K.W. Church. ISBN 0-89838-250-5. Simulated Annealing for VLSI Design. D.F. Wong. H.W. Leong. c.L. Liu. ISBN 0-89838-256-4. Polycrystalline Silicon for Integrated Circuit Applications. T. Kamins. ISBN 0-89838-259-9. FET Modeling for Circuit Simulation. D. Divekar. ISBN 0-89838-264-5. VLSI Placement and Global Routing Using Simulated Annealing. C. Sechen. ISBN 0-89838-281-5. Adaptive Filters and Equalizers. B. Mulgrew. C.F.N. Cowan. ISBN 0-89838-285-8. Computer-Aided DeSign and VLSI Device Development, Second Edition. K.M. Cham, S-Y. Oh. J.L. Moll.
K. Lee. P. Vande Voorde. D. Chin. ISBN: 0-89838-277-7. Automatic Speech Recognition. K-F. Lee. ISBN 0-89838-296-3. Speech Time-Frequency Representations. M.D. Riley. ISBN 0-89838-298-X. A Systolic Array Optimizing Compiler. M.S. Lam. ISBN: 0-89838-300-5. Algorithms and Techniques for VLSI Layout Synthesis. D. Hill. D. Shugard. J. Fishburn. K. Keutzer.
ISBN: 0-89838-301-3. Switch-Level Timing Simulation of MOS VLSI Circuits. V.B. Rao. D.V. Overhauser. T.N. Trick.
LN. Hajj. ISBN 0-89838-302-1. VLSI for Artificial Intelligence. J.O. Delgado-Frias. W.R. Moore (Editors). ISBN 0-7923-9000-8. Wafer Level Integrated Systems: Implementation Issues. S.K. Tewksbury. ISBN 0-7923-9006-7. The Annealing Algorithm. R.H.J.M. Otten & L.P.P.P. van Oinneken. ISBN 0-7923-9022-9. VHDL: Hardware Description and Design. R. Lipsett. C. Schaefer and C. Ussery. ISBN 0-7923-9030-X. The VHDL Handbook. D. Coelho. ISBN 0-7923-9031-8. Unified Methods for VLSI Simulation and Test Generation. K.T. Cheng and V.D. Agrawal.
ISBN 0-7923-9025-3. ASIC System DeSign with VHDL: A Paradigm. S.S. Leung and M.A. Shanblatt. ISBN 0-7923-9032-6., BiCMOS Technology and Applications. A.R. Alvarez (Editor). ISBN 0-7923-9033-4. Nonlinear Digital Filters: Principles and Applications. 1. Pitas and A.N. Venetsanopoulos.
ISBN 0-7923-9049-0. Algorithmic and Register-Transfer Level Synthesis: The System Architect's Workbench. D.E. Thomas.
E.D. Lagnese. R.A. Walker. J.A. Nestor. J.V. Rajan. R.L. Blackburn. ISBN 0-7923-9053-9. VLSI Design for Manufacturing: Yield Enhancement. S.W. Director. W. Maly. A.J. Strojwas.
ISBN 0-7923-9053-7. Testing and Reliable Design of CMOS Circuits. N .K. Jha. S. Kundu. ISBN 0-7923-9056-3. Hierarchical Modeling for VLSI Circuit Testing. D. Bhattacharya. J.P. Hayes. ISBN 0-7923-9058-X. Introduction to Analog VLSI Design Automation. M. Ismail. J. Franca. ISBN 0-7923-9071-7. Steady-State Methods for Simulating Analog and Microwave Circuits. K. Kundert.
A. Sangiovanni-Vincentelli. J. White. ISBN 0-7923-9069-5. Principles of VLSI System Planning: A Framework for Conceptual Design. A.M. Dewey. S.W. Director.
ISBN 0-7923-9102-0. Mixed-Mode Simulation. R. Saleh. A.R. Newton. ISBN 0-7923-9107-1. Automatic Programming Applied to VLSI CAD Software: A Case Study. D. Setliff. R.A. Rutenbar.
ISBN 0-7923-9112-8.
MODELS FOR LARGE INTEGRATED CIRCUITS
by
Patrick Dewilde Delft University of Technology
and
Zhen-Qiu Ning Delft University of Technology
~.
" KLUWER ACADEMIC PUBLISHERS Boston/Dordrecht/London
Dl5trlbutOf'S for North America: Kluwer Academic Publishers 101 Philip Drive Assinippi Park Norwell , Massachusetts 02061 USA
Dbtributol'5 for all other countries: Kluwer Academic Publishers Group Distribution Centre Post OUice 80_ 322 3300 AH Dordrecht, THE NETHERLANDS
Ubr:uy of Cont:rt'Sli Cataloging-in-Publication Data
Dewilde, P. Models for large integrated circuits I by Patrick Ikwilde and Zhen
-Qiu Ning. p. em. - (Kluwer international series in engineering and
computer science; 103. VLSI, computer architecture. and digital signal processing)
Includes bibliographical references and index. ISBN·IJ: 978·\·4612-8833-6 e·ISBN-U: 978·1-4613·1555-1 DOl: 10.1007/978-1-4613-1555-1 I. Metal oxide semiconductors- Mathematical models. 2. Integrated
circuits-Mathematical models. I. Ning, Zhen-Qiu. II .Title. III. Series; Kl uwer irl\ernational series in cngillecring and computer science: SEeS 103. IV. Series: Kluwer international series in enginetring and computer science. digital signal processing. TK7g71.99.M44D49 1990 621.381 '52- dc20
VLS1. computer architecture, and
Copyricbt © 1990 by Kluwer Academic Publishers Softcover reprint of the hardcover 1st edition 1990
90-4684 CIP
All righlS reserved. No part of this publi1;ation may be reproduced, stored in a retrieval system or transmitted in any form or by any means, mechanical, photocopying, recording, or otherwise, without the prior written permiSliion of the publisher, Kluwer Academic Publishers, 101 Philip Drive, Assinippi Park, Norwell, Massa1;huseltS 02061.
PREFACE
I. INTRODUCTION
1.1 Modeling of MOS Devices
1.2 Parasitic Models. . .
1.3 Background from Algebra
1.4 Background from Analysis
1.5 Overview of the Book .
CONTENTS
2. BOUNDARY VALUE PROBLEMS IN VLSI MODELING
2.1 Field Equations . . . . . . . .
2.2 Integral Equations: the MOSFET Case
2.3 Integral Equations: Parasitic Capacitance
3. GREEN'S FUNCTION FOR STRATIFIED MEDIA
3.1 Definition. . . . . . . . . . .
3.2 The Bounded Multilevel Dielectric Problem
3.3 The Unbounded Multilevel Dielectric Problem
4. GALERKIN BOUNDARY FINITE ELEMENTS
4.1 Element and Local Shape Function
4.2 An Optimal Solution . . '. .
4.3 Reduction Using Constraints
4.4 Evaluation of Green's Function Integrals
4.5 Determination of the Number of Terms Required for Green's
Function
4.6 Results and Comparisons
5. POINT COLLOCATION AND FURTHER SIMPLlFICA TlONS
5.1 Point Collocation . . . . . . . . .
5.2 Further Reduction of Point-Collocation Integrals
5.3 The Capacitance Matrix . . . . . . .
ix
1
3
6
II
22
32
39
39
42
46
53
53
54
59
71
71
74 77
83
89
90
97
97
100
104
vi
6. REDUCED MODELS. . . . . .
6.1 Preliminaries. . • . • . .
6.2 The Generalized Schur Algorithm
6.3 Approximation Theory and Error Analysis
6.4 Architectures. . . . . . .
7. HIERARCHICAL REDUCED MODELS
7.1 Two Dimensional Ordering
7.2 Hierarchical Approximants
7.3 The Sparse Inverse Approximation
8. ON THE MODELING OF A SHORT-CHANNEL MOSFET BELOW
THRESHOLD •..........
8.1 Analytical Solution of the Poisson Equation
8.2 Boundary Conditions
8.3 Discussion
9. PARASmC CAPACITANCES AND THEIR LINEAR
APPROXIMATION
9.1 Parallel Conductors
9.2 Comers
9.3 Crossing Strips
9.4 Combination of Corner and Crossing Strips
10. INTERCONNECTION RESISTANCES
10.1 Introduction . . . . . . .
10.2 Finite Element Method. . . .
10.3 The Boundary Finite Element Method
11. HYBRID FINITE ELEMENTS .
11.1 Introduction . . . . .
11.2 Direct Hybrid Field Modeling
11.3 Extension to the Poisson Case
11.4 Using a Scattered Field. .
107
107
114
123
130
137
138
141
144
147
147
151
154
157 157
163
164
166
169
169
169
178
185
185
186
192
194
12. APPENDICES . • . . . . . • . •
12.1 Appendix 3.1: Solution of Equation (3.8)
12.2 Appendix 3.2: Fourier Integral Evaluation
12.3 Appendix 4.1: Evaluation of Singular Integrals .
12.4 Appendix 4.2: Derivation of (4.41)
12.5 Appendix A.5
INDEX . . . • . . . • . •
vii
197
197
201
206
2lO
211
215
PREFACE
A modern microelectronic circuit can be compared to a large construction, a large city,
on a very small area. A memory chip, a DRAM, may have up to 64 million bit locations
on a surface of a few square centimeters. Each new generation of integrated circuits -
generations are measured by factors of four in overall complexity - requires a substantial
increase in density from the current technology, added precision, a decrease of the size of
geometric features, and an increase in the total usable surface. The microelectronic
industry has set the trend. Ultra large funds have been invested in the construction of
new plants to produce the ultra large-scale circuits with utmost precision under the most
severe conditions.
The decrease in feature size to submicrons - 0.7 micron is quickly becoming available -
does not only bring technological problems. New design problems arise as well. The
elements from which microelectronic circuits are build, transistors and interconnects,
have different shape and behave differently than before. Phenomena that could be
neglected in a four micron technology, such as the non-uniformity of the doping profile
in a transistor, or the mutual capacitance between two wires, now play an important role
in circuit design. This situation does not make the life of the electronic designer easier:
he has to take many more parasitic effects into account, up to the point that his ideal
design will not function as originally planned.
This book is about global modeling of large integrated circuits with very small,
submicron dimensions. It describes what physical effects are of importance to the
designer in such circuits, and how these effects can be captured in meaningful models.
The book presents a fundamental solution to a fundamental problem: it shows how to
obtain accurate yet reduced models for intricate physical effects in large but tight
integrated circuits. It presents the problem, develops theory, gives solutions and
evaluates their quality. The book is primarily aimed at engineers and scientists who
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study modeling, the precise behavior of VLSI or ULSI devices, who develop verification
programs, solid state engineers. Yet, it has also been written with the chip designer in
mind. By reading the book a designer will increase his knowledge of large scale physical
effects in solid state devices, and his understanding of how modeling and verification
programs work. The use of such programs is often tricky, verification results are hard to
interpret, insight in the numerics is required.
The accurate and reduced modeling of large systems is a central problem in science and
technology. The classical example is Newton's model of the planetary system, where he
replaced the action of bodies on each other by the attraction of virtual masses placed at
their center of gravity. Or take the band-model of quantum mechanics which predicts the
behavior of an electron in a lattice containing an almost infinite number of charge
carriers. The situation that we face in this book has the same flavor.
In the top layers of the wafer, a very large number of circuit components have been
diffused, implanted or deposited. All these components, and especially the interconnects
influence each other. If all these influences were taken into account, an impossibly large
model would result. On the other hand, the classical quick and dirty simple neglect of all
influences will result in hopeless inaccuracies. What is needed, is a systematic way to
deduce precise yet simple models. We are after models, not just fields distributions. The
exact value of potentials in various points is not really of importance. We want a
reduced equivalent circuit that behaves almost exactly like the original in all important
design circumstances. The complexity of the model plays an important role. Also, the
complexity of the method or algorithm that produces it. Is it possible to produce reduced
models in a systematic way? We show in the book that the answer is yes.
The book is structured as follows. We start out with an overview of the basic
mathematics that we will need and the notation that we will use. Next, we quickly come
to the heart of our subject and consider three prototype situations: sheet resistance,
transistor threshold detennination and three dimensional interwire capacitance. We
discover that in all three cases the finite element method is feasible and capable of
accurate modeling. Compared to other methods (finite difference, Fourier analysis) it is
xi
both simpler and leading to models with appealing physical properties. We shall use it as
our main working horse, with very good results. However, the FE models obtained are
still much too complex. This is due to two factors: firstly, a viable discretization of the
continuum requires a fine mesh, and secondly, the model introduces many internal
variables which may be necessary to compute the distribution of the field but are not
relevant to the model. The following chapters are therefore devoted to model reduction.
There is the fundamental question of model reduction methodology, where we present
strong, original results. Then there is the question of computational complexity, we have
obtained powerful new results as well. The overall method has been implemented in a
software package called SPACE, we show experimental results, examples and
performance figures. The last chapters of the book are devoted to generalizations and
applications to various problems.
Acknowledgements
Much of the work presented in this book is the result of an intense collaboration between
seven researchers: A. van Genderen, N. van der Meijs, H. Nelis, E. Deprettere, F.L.
Neerhoff and the authors. The work was funded partially by the Commission of the EEC
under the Esprit 991 project, by the IOP-IC program of the Dutch Ministery of Economic
Affairs under DEL 45.009 and by the STW (FOM Beleidsruimte) under DEL 77.1260.
The very supportive attitude of the program officers in these two programs, Ir. J.
Cauwenbergh, Dr. B. Geerken and Dr. C. Maessen is hereby acknowledged, as well as
that of evaluators, especially Ir. L. Nederlof and E. Roza of Philips Research Labs.
Many colleagues, fellow researchers and students have provided valuable background
information and cooperation. With respect to the material in this book we wish to
mention contributions of Prof. H. Blok of Delft University of Technology (for the theory
of chapter 9) and of Prof. H. Dym (for the material on model reduction). Without the
encouragement and friendship of our colleagues in Delft, Eindhoven, Twente, Rehovot,
Stanford, Princeton, Berkeley and the atmosphere of openness and cooperation still
existing between universities all over the world, our work would have been much more
arduous and might not have led to successful results. Last but not least we wish to
extend our gratitude to those who have helped us materially and psychologically: Mrs. C.
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Boers (secretary of the Network Theory Section at Delft University of Technology), our
wives Anne and Xiuchun, our children and many friends at large.