Microelectronics Reliability xxx (2015) xxx–xxx

MR-11730; No of Pages 9

Contents lists available at ScienceDirect

Microelectronics Reliability

j ourna l homepage: www.e lsev ie r .com/ locate /mr

Modelling the impact of refinishing processes on COTS components for use inaerospace applications

S. Stoyanov ⁎, C. BaileyComputational Mechanics and Reliability Group, Department of Mathematical Sciences, University of Greenwich, London SE10 9LS, United Kingdom

⁎ Corresponding author.E-mail addresses: s.stoyanov@gre.ac.uk (S. Stoyanov),

http://dx.doi.org/10.1016/j.microrel.2015.07.0300026-2714/© 2015 Published by Elsevier Ltd.

Please cite this article as: S. Stoyanov, C. Bapplications, Microelectronics Reliability (20

a b s t r a c t

a r t i c l e i n f o

Article history:Received 25 June 2015Received in revised form 9 July 2015Accepted 9 July 2015Available online xxxx

Keywords:Commercial off-the shelf componentsModellingRefinishingReliability

Commercial off the shelf components (COTS) are being adopted by electronic equipment manufacturers for usein aerospace applications. To ensure that these componentsmeet the quality and reliability standards, refinishingprocesses, such as hot solder dip and laser deballing/reballing, are used to replace component lead-free solderterminations with tin–lead solder. These processes provide a risk mitigation strategy against tin whiskers in-duced short circuit failures. Being an additional step to the subsequent PCB assembly process it is importantthat this additional process does not impose significant thermo-mechanical stress which can impact subsequentreliability. As part of a major study in collaboration with industry partners, process models have been developedto predict the thermo-mechanical behaviour of components when subjected to the refinishing process. Thispaper details the techniques used to provide model input data (e.g., process parameters and package geomet-ric/materials data) as well as the development and application of these modelling techniques to the refinishingprocess.

© 2015 Published by Elsevier Ltd.

1. Introduction

The use of electronic components in the aerospace industry repre-sents less than 1% of the total component market where the majority ofpackaged components are designed tomeet the requirements of the con-sumer electronics market. Hence chip and package design companies aremainly focused on thesemainmarket sectorswhich unfortunately for theaerospace industry means that packaged component designs may notmeet their full requirements. For example, at present, COTS componentsare predominantly packaged using lead-free (Pb-free) materials to com-ply with legislations and market trends [1,2]. These components areprone to tin whiskers and hence pose a major reliability risk whenassembled on printed circuit boards [3]. To address this, aerospace com-panies are using a refinishing step before board assembly to removeproblematic lead-free finishes. This is illustrated in Fig. 1.

Refinishing involves the processing of components to completelyreplace the whisker prone Pb-free tin finish with SnPb alloy, by hot sol-der dipping (HSD) or laser deballing/reballing. When all of the Pb-freefinish has been replaced (e.g., up to the package epoxy mouldingcompound or body) with SnPb alloy, typically containing 3 to 5% Pb,the part is then considered to pose no further tin whisker risk. Industrygenerally relies on GEIA-STD-005-2 and ANSI/GEIA-STD-0006 for guid-ance on mitigation techniques [4,5].

While these standards represent a useful effort to regulaterefinishing processes, it is well recognised in the industry that the

c.bailey@gre.ac.uk (C. Bailey).

ailey, Modelling the impact15), http://dx.doi.org/10.1016

data base underpinning the standard is limited and hence the standardhas to adopt a conservative tone. As experience with HSD has advancedthere emerges a view that extensive part qualification and the recom-mended qualification environments may be overly onerous and indeedpossibly damaging to some component types. Modelling approachescan contribute to a better physical understanding of potential damagemechanisms and aid safer engineering judgements while reducingrisk and cost [6,7].

Experimental and modelling studies on HSD indicate that there arepotential risks for thermo-mechanical damage due to thermal loadsthat result in thermal shock or as a result of large thermal gradients [6,8–12]. Therefore, the electronic components subjected to the refinishingprocess require careful consideration of their thermal domains. Temper-ature fields and gradients to which the IC die is exposed are of particularinterest. Assessing vulnerability of different electronic components tothermal loads from the refinishing processes requires good understand-ing of how heat propagates throughout the package, and what temper-ature fields develop as a result of a particular package design. A questionof critical importance is how the heat path from the dipped terminationsto the chip is affected by different design features related to the internalpackage structure andmaterials used. Such knowledge can help optimisethe refinishing process control and also inform on package design attri-butes that indicate greater risk of damage susceptibility.

2. Modellingmethodology and tools for assessing COTS components

A critical part of the overall modelling methodology is the gatheringof relevant model input data. These data requirements refer to process

of refinishing processes on COTS components for use in aerospace/j.microrel.2015.07.030

Fig. 1. Using COTS components for aerospace applications with a refinishing process.

2 S. Stoyanov, C. Bailey / Microelectronics Reliability xxx (2015) xxx–xxx

operational conditions aswell as geometric andmaterial characterisationdata of the simulated product. Employing tools and techniques that cangenerate relevant model input data becomes a principal requirement.Fig. 2 details a generic diagram for the modelling and assessment meth-odology showing the integration of electronic product characterisationwith finite element based simulation steps.

Using finite element analysis (FEA) software tools to set and solveengineering problems should not be seen as being exact science. Adesign engineer that uses these tools to analyse physical phenomenamust also apply a significant amount of good engineering judgement.There are many aspects in FEA where experience plays a role andhelps to avoid errors. The capabilities that different FEA software pack-ages offer vary widely. Most general purpose FEA commercial codeshave common features, including:

• Different analysis capabilities, e.g., stress analysis, heat conductionand dynamic behaviour

• Libraries of elements with different capabilities, e.g., 3D, 2D, axisym-metric, beam, plate and shell

• Material behaviour models, e.g., elastic, elastic–plastic, creep, visco-plastic and anisotropic

• Automatic mesh generation that helps in minimising labour requiredto define the finite element mesh model. Note, although this capabil-ity is usually available, in practice user input in controlling themesh isalways required.

• Range of boundary conditions and loads, e.g., point constraints to pre-vent free body motion in stress analysis, pressure, heat fluxes andfixed temperature

• Graphical pre- and post-processing environment, e.g., to plot tempera-ture contours, deformed shape, stress contours and graphs of variables.

Modern COTS components are marked with extreme diversity interms of constructional design, internal features and materials beingused. The decision for model representation is an important one. Forexample 2D models are easy to develop but less accurate than full 3Dmodels. The latter model is also more computationally expensive toundertake. The use of 3D slice-models is often found appropriatewhen a balance between complexity and simulation run times need tobe realised. This modelling approach is particularly valuable in Designfor Reliability/Robustness studies where a large number of designs ora variety of different load profiles has to be simulated, or when the

Fig. 2.Modelling methodology underpinned by component/assembly characterisa

Please cite this article as: S. Stoyanov, C. Bailey, Modelling the impactapplications, Microelectronics Reliability (2015), http://dx.doi.org/10.101

simulated material behaviour or physics are complex. For example, 3Dslice models are used to assess the solder joint fatigue reliability ofCOTS components under test and real environment conditions [13,14].Simulation of local effects can be addressed by using the global–local(or sub-modelling) approach [15–17].

Physics of Failure (PoF) reliability analysis of a component or deviceis based on the knowledge of the failuremodes andmechanisms aswellas the techniques that can be used to describe the relevant physicalprocesses in the device under certain environmental stress conditions(such as temperature changes and mechanical forces). In the reliabilityanalysis of assembled electronic components, for example, thermal–mechanical fatigue is considered a major failure mechanism. Asdiscussed above, the Finite Element method can be used to predictthe stress and thermal state aswell as the “damage” in electronics parts.

Generally, PoF lifetimemodels are obtained from experimental dataand detailed results from Finite Element simulation. For example,physic-of-failure models for failures of interconnects (i.e., wire bondand solder joints) in electronics packages such as IGBT power modulesand Ball Grid Arrays, have been developed in recent years [18–22]. Anumber of lifetimemodels with respect to different failure mechanismsin semiconductor devices, such as stress migration and corrosion, arealso developed and can be used to assess reliability [23].

The procedure of deriving lifetime models can be summarised asfollows:

• Define failure criteria• Experimentally test the device or a test specimen until failures occur• Repeat the experiment under different conditions or using geometri-cally different test specimens but the same materials. For example, inthe case of failure of wire bonds and solder joints, the same solder orwire bond materials must be used

• Build Finite Element Models that are identical in geometry and testconditions as in the tests

• For each failure site (for example chip solder, solder joint, wire bond)damage indicators are obtained using FEM. Simple analytical formulaesuch as a power law function can then be used to fit the lifetime vs.damage indicator data (stress, temperature, accumulated plasticstrain, etc.). The resulting relationship is the lifetime model

As thermo-mechanical reliability of solder interconnects is a primarypackaging issue, and also as a result of the adoptions of lead-free

tion, finite element thermo-mechanical simulations and design optimisation.

of refinishing processes on COTS components for use in aerospace6/j.microrel.2015.07.030

Fig. 3. Examples of X-ray 2D and 3D tomography imaging of the internal structure of a QFN component.

3S. Stoyanov, C. Bailey / Microelectronics Reliability xxx (2015) xxx–xxx

materials, advanced modelling and life prediction methodologies havebeen developed and used extensively in assessing component reliabilityof PCB assemblies [18–21]. The lifetime prediction methodology devel-oped by Darveaux has been particularly advanced as experimental fail-ure data for families of BGAs has been correlated to model predictionsfor solder joint crack initiation and crack propagation [18,19].

3. Gathering data for modelling

At present, most FEA work relies on assumptions for linear elasticbehaviour of most package and assembly materials. While for some ICand packaging materials this is a valid assumption, other materialsobey more complex non-linear material behaviour. A good example isthe solder alloy materials that have been extensively researched andas a result visco-plastic and creep constitutive laws in forms that canbe taken by FEA codes. Other packaging materials such as mouldingcompounds, underfills and conformal coatings are often assumed elasticalthough their true behaviour is visco-elastic. In addition, their physicalproperties vary substantially over the range of commercial products andmanufacturers. Key properties such as processing or cure temperatures,glass transition temperature, temperature dependent modulus andcoefficient of thermal expansion, among others, are rarely available.Continuing research in this area and increasing customer demands forcomprehensive and accurate material characterisation data to be sup-plied by material manufacturers is helping to address this challenge.

Technical datasheets of electronic components provide valuable in-formation and data related to outline dimensions of a component, andtypically detail operational and assembly related specifications andguidelines. A datasheet rarely details the thermal andmechanical prop-erties of the materials in the package. Even in cases where such data isprovided, material related parameters may not be comprehensivelyspecified and may not suffice as input data required for finite elementanalysis. Therefore, any tasks that require the use of modelling oftenhave to involve some additional effort on package/assembly

Fig. 4. Example of a CAD model of the internal package structure of a

Please cite this article as: S. Stoyanov, C. Bailey, Modelling the impactapplications, Microelectronics Reliability (2015), http://dx.doi.org/10.1016

characterisation. This would normally result in the use of techniquesthat are common in failure and inspection analyses but are also particu-larly suitable to gather missing model input data.

3.1. Component characterisation

The most common non-destructive methods include visual inspec-tion using optical microscopy, X-ray microscopy, scanning acousticmicroscopy, X-ray fluorescence spectroscopy, etc. Optical imaging sys-tems have the capability to provide dimensional measurements. Thisis particularly relevant when it comes to gathering geometric data andto verifying data against datasheet specifications. X-ray can be used toverify and measure dimension of internal package attributes such asdie size and location of die, lead-frame shape, bond wire alignmentand pattern of 1st level solder joints in BGA components. In anauthenticity-related analysis, X-raymicroscopy can help detect anoma-lies such asmissing bondwires and die related anomalies. In relation toFEA data requirements, X-ray microscopy can provide information onthe layout of the internal structures and can also be used tomeasure di-mensions. Examples of X-ray generated images of the internal structureof an electronic component are presented in Fig. 3.

State-of-the-art X-ray systems can be used to perform both conven-tional 2D X-ray andmore advanced 3D Computed Tomography (3D-CT)scans. X-ray computed tomography (CT) is a micro-focus based X-raytechnique. CT is arguably the best tool to investigate complex electroniccomponents such as ball grid arrays and chip-scale packages. 3D CT-scan equipment can also generate 3D CAD model of the internal struc-ture of the package. This CAD model is produced in an STL file format.This CADmodel can then be used for evaluating dimensions of the inter-nal structure of interest (note that accuracy is dependent on the resolu-tion of the CT scan). Fig. 4 shows an example a CAD model obtainedfrom the 3D CT scans.

Scanning Electron Microscopy (SEM) is a technique for viewing,imaging, and analysing the surface structures of a wide range of

LQFP component in STL file format generated from 3D CT-scan.

of refinishing processes on COTS components for use in aerospace/j.microrel.2015.07.030

Fig. 5. Example of an SEM image taken on the cross-section of a LQFP component.

4 S. Stoyanov, C. Bailey / Microelectronics Reliability xxx (2015) xxx–xxx

materials. SEM is arguably the most useful microscopy technique forelectronic component characterisation and failure analysis. In terms ofgenerating data for FEA, SEM produces images that enable digital mea-surements of dimensions, for example layer thicknesses revealed in across-sectional package surface. SEM has different variants and can beused in different ways, for example, images produced can be digital orphotographic images. The high-resolution SEM is capable of magnifyingan image in excess of 50,000 times and can resolve particles and struc-tures smaller than 10 nm. An example of an SEM image is shown in Fig. 5.

Scanning acoustic microscopy (SAM) detects anomalies in packageconstruction, and in particular the existence of defects such as popcorncracking in the moulding compounds, interfacial delamination suchas delamination between lead-frame and moulding compounds orbetween die and lead-frame, and voids in the die attach layers. Fig. 6details examples of C-mode SAM images revealing minor delaminationat the lead-frame fingers of QFP type components.

3.2. Materials characterisation

The main material identification techniques used to verify materialsand material compositions is Scanning Electronic Microscopy/EnergyDisperse Spectroscopy (SEM–EDX). Using SEM with an attachedenergy-dispersive X-ray spectrometer, it is possible to identify the ele-ments which compose a sample and to perform elemental mapping,or in other words to find out the distribution of the various elementsin a sample. Sample sizes can range from micrometre-sized particlesmounted on a smooth substrate to samples several centimetres in size.

Using these techniques we have undertaken a number of composi-tional studies of the underfill and solder ball materials found in a flip-chip ball grid array (fcBGA). In this case the study reveals that theunderfill is a polymer matrix with silica (SiO2) particles inside. SEM–

Fig. 6. Examples of CSAM generated images used to identify de

Please cite this article as: S. Stoyanov, C. Bailey, Modelling the impactapplications, Microelectronics Reliability (2015), http://dx.doi.org/10.101

EDX has also been used to characterise the solder jointmaterial compo-sition, where the study confirmed that in this case the flip-chip solderjoints (1st level solder joints in the fcBGA) are tin–lead based whilethe external second-level BGA solder balls are lead-free SnAgCu solder.Such information is very important for subsequent FEAmodelling to en-sure that correct material identification and properties are made.

It should be clear that SEM–EDX can only identify elemental compo-sition. After identifying all materials, themechanical and physical prop-erties of the materials need to be extracted from material libraries andpublished data, or alternativelymeasuredwith relevant tests for respec-tivematerial properties. Typically,most of thematerials found in today'selectronic components are fairly standard, and in particular the metalmaterial properties are well established and available. Material systemsbased on epoxies such as the moulding compound and some die attachmaterials however may vary with manufacturer and package type. Forepoxies, the nature/shape/content of filler particles and their mechani-cal and thermal properties may not be readily available in the literature.

DynamicMechanical Analysis (DMA) and Thermo-mechanical Anal-ysis (TMA) are the techniques most widely used to characterise amaterial's properties. DMA uses the application of small cyclic deforma-tion to the sample thus allowing responses of the material stress, tem-perature, frequency, etc. to be studied. Unlike DMA, TMA applies aconstant static force to the sample and measures how the materialchanges as temperature or time vary. Data from DMA is typically usedto derive the Young's modulus values for the material while coefficientof thermal expansion is obtained from TMA [24].

4. Modelling the refinishing process

Once a COTS component has been fully characterised in terms of itsgeometric construction and materials properties, then this data can beused as inputs to the process models. These models can then be usedto optimise the refinishing process parameter/controls to ensure thattemperature gradients and stress magnitudes do not affect packagereliability. The following details process models for both hot-solderdipping and laser de-balling and re-balling.

4.1. Hot solder dip for leaded components

The starting point for package vulnerability evaluation to hot solderdip loads is a good understanding of the process-induced temperaturesin the refinished components and how the heat generated inside thesecomponents transfers in their respective domains. For a given packagetype, thermal performance can vary substantially depending on thedesign of the package internal construction and the path of heat transferthrough the package leads or its body, both in heating and cooling.

A package design that may provide improved thermal performancein cooling could have poor thermo-mechanical response to the hot

lamination damage at the lead-frame of the components.

of refinishing processes on COTS components for use in aerospace6/j.microrel.2015.07.030

(b) Thermally enhanced lead-frame(a) Standard lead-frame leaded package

Molten Solder

Molten Solder

Fig. 7. Heat path from refinishing thermal load in the case of different designs for the internal structure of the leaded components.

5S. Stoyanov, C. Bailey / Microelectronics Reliability xxx (2015) xxx–xxx

solder dip process. The main concern is the amount of heat conductedinto the package from the dipped terminations. Dipping is dominatedby conduction and hence the heat flux towards package internals, andin particular to the die, can be substantial. The temperature at dielevel as well as temperature change rates must be controlled and com-plywith themanufacturers' recommendations. From thedesign point ofview, the requirements for safe hot solder dipping (HSD) are opposite tothose typically considered to ensure good thermal performance of thepackage.

Fig. 7 illustrates the two principal design differences in the context ofthe refinishing process. Package designs that follow the “standard” lead-frame construction result in less severe thermal load for the IC die com-paredwith constructionwhere one ormore leads are directly connectedto the die paddle. In the latter case, there is a direct conductive heat paththrough the metal lead-frame (typically copper, a metal with very highthermal conductivity) from the dipped in the molten solder termina-tions to the die.

Finite element thermal modelling that investigated design featuresin the context of the refinishing process is reported in reference [25].This study identifies that leaded components with very large numberof leads and respectively wire bondsmay still havemuch larger thermalresistance comparedwith componentswith a small number of leads butwith direct paths in the form of leads directly connected to the die pad-dle. Therefore, in solder dipping components with thermally enhancedlead-frames that are good for heat dissipation in operation are poten-tially more vulnerable when subjected to the refinishing process.

Fig. 8. Example of thermal responses (temperature contours, °C) of an electronic component to sof two different designs of the internal lead-frame and die paddle construction. Results visuali

Please cite this article as: S. Stoyanov, C. Bailey, Modelling the impactapplications, Microelectronics Reliability (2015), http://dx.doi.org/10.1016

Fig. 8 showsmodelling results that predict the thermal effect differencesbetween “standard” and “enhanced” lead-frame design for same pack-age construction, this being a Pentawatt component. It is evident thatthe features of the internal design can make very substantial differenceto the thermal response, and therefore can have the greatest influenceand impact on the package susceptibility to damage under refinishingloads.

A detailed thermal modelling capability for the double diprefinishing process is developed and reported in reference [7]. Themodel of the double dip refinishing process captures all individual pro-cess steps, with their respective process conditions, and generates tran-sient temperature predictions over the refinishing process duration.Process steps and respective model related conditions are provided inFig. 9 and Table 1 respectively.

A representative test chip is instrumented first with thermocouples(TC) as amethod of validating the developed thermalmodel of the HSD.A full detailed three-dimensional model of the chip is developed andtransient thermal analysis performed using ANSYS [26]. The thermalmodel of the refinishing process is found to accurately predict the ther-mal transient response of a package during re-finishing. Fig. 10 providesa reference to themodel validation outcome by showing themodel pre-diction and the experimental TC data for temperature at the centre ofthe silicon die of the test package. A detailed outline of this study andrelated discussions are available with reference [7].

Similarly, stress-based finite element models for assessing the risksfor component damage induced by the process thermal loads are also

older dipping of package leads in a 250 °Cmolten solder for 3 s. Results illustrate the effectssed over half of the package domain.

of refinishing processes on COTS components for use in aerospace/j.microrel.2015.07.030

Fig. 9. Process steps for double dip refinishing process.

6 S. Stoyanov, C. Bailey / Microelectronics Reliability xxx (2015) xxx–xxx

developed and validated. As part of this work, the failure mode ofbi-material delamination between package interfaces is studied. It wasfound that the risk of damage is influenced strongly by the design ofthe component, and in particular it depends on the thermal path fromthe solder bath to the package internals. First, stress damage limits arederived by correlating the model predictions to a set of test data gath-ered under a range of stress-promoting solder dip process conditions,i.e., longer dip times and higher solder bath temperature. Then, the de-veloped thermo-mechanical model has been validated on two differentpart constructions. As an example, Fig. 11 shows model predictions forstress contours at EMC to copper interface below and above damagelimit for a quad flat package subjected to single side solder dipping.The thermal load in this case has been elevated beyond normal solderdip process conditions (dip time and solder temperature) in order to in-duce detectable delamination damage under CSAM examination. Theimage at the right side of the figure is the CSAM result revealing delam-ination at the lead interfaces of the dipped side.

4.2. Laser deballing–reballing of BGA

For RoHS-compliant Ball Grid Arrays (BGAs), replacing thePb-free solder balls with tin–lead solder balls requires deballingand then reballing of the package. With the development andcommercialisation of laser high speed solder ball jetting equipment,the process of laser-assisted deballing and reballing of BGA compo-nents has emerged as a viable alternative to the use of conventionalreflow process.

The most attractive feature of processes that perform deballing andreballing on a ball-by-ball basis is considered to be the localised thermalimpact that the process has on the package. This has been at least the

Table 1Summary of solder dip steps with the respective mode of heat transfer and FEA model bounda

Main process step Mode of heat transfer

Pre-heating Controlled uniform forced heat convection in a pre-heateMoving package inambient enclosure

Uniform heat convection in HSD enclosure and radiation

Solder dip Conduction heat transfer for the solder dipped leads.Natural convection for the balance of the component.

Flux Conduction heat transfer for the fluxed leads. Naturalconvection for the balance of the component.

Air cooling Uniform heat convection and radiation heat loss

Water rinse Uniform forced heat convection in water

Please cite this article as: S. Stoyanov, C. Bailey, Modelling the impactapplications, Microelectronics Reliability (2015), http://dx.doi.org/10.101

perception to date. Thermal modelling of hot nitrogen deballing ofBGAs confirmed that the process causes only localised thermal effects,thus making this process a very safe choice [15,17].

A transient finite element model is used to predict the thermal andmechanical behaviours of the package including those at the vicinityof the BGA pad on which a Pb-free solder ball is removed and then alaser melted SnPb solder droplet is deposited to form a new solderball. The investigation is carried out on a representative package forthe BGA lidded type components with body size 27.0 × 27.0 mm and688 ball connections. The I/O pitch size is 1.00mmand the package sub-strate thickness is 0.75 mm. All simulations are undertaken using finiteelement analysis software ANSYS [26].

A principal finding is that first-level solder interconnects are not af-fected by the temperatures induced by the deballing–reballing process-es. The temperature front from the processed BGA substrate padpropagates laterally only as far as few adjacent pads. Therefore, a negli-gible impact on inducing thermo-mechanical stresses outside the localregion of the processed pad should be expected. In the extreme caseof direct heat path between a second-level ball and first-level solder in-terconnects the heat conducted towards the package die is still minimal.This is shown in Fig. 12. In the case of the investigated package temper-ature at the first-level interconnects increasesmarginally. Themain dis-advantage of the de-balling is the slow rate of processing but given thatthe process brings no risk of damage this may be accepted for someapplications.

Fig. 13 shows an example of model generated thermo-mechanicalpredictions for the BGA package response to the hot nitrogen deballingprocess. Temperature results are at a time of 4 s which corresponds tothe time of maximum temperature to which the ball is heated and atwhich the detachment of the ball from the BGA pad takes place. Stressmodel prediction refers to the state of the copper structure in the BGAsubstrate beneath the processed pad, before and after deballing,where regions which have undergone yielding (damage indicator) areidentified. Minimal additional yielding near the BGA is predicted as aresult of the deballing thermal load, with plastic strain level wellbelow levels of concern. A detailed outline of the results can be foundin reference [15]. A similar modelling approach is applied to the studyof the laser assisted reballing, and a similar conclusion for much local-ised thermal and stress effects is drawn [17].

In the case of laser assisted reballing, the solidification of thedroplet is also accurately modelled by accounting for the latentheat loss, and predictions on solder ball freezing times are obtained.The reballing model results show that the actual process takes placeover amillisecond time range. The droplet occupies the pad area almostinstantaneously and in the case of a 500 °C initial temperature it takesabout 6–7 ms to trigger the solidification process. The solder ball solid-ifies after 36 ms, timed from its initial impact with the pad. Transientstates of the solidification of the deposited solder droplet are shownin Fig. 14.

ry conditions.

Model boundary conditions

r Imposed temperature profile at the external package surfaceRadiation and convection at ambient temperature for the entire externalboundary of the component.Molten solder temperature at the boundary of the solder dipped leads.Natural convection at ambient temperature for the balance of thecomponent.Flux temperature at the boundary of the fluxed leads. Natural convection atambient temperature for the balance of the component.Natural or forced convection at air cool temperature for the entire externalboundary of the component, and heat transfer due to radiation.Forced convection at air agitated water for the entire external boundary ofthe component.

of refinishing processes on COTS components for use in aerospace6/j.microrel.2015.07.030

Fig. 10. Model and thermocouple temperature at die centre of a test QFP subjected to the double dip refinishing process.[7]

7S. Stoyanov, C. Bailey / Microelectronics Reliability xxx (2015) xxx–xxx

5. Future challenges

The need of ruggedisation of COTS component intended for aero-space applications, and in-depth understanding of the possible implica-tions for subsequent performance and reliability, is only one challengethat the industry faces. Subsequent PCB assembly of COTS components,possible use of conformal coatings as an additional whisker mitigationstrategy, and finally qualification/reliability testing all impose theirown challenges and own risks for quality and reliability [16]. Thermo-mechanicalmodelling has the potential to generate valuable knowledgeon the effects of the respective assembly process and test/operationalconditions on COTS-based aerospace assemblies, and hence enable in-formed decision related to design, component selection and equipmentemployment in the field, but some new advances to improve accuracyare still required. In particular, the methodology of linking processmodels for COTS refinishing into PCB assemblymodels and then into re-liability prediction models can enable a more realistic model-based as-sessment approach to quality and reliability of COTS packages inaerospace equipment.

Newdevelopments in electronicsmaterials, for example sintered sil-ver interconnections and green moulding compounds, are emerging allthe time and such materials are adopted more often in new packagesand board assembly. The characterisation and impact of thesematerialson component performance and reliability are not always sufficientlyassessed. Modelling is to play an important role, along with other tech-niques, in assessing and understanding how these new materials be-have. This will require development of suitable material models that

10 MPa

Fig. 11. Comparison of FEA stress contours, above and below the damage limit, at EMC to cointerfaces of the dipped side.

Please cite this article as: S. Stoyanov, C. Bailey, Modelling the impactapplications, Microelectronics Reliability (2015), http://dx.doi.org/10.1016

can then be used in FEAmodelling evaluations. The demand for physicsof failure model predictions will continue to grow. Accurate predictivemodels for assessing the impact of combination loads as seen in thereal operational environment of the equipment are also needed.

6. Conclusions

Refinishing processes for COTS are now being used widely to miti-gate the risk of tin whiskers. This process at present is predominantlyused for leaded componentswhich are believed to havemore robust re-sponses to the thermal shock induced by the solder bath through thedipped package leads. Advanced thermal and thermo-mechanicalmodels for hot solder dipping have been demonstrated and validated.Modelling of the effect of hot solder dip loads has shown that basedon the component design and internal structure, components mayhave very different susceptibility to thermo-mechanical damage.Modelling results for temperature and stress confirmed that leadedcomponents with a direct heat path through the lead frame to thecentral paddle are more vulnerable.

Modelling can be used to optimise the refinishing process by fullyunderstanding the rates of temperature change in the package (assessif this is within the manufacturers' limits) and stress evolution in thepackage (can it lead to stress related problems that will impact reliabil-ity?). Such model predictions can inform on package attributes andtheir respective values that can be used to provide initial vulnerabilityassessment of a component. Laser assisted refinishing processes fordeballing and reballing of BGAs are found to have very localised thermal

Thermal Load Illustration

pper leads (dipped side) interfaces and CSAM result revealing delamination at the lead

of refinishing processes on COTS components for use in aerospace/j.microrel.2015.07.030

Fig. 12. Temperature graphs over vacuumde-balling (left) and laser reballing (right) processing times at four different locations defined along the shortest copper path from second-levelBFA ball to a first-level BGA solder joint.

Global Thermal ModelTemperature predictions (°C)

Local Thermal ModelTemperature predictions (°C)

Local Stress ModelPlastic yielding regions in BGA substrate copper structure

Before deballing (post manufacture residual state)

After de-balling

Plastic yielding No plastic yielding

BGA substrate copper structure

Fig. 13. Thermo-mechanical predictions for temperature andplastic strain in the BGApackage. Localmodel results focus on behaviour in the vicinity of the processedBGApad, and theBGAsubstrate structure beneath.

8 S. Stoyanov, C. Bailey / Microelectronics Reliability xxx (2015) xxx–xxx

Please cite this article as: S. Stoyanov, C. Bailey, Modelling the impact of refinishing processes on COTS components for use in aerospaceapplications, Microelectronics Reliability (2015), http://dx.doi.org/10.1016/j.microrel.2015.07.030

Fig. 14. The solidification process for the BGAmodern solder droplet. Initial solder droplet temperature upon impact on BGA pad is 500 °C. Solder volume assumed results in formed solderball with a diameter of 0.6 mm.

9S. Stoyanov, C. Bailey / Microelectronics Reliability xxx (2015) xxx–xxx

and stress effects on this family of leadless components. Future model-ling challenges relate to linking process models for COTS componentruggedisation to models of reflow process and reliability.

Acknowledgements

The authors acknowledge the contributions made by MicrossComponents Ltd., Selex ES, Rolls Royce, Cassidian-EADS DeutschlandGmbH, and General Dynamics. We would particularly like to thankJohn Roulston (Scimus Solutions Ltd.) and Paul Stewart (Selex ES) forthe valuable discussions, and for their inputs to the project and overallsupport.

References

[1] European Union, Directive 2002/96/EC of the European Parliament and of theCouncil of 27 January 2003 on waste of electrical and electronic equipment, Off. J.Eur. Union (February 13, 2003) (p. L37/24-L37/38).

[2] European Union, Directive 2002/95/EC/of the European Parliament and of theCouncil of 27 January 2003 on the restriction of the use of certain hazardoussubstances in electrical and electronic equipment, Off. J. Eur. Union (February 13,2003) (p. L37/19-L37/23).

[3] D. Pinsky, M. Osterman, S. Ganesan, Tin whiskering risk factors, IEEE Trans. Compon.Packag. Technol. 27 (2) (June 2004) 427–431.

[4] GEIA-STD-0005-2 Standard for Mitigating the Effects of Tin Whiskers in Aerospaceand High Performance Electronic Systems, 2005.

[5] ANSI/GEIA-STD-0006 Standard for Requirements for Using Solder Dip to Replace theFinish on Electronic Piece Parts, 2008.

[6] C. Bailey, S. Stoyanov, C. Best, C. Yin, M.O. Alam, P. Tollafield, P. Stewart, J. Roulston,Assessment of refinishing processes for electronic components in high reliabilityapplications, Proceedings of 15th Electronics Packaging Technology Conference(EPTC 2013). Singapore December 11–13 2013, pp. 156–161.

[7] S. Stoyanov, et al., Modelling methodology for thermal analysis of hot solder dipprocess, Microelectron. Reliab. 53 (2013) 1055–1067.

[8] S. Sengupta, et al., Assessment of thermomechanical damage of electronic parts dueto solder dipping as a postmanufacturing process, IEEE Trans. Electron. Packag.Manuf. 30 (2) (2007) 128–137.

[9] S. Mathew, et al., Assessment of solder dipping as a tin whisker mitigation strategy,IEEE Trans. CPMT 1 (6) (2011) 957–963.

[10] R. Winslow, et al., Hot solder dip and minimizing thermal gradients, Proc. IMAPSInternational Symposium, San Diego, USA October 2006, pp. 513–520.

Please cite this article as: S. Stoyanov, C. Bailey, Modelling the impactapplications, Microelectronics Reliability (2015), http://dx.doi.org/10.1016

[11] S. Meschter, S. McKeown, Effect of hot solder dipping on part stresses, Proc. of ASMEInt. Mechanical Engineering Congress and Exposition, Boston, Massachusetts, USAOct–Nov 2008, pp. 183–190.

[12] C.Y. Yin, C. Best, C. Bailey, S. Stoyanov, M.O. Alam, Statistical analysis of the impactsof refinishing process on the reliability of microelectronics components, 13thInternational Conference on Electronic Packaging Technology and High DensityPackaging (ICEPT-HDP), Guilin, China August 13–16 2012, pp. 1377–1381.

[13] B. Zahn, Solder joint fatigue life model methodology for 63Sn37Pb and95.5Sn4Ag0.5Cu materials, Proc. ECTC 2003 2003, pp. 83–94.

[14] S. Stoyanov, W. Mackay, C. Bailey, D. Jibb, C. Gregson, Lifetime assessment of elec-tronic components for high reliability aerospace applications, Proceedings of IEEE6th Electronics Packaging Technology Conference, Singapore December 8–102004, pp. 324–329.

[15] S. Stoyanov, A. Dabek, C. Bailey, Hot nitrogen deballing of ball grid arrays, Proceed-ings 37th International Spring Seminar on Electronics Technology (ISSE 2014), Dres-den, Germany May 7–11, 2014, pp. 1–6.

[16] S. Stoyanov, A. Dabek, C. Bailey, Thermo-mechanical sub-modelling of BGA com-ponents in PCB reflow, Proceedings of 36th International Spring Seminar onElectronics Technology (ISSE 2013), Alba Iulia, Romania May 8–12, 2013,pp. 253–258.

[17] S. Stoyanov, A. Dabek, C. Bailey, Thermo-mechanical impact of laser-induced solderball attach process on ball grid arrays, Proceedings of 5th Electronics System-integration Technology Conference (ESTC 2014), Helsinki, Finland September16–18, 2014, pp. 1–6.

[18] R. Darveaux, K. Banerji, A. Mawer, G. Doby, Reliability of plastic ball grid arrayassembly, in: J. Lau (Ed.), Ball Grid Array Technology, McGraw-Hill, New York1995, pp. 379–442.

[19] R. Darveaux, Effect of simulation methodology on solder joint crack growth correla-tion, Proceedings of 50th Electronic Components and Technology Conference May2000, pp. 1048–1058.

[20] A. Schubert, et al., Fatigue life models for SnAgCu and SnPb solder joints evaluatedby experiments and simulation, Proceedings of ECTC Conference 2003, pp. 603–610.

[21] A. Syed, Accumulated creep strain and energy density based thermal fatiguelife prediction models for SnAgCu solder joints, Proceedings of ECTC 2004,pp. 737–746.

[22] P. Quintero, T. Oberc, P. McCluskey, Reliability assessment of high temperature lead-free device attach technologies, Proceedings of Electronic Components and Technol-ogy Conference 2008, pp. 2131–2138.

[23] JEDEC Standard: Failure Mechanisms and Models for Semiconductor Devices,JEP122C, March 2006.

[24] M. Brown, Introduction to Thermal Analysis: Techniques and Applications, SpringerScience and Business Media, 2006.

[25] S. Stoyanov, et al., Study of impact of thermal refinishing process on reliability ofCOTS components, 20th International Workshop on Thermal Investigations of ICsand Systems; London, UK Sep 24–26 2014, pp. 1–6.

[26] ANSYS Multiphysics Documentation, www.ansys.com.

of refinishing processes on COTS components for use in aerospace/j.microrel.2015.07.030