Modeling of Substrate Depletion, Self-heating, Noise and...

Modeling of Substrate Depletion, Self-heating,Noise and High Frequency Effects in Fully

Depleted SOI MOSFETs

A Thesis Submitted

in Partial Fulfillment of the Requirements

for the Degree of

Doctor of Philosophy (Ph.D.)

by

Pragya Kushwaha

(11204073)

to the

Department of Electrical Engineering

Indian Institute of Technology Kanpur

October, 2016

CERTIFICATE

It is certified that the work contained in the thesis entitled “Modeling of Substrate Depletion,

Self-heating, Noise and High Frequency Effects in Fully Depleted SOI MOSFETs”, by

Pragya Kushwaha (Roll No. 11204073), has been carried out under my supervision and that

this work has not been submitted elsewhere for a degree.

October, 2016 Dr. Yogesh Singh Chauhan

Associate Professor,

Department of Electrical Engineering,

Indian Institute of Technology, Kanpur.

ii

SYNOPSIS

Name of the Student: Pragya Kushwaha

Roll Number: 11204073

Degree for which Submitted: Ph.D.

Department: Electrical Engineering

Thesis Title: Modeling of Substrate Depletion, Self-heating, Noise and High Frequency Ef-

fects in Fully Depleted SOI MOSFETs

Name of the Thesis Supervisor: Dr. Yogesh Singh Chauhan

Month and Year of the Submission: September, 2016

In order to facilitate high performance at low power consumption, the MOSFET size

is shrinking continuously. In sub-micron technology regime, the bulk MOSFET has started

facing severe short channel effects and excessive power dissipation. To overcome these chal-

lenges, different architectures (Fully depleted silicon on insulator and FinFET) and different

channel materials (MoS2, III-V and Graphene) are gaining momentum as viable options. In

advanced silicon nodes, fully depleted silicon on insulator (FD-SOI) and FinFET are two main

competitors. FD-SOI is a planar structure device, like the bulk MOSFET and it reduces man-

ufacturing complexities in comparison to non-planar structures (FinFET). It offers several ad-

ditional features as compared to the bulk MOSFETs: (i) complete dielectric isolation from the

substrate, resulting in lower junction leakage, capacitance, and latch-up immunity; (ii) lightly

doped/undoped silicon body provides immunity against the process induced variations; (iii)

ultra-thin buried oxide (BOX) enables threshold voltage tuning via back gate; (iv) the use of

different work-function metal gates and substrate doping allow to achieve multi-threshold fla-

vor on a single chip.

An accurate and computationally efficient compact model is required to simulate circuits

prior to the real device fabrication. Developing a compact model for FD-SOI MOSFETs is a

challenging task, due to the presence of two non-symmetric interfaces and their independent

bias conditions. Coupling between front and back gates makes the surface potential and mo-

iii

iv

bility calculations more complex. Furthermore, FD-SOI MOSFET faces carrier fluctuations

from both the interfaces which affect various device properties, especially for different back-

bias conditions. For example, carrier mobility and channel noise are dependent on interface

quality and therefore, conventional bulk MOSFET based models may not be valid for FD-SOI

MOSFETs. Another advantage of FD-SOI MOSFET includes threshold voltage tuning facility

through back-bias. However, some fraction of the applied back-gate bias drops in the substrate

region, thereby changing the effective back-bias and threshold voltage shifts. Also, the SOI

MOSFETs are more prone to self-heating due to the presence of BOX below the channel, since

SiO2 has lower thermal conductivity as compared to silicon material.

FD-SOI MOSFETs with high resistivity substrate are also attracting the radio frequency

(RF) circuit designers for high-frequency applications. However, at high frequencies, the device

characteristics have frequency dependence via several inherent phenomena, like self-heating

effect, substrate effect, and gate resistance effect. For example, the substrate resistance-induced

thermal noise gets coupled with the channel noise at high frequencies. Thus, DC compact

model is not sufficient to predict correct device behavior observed from measured data over

a wide frequency range. For a robust compact model, it is important to capture all such real

device effects.

In this thesis, we attempt to investigate and model some of the above issues. The proposed

models are developed within the framework of the BSIM-IMG model, which is the latest indus-

try standard surface potential based model for FD-SOI MOSFETs. The thesis is organized into

eight chapters as follows:

In Chapter 1, we discuss the challenges involved in CMOS scaling and also discuss the

available solutions for it, beyond 20 nm gate lengths. Benefits inherent with FD-SOI MOSFET’s

architecture are discussed in detail along with the discussion on current market survey. Then we

explain the need of compact models and finally, the basic flow chart of the BSIM-IMG model’s

working is presented.

In Chapter 2, the non-physical capacitance behavior in the BSIM-IMG 102.5 model is dis-

cussed. The origin of the issue was the assumption of constant displacement field at the back

interface, while calculating the initial guess for the front gate surface potential. In this chapter,

we propose the improved surface potential calculation for the independent double gate MOS-

FETs. The improved model is implemented in the BSIM-IMG 102.6 model, which shows

v

distinctive improvement over BSIM-IMG 102.5 model. The model shows accurate behavior for

C-V and I-V characteristics, while keeping smooth behavior for their higher order derivatives.

In independent double gate MOSFETs, the vertical electric field changes its sign according

to the front and back gate biases, which result in a non-unique relationship between electric field

and carrier distribution. In this chapter, we also develop an effective mobility model for a wide

range of back gate biases, solely dependent on technology parameters. This effective mobility

model allows the user to predict the deviation in device characteristics due to the variations in

the device structure. The model has shown good agreement with the measured data obtained

from CEA-LETI as well as with the data reported earlier in literature.

UTB-SOI MOSFETs are famous for their threshold voltage tuning facility through back-

bias. Some fraction of this applied back-bias drops in the substrate region below the BOX,

which depletes the substrate. In Chapter 3, we discuss the impact of substrate depletion on

device characteristics. We have proposed an approach to include the effect of substrate depletion

in a surface potential based compact model for UTB-SOI MOSFETs. The proposed model

is extensively verified for both NMOS and PMOS with geometrical and temperature scaling.

Model validation is done at 50 nm technology node with the state of the art UTB-SOI MOSFETs

provided by Low-power Electronics Association and Project (LEAP) and excellent agreement

with the experimental data is achieved.

Chapter 4 begins with a discussion on self-heating effect in FD-SOI MOSFETs. Higher

device heating in this MOSFET results in higher thermal resistance. From 3D TCAD simula-

tions, we observed that device thermal resistance increases further with the reduction in channel

length. The impact of geometrical scaling on the thermal resistance is investigated in this chap-

ter. A new behavioral model to capture geometrical scalability of thermal resistance is proposed

and validated against the TCAD and experimental data.

Chapter 5 explains that the flicker noise behavior in independent double gate MOSFETs is

different from bulk MOSFETs, due to presence of different interface qualities and bias con-

ditions at front and back gates, respectively. Thus, a flicker noise model dedicated to FD-SOI

MOSFETs, which can capture device behavior accurately from weak to strong inversion regions

is required. In this chapter, we have developed a physics-based unified flicker noise model for

independent double gate MOSFETs. This model predicts correct flicker noise behavior for a

wide range of the front and back gate biases. The model is validated against noise measurement

vi

data from 1 Hz to 65 kHz. The proposed model is computationally efficient and implementable

in any SPICE model for circuit simulations.

In Chapter 6, we first discuss the RF properties of the FD-SOI MOSFETs. A new RF

model capturing all the high-frequency effects is proposed. Step-by-step parameter extraction

methodology of the BSIM-IMG model is also proposed and validated against the measured S-

parameter data. The model is validated over a wide range of biases and frequencies, and shows

excellent agreement with the experimental data.

Chapter 7 contains the noise measurements for ultra-thin body and thin buried oxide (UTBB)

FD-SOI MOSFETs in the RF frequency range. We analyze the impact of front and back gate

biases on thermal noise behavior, along with the discussions on the secondary effects in FD-

SOI MOSFETs, which contribute to the thermal noise. Using calibrated TCAD simulations, we

show that the noise figure changes with the substrate doping and buried oxide thickness.

Finally, Chapter 8 summarizes the research work carried out in this thesis and also suggests

the scope of future work in this area.

Dedicated toMy late Grandparents

Acknowledgement

Above all, I thank my parents for their love and moral support. Living away from family is

not easy, but they always make me feel like they are there for me. This would not have been

possible without my parents.

I sincerely thank my supervisor, Dr. Yogesh Singh Chauhan for giving me the opportunity to

work with him. Along with my academic research activities, he continually encouraged me to

explore industrial experiences. All this is possible today, because he believed in me, more than

I believed in myself.

I am very thankful to my mother-in-law who allowed me to live my dream and to give me a

supportive husband like Harshit.

I am deeply indebted to my teachers at IIT Kanpur, especially Prof. Aloke Dutta, Prof. B.

Mazhari, Prof. S.S.K. Iyer and Prof. S. Qureshi for giving me deep insight and proper back-

ground during the course work.

I am also obliged to Prof. Chenming Hu and Dr. Sourabh Khandelwal from the University of

California Berkeley, USA for their continual feedback and technical discussions.

I am very thankful to my labmates and friends Bala Krishna, Yogendra Sahu, Avirup Dasgupta,

Chetan Dabhi, Sudip Ghosh, Girish for useful discussions. Special thanks to Chetan Gupta and

Ravi Goel as their jokes were very helpful at the time of work pressure.

I forever owe utmost gratitude to almighty GOD, whose blessings provide me faith and strength

to carry on my work.

viii

Contents

List of Figures xi

List of Abbreviations xxi

List of Symbols xxii

1 Introduction 11.1 CMOS Scaling Challenges . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.2 Alternative Solutions to Scale CMOS Further . . . . . . . . . . . . . . . . . . 3

1.2.1 Alternative Channel Materials . . . . . . . . . . . . . . . . . . . . . . 3

1.2.2 Alternative Device Architectures . . . . . . . . . . . . . . . . . . . . . 3

1.3 FinFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.4 FD-SOI MOSFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.5 Compact Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.6 The BSIM-IMG Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.7 Thesis Goals and Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2 Surface Potential and Effective Mobility Modeling in FD-SOI MOSFETs 202.1 Surface Potential Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.1.1 Improved Surface Potential Calculation . . . . . . . . . . . . . . . . . 21

2.1.2 Model Validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2.1.3 Benchmark Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

2.2 Effective Mobility in FD-SOI MOSFET . . . . . . . . . . . . . . . . . . . . . 28

2.2.1 Mobility and Threshold Voltage Extraction . . . . . . . . . . . . . . . 29

2.2.2 Proposed Effective Mobility Model . . . . . . . . . . . . . . . . . . . 33

2.2.3 Model Validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

2.3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

3 Modeling the Impact of Substrate Depletion in FD-SOI MOSFETs 413.1 Modeling of Substrate Depletion Effect . . . . . . . . . . . . . . . . . . . . . 41

3.2 TCAD Calibration Against Experimental Data . . . . . . . . . . . . . . . . . . 45

3.3 Parameter Extraction and Model Validation . . . . . . . . . . . . . . . . . . . 45

3.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

ix

CONTENTS x

4 Thermal Resistance Modeling in FD-SOI MOSFETs 634.1 Device Structure and Simulation Setup . . . . . . . . . . . . . . . . . . . . . . 64

4.2 Thermal Resistance behavior and Modeling . . . . . . . . . . . . . . . . . . . 65

4.2.1 Thermal Resistance with Length Scaling . . . . . . . . . . . . . . . . 68

4.2.2 Thermal Resistance with Width Scaling . . . . . . . . . . . . . . . . . 71

4.3 Impact of Ambient Temperature on Thermal Resistance . . . . . . . . . . . . . 72

4.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

5 A Unified Flicker Noise Model for FD-SOI MOSFETs including Back bias Effect 785.1 Proposed Flicker Noise Model . . . . . . . . . . . . . . . . . . . . . . . . . . 79

5.2 Electrical Characterization Setup . . . . . . . . . . . . . . . . . . . . . . . . . 84

5.3 Results and Discussions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

5.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

6 RF Modeling of FD-SOI MOSFETs 916.1 RF Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

6.2 RF Modeling and Parameter Extraction . . . . . . . . . . . . . . . . . . . . . 93

6.2.1 Thermal Resistance Network . . . . . . . . . . . . . . . . . . . . . . . 95

6.2.2 Substrate Parasitic Network . . . . . . . . . . . . . . . . . . . . . . . 99

6.2.3 Gate Parasitic Network . . . . . . . . . . . . . . . . . . . . . . . . . . 103

6.3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

7 Characterization of High-frequency Noise in UTBB FD-SOI MOSFETs 1097.1 Thermal noise and related parameters . . . . . . . . . . . . . . . . . . . . . . 110

7.2 TCAD Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

7.3 Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

7.4 Secondary Noise Sources in FD-SOI MOSFET . . . . . . . . . . . . . . . . . 113

7.5 Results and Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

7.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

8 Conclusion 125

A List of Publications 127A.1 Journal Papers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

A.2 Conference Papers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

List of Figures

1.1 Cross-sectional transmission electron micrograph (TEM) of Intels 32nm node p-channel

MOSFET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.2 Leakage paths in bulk architecture. These leakage current constitutes a major propor-

tion of total power consumed by the chip [9]. . . . . . . . . . . . . . . . . . . . . 2

1.3 Cross-section illustration of the double-gated bilayer graphene FET [21]. . . . . . . . 4

1.4 The FinFET is a 3D architecture which saves a larger electrical area because channel

width Wg = 2Hfin + Tfin and Wg is larger than the fin pitch. Here Hfin and Tfin are

the height and thickness of the fin [15]. . . . . . . . . . . . . . . . . . . . . . . . 4

1.5 Comparison of 3-D transistor channel profiles [29]. . . . . . . . . . . . . . . . . . 5

1.6 Comparison of electrostatic potential distributions shown in color and electric field lines

illustrated with arrows. Bias conditions are VGS = 0.75 V and VDS = 0.05 V [30]. . . 6

1.7 ST’s vision on advanced CMOS Roadmap Evolution [33]. . . . . . . . . . . . . . . 7

1.8 Smart CutTM process adapted for FD-SOI MOSFETs [39]. . . . . . . . . . . . . . . 8

1.9 (a) The 2-D constant potential contours for an SOI MOSFET is shown [40]. The 2-D

fields from the source/drain penetrate into the thick buried oxide (BOX) region which

increases SCEs. (b) Cross-sectional view of a FD-SOI device is illustrated [44]. Thin-

ning the BOX and choosing a high doping level for the back plane (BP), drastically

reduces the fringing fields and improves the DIBL. . . . . . . . . . . . . . . . . . . 9

1.10 (a) Topdown SEM picture of a 0.08 μm2 SRAM cell. (b) Butterfly curves of SRAM,

showing SNM modulation with back bias. Back bias is effective in achieving higher

SNM [40]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.11 (a) A trap rich layer underneath the buried oxide is used to freeze the parasitic surface

conduction in advanced HRSOI wafers [39]. (b) Illustration of RFSOI market trends [46]. 10

1.12 A compact model includes core and real-device models to capture device behavior ac-

curately [47]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1.13 An illustration of basic working principle of the BSIM-IMG model [49]. . . . . 11

2.1 Front-Gate Capacitance Cfgfg vs front gate voltage Vfg characteristics at Vds = 0

V, Vbg = 0 V, L = 961 nm, W = 10 μm. Fully depleted device has capacitance

in depletion and inversion region because there is no carrier when Vfg < 0V . . . 22

2.2 Comparison between previous and improved initial guess for front-gate surface

potential. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

xi

LIST OF FIGURES xii

2.3 Normalized total gate capacitance Cfgfg vs. Vfg at Vbg = 0 V. (a) NMOS device and (b)

PMOS device, with device dimensions (W = 2160 μm, L = 961 nm),(W = 3360 μm, L

= 344 nm) and (W = 4800 μm, L = 56 nm) Symbols: Data [4], Lines: the BSIM-IMG

model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

2.4 Back-bias tuning Vbg = [-1, 0, 1] V (a) Ids vs. Vfg characteristic for channel lengths L

= 961 nm. (b) Transconductance (gm) vs Vfg characteristic for channel lengths L = 961

nm. Symbols: Data [4], Lines: the BSIM-IMG model. . . . . . . . . . . . . . . . . 25

2.5 Back-bias tuning Vbg = [-1, 0, 1] V (a) Ids vs. Vfg characteristic for channel lengths L =

52 nm. (b) Transconductance (gm) vs Vfg characteristic for channel lengths L = 52 nm.

Symbols: Data [4], Lines: the BSIM-IMG model. . . . . . . . . . . . . . . . . . . 26

2.6 Benchmark Tests (a) AC source-drain charge symmetry test results with NMOS deviceWL = 10/0.052 μm. Vfg = 1.2 V, and Vbg = -0.1 V. δcsd =

(is−+id−)+(is+−id+)(is−−id−)+(is++id+) =

Css−Cdd

Css+Cdd

and its derivative vs. Vx where drain and source biases are swept in opposite direction.

(b) Gummel Symmetry Test in n channel device: Third order derivative of drain current

d3Ix/dV3

x has odd symmetry around Vds = 0 V. Vfg varies from 0 to 0.8 V in steps of

0.2 V, back-gate voltage Vbg = -1 V and drain voltage sweep is from -0.2 V to 0.2 V. . . 27

2.7 The impact of back gate bias on measured Cgc and Ids is illustrated. (a) Cgc vs Vfg

characteristic. (b) Ids vs Vfg characteristic. Back gate bias Vbg sweeps from -8 to 8 V

with the step size of 2 V. Device dimensions are: Lg = 10 μm, Wg = 50 μm, Tox = 1.2

nm, Tbox = 25 nm, TSi = 8 nm. All lines are showing measurement data. . . . . . . . 30

2.8 Photograph of 200 mm Wafer Characterization Setup from Cascade with Keysights

B1500A semiconductor device parameter analyzer. Photograph of DC probes is illus-

trated along with the snapshot of device-under-test (DUT) received from CEA-LETI.

Note: The chuck is treated as substrate terminal. Back-bias tuning is done through the

chuck. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

2.9 (a) Mobility μ vs Vfg curve, by using definition (2.13). Device dimensions are: Lg =

10 μm, Wg = 50 μm, Tox = 1.2 nm, Tbox = 25 nm, TSi = 8 nm. All lines are showing

measurement data. (b)dCgc

dVfgvs Vfg for different Vbg is illustrated. Device dimensions

are: Lg = 10 μm, Wg = 50 μm, Tox = 1.2 nm, Tbox = 25 nm, TSi = 8 nm. All lines are

showing measurement data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

2.10 Vth vs Vbg curve extracted fromdCgc

dVfgvs Vfg characteristic. Device dimensions are: Lg

= 10 μm, Wg = 50 μm, Tox = 1.2 nm, Tbox = 25 nm, TSi = 8 nm. . . . . . . . . . . . 33

2.11 (a) μeff vs Eeff behavior of FD-SOI MOSFET is illustrated. Here, α = 0.72 and β

= 1.1, U0 = 380 cm2/V-s, UA = 0.83 cm/MV and EU = 1.85. Device dimensions are:

Lg = 10 μm, Wg = 50 μm, Tox = 1.2 nm, Tbox = 25 nm, TSi = 8 nm. Black solid line:

Predictive Model, Symbols: Measurement Data. (b) μeff vs Eeff behavior of FD-SOI

MOSFET. Device dimensions are: Lg = 10 μm, Wg = 10 μm, Tox = 1.75 nm, Tbox

= 145 nm, TSi = 11 nm. Red solid line: Predictive Model, Symbols: Experimental

Data [32]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

LIST OF FIGURES xiii

3.1 (a) Schematic of a fully depleted silicon on insulator (FD-SOI) MOSFET [11]. To

have back-baising, the front side contact is used to the substrate/well [12]. A shallow

p++/n++ implant is performed below BOX to form a thin back-plane (BP) layer over

a p-type substrate. Doping level difference between the BP and silicon body is used

for a desired dynamic VT shift. (b) An illustration of four regions where the back-

gate potential drops: (i) workfunction difference between the back-gate and n+ source

junction (Δφ2), source is taken as common terminal; (ii) substrate depletion below the

BOX (Vsubdep); (iii) potential drop across the back-oxide (Vbox); (iv) back-gate surface

potential (ψs2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.2 Gamma factor γL at various gate lengths for FD-SOI at Vbg = 0 V and Vds = 0.05 V.

Symbols: TCAD Data, Line: the BSIM-IMG model. . . . . . . . . . . . . . . . . . 44

3.3 Threshold voltage shift vs. the back-gate voltage Vbg, for three NMOSs, one with a

highly doped n-type back-plane (1018cm−3) and other two with a moderately (1017cm−3)

and lightly doped (1016cm−3) n-type back-plane. The substrate depletion effect re-

duces with increase in back-plane doping. Symbols: TCAD Data, Lines: the BSIM-

IMG model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3.4 Threshold voltage shift vs. the back-gate voltage Vbg. (a) Two NMOSs, one with a

p-type back-plane BP-P and one with an n-type back-plane BP-N are shown. (b) Two

PMOSs, one with a p-type back-plane BP-P and one with an n-type back-plane BP-

N are shown. The substrate depletion effect is turned on in the model as parameter

BPFACTOR �= 0. Symbols: Data [17], Lines: the BSIM-IMG model. . . . . . . . . . 46

3.5 Case 1: For Vbg < 0 V, the substrate goes in inversion region and shifts the channel in

accumulation region which results in higher device threshold voltage. Case 2: For Vbg

� Vdd, the substrate goes in accumulation region and shifts the channel in inversion

region which results in lower device threshold voltage. Case 3: For 0 V < Vbg < Vdd,

the substrate goes in the depletion which delays the inversion in the channel. Line:

TCAD Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

3.6 Threshold voltage shift vs. the back-gate voltage Vbg, for three NMOSs with p-type

back-plane (1016cm−3), two with thick BOX (300 nm, 100 nm) and one with thin BOX

(10 nm). The substrate depletion effect increases with reduction in BOX thickness.

Symbols: TCAD Data, Lines: the BSIM-IMG model. . . . . . . . . . . . . . . . . 47

3.7 (a) Calibration of TCAD models for drift diffusion transport with experimental

data [1]. TCAD device parameters are: gate work function = 4.9 eV, source/

drain Doping = 1e20 cm−3, body doping = 1e15 cm−3, interface charge = 16e10

cm−2, source resistance = 200 Ω · μm. Device dimensions are: Channel length

Lg = 961 nm, Gate width Wg = 10 μm, Effective oxide thickness Tox = 2.4 nm,

Back gate oxide thickness Tbox = 10 nm, Channel silicon thickness Tsi = 12 nm.

(b) Drain current Ids vs front gate bias Vfg characteristics from the measurement

and calibrated TCAD simulations. Bias conditions are: Front gate voltage Vfg= 0 to 1.2 V, Back gate voltage is Vbg = 0 V, Drain voltage Vds = 0.05, 1.2 V.

Lines: TCAD data, Symbols: Measured data. . . . . . . . . . . . . . . . . . . 48

3.8 An illustration of DC parameter extraction flow in FD-SOI MOSFETs. . . . . . 49

LIST OF FIGURES xiv

3.9 Normalized total gate capacitance Cfgfg vs. Vfg at Vbg = 0.0V . (a) NMOS device and

(b) PMOS device, with device dimensions (W = 2160 μm, L = 961 nm),(W = 3360 μm,

L = 344 nm) and (W = 4800 μm, L = 56 nm) Symbols: Data [1], Lines: the BSIM-IMG

model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

3.10 (a) Threshold voltage vs. Lset characteristics for NMOS device at different back-bais

Vbg=[-1, 0, 1] V at Vds = 0.05 V and 1.5 V. (b) Threshold voltage vs. Lset characteristics

for PMOS device at different back-bais Vbg=[-1, 0, 1] V at |Vds| = 0.05 V and 1.5 V.

Dotted lines are showing that the substrate depletion effect is turned off in the model as

parameter BPFACTOR = 0. Solid lines are showing that the substrate depletion effect

is turned on in the model as parameter BPFACTOR �= 0. Symbols: Data [1], Lines: the

BSIM-IMG model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

3.11 Back-bias tuning Vbg = [-1, 0, 1] V. (a) Ids vs. Vfg characteristics for channel lengths

L = 961 nm at |Vds| = 0.05 V. (b) Transconductance (gm) vs. Vfg characteristics for

channel lengths L = 961 nm at |Vds| = 0.05 V. Symbols: Data [1], Lines: the BSIM-

IMG model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

3.12 Back-bias tuning Vbg = [-1, 0, 1] V. (a) Ids vs. Vfg characteristics for channel lengths L

= 52 nm at |Vds| = 0.05 V. (b) Transconductance (gm) vs. Vfg characteristics for channel

lengths L = 52 nm at |Vds| = 0.05 V. Symbols: Data [1], Lines: the BSIM-IMG model. 53

3.13 Back-bias tuning Vbg = [-1, 0, 1] V. (a) Second derivative of drain current gm′ vs. Vfg

characteristics for channel lengths L = 961 nm at |Vds| = 0.05 V. (b) Third derivative of

drain current gm′′ vs. Vfg characteristics for channel lengths L = 961 nm at |Vds| = 0.05

V. Symbols: Data [1], Lines: the BSIM-IMG model. . . . . . . . . . . . . . . . . . 54

3.14 (a) The drain current Ids vs. the drain voltage (Vds) for channel lengths Leff = 961 nm

at |Vfg| = 1.2 V. (b) The output conductance gds vs. Vds for channel lengths Leff = 961

nm at |Vfg| = 1.2 V. Symbols: Data [1], Lines: the BSIM-IMG model. . . . . . . . . . 55

3.15 (a) The drain current Ids vs. the drain voltage (Vds) for channel lengths Leff = 52 nm at

|Vfg| = 1.2 V. (b) The output conductance gds vs. Vds for channel lengths Leff = 52 nm

at |Vfg| = 1.2 V. Symbols: Data [1], Lines: the BSIM-IMG model. . . . . . . . . . . 56

3.16 (a) Threshold voltage vs. Lset characteristics for NMOS device at different temper-

atures T = -40, 25, 85 ◦C. (b) Threshold voltage vs. Lset characteristics for PMOS

device at different temperatures T = -40, 25, 85 ◦C. Bias conditions are: |Vds| = 0.05 V

and 1.5 V and Vbg = 0 V. Symbols: Data [1], Lines: the BSIM-IMG model. . . . . . . 57

3.17 (a) Ids vs. Vfg characteristics for L = 961 nm in logarithmic and linear scale with

temperature set at T = -40, 25, 85◦C. (b) Ids vs. Vfg characteristics for L = 52 nm in

logarithmic and linear scale with temperature set at T = -40, 25, 85◦C. Bias conditions

are: |Vds| = 0.05 V (linear mode) and Vbg = 0 V. Symbols: Data [1], Lines: the BSIM-

IMG model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

4.1 Fully Depleted Silicon On Insulator (FD-SOI) MOSFET structure using Sen-

taurus Technology Computer Aided Design (TCAD) Tool [14]. . . . . . . . . . 64

LIST OF FIGURES xv

4.2 Rth−Cth Network for modeling of Self-Heating effect [18]. Rth andCth are the

thermal resistance and capacitance of the thermal network, respectively. ΔT =TDEV ICE − TNOM is the temperature rise where TDEV ICE and TNOM are the

device and ambient temperature, respectively. P is the power dissipated (P =IdsVds) in the device where Ids and Vds are the drain current and drain voltage,

respectively [19]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

4.3 Calibration of TCAD models for drift diffusion transport with experimental data

of FD-SOI MOSFET. Device dimensions are: Channel length Lg= 52 nm, Gate

width Wg= 10 μm, Front gate oxide thickness Tox= 1.9 nm, Back gate oxide

thickness Tbox= 10 nm, Channel silicon thickness Tsi= 12 nm. Bias conditions

are: Front gate voltage Vfg= 0 to 1.1 V, Back gate voltage Vbg= 0 V, Drain

voltage Vds= 0.05, 1.2 V. Symbols: Experimental Data, Lines: TCAD Data.

Experimental Data is from LEAP Japan’s FD-SOI technology [15]. . . . . . . . 66

4.4 Device dimensions are: Lg =Wg = 10 μm. For long channel length devices, the

heat dissipates more through the substrate. Long channel length/width device

is studied to show that the self-heating effect is negligible in such MOSFETs.

Bias conditions are: Vds= 1.0 V, Vfg= 1.2 V, Vbg= 0 V. . . . . . . . . . . . . . . 66

4.5 Device dimensions are: Lg = 30 nm, Wg = 10 μm. For short channel length

devices, substrate heat dissipation becomes comparable to the top contacts dis-

sipation. Bias conditions are: Vds= 1.0 V, Vfg= 1.2 V, Vbg= 0 V. . . . . . . . . . 67

4.6 ΔT vs. power dissipation (P) normalized by gate width. For same power dissi-

pation level, short channel length device experiences more ΔT as compared to

long channel length device, indicating higher Rth. TNOM and TDEV ICE are the

ambient and device temperatures, respectively. Device dimensions are: Gate

width Wg= 10 μm, Front gate oxide thickness Tox= 1.9 nm, Back gate oxide

thickness Tbox= 10 nm, Channel silicon thickness Tsi= 12 nm. Lines: TCAD

Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

4.7 Rth variation with channel length (Lg). Rth1 = 21, RTHL = 0.0031, ΔLth =

0.07. Symbols: Experimental Data [23], Solid Line: Model. . . . . . . . . . . 68

4.8 Rth vs channel length (Lg) characteristic for NMOS and PMOS devices. The

model shows excellent agreement with the experimental data [30] for both

NMOS and PMOS devices. For NMOS parameter values are Rth1 = 2.75,

RTHL = 0.03, ΔLth = 0.24 and β = 0.78. For PMOS parameter values are

Rth1 = 2.15, RTHL = 0.03, ΔLth = 0.0748 and β = 0.5. Symbols: Data [30],

Lines: Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

4.9 Importance of parameter ΔLth in Rth modeling is illustrated. Rth vs channel

length (Lg) characteristic for NMOS device with channel width Wg = 10 μm,

oxide thickness Tox1 = 1.9 nm, buried oxide thickness Tbox = 10 nm and body

thickness Tsi = 12 nm. Parameter values are: Rth1 = 13, ΔLth = 0.170 and β= 1. Blue Line: the BSIM-IMG model without ΔLth parameter, Red Line: the

BSIM-IMG model with ΔLth parameter. . . . . . . . . . . . . . . . . . . . . 69

LIST OF FIGURES xvi

4.10 Importance of parameter RTHL in Rth modeling is illustrated. Rth vs channel

length (Lg) characteristic for NMOS device with channel width Wg = 10 μm,

oxide thickness Tox1 = 1.9 nm, buried oxide thickness Tbox = 10 nm and body

thickness Tsi = 12 nm. Parameter values are: Rth1 = 13, ΔLth = 0.170 and β= 1, α = 0.95. Symbols: TCAD Data, Lines: the BSIM-IMG model. . . . . . . 70

4.11 Rth vs channel length (Lg) characteristic for NMOS device (Tox1 = 1.9 nm, Tbox= 10 nm, Tsi = 12 nm) for different channel widths (0.1, 0.24, 0.48, 1, 5, 10

μm). Rth1 = 13, RTHL = 0.8, ΔLth = 0.170 and β = 1, α = 0.95. Symbols:

TCAD Data, Lines: the BSIM-IMG model. . . . . . . . . . . . . . . . . . . . 71

4.12 Rth vs 1/Wg characteristic for NMOS device for different channel lengths

(0.03, 0.05, 0.1, 0.5, 5, 10 μm). Rth1 = 13, RTHL = 0.8, ΔLth = 0.170 and β= 1, α = 0.95. Symbols: TCAD Data, Lines: the BSIM-IMG model. . . . . . . 72

4.13 Rth variation with ambient temperature (from −40 ◦C to 125 ◦C). Lines: TCAD

Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

4.14 Ids vs Vds characteristic with temperature set at T = −40◦C, 25◦C, 125◦C. Bias

conditions are: Vfg = 1.2 V and Vbg = 0 V. Device dimensions are: Channel

length Lg = 30 nm, Gate width Wg = 10 μm, Front gate oxide thickness Tox =

1.9 nm, Back gate oxide thickness Tbox = 10 nm, Channel silicon thickness Tsi= 12 nm. Symbols: TCAD Data, Lines: the BSIM-IMG model. . . . . . . . . . 73

5.1 A section of the transistor channel with width W and length Δx is illustrated. . . . . . 79

5.2 An illustration of flicker noise modeling in FD-SOI transistors. . . . . . . . . . . . . 80

5.3 The schematic of the electrical characterization setup used for low-frequency noise

measurements. The device under test (DUT) is having ground-signal-ground pads for

connection. The FD-SOI wafer is provided by CEA-LETI. . . . . . . . . . . . . . . 83

5.4 Electrically shielded (Faraday Cage) probe station is illustrated. (a) Outside view. (b)

Inside view. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

5.5 Impact of back bias on noise power spectral density (a) Sid vs frequency characteristics

for Vbg = -3, 0, 3 V. Device dimensions are: length Lg = 100 nm, channel width Wg =

0.5 μm, number of fingers NF = 80. (b) Sid vs frequency characteristics for Vbg = -3, 0,

3 V. Device dimensions are: length Lg = 50 nm, channel width Wg = 0.25 μm, number

of fingers NF = 80. All the devices have Tox = 1.2 nm, Tbox =25 nm and Tsi = 8 nm. . 85

5.6 (a) Sid vs Ids characteristics for different back bias. Device dimensions are: length Lg

= 100 nm, channel width Wg = 0.5 μm, number of fingers NF = 80. (b) Sid vs Idscharacteristics at Vbg = -3, 0, 3 V. Device dimensions are: length Lg = 50 nm, channel

width Wg = 0.25 μm, number of fingers NF = 80. All the devices have Tox = 1.2 nm,

Tbox =25 nm and Tsi = 8 nm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

6.1 Schematic of a fully depleted silicon on insulator (FD-SOI) transistor [2] with

the high resistivity (HR) substrate without trap rich layer below BOX. Device

dimensions are: Channel length Lg = 100 nm, Gate width Wg = 0.5μm, Num-

ber of fingers NF = 60, Front gate oxide thickness Tox = 1.2 nm, Back gate oxide

thickness Tbox = 10 nm, Channel silicon thickness Tsi = 8 nm. . . . . . . . . . . 91

LIST OF FIGURES xvii

6.2 N-channel MOSFETs for two-port RF characterization. (a) Setup picture. (b)

Picture of the actual DUT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

6.3 Photograph of experimental setup used to perform RF measurements under dif-

ferent bias conditions. Wafer is visible on chuck along with RF probes. . . . . . 93

6.4 (a) Drain current (Ids) vs. front gate voltage Vfg characteristics. (b) Trans-

conductance (gm) vs. front gate voltage Vfg characteristics for Lg = 100 nm.

Bias conditions are: Vds = 50 mV and 1.1 V, Substrate is grounded Vbg = 0 V.

Symbols: Experimental Data, Lines: BSIM-IMG model. . . . . . . . . . . . . 94

6.5 (a) Ids vs. drain voltage Vds characteristics. (b) Output conductance gds vs. drain

voltage Vds characteristics for Lg = 100 nm. Bias conditions are: Vfg = 0.9 V to

1.1 V in steps of 0.1 V, Substrate is grounded Vbg = 0 V. Thermal resistance

Rth value extracted from step 2 shown in Figure 6.15 is used here. Symbols:

Experimental Data, Lines: BSIM-IMG model. . . . . . . . . . . . . . . . . . . 95

6.6 (a) Measured and extracted real part of Y22 for Lg = 100 nm. 1st order thermal

network is used for fitting till 20 MHz range. Bias conditions are: Vfg = Vds =

1.1 V and Vbg = 0 V. Symbols: Experimental Data, Lines: BSIM-IMG model.

(b) Hot-chuck measurement result is used to determine the slope of Ids versus

temperature (T) for Lg = 100 nm, Wg = 0.5μm, NF = 60. A line is drawn to

show trend. Bias conditions are: Vfg =Vds = 1.1 V. . . . . . . . . . . . . . . . . 96

6.7 (a) Measured and extracted real part of Y22 for Lg = 100 nm. Five resistor-

capacitor substrate network is used to validate the BSIM-IMG model in the

medium frequency range. Bias conditions are: Vfg = Vds = 1.1 V and Vbg =

0 V. Symbols: Experimental Data, Lines: BSIM-IMG model. (b) Substrate

network: Five R’s and five C’s along with three capacitances (Csbox/Cdbox are

capacitances between source/drain to BOX and Cox2 is BOX capacitance.) are

used to validate the model for the wide frequency range. We have neglected

deep well junction capacitances. Gate parasitic network: Two resistors (gate

resistance Rg, gate terminal to contact-pad resistance Rc) in the series along

with front gate capacitance Cox1 are used to validate model above GHz range. . 97

6.8 Measured and simulated S-parameter: (a) Smith chart validation for S11 and

S22 for channel lengths Lg = 30 nm, 100 nm. (b) The phase of S11 and S22 for

Lg = 100 nm. Bias conditions are: Vfg = Vds = 1.1 V and Vbg = 0 V. Symbols:


6.9 Current gain |H21| variation with frequency for Lg = 100 nm. Current gain

reduces as frequency increases (| iLiin| = gm

wT ∗CGG, wT = 2 ∗ π ∗ freq). Here iL/iin

are output/input currents. Bias conditions are: Vfg = Vds = 1.1 V and Vbg = 0 V.

Symbols: Experimental Data, Lines: BSIM-IMG model. . . . . . . . . . . . . 98

LIST OF FIGURES xviii

6.10 (a) Measured and extracted imaginary part of Y11/(2π · freq) vs. front gate

voltage characteristic for Lg = 100 nm. Note that CGG can also be measured

using C-V measurements of large area devices, which is not shown here. Bias

conditions are: Vds = 0 V and Vbg = 0 V. (b) Measured and extracted imaginary

part of Y11 for Lg = 100 nm. Low frequency measured data is not shown here.

Bias conditions are: Vfg = Vds = 1.1 V and Vbg = 0 V. Symbols: Experimental

Data, Lines: BSIM-IMG model. . . . . . . . . . . . . . . . . . . . . . . . . . 99

6.11 Measured and extracted real part of H11 (gate resistance) vs frequency char-

acteristic for Lg = 100 nm. Symbols: Experimental Data, Lines: BSIM-IMG

model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

6.12 Measured and extracted real part of Y22 for Lg = 100 nm. Above GHz range,

gate resistor plays major role in predicting device behavior correctly due to its

lower time constant. Excellent fitting with experimental data shows the impor-

tance of thermal, substrate and gate networks. Bias conditions are: Vfg = Vds =

1.1 V and Vbg = 0 V. Symbols: Experimental Data, Lines: BSIM-IMG model. . 100

6.13 RF Fitting results are demonstrated for two channel lengths, named as device A

and B. Device A dimensions are Lg = 30 nm, Wg = 1μm, NF = 30 and Device

B dimensions are Lg = 100 nm, Wg = 0.5μm, NF = 60. Both devices have

similar front/back gate oxide thickness and channel thickness as follows: Tox =

1.2 nm, Tbox = 10 nm, Tsi = 8 nm. (a) Real Y22 vs. frequency characteristic. (b)

The imaginary part of Y11/(2π · freq) vs. frequency characteristic. Symbols:


6.14 RF Fitting results are demonstrated for two channel lengths, named as device A

and B. Device A dimensions are Lg = 30 nm,Wg = 1μm, NF = 30 and Device B

dimensions are Lg = 100 nm, Wg = 0.5μm, NF = 60. Both devices have similar

front/back gate oxide thickness and channel thickness as follows: Tox = 1.2 nm,

Tbox = 10 nm, Tsi = 8 nm. (a) Real H11 vs. frequency characteristic. (b) |H21|vs. frequency characteristic. Symbols: Experimental Data, Lines: BSIM-IMG

model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

6.15 An illustration of RF parameter extraction flow in FD-SOI MOSFETs. . . . . . 103

7.1 Schematic of the ultra-thin body and thin buried oxide fully depleted silicon on

insulator (UTBB FD-SOI) MOSFET. The Device under test (DUT) is from 28

nm technology node fabricated at CEA-LETI. . . . . . . . . . . . . . . . . . . 110

LIST OF FIGURES xix

7.2 (a) Calibration of TCAD models for drift diffusion transport with experimental

data of FD-SOI MOSFET. TCAD device parameters are: gate work function =

4.9 eV, source/ drain Doping = 1e20 cm−3, body doping = 1e15 cm−3, interface

charge = 7e10 cm−2, source resistance = 200 Ω · μm. Device dimensions are:

Channel length Lg = 100 nm, Gate width Wg = 40 μm, Effective oxide thick-

ness Tox = 1.2 nm, Back gate oxide thickness Tbox = 25 nm, Channel silicon

thickness Tsi = 8 nm. (b) Drain current Ids vs front gate bias Vfg characteristic

for different back gate biases (Vbg) from the measurement as well as calibrated

TCAD simulations. Bias conditions are: Front gate voltage Vfg = 0 to 1.2 V,

Back gate voltages are Vbg = -3, 0, 3 V, Drain voltage Vds = 1.2 V. Symbols:

Measured Data, Lines: TCAD Data. . . . . . . . . . . . . . . . . . . . . . . . 112

7.3 (a) Bench synopsis for RF noise figure measurement. A separate DC power sup-

ply (not shown here) is used for applying back-gate bias through substrate. (b)

Photograph of the experimental setup for the noise figure measurement. Picture

of the actual DUT along with the probes is also illustrated. The noise measure-

ments were performed at IMS lab in University of Bordeaux1, France. . . . . . 113

7.4 Schematic of the substrate network showing substrate induced noise source in

FD-SOI MOSFET. Rsub is the equivalent substrate resistance while Csub is the

substrate capacitance. Vfg/Vbg are the applied front/back gate voltages and Vd/Vsare the drain/source voltages. The substrate coupling results in higher NFmin

due to Rsub induced thermal noise at the drain [20]. . . . . . . . . . . . . . . . 113

7.5 (a) NFmin vs. substrate doping characteristic. The substrate depletion and the

substrate resistance Rsub induced thermal noises also contribute to the overall

noise, creating fluctuations in NFmin. (b) NFmin vs. BOX thickness charac-

teristic. NFmin increases further with BOX thinning due to an increase in the

substrate coupled thermal noise. Line with symbol: TCAD data. . . . . . . . . 114

7.6 (a) Measured NF50 vs. frequency characteristics of different front-gate biases

Vfg = 0.8, 1, 1.2, 1.4 V. Frequency is swept from 1 to 18 GHz with the step

size of 1 GHz. The inset figure shows the NF50 vs Vfg characteristics for two

channel lengths Lg = 50, 100 nm. (b) NF50 vs. frequency characteristics for

different back-gate biases Vbg = -3, 0, 3 V. The inset figure shows the NF50 vs

Vbg characteristic for Lg = 100 nm. (c) NF50 vs. frequency characteristics for

different drain biases Vds = 1, 1.2, 1.4 V. The inset figure shows the NF50 vs

Vds characteristic for Lg = 100 nm. Device dimensions are: Wg=1 μm, NF =

40, Tox = 1.2 nm, Tbox = 25 nm, Tsi = 8 nm. . . . . . . . . . . . . . . . . . . . 115

7.7 (a) Measured NFmin vs. frequency characteristics. (b) NFmin vs. frequency

characteristics from TCAD simulations. (c) NFmin vs. frequency characteris-

tics extracted from s-parameter measurements for an FD-SOI MOSFET (Lg =

100 nm) with highly doped substrate below the BOX. Frequency is swept from

1 to 18 GHz with the step size of 0.5 GHz. Bias conditions are: Vfg = 1.2 V and

Vds = 1.2 V. Parameter values used to calculate NFmin for the device are: Rgs

= 37.47 Ω and Rn = 1.7, 2.02, 2.35 kΩ for Vbg = -3, 0, 3 V, respectively. Cgs =

Cgg - Cgd, where Cgg and Cgd are shown in Fig. 7.11b. . . . . . . . . . . . . . 116

LIST OF FIGURES xx

7.8 (a) The top figure showsGopt vs. frequency characteristics while the bottom fig-

ure shows Bopt vs. frequency characteristics, both from TCAD simulations. (b)

The top figure shows Gopt vs. frequency characteristics while the bottom figure

shows Bopt vs. frequency characteristics extracted from S-parameter measure-

ments. Bias conditions are: Vfg = 1.2 V and Vds = 1.2 V. Parameter values used

to calculate the noise parameters for Lg = 100 nm device are: Rgs = 37.47 Ωand Rn = 1.7, 2.02, 2.35 kΩ for Vbg = -3, 0, 3 V, respectively. Cgs = Cgg - Cgd,

where Cgg and Cgd are shown in Fig. 7.11b. . . . . . . . . . . . . . . . . . . . 117

7.9 (a) Measured Γopt vs. frequency characteristics. (b) Γopt vs. frequency char-

acteristics from TCAD simulations. (c) Γopt vs. frequency characteristics ex-

tracted from S-parameter measurements. Bias conditions are: Vfg = 1.2 V and

Vds = 1.2 V. Parameter values used to calculate the Γopt are: Rgs = 37.47 Ω and

Rn = 1.7, 2.02, 2.35 kΩ for Vbg = -3, 0, 3 V, respectively. Cgs = Cgg - Cgd, where

Cgg and Cgd are shown in Fig. 7.11b. . . . . . . . . . . . . . . . . . . . . . . . 118

7.10 (a) Rn vs. Vfg characteristics for different back-gate biases: Vbg = -3, 0, 3 V.

(b) Noise power spectral density Sid from TCAD simulations vs. frequency

characteristics for different back-gate biases: Vbg = -3, 0, 3 V. Bias conditions

are: Vfg = 1.2 V and Vds = 1.2 V. Device dimensions are: Lg = 100 nm, Wg=1

μm, NF = 40, Tox = 1.2 nm, Tbox = 25 nm, Tsi = 8 nm. . . . . . . . . . . . . . . 119

7.11 (a) Real part of Y21 extracted from S-parameter measurements, vs. frequency

for different back-gate biases: Vbg = -3, 0, 3 V. Inset shows gm (DC measured

data) vs. Vfg characteristics for different back-gate biases: Vbg = -3, 0, 3 V. (b)

Cgg and Cgd extracted from S-parameter measurements vs. frequency charac-

teristics for different back-gate biases: Vbg = -3, 0, 3 V. Bias conditions are: Vfg= 1.2 V and Vds = 1.2 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

List of Abbreviations

MOSFET Metal Oxide Semiconductor Field Effect Transistor

SHE Self Heating Effect

SHMOD Self-Heating Mode

BSIM Berkeley Short-Channel Insulated Gate Field-Effect Transistor Model

IMG Independent Multi Gate

FD Fully Depleted

SOI Silicon on Insulator

UTBB Ultra Thin Body and BOX

RF Radio Frequency

TCAD Technology Computer Aided Design

EOT Effective Oxide Thickness

DIBL Drain Induced Barrier Lowering

SCE Short Channel Effects

G-S-G Ground-Signal-Ground

xxi

List of Symbols

Leff Effective Channel Length

Weff Effective Channel Width

Vth Threshold Voltage

ψs1 Front-gate Surface Potential

ψs2 back-gate Surface Potential

Es1 Front-gate Surface Electric Field

Es2 Back-gate Surface Electric Field

Nc Conduction Band Density of States

Vch Channel Potential

TSi Silicon Body Thickness

Qdep Depletion Charge

Qinv Inversion Charge

Qf Front-gate Charge

Qb Back-gate Charge

φf Fermi Potential

q Electron Charge

εSi Relative Permittivity of Silicon

εox Relative Permittivity of Oxide

Nsub Substrate Doping

TDEV ICE Device Temperature

TNOM Ambient Temperature

Rth Thermal Resistance

Cth Thermal Capacitance

Ids Drain Current

Vds Drain Voltage

Sid Drain Current Noise Power Spectral Density

fT Cutoff Frequency

xxii

Chapter 1

Introduction

1.1 CMOS Scaling Challenges

Application of electronic devices in telecommunication, health care, automobile, comput-

ing and various other fields have given birth to the need of low power and high-speed devices.

About the growth of these devices, Gordon Moore (Intel co-founder) predicted that “over the

history of computing hardware, semiconductor chips would become two times powerful in ev-

ery two years at low cost, and they would ultimately be so small, that they could be embedded

in homes, cars and smartphones” [1].

Planar bulk silicon MOSFET has been the driving force behind Very Large Scale Integration

(VLSI) for high-performance computing [2]. However, the scaling of conventional planar bulk

MOSFET cannot be continued forever with the same rate as Moore’s law suggested [3]. Pla-

nar bulk silicon MOSFET transfer characteristics degrade with the gate length (Lg) reduction.

Furthermore, shrinking the gate lengths degrades the subthreshold swing (SS) and reduces the

device threshold voltage (i.e., Vth roll-off), which implies that it is difficult to switch off the

device completely. All these issues are collectively known as short channel effects (SCEs) [4].

Due to these SCEs, the device characteristics become sensitive to the gate length variation

which in turn increases process induced variability [5]. In order to reduce the SCEs, it is must

to reduce gate dielectric thickness (Tox) in proportion to Lg. The thin gate dielectric layer, how-

ever, is prone to quantum-mechanical tunneling as it increases gate leakage current [6]. High-k

dielectric with metal gate (HKMG) was introduced to solve this gate leakage issue (see Fig.

1

1.1 CMOS Scaling Challenges 2

Figure 1.1: Cross-sectional transmission electron micrograph (TEM) of Intels 32nm node p-channel

MOSFET.

Figure 1.2: Leakage paths in bulk architecture. These leakage current constitutes a major proportion of

total power consumed by the chip [9].

1.1) [7].

Below 30 nm physical gate lengths, source and drain junctions are so close that the

gate faces difficulty in keeping electrostatic control over the channel. The poor gate control

on sub-surface leakage paths (i.e., leakage paths that are far from the gate [8]), increases off-

state leakage currents as shown in Fig. 1.2. These leakage currents further increase with the

drain potential, and this is called drain induced barrier lowering (DIBL) effect [10]. These new

1.2 Alternative Solutions to Scale CMOS Further 3

challenges to Lg scaling have demanded the solutions like retrograde substrate doping profile,

shallow source/drain extensions, halo implants and strained silicon [4, 11]. Adoption of these

solutions for the scaling of planar MOSFETs make the fabrication process more complex [12].

A promising alternative to scale CMOS further is to choose new MOSFET architectures (Fully

depleted SOI (FD-SOI) [13] and FinFET [14, 15]) and different channel materials (MoS2 [16],

III-V [17] and Graphene [18]).

1.2 Alternative Solutions to Scale CMOS Further

The increasing difficulties in Si CMOS scaling has created the need of investigation of alterna-

tive channel materials and device architectures.

1.2.1 Alternative Channel Materials

New channel materials like germanium (Ge) [19] and III-V compound semiconductor [20] have

opened an era of ultra-low-power and high-speed devices. Recently, two dimensional (2D)

layered materials (bilayer graphene, bilayer MoS2) have supported field-controlled bandgap

tuning [21] (see Fig. 1.3). It gives a new platform to design new electronic and optoelectronic

devices. However, a high quality gate dielectric is required to apply large vertical electric fields

in such devices. However, such attempts for high mobility materials are facing fabrication

challenges, as these materials can support either n type (III-V compound semiconductor) or p

type (Ge) devices but not both, which are required for CMOS circuit designs.

1.2.2 Alternative Device Architectures

As the bulk silicon MOSFET scaling is reaching its practical limit, alternative architectures

to increase chip functionality are required to maintain Si revolution. In silicon technology, Fully

depleted SOI (FD-SOI) and FinFET are the two main competitors at sub-micron technology

nodes. These new device architectures have better gate electrostatics, as channel is surrounded

by the gate from multiple sides [22]. Furthermore, both structures use ultra-thin body which

1.3 FinFETs 4

Figure 1.3: Cross-section illustration of the double-gated bilayer graphene FET [21].

Figure 1.4: The FinFET is a 3D architecture which saves a larger electrical area because channel width

Wg = 2Hfin + Tfin and Wg is larger than the fin pitch. Here Hfin and Tfin are the height and thickness

of the fin [15].

eliminates the sub-surface leakage paths and, hence, unwanted leakage currents are also sup-

pressed [23]. Moreover, these architectures use undoped body which eliminates the Coulomb

and surface roughness scattering and this results in improved on-state drive current (Ion) as

compared to the bulk MOSFETs [24]. In these structures, channel doping is not required to

adjust threshold voltage. Thus, random dopant fluctuations, a major cause of process variability

in bulk MOSFETs, are eliminated [25–27].

1.3 FinFETs 5

Figure 1.5: Comparison of 3-D transistor channel profiles [29].

1.3 FinFETs

The FinFET in Fig. 1.4 is a thin-body non-planar MOSFET constructed on silicon-on-insulator

(SOI) or bulk substrate, using patterning and etching technologies. Improvement in SS (i.e.,

60 mV/decade at room temperature) and suppression in SCEs are obtained by reducing the fin

size [10]. This technology is used within Integrated Circuits (ICs) due to lower power con-

sumption. FinFET technology offers better scalability, which increases integration level within

ICs [28]. A gate-all-around (GAA) FET structure (see Fig. 1.5) provides a superior electrostatic

integrity; however, the stacked-NW GAA FET technology involves fabrication complexities,

like formation of high aspect ratio fin structure etc [29]. Recently, an evolutionary multi-gate

transistor architecture, the inserted-oxide FinFET (iFinFET), is proposed to overcome these

fabrication issues. Fig. 1.6 shows that, iFinFET has better gate control as the fringing electric

field enhances the coupling between the gate and channel regions [30]. Currently, Intel has

launched its first CPU (Ivy Bridge processor [31]) and Samsung has manufactured its Exynos

Octa 7 chips [31] using 22 nm and 14 nm FinFET technologies, respectively. GlobalFoundries

(GF) has announced to deploy a 7 nm FinFET process which will reach to the customer by the

end of year 2018 [32].

1.4 FD-SOI MOSFETs 6

Figure 1.6: Comparison of electrostatic potential distributions shown in color and electric field lines

illustrated with arrows. Bias conditions are VGS = 0.75 V and VDS = 0.05 V [30].

1.4 FD-SOI MOSFETs

The FD-SOI is envisioned to have lower unit cost than FinFET due to complexity involved

with the FinFET design process. Fig. 1.7 shows that FD-SOI is cheaper, surmounts planar

bulk MOSFET and meets bulk FinFET in the performance/power ratio [33]. At the same time,

it supports the semiconductor industry on racetrack with Moore’s Law. Currently, Samsung,

ST Microelectronics and NXP are using 28 nm FD-SOI in their volume production [34]. GF

has fabricated industry’s first 22 nm FD-SOI technology platform (called as 22FDX) which

becomes the best option for cost-sensitive applications at the lowest operating voltage (0.4 V)

[35, 36]. GF also announced that, it will go for 12 nm FD-SOI (12FDX) process, which will

come into the market in 2020 [37]. In literature, FD-SOI MOSFET is also known with other

names like independent double gate MOSFET or ultra-thin-body silicon-on-insulator (UTB-

SOI) MOSFET [26, 38].

To have better control of gate on the channel, UTB-SOI MOSFETs demand extremely thin

(subnanometer) and uniform silicon film. This requirement is met with tolerance of ± 0.5 nm

by Soitec’s smart cut process [39] as shown in Fig. 1.8. It is based on wafer bonding and

layer-splitting (i.e., hydrogen implantation) technology [39]. This process is used to transfer an

1.4 FD-SOI MOSFETs 7

Figure 1.7: ST’s vision on advanced CMOS Roadmap Evolution [33].

ultra-thin silicon (i.e., a thin layer of crystalline material) on oxide layer from a defect free high

quality donor substrate.

Thick BOX below the channel eliminates source/drain-to-substrate depletion capacitance,

but it allows electric field penetration from the drain into the channel [40] and increases DIBL.

To address this issue, a doped thin layer of silicon (ground plane or back plane) is used below

thin BOX [41] (see Fig. 1.9b), which acts as a second gate to shield the field penetration into the

channel, and improves DIBL. Furthermore, UTB-SOI with thin BOX (UTBB-SOI) is widely

known for its multi-threshold voltage (Vth) technology, because Vth tuning through back-biasing

becomes effective via thin BOX [42, 43]. To illustrate its application, a 6T SRAM cell with

TBOX = 25 nm is shown in Fig. 1.10a. The back-bias modulates the static noise margin (SNM)

of SRAM cell as shown in Fig. 1.10b.

Historically, RF switches were built on AsGa substrates (i.e., 150 mm AsGa wafers). Com-

pared to 150 mm AsGa wafers, 200 mm RF-SOI wafers (see Fig. 1.11a) offer a significant die

cost advantage [45]. Furthermore, RFSOI wafer (i.e., FD-SOI on high resistivity (HR) silicon

substrate) offer high linearity, electrical isolation and low insertion loss over a wide frequency

1.5 Compact Modeling 8

Figure 1.8: Smart CutTM process adapted for FD-SOI MOSFETs [39].

range. Thus, market trends are showing rapid adoption of HRSOI substrate (see Fig. 1.11b) for

manufacturing of front end module and RF antenna switches [46].

1.5 Compact Modeling

Today IC design houses are closely engaged with their foundry partners, to meet time to

market requirement, for electronic products from advanced technology nodes. The communi-

cation between these two parties occurs at a number of stages, from product definition stage

to final product validation stage, through a set of technology definitions also called as process

design kit (PDK) [47]. Compact models are a primal part of a PDK, as they are used to predict

the MOSFET’s electrical characteristics (i.e., terminal currents, charges and capacitances) for a

given bias and temperature. A compact model is a concise mathematical description of device

physics, and it is usually coded in a programming language like C or Verilog-A [48]. A good

compact model should capture all real-device effects accurately as shown in Fig.1.12.

1.6 The BSIM-IMG Model 9

(a) (b)

Figure 1.9: (a) The 2-D constant potential contours for an SOI MOSFET is shown [40]. The 2-D fields

from the source/drain penetrate into the thick buried oxide (BOX) region which increases SCEs. (b)

Cross-sectional view of a FD-SOI device is illustrated [44]. Thinning the BOX and choosing a high

doping level for the back plane (BP), drastically reduces the fringing fields and improves the DIBL.

(a) (b)

Figure 1.10: (a) Topdown SEM picture of a 0.08 μm2 SRAM cell. (b) Butterfly curves of SRAM,

showing SNM modulation with back bias. Back bias is effective in achieving higher SNM [40].

1.6 The BSIM-IMG Model

In view of the great potential for low power and high performance applications, a com-

putationally efficient compact model for FD-SOI MOSFET is urgently required. Models for

independent double gate MOSFET have been reported in literature [50–56], but all the re-


(a)

(b)

Figure 1.11: (a) A trap rich layer underneath the buried oxide is used to freeze the parasitic surface

conduction in advanced HRSOI wafers [39]. (b) Illustration of RFSOI market trends [46].

ported models are iterative in nature, which may decrease computational efficiency of a com-

pact model. Recently, the BSIM-IMG model has been declared as the industry standard model

for UTB-SOI MOSFETs [57]. The BSIM-IMG model is a surface potential-based compact

model [49, 58, 59] as all the terminal charges and currents are calculated in terms of surface

potential.

Front/back gate surface potentials and inversion charge densities at the source and drain

ends are obtained by solving the Poisson’s equation. The drain current for a long-channel UTB-

SOI MOSFET in the BSIM-IMG model is calculated using drift-diffusion transport. Fig. 1.13


Figure 1.12: A compact model includes core and real-device models to capture device behavior accu-

rately [47].

Poisson’s

equation

Front and back gate surface potentials, ψs1 and ψs2

Total inversion charge and terminal Charges

Terminal Current

Calculation

Capacitance

Calculation

Figure 1.13: An illustration of basic working principle of the BSIM-IMG model [49].

illustrates the basic working principle of the model. For a complete description of the I-V and

C-V models of the BSIM-IMG model, the readers may refer to [60].

1.7 Thesis Goals and Outline 12

1.7 Thesis Goals and Outline

The goal of this thesis is to develop a compact model for FD-SOI MOSFET for a wide range of

back biases and frequencies. The thesis is organized as follows:

In Chapter 2, the non-physical capacitance behavior in the BSIM-IMG 102.5 model is dis-

cussed. The origin of the issue was the assumption of constant displacement field at the back

interface, while calculating the initial guess for the front gate surface potential. In this chapter,

we propose the improved surface potential calculation for the independent double gate MOS-

FETs [61]. The improved model is implemented in the BSIM-IMG 102.6 model which shows

distinctive improvement over BSIM-IMG 102.5 model. The model shows accurate behavior for

C-V and I-V characteristics, while keeping smooth behavior for their higher order derivatives.

In independent double gate MOSFETs, the vertical electric field changes its sign according

to the front and back gate biases, which result in a non-unique relationship between electric

field and carrier distribution. In this chapter, we also develop an effective mobility model for a

wide range of back gate biases, solely dependent on technology parameters [62]. This effective

mobility model allows the user to predict the deviation in device characteristics due to variations

in the device structure. The model has shown good agreement with the measured data obtained

from CEA-LETI as well as with the data reported in literature.

UTB-SOI MOSFETs are famous for their threshold voltage tuning facility through back-

bias. Some fraction of this applied back-bias drops in the substrate region below the BOX,

which depletes the substrate. In Chapter 3, we discuss the impact of substrate depletion on

device characteristics. We have proposed an approach to include the effect of substrate depletion

in a surface potential based compact model for UTB-SOI MOSFETs [63]. The proposed model

is extensively verified for both NMOS and PMOS with geometrical and temperature scaling.

Model validation is done at 50 nm technology node with the state of the art UTB-SOI MOSFETs

provided by Low-power Electronics Association and Project (LEAP) and excellent agreement

with the experimental data is achieved.

Chapter 4 begins with a discussion on self-heating effect in FD-SOI MOSFETs. Higher

device heating in this MOSFET results in higher thermal resistance. From 3D TCAD simula-

1.7 Thesis Goals and Outline 13

tions, we observed that device thermal resistance increases further with the reduction in channel

length. The impact of geometrical scaling on the thermal resistance is investigated in this chap-

ter. A new behavioral model to capture geometrical scalability of thermal resistance is proposed

and validated against the TCAD and experimental data [64].

Chapter 5 explains that the flicker noise behavior in independent double gate MOSFETs

is different from bulk MOSFETs, due to presence of different interface qualities and bias con-

ditions at front and back gates, respectively. Thus, a flicker noise model dedicated to FD-SOI

MOSFETs is required which can capture device behavior accurately from weak to strong in-

version regions. In this chapter, we have developed a physics-based unified flicker noise model

for independent double gate MOSFETs [65]. This model predicts correct flicker noise behav-

ior for a wide range of the front and back gate biases. The model is validated against noise

measurement data from 1 Hz to 65 kHz. The proposed model is computationally efficient and

implementable in any SPICE model for circuit simulations.

In Chapter 6, we first discuss the RF properties of the FD-SOI MOSFETs. A new RF

model capturing all the high-frequency effects is proposed. Step-by-step parameter extraction

methodology of the BSIM-IMG model is also proposed and validated against the measured S-

parameter data [66]. The model is validated over a wide range of biases and frequencies, and

shows excellent agreement with the experimental data.

Chapter 7 contains the noise measurements for ultra-thin body and thin buried oxide (UTBB)

FD-SOI MOSFETs in the RF frequency range. We analyze the impact of front and back gate

biases on thermal noise behavior; along with the discussions on the secondary effects in FD-SOI

MOSFETs, which contribute to the thermal noise [67]. Using calibrated TCAD simulations, we

show that the noise figure changes with the substrate doping and buried oxide thickness.

Finally, Chapter 8 summarizes the research work carried out in this thesis and also suggests

the scope of future work in this area.

Bibliography

[1] “Moore’s law-transistors per microprocessor.” [Online]. Available: https://people.hofstra.

edu/geotrans/eng/ch2en/conc2en/mooreslaw.html

[2] S.-M. Kang and Y. Leblebici, CMOS Digital Integrated Circuits. Tata McGraw-Hill

Education, 2003.

[3] “Keeping up with moore’s law proves difficult for intel.” [Online]. Available:

https://www.cnet.com/news/keeping-up-with-moores-law-proves-difficult-for-intel/

[4] S. Thompson, P. Packan, and M. Bohr, “Mos scaling: Transistor challenges for the 21st

century,” 1999.

[5] C. Shin, Variation-Aware Advanced CMOS Devices and SRAM, publisher = Springer Se-ries in Advanced Microelectronics, vol=56, year = 2016.

[6] N. Haron and S. Hamdioui, “Why is CMOS scaling coming to an END?” in Proc. of 3rdIEEE International Design and Test Workshop, pp. 98–103, December 2008.

[7] K. Mistry, C. Allen, C. Auth, B. Beattie, D. Bergstrom, M. Bost, M. Brazier, M. Buehler,

A. Cappellani, R. Chau, C. H. Choi, G. Ding, K. Fischer, T. Ghani, R. Grover, W. Han,

D. Hanken, M. Hattendorf, J. He, J. Hicks, R. Huessner, D. Ingerly, P. Jain, R. James,

L. Jong, S. Joshi, C. Kenyon, K. Kuhn, K. Lee, H. Liu, J. Maiz, B. McIntyre, P. Moon,

J. Neirynck, S. Pae, C. Parker, D. Parsons, C. Prasad, L. Pipes, M. Prince, P. Ranade,

T. Reynolds, J. Sandford, L. Shifren, J. Sebastian, J. Seiple, D. Simon, S. Sivakumar,

P. Smith, C. Thomas, T. Troeger, P. Vandervoorn, S. Williams, and K. Zawadzki, “A 45nm

logic technology with high-k+metal gate transistors, strained silicon, 9 cu interconnect

layers, 193nm dry patterning, and 100 percent pb-free packaging,” in Proc. of TechnicalDigest of IEDM, pp. 247–250, 2007.

[8] D. Neamen, Semiconductor Physics And Devices, 3rd ed. New York, NY, USA: McGraw-

Hill, Inc., 2003.

[9] K. Roy, S. Mukhopadhyay, and H. Mahmoodi Meimand, “Leakage current mechanisms

and leakage reduction techniques in deep-sub micrometer CMOS circuits,” vol. 91, no. 2,

pp. 305–327, 2003.

14

BIBLIOGRAPHY 15

[10] J.-P. Colinge, FinFETs and Other Multi-Gate Transistors Integrated Circuits and Systems.

Springer Science and Business Media, 2008.

[11] Y. Zhang, H. Zhu, H. Wu, Y. Zhang, Z. Zhao, J. Zhong, H. Yang, Q. Liang, D. Wang,

J. Li, C. Jia, J. Liu, Y. Zhao, C. Li, L. Meng, P. Hong, J. Li, Q. Xu, J. Gao, X. He, Y. Lu,

Y. Zhang, T. Yang, Y. Wang, H. Cui, C. Zhao, H. Yin, H. Zhong, H. Yin, J. Yan, W. Wang,

D. Chen, H. Yu, S. Yang, and T. Ye, “Planar bulk MOSFETs with self-aligned pocket well

to improve short-channel effects and enhance device performance,” IEEE Transaction onElectron Devices, vol. 62, no. 5, pp. 1411–1418, 2015.

[12] P. Magarshack, P. Flatresse, and G. Cesana, “UTBB FD-SOI: A process/design symbio-

sis for breakthrough energy-efficiency,” in Proc. of Design, Automation Test in EuropeConference Exhibition, pp. 952–957, 2013.

[13] Q. Xie, C. Jung Lee, J. Xu, C. Wann, J. Sun, and Y. Taur, “Comprehensive Analysis

of Short-Channel Effects in Ultrathin SOI MOSFETs,” IEEE Transaction on ElectronDevices, vol. 60, no. 6, pp. 1814–1819, 2013.

[14] E. Amat, A. Calomarde, C. Almudever, N. Aymerich, R. Canal, and A. Rubio, “Impact of

FinFET and IIIV/Ge Technology on Logic and Memory Cell Behavior ,” IEEE Transac-tions on Device and Materials Reliability, vol. 14, no. 1, pp. 344–350, 2014.

[15] N. Paydavosi, S. Venugopalan, Y. S. Chauhan, J. P. Duarte, S. Jandhyala, A. M. Niknejad,

and C. Hu, “BSIM-SPICE models enable FinFET and UTB IC designs,” IEEE Access,

vol. 1, no. 3, pp. 201–215, 2013.

[16] K. Majumdar, C. Hobbs, and P. D. Kirsch, “Benchmarking Transition Metal Dichalco-

genide MOSFET in the Ultimate Physical Scaling Limit,” IEEE Electron Device Letters,

vol. 35, no. 3, pp. 402–404, 2014.

[17] N. Agrawal, Y. Kimura, R. Arghavani, and S. Datta, “Impact of Transistor Architecture

(Bulk Planar, Trigate on Bulk, Ultrathin-Body Planar SOI) and Material (Silicon or IIIV

Semiconductor) on Variation for Logic and SRAM Applications ,” IEEE Transaction onElectron Devices, vol. 60, no. 10, pp. 3298–3304, 2013.

[18] F. Schwierz, “Graphene-based FETs,” pp. 131–138, 2012.

[19] R. Pillarisetty, “Academic and industry research progress in germanium nanodevices,”

Nature 2011, pp. 324–328, 2011.

[20] J. Del Alamo, “Nanometre-scale electronics with III-V compound semiconductors,” Na-ture 2011, pp. 317–323, 2011.

[21] T. Chu and Z. Chen, “Bandgap engineering in 2D layered materials,” in Proc. of TechnicalDigest of IEDM, pp. 707–710, 2015.

BIBLIOGRAPHY 16

[22] J. G. Fossum and V. P. Trivedi, Fundamentals of Ultra-Thin-Body MOSFETs and Fin-FETs. Cambridge University Press, 2013.

[23] Y.-K. Choi, K. Asano, N. Lindert, V. Subramanian, T.-J. King, J. Bokor, and C. Hu,

“Ultrathin-body SOI MOSFET for deep-sub-tenth micron era,” IEEE Electron Device Let-ters, vol. 21, no. 5, pp. 254–256, 2000.

[24] C. Hu, Modern Semiconductor Devices for Integrated Circuits. Prentice Hall, 2010.

[25] M.-H. Chiang, J.-N. Lin, K. Kim, and C.-T. Chuang, “Random dopant fluctuation in

limited-width FinFET technologies,” IEEE Transaction on Electron Devices, vol. 54, pp.

2055–2060, 2007.

[26] S. Markov, A. Zain, B. Cheng, and A. Asenov, “Statistical variability in scaled generations

of n-channel UTB-FD-SOI MOSFETs under the influence of RDF, LER, OTF and MGG,”

pp. 1–2, 2012.

[27] Y. Yang, S. Markov, B. Cheng, A. Zain, X. Liu, and A. Cheng, “Back-gate bias dependence

of the statistical variability of FDSOI MOSFETs with thin BOX,” IEEE Transaction onElectron Devices, vol. 60, no. 2, pp. 739–745, 2013.

[28] “FinFET technology market 2016.” [Online]. Available: http://www.researchandmarkets.

com/research/pflc9w/finfet technology

[29] “Sustaining the silicon revolution from 3-D transistors to 3-D integration.” [Online].

Available: https://people.eecs.berkeley.edu/∼tking/presentations/KingLiu SPIEAL2015

[30] P. Zheng, D. Connelly, F. Ding, and T.-J. K. Liu, “Considerations for ultimate CMOS

scaling,” IEEE Transaction on Electron Devices, vol. 62, no. 12, pp. 3945–3950, 2015.

[31] “FinFET Technology Market by Technology.” [Online].

Available: http://www.researchandmarkets.com/reports/3617030/

finfet-technology-market-by-technology-22nm

[32] “Microprocessor Report-FD-SOI offers alternative to FinFET.”

[Online]. Available: http://globalfoundries.com/docs/default-source/PDF/

FD-SOI-Offers-Alternative-to-FinFET.pdf

[33] “FD-SOI keeps moore’s law on track,” 2014. [Online]. Available: http://www.

advancedsubstratenews.com/2014/02/fd-soi-keeps-moores-law-on-track/

[34] “Great FD-SOI start for 2016: Samsung, GF, Renesas, NXP/Freescale, ST, Soitec,” 2016.

[Online]. Available: http://semimd.com/hars/

[35] “GLOBALFOUNDRIES launches industry’s first 22nm FD-SOI technology platform.”

[Online]. Available: http://www.globalfoundries.com/newsroom/press-releases/2015/07/

13/globalfoundries-launches-industry-s-first-22nm-fd-soi-technology-platform

BIBLIOGRAPHY 17

[36] “Globalfoundries 22nm FD-SOI: What happens when,” 2015.

[Online]. Available: https://www.semiwiki.com/forum/content/

4820-globalfoundries-22nm-fd-soi-what-happens-when.html

[37] “GlobalFoundries to Continue FD-SOI Tech, Adds 12nm 12FDX Node To Roadmap,”

September 2016. [Online]. Available: http://www.pcper.com/news/Processors/

GlobalFoundries-Continue-FD-SOI-Tech-Adds-12nm-%E2%80%9C12FDX%E2%80%

9D-Node-Roadmap

[38] C. Fenouillet-Beranger, P. Perreau, T. Benoist, C. Richier, S. Haendler, J. Pradelle, J. Bus-

tos, P. Brun, L. Tosti, O. Weber, F. Andrieu, B. Orlando, D. Pellissier-Tanon, F. Abbate,

C. Pvichard, R. Beneyton, M. Gregoire, J. Ducote, P. Gouraud, A. Margain, C. Borowiak,

R. Bianchini, N. Planes, E. Gourvest, K. K. Bourdelle, B. Y. Nguyen, T. Poiroux, T. Skot-

nicki, O. Faynot, and F. Boeuf, “Impact of local back biasing on performance in hy-

brid FDSOI/bulk high-k/metal gate low power (LP) technology,” Solid-State Electronics,

vol. 88, pp. 15–20, 2013.

[39] “Smart cut with soitecs proprietary technology.” [Online]. Available: https://www.soitec.

com/en/products/smart-cut

[40] Q. Liu, F. Monsieur, A. Kumar, T. Yamamoto, A. Yagishita, P. Kulkarni, S. Ponoth,

N. Loubet, K. Cheng, A. Khakifirooz, B. Haran, M. Vinet, J. Cai, J. Kuss, B. Linder,

L. Grenouillet, S. Mehta, P. Khare, N. Berliner, T. Levin, S. Kanakasabapathy, A. Upham,

R. Sreenivasan, Y. L. Tiec, N. Posseme, J. Li, J. Demarest, M. Smalley, E. Leobandung,

S. Monfray, F. Boeuf, T. Skotnicki, K. Ishimaru, M. Takayanagi, W. Kleemeier, H. Bu,

S. Luning, T. Hook, M. Khare, G. Shahidi, B. Doris, and R. Sampson, “Impact of back

bias on ultra-thin body and BOX (UTBB) devices,” pp. 160–161, 2011.

[41] C. Sampedro, F. Gamiz, L. Donetti, and A. Godoy, “Reaching sub-32 nm nodes: ET-

FDSOI and BOX optimization,” Solid-State Electronics, vol. 70, pp. 101–105, 2012.

[42] C. Fenouillet-Beranger, O. Thomas, P. Perreau, J. P. Noel, A. Bajolet, S. Haendler, L. Tosti,

S. Barnola, R. Beneyton, C. Perrot, C. de Buttet, F. Abbate, F. Baron, B. Pernet, Y. Campi-

delli, L. Pinzelli, P. Gouraud, M. Cass, C. Borowiak, O. Weber, F. Andrieu, K. K. Bour-

delle, B. Y. Nguyen, F. Boedt, S. Denorme, F. Boeuf, O. Faynot, and T. Skotnicki, “Ef-

ficient Multi-Vt FDSOI technology with UTBOX for low power circuit design,” VLSITechnology Digest of Technical Papers, IEEE Symposium on, pp. 65–66, 2010.

[43] C. Navarro, N. Rodriguez, A. Ohata, F. Gamiz, F. Andrieu, C. Fenouillet-Beranger,

O. Faynot, and S. Cristoloveanu, “Multibranch Mobility Analysis for the characteriza-

tion of FDSOI Transistors,” IEEE Electron Device Letters, vol. 33, no. 8, pp. 1102–1104,

2012.

[44] J. Noel, O. Thomas, C. Fenouillet. Beranger, M. A. Jaud, P. Scheiblin, and A. Amara, “A

simple and efficient concept for setting up multi-Vt devices in thin BOX fully-depleted

SOI technology.”

BIBLIOGRAPHY 18

[45] “SOITEC and UCL boost the RF performance of SOI sub-

strates.” [Online]. Available: http://www.advancedsubstratenews.com/2013/12/

soitec-and-ucl-boost-the-rf-performance-of-soi-substrates/

[46] “RF SOI: Replacing GaAs, one smartphone at a time.” [On-

line]. Available: http://www.soiconsortium.org/fully-depleted-soi/presentations/

interconnected-world-2015/GLOBALFOUNDRIES%20RFSOI%20Technology%

20SOI%20Consortium%20Shanghai%20September%202015.pdf

[47] Y. S. Chauhan, S. Venugopalan, M. A. Chalkiadaki, M. A. U. Karim, H. Agarwal, S. Khan-

delwal, N. Paydavosi, J. P. Duarte, C. C. Enz, A. M. Niknejad, and C. Hu, “BSIM6: Ana-

log and RF compact model for bulk MOSFET,” IEEE Transaction on Electron Devices,

vol. 61, no. 2, pp. 234–244, 2014.

[48] M. Dunga, “Nanoscale cmos modeling,” Ph.D. Dissertation, UC Berkeley, 2007.

[49] “BSIM-IMG technical manual.” [Online]. Available: http://www-device.eecs.berkeley.

edu/bsim/Files/BSIMIMG/{BSIMIMG102}.7.0/BSIMIMG102.7.0 Technical Manual.

pdf

[50] H. Lu and Y. Taur, “An analytic potential model for symmetric and asymmetric DG MOS-

FETs,” IEEE Transaction on Electron Devices, vol. 53, pp. 1161–1168, 2006.

[51] A. Roy, J. Sallese, and C. Enz, “A closed-form charge-based expression for drain current

in symmetric and asymmetric double gate MOSFET,” Solid-State Electronics, vol. 50, pp.

687–693, 2006.

[52] A. Sahoo, P. Thakur, and S. Mahapatra, “A computationally efficient generalized poisson

solution for independent double-gate transistors,” IEEE Transactions on Electron Devices,

vol. 57, pp. 632–636, 2010.

[53] G. Dessai and G. Gildenblat, “Solution space for the independent-gate asymmetric

DGFET,” Solid-State Electronics, vol. 54, pp. 382–384, 2010.

[54] A. Ortiz-Conde and F. Garcia-Sanchez, “Generic complex-variable potential equation for

the undoped asymmetric double-gate MOSFET,” Solid-State Electronics, vol. 57, pp. 43–

51, 2011.

[55] S. Jandhyala and S. Mahapatra, “An efficient robust algorithm for the surface-potential cal-

culation of independent DG MOSFET,” IEEE Transactions on Electron Devices, vol. 58,

pp. 1663–1671, 2011.

[56] M. Miura-Mattausch, H. Kikuchihara, U. Feldmann, T. Nakagawa, M. Miyake, T. Iizuka,

and H. Mattausch, “HiSIM-SOTB: A compact model for SOI MOSFET with ultra-thin

si-layer and BOX,” Nanotech, vol. 2, pp. 792–795, 2012.

BIBLIOGRAPHY 19

[57] “BSIM-IMG, independent multi-gate model.” [Online]. Available: http://www-device.

eecs.berkeley.edu/bsim/?page=BSIMIMG

[58] D. D. Lu, M. V. Dunga, C.-H. Lin, A. M. Niknejad, and C. Hu, “A computationally effi-

cient compact model for fully-depleted SOI MOSFETs with independent controlled front

and back-gates,” Solid-State Electronics, vol. 62, pp. 31–39, 2011.

[59] S. Khandelwal, Y. S. Chauhan, D. D. Lu, S. Venugopalan, M. A. U. Karim, A. B. Sachid,

B. Y. Nguyen, O. Rozeau, O. Faynot, A. M. Niknejad, and C. C. Hu, “BSIM-IMG: A com-

pact model for ultra-thin body SOI MOSFETs with back-gate control,” IEEE Transactionson Electron Devices, vol. 59, no. 8, pp. 2019–2026, 2012.

[60] D. D. Lu, “Compact models for future generation cmos,” Ph.D. Dissertation, UC Berkeley,

2011.

[61] P. Kushwaha, C. Yadav, H. Agarwal, Y. S. Chauhan, J. Srivatsava, S. Khandelwal, J. P.

Duarte, and C. Hu, “BSIM-IMG with improved surface potential calculation recipe,” inProc. IEEE India Conference (INDICON), pp. 1–4, 2014.

[62] P. Kushwaha, H. Agarwal, M. Bhoir, N. R. Mohapatra, S. Khandelwal, J. P. Duarte, Y.-

K. Lin, H.-L. Chang, C. Hu, and Y. S. Chauhan, “Predictive effective mobility model for

FDSOI transistors using technology parameters,” Aug. 2016.

[63] P. Kushwaha, N. Paydavosi, S. Khandelwal, C. Yadav, H. Agarwal, J. Duarte, C. Hu, and

Y. S. Chauhan, “Modeling the impact of substrate depletion in FDSOI MOSFETs,” Solid-State Electronics, vol. 104, pp. 6 – 11, 2015.

[64] P. Kushwaha, B. K. Krishna, H. Agarwal, S. Khandelwal, J. P. Duarte, C. Hu, and

Y. S. Chauhan, “Thermal resistance modeling in FDSOI transistors with industry stan-

dard model BSIM-IMG,” Elsevier Microelectronics Journal, vol. 56, pp. 171 – 176, 2016.

[65] P. Kushwaha, H. Agarwal, C. Hu, and Y. S. Chauhan, “A unified flicker noise model

for FDSOI MOSFETs including back-bias effect,” Submitted in IEEE Trans. on ElectronDevices, Aug. 2016.

[66] P. Kushwaha, S. Khandelwal, J. P. Duarte, C. Hu, and Y. S. Chauhan, “RF modeling

of FDSOI transistors using industry standard BSIM-IMG model,” IEEE Transactions onMicrowave Theory and Techniques, vol. 64, no. 6, pp. 1745–1751, June 2016.

[67] P. Kushwaha, A. Dasgupta, Y. Sahu, S. Khandelwal, C. Hu, and Y. S. Chauhan, “Charac-

terization of RF noise in UTBB FD-SOI MOSFET,” IEEE Journal of the Electron DevicesSociety, no. 99, pp. 1–1, 2016.

Chapter 2

Surface Potential and Effective MobilityModeling in FD-SOI MOSFETs

Fully depleted silicon on insulator (FD-SOI) MOSFET is a prominent option to overcome short

channel effects at sub-micron technology node [1, 2]. FD-SOI MOSFET has lightly doped body

which reduces process induced variability and increases yield [3–6]. Threshold voltage tuning

via back biasing through thin BOX provides multi-threshold (High-Vth and Low-Vth) flavor

on same chip which provides facility to have high performance at low power consumption

[7–10]. An industry standard compact model must be able to calculate terminal (drain, source,

front/back-gate) charges and currents, which are then utilized by circuit simulators to solve a

complete circuit under different analyses such as dc, ac, transient, etc. In this chapter, we first

introduce a methodology to calculate surface potential in FD-SOI MOSFETs. Then we will

discuss the challenges involved in defining efficient mobility in FD-SOI MOSFETs and will

derive a technology parameter based mobility model for a wide range of back gate biases.

2.1 Surface Potential Modeling

The two independent (front- and back-) gates control the channel charge in FD-SOI MOSFETs

which enables low power and high-speed applications [11]. Developing a compact model for

FD-SOI MOSFETs is a challenging task due to the nature of the Poisson’s solution at the two

boundary conditions. It’s well known that the Poisson’s solution for FD-SOI MOSFETs lies in

trigonometric and hyperbolic solutions, creating the desired numerical robustness highly com-

plicated; however, fast speed, numerical robustness, and accuracy are essential characteristics

of a compact model for circuit design. In this section, we present the recipe of calculating sur-

face potential in the FD-SOI MOSFETs which improves model’s accuracy and computational

efficiency. We have shown the model validation against the measurement data along with the

20

2.1 Surface Potential Modeling 21

discussion on the benchmark tests which BSIM-IMG model has passed successfully.

2.1.1 Improved Surface Potential Calculation

The relationship between the front-gate surface potential (ψs1) and the back-gate surface poten-

tial (ψs2) is obtained using the Poisson’s equation [12] as:

E2s1 − E2

s2 =2qNcVtm

εSi

(exp

ψs1 − Vch

Vtm− exp

ψs2 − Vch

Vtm

)(2.1)

where Es1 and Es2 are the front and back gate surface electric fields, respectively as follows:

Es1 =Cox(V

∗fg − ψs1)

εsi

(2.2)

Es2 =Cbox(V

∗bg − ψs2)

εsi

(2.3)

where V ∗fg = Vfg − Δφ1, V

∗bg = Vbg − Δφ2 are front and back gate voltages and Δφ1, Δφ2 are

the work function differences between the front-gate/back-gate and n+ source junction. q is the

electron charge, Vtm is the thermal voltage, Nc is the conduction band density of states and Vch

is the channel potential. To maintain consistency in the solution, back-gate surface potential

(ψs2) is calculated in terms of ψs1 [12].

ψs2 =Csi

Csi + Cbox

ψs1 +Cbox

Csi + Cbox

V ∗bg (2.4)

where CSi =εSi

TSiand TSi is the silicon body thickness. Using equation (2.4) in (2.1), we get an

implicit equation in terms of ψs1 which can be represented in normalized form as follows

(xfg − x

G

)2

− (B(xbg − x))2 = exp(x− xn)− exp(αSix+ αoxxbg − xn) (2.5)

where xfg/bg =V ∗

fg/bg

Vtm, x = ψs1

Vtmand xn =

Vch

Vtm, G = Tox

εox

√2qNcεSi

Vtmand B = 1

TSi+εSiεox

Tbox

√εSiVtm

2qNc

Using first order householder’s method, we get most accurate ψs1 to calculate accurate val-

ues of Es1, ψs2 and Es2. From Gauss’s law, we get inversion charge which gives accurate be-

havior for not only current-voltage characteristics but also for higher order derivatives of drain

current in all regions of operation. However during capacitance simulation, it was observed

that in the regime where the back-gate voltage exceeds the front-gate voltage considerably, the


��

��

��

��

��

��

��

��

��

��

��

� � �

��

� � �

��

�� !

��

��

"��#�$#��#��%�&

'(�)

Figure 2.1: Front-Gate Capacitance Cfgfg vs front gate voltage Vfg characteristics at Vds = 0 V, Vbg = 0

V, L = 961 nm, W = 10 μm. Fully depleted device has capacitance in depletion and inversion region

because there is no carrier when Vfg < 0V .

��

��

��

��

��

��

��

��

��

��

��

�

��

Figure 2.2: Comparison between previous and improved initial guess for front-gate surface potential.

predicted capacitances were nonphysical, as shown in Fig. 2.1. The origin of the issue was

Es2 approximation as a constant displacement field [13] for calculating the initial guess of the

front-gate surface potential required to solve (2.5), given by equation (2.6). This is depicted by

the dotted line in Fig. 2.2.

ψ0s1 = 0.5

[Ψwinv +Ψinv −

√(Ψwinv −Ψinv)2 + 30

](2.6)

where Ψinv = ln(200C1

)+ Vch, Ψwinv = V ∗

fg −√fE2, teff = TSi +

εSi

εox(Tox + Tbox)


and C1 = 2qNcVtm

εSi

(εSi

εox

Tox

Vtm

)2

and fE2 =

[V ∗

fg − V ∗bg

εSiεox

Tox

teff

]2We resolved this issue in capacitance by taking improved initial guess for front surface

potential from S. Jandhyala et al., [14] as shown in Fig. 2.2. We follow a two step approach to

arrive at accurate initial guess for (2.5). First we use the fact that, when the back-gate is in weak

inversion region, the effective conduction path will be very near to front surface. Hence we

can assume infinite thickness of body and the initial guess for the front-gate surface potential is

obtained independent of back-gate by solving simplified form of Poisson’s equation (4.9).

(Cox

V ∗fg − ψs1

εSi

)2

=2qNcVtm

εSi

expψs1 − Vch

Vtm(2.7)

The initial guess ψ0s1 (2.8) is required to solve (2.7), by assuming that for higher front gate

voltages, we can neglect ψs1 in the left hand side of equation (2.7) in comparison to exponential

of ψs1 term in the right hand side.

ψ0s1 =

⎧⎨⎩V

∗fg if V ∗

fg < 0

min[V ∗

fg,(Vch + 2Vtm ln[

V ∗fgCox√

2qNcVtmεsi]) ]

otherwise(2.8)

The implicit equation (2.7) is solved using two iterations of Halley’s algorithm. This solution is

used as the initial guess for the second step discussed next. When back-side is in weak inversion

region, we can neglect second exponential term on right hand side of equation (2.5), to obtain

(2.9).

f(x) ≡(xfg − x

G

)2

− (B(xbg − x))2 − exp(x− xn) = 0 (2.9)

The implicit equation (2.9) is solved using Halley’s algorithm for a maximum of four iterations

and stops when the error in surface potential becomes less than 1 nV. Halley’s algorithm is a

second order Householder’s method [15] and can be written as

xn+1 = xn − 2f(x)f ′(x)2[f ′(x)]2 − f(x)f ′′(x)

(2.10)

where xn, xn+1 are the iterant solutions and f ′(x), f ′′(x) are the first and second derivatives of

equation (2.9) with respect to x. The initial guess thus obtained from the two step procedure

for computation of surface potential from (2.5) is depicted by the solid line in Fig. 2.2. With

this modified surface potential calculation recipe, model is now showing correct behavior for


(a)

(b)

Figure 2.3: Normalized total gate capacitance Cfgfg vs. Vfg at Vbg = 0 V. (a) NMOS device and (b) PMOS

device, with device dimensions (W = 2160 μm, L = 961 nm),(W = 3360 μm, L = 344 nm) and (W =

4800 μm, L = 56 nm) Symbols: Data [4], Lines: the BSIM-IMG model.

capacitance for all ranges of the front-gate voltages (Vfg) as shown in Fig. 2.1 by solid line.

Verification of improved surface potential calculation with the experimental data is discussed in

next section.


-1.0 -0.5 0.0 0.510-14

10-9

10-4

Vbg= - 1, 0, 1 V T= 25°C

PMOS

|Vds| = 50 mV

I ds (m

A)

Front Gate Voltage (V)

Symbols: Measured DataLines : Our Model

L = 961 nmW = 10 μm

0.00

0.02

0.04

Ids (mA

)

Vbg= - 1, 0, 1 V

(a)

-1.0 -0.5 0.0 0.50.00

0.02

0.04

0.06

0.08 PMOS

|Vds| = 50 mV

g m (m

A/V

)



L = 961 nmW = 10 μm

Vbg= - 1, 0, 1 V

T= 25°C

(b)

Figure 2.4: Back-bias tuning Vbg = [-1, 0, 1] V (a) Ids vs. Vfg characteristic for channel lengths L = 961

nm. (b) Transconductance (gm) vs Vfg characteristic for channel lengths L = 961 nm. Symbols: Data [4],

Lines: the BSIM-IMG model.

2.1.2 Model Validation

In this section, we have shown the BSIM-IMG model validation with measured data at 50

nm technology node [4]. Model’s C-V characteristics validation with experimental data [4] is

shown in Fig. 2.3 for NMOS and PMOS at |Vbg| = 0 V and |Vds| = 0 V from long to short device

dimensions. The model has correct behavior for the capacitance in all regions of operation

from depletion to inversion. In short channel devices, the dominance of source-drain charge

sharing and parasitic capacitance (overlap and fringing) becomes necessary, as a result, gate

capacitance increases in depletion region as shown in Fig. 2.3. Fig. 2.4a and Fig. 2.5a show the


-1.0 -0.5 0.0 0.510-14

10-9

10-4

T= 25°C PMOS

|Vds| = 50 mV

I ds (m

A)



L = 52 nmW = 10 μm

Vbg= - 1, 0, 1 V

Vbg= - 1, 0, 1 V

0.0

0.1

0.2

0.3

0.4

0.5

Ids (mA

)

(a)

-1.0 -0.5 0.0 0.50.0

0.2

0.4

0.6

0.8

1.0PMOS

|Vds| = 50 mV

g m (m

A/V

)



L = 52 nmW = 10 μm

Vbg= - 1, 0, 1 V

T= 25°C

(b)

Figure 2.5: Back-bias tuning Vbg = [-1, 0, 1] V (a) Ids vs. Vfg characteristic for channel lengths L = 52

nm. (b) Transconductance (gm) vs Vfg characteristic for channel lengths L = 52 nm. Symbols: Data [4],


drain current behavior in linear and subthreshold region with respect to the front-gate voltage

for different back-gate biases at |Vds| = 0.05 V. In the PMOS device, drain current decreases

with positive back-gate bias (Vbg = 1 V) due to higher threshold voltage while increases with

negative back bias (Vbg = -1 V) due to lower threshold voltage. The model has captured all

real device effects (Vth-roll off, drain induced barrier lowering, etc.) and shows good agreement

with the experimental data for short channel devices [4]. Current derivatives of a model are

important for digital and analog applications. The BSIM-IMG model has continuous behavior

for transconductance (gm) as shown in Fig. 2.4b and Fig. 2.5b for two channel lengths. Good


��

�

�

��

��

��

�

��

��

��

��

(a)

��

��

��

��

��

��

��

��

��

��

��

��

��

��

�

��

��

��

��

��

��

��

(b)

Figure 2.6: Benchmark Tests (a) AC source-drain charge symmetry test results with NMOS device WL

= 10/0.052 μm. Vfg = 1.2 V, and Vbg = -0.1 V. δcsd =(is−+id−)+(is+−id+)(is−−id−)+(is++id+) = Css−Cdd

Css+Cddand its derivative

vs. Vx where drain and source biases are swept in opposite direction. (b) Gummel Symmetry Test in n

channel device: Third order derivative of drain current d3Ix/dV3

x has odd symmetry around Vds = 0 V.

Vfg varies from 0 to 0.8 V in steps of 0.2 V, back-gate voltage Vbg = -1 V and drain voltage sweep is from

-0.2 V to 0.2 V.

2.2 Effective Mobility in FD-SOI MOSFET 28

agreement of gm ensures efficient implementation of mobility module.

2.1.3 Benchmark Tests

In developing phase of a compact model, it passed through a series of benchmark test to ensure

its applicability for circuit design applications. Along with the benchmark tests, speed and

convergence tests are another important key factors for a compact model. Evaluating continuity

of all charges present in MOSFET model is necessary. AC symmetry test is used to check

MOSFET charge model symmetry [16]. By small signal AC excitation (in-phase and antiphase)

on two terminals (source and drain, respectively), a small signal ac current is generated at the

third terminal (gate). The capacitance is calculated from the imaginary part of generated small

signal AC current which is then used to derive quantity δcsd to check the charge symmetry of

model. Fig. 2.6a shows that model is continuous and non-singular around Vds = 0 V which

preserves symmetric behavior of charge in the BSIM-IMG model. Gummel symmetry test

is performed to check model’s source/drain symmetry for I-V characteristics. In Gummel-

symmetry test, model’s symmetric behavior with respect to source/drain interchange is required

at Vds = 0 V. The Gummel symmetry test of the BSIM-IMG model for higher-order current

derivatives is shown in Fig. 2.6b for non-zero back-gate bias Vbg = -1 V. Fig. 2.6b demonstrates

that there is no singularity around Vds = 0 V, which ensures model’s symmetric behavior [16, 17].

2.2 Effective Mobility in FD-SOI MOSFET

In bulk MOSFET, the inversion layer mobility follows a universal relation and is independent of

substrate bias, the substrate doping and oxide thickness when plotted against effective transverse

electric field Eeff(bulk) [18],

Eeff(bulk) =Qdep + ηQinv

εSi(2.11)

where Qdep, Qinv are the depletion and inversion charges respectively, εSi is the relative permit-

tivity of silicon and η is 1/2 for NMOS and 1/3 for PMOS MOSFETs. This universal mobility

curve (UMC) is considered as a reference curve to compare any new technology and is very

useful to understand the bulk MOSFET physics [19]. Unfortunately, the same definition of

Eeff(bulk) is not applicable to the FD-SOI MOSFETs because electric field at the back interface

(Es2) is not always equal to zero as in bulk MOSFETs [20]. This strong front- and back-gate

coupling makes the effective electric field [19] and inversion layer mobility [21] calculations

difficult in the FD-SOI MOSFETs as compared to the bulk MOSFETs. This had led to lots of

discussion on the non-universality of mobility in literature [8, 19], highlighting the importance


of Es2. To account the impact of Es2 on mobility, the models proposed till date [22–24] have

tried to include back gate electric field Es2 along with the front-gate electric field Es1 which

results in effective electric field

Eeff(soi) =Qb + ηQinv

εSi+ Es2 (2.12)

Unfortunately, the lumped parameter Eeff is not a convenient quantity to use, when expressed

in terms of Qb and Qinv [20, 24] as their measurements are difficult [25]. In this work, we

have proposed a complete technology parameter based compact model for Eeff and effective

mobility μeff . Due to some manufacturing variations, technology parameters (Tox/box, Vth,

Vfg/bg, Δφ) show slight device to device variations. Also, devices fabricated using different

processes have different technology parameters. This results in deviation of mobility and hence

the device characteristics. The proposed predictive model captures these variations and predicts

the effective mobility for a wide range of back bias. In this section, first, we will explain the

mobility and the threshold voltage extraction method. Then we will derive the effective mobility

model. We conclude this section with discussions on the model validation against measurement

data.

2.2.1 Mobility and Threshold Voltage Extraction

FD-SOI devices from CEA-LETI were used for C-V and I-V measurements. The device chosen

for this work has dimensions: channel length Lg = 10 μm, channel widthWg = 50 μm and front-

gate oxide thickness Tox = 1.2 nm, back gate oxide thickness Tbox = 25 nm and silicon channel

thickness TSi = 8 nm. Measurements are performed at NanoLab, Indian Institute of Technology

Kanpur, India. I-V and C-V measurements are done using Keysights B1500A semiconductor

device parameter analyzer as demonstrated in Fig. 6.3. I-V measurements are done at drain

voltage (Vds) = 10 mV while C-V measurements are done at Vds = 0 V.

2.2.1.1 MOBILITY EXTRACTION BY SPLIT-CV METHOD

Fig. 2.7a shows the variation in gate to channel capacitance (Cgc) as a function of Vfg for

different Vbg. For high positive Vbg (i.e., Region-I), there is a plateau in Cgc - Vfg characteristics.

This plateau indicates the formation of inversion layer at back side channel while there is no

channel formed yet at the front interface [26, 27]. In region II, the front gate voltage is high,

which results in coexistence of front as well as back channel inversion [28]. Fig. 2.7b shows the

variation in drain current Ids with Vfg for different Vbg. As Vbg increases, Vth of device decreases


(a)

(b)

Figure 2.7: The impact of back gate bias on measured Cgc and Ids is illustrated. (a) Cgc vs Vfg charac-

teristic. (b) Ids vs Vfg characteristic. Back gate bias Vbg sweeps from -8 to 8 V with the step size of 2 V.

Device dimensions are: Lg = 10 μm, Wg = 50 μm, Tox = 1.2 nm, Tbox = 25 nm, TSi = 8 nm. All lines

are showing measurement data.


Figure 2.8: Photograph of 200 mm Wafer Characterization Setup from Cascade with Keysights B1500A

semiconductor device parameter analyzer. Photograph of DC probes is illustrated along with the snapshot

of device-under-test (DUT) received from CEA-LETI. Note: The chuck is treated as substrate terminal.

Back-bias tuning is done through the chuck.

which results in high Ids while with negative Vbg, inversion gets delayed and result in reduced

Ids [7]. The split C-V method is widely used for determining the mobility, because it estimates

carrier density accurately [18]. Using this approach, the channel mobility is extracted using the

Cgc vs Vfg characteristics and drain current measurements at different back gate biases [26] as

follows

μ =LeffIds

WeffQinvVds(2.13)

where Weff , Leff are the channel width and length respectively and Cox is front gate oxide

capacitance. Qinv is the charge per unit area which is obtained by integrating the measured Cgc

- Vfg characteristic. To neglect the effect of horizontal electric field on channel mobility, the

measurements were carried out at Vds = 10 mV. Also the mobility curves were corrected for

access resistance Raccess = 2*103 Ω.μm, calculated using Ron(L) method [29]. The corrected

mobility curves show that the Raccess has negligible effect due to the use of long channel length

device. The extracted μ vs Vfg characteristic for different back gate biases are shown in Fig.

2.9a.


(a)

(b)

Figure 2.9: (a) Mobility μ vs Vfg curve, by using definition (2.13). Device dimensions are: Lg = 10 μm,

Wg = 50 μm, Tox = 1.2 nm, Tbox = 25 nm, TSi = 8 nm. All lines are showing measurement data. (b)dCgc

dVfgvs Vfg for different Vbg is illustrated. Device dimensions are: Lg = 10 μm, Wg = 50 μm, Tox = 1.2

nm, Tbox = 25 nm, TSi = 8 nm. All lines are showing measurement data.


Figure 2.10: Vth vs Vbg curve extracted fromdCgc

dVfgvs Vfg characteristic. Device dimensions are: Lg = 10

μm, Wg = 50 μm, Tox = 1.2 nm, Tbox = 25 nm, TSi = 8 nm.

2.2.1.2 Threshold Voltage Extraction

Fig. 2.7b shows that back-gate bias has a significant influence on Vth, thus it is important to

extract Vth accurately. There are several methods available in the literature to obtain threshold

voltage of MOS transistors [30, 31]. The derivative of the gate to channel capacitance method

(see Fig. 2.9b) gives much better resolution in channel separation because it is less sensitive

to series resistance as compared to the current measurements [32]. Extracted threshold voltage

from the peak ofdCgc

dVfgcurve is shown in Fig. 2.10.

2.2.2 Proposed Effective Mobility Model

In a FD-SOI MOSFET, the two boundary conditions from Gauss law at the front- and back-

gates are given as

εsiEs1 = Qf =εoxTox

(Vfg −Δφ1 − ψs1) (2.14)

εsiEs2 = Qb =εoxTbox

(Vbg −Δφ2 − ψs2) (2.15)

where Qf and Qb are the front/back gate charges, respectively. εsi and εox are the silicon and

oxide material permittivity, respectively. Δφ1 and Δφ2 are the work function differences be-

tween the front-gate/back-gate and n+ source junction, Tox and Tbox are the oxide thicknesses at

front- and back-gates, respectively. Es1 and Es2 are the surface electric fields and ψs1 and ψs2


are the surface potentials at the front- and back-gates, respectively.

Es1 =Vfg −Δφ1 − ψs1

3Tox(2.16)

Es2 =Vbg −Δφ2 − ψs2

3Tbox(2.17)

We have assumed ψs1 = ψs2 = 2φf at threshold condition, where φf is the Fermi potential.

Effective mobility (μeff ) can be expressed as a function of Eeff (i.e., average of front and back

surface electric fields). Using (2.16) and (2.17), Eeff becomes

Eeff =1

6Tox

[(Vfg −Δφ− 2φf )− Tox

Tbox(Vbg −Δφ− 2φf )

]

=1

6Tox

[Vfg − Tox

TboxVbg −

(1− Tox

Tbox

)(Δφ+ 2φf )

] (2.18)

where Δφ1 = Δφ2 = Δφ for derivation simplicity. In thin BOX FD-SOI MOSFETs, the techno-

logical variations at the back interface like oxide thickness, interface quality and work-function

play an important role. We have expressed Vbg in terms of threshold voltage Vth which auto-

matically captures all these process variations in our model [33]. This relation also helps in

capturing the effect of back bias on carrier distribution which makes effective mobility curves,

nearly independent of back gate bias. As shown in Fig. 2.10, Vth can be expressed as

Vth = −mVbg + Vth0 (2.19)

where m is representing the slope and Vth0 is the threshold voltage at zero back gate bias. By

incorporating (2.19) in (2.18), we get final expression for Eeff as,

Eeff =1

6Tox

[Vfg +

ToxmTbox

V′th −

(1− Tox

Tbox

)(Δφ+ 2φf )

]

=1

6Tox

[Vfg + αV

′th − β(Δφ+ 2φf )

] (2.20)

where V′th = |Vth| - Vth0 and α = Tox

mTbox, β =

(1− Tox

Tbox

). Here, α and β are taken as model

parameters. To account for different Δφ1 and Δφ2 conditions, β can be tuned further.


(a)

(b)

Figure 2.11: (a) μeff vs Eeff behavior of FD-SOI MOSFET is illustrated. Here, α = 0.72 and β = 1.1,

U0 = 380 cm2/V-s, UA = 0.83 cm/MV and EU = 1.85. Device dimensions are: Lg = 10 μm, Wg = 50 μm,

Tox = 1.2 nm, Tbox = 25 nm, TSi = 8 nm. Black solid line: Predictive Model, Symbols: Measurement

Data. (b) μeff vs Eeff behavior of FD-SOI MOSFET. Device dimensions are: Lg = 10 μm, Wg = 10 μm,

Tox = 1.75 nm, Tbox = 145 nm, TSi = 11 nm. Red solid line: Predictive Model, Symbols: Experimental

Data [32].

2.2.3 Model Validation

The results for mobility discussed in Section 2.2.1 plotted by our proposed model are shown in

Fig. 2.11a. Eeff is negative for Vbg > 0 V and as Vfg increases, the charge centroid shifts from

the back interface to the front interface and Eeff changes it’s sign from negative to positive. In

strong inversion region, the effective mobility curves are converging into the single curve. This

single mobility curve is predicted using our effective mobility model where μeff is a function

2.3 Summary 36

of proposed Eeff as (2.21). The solid black line shown in Fig. 2.11a is predicting the effective

mobility behavior for different back bias.

μeff =U0

1 + UA · |Eeff |EU (2.21)

where Eeff is electric field in MV/cm. U0 is low field mobility parameter while UA and EUparameters are used to capture surface roughness scattering [34]. When amount of inversion

charge is lower in the channel, mobility gets limited by coulomb scattering [35]. Note that

our model does not consider the coulomb scattering. To check the model validity for FD-SOI

MOSFETs with different set of technology parameters (Tox, Tbox and Tsi), we have plotted

proposed μeff vs Eeff for the experimental data obtained from [32]. The model shows good

agreement for this thick BOX FD-SOI MOSFET for a wide range of back bias as shown in Fig.

2.11b. The proposed model is able to predict the mobility for differently processed FD-SOI

MOSFETs as shown in Fig. 2.11a and Fig. 2.11b. These results also show that the inclusion of

threshold voltage in our model makes mobility curves independent of back bias.

2.3 Summary

In this chapter, we have presented an improved surface potential based compact model for FD-

SOI MOSFETs. The model has shown excellent static and dynamic behavior for extreme bias

along with the geometrical scaling. The effective mobility model for FD-SOI MOSFETs is

presented for a wide range of back gate bias. The model demonstrates excellent agreement

with the measured data as well as with the data reported earlier in literature. The novelty in the

proposed model is its dependency, solely on technology parameters which are monitored daily

in the practical engineering world by circuit designers.

Bibliography

[1] Q. Xie, C. J. Lee, J. Xu, C. Wann, J. Sun, and Y. Taur, “Comprehensive Analysis of Short-

Channel Effects in Ultrathin SOI MOSFETs,” IEEE Transactions on Electron Devices,

vol. 60, no. 6, pp. 1814–1819, 2013.

[2] N. Agrawal, Y. Kimura, R. Arghavani, and S. Datta, “Impact of Transistor Architecture

(Bulk Planar, Trigate on Bulk, Ultrathin-Body Planar SOI) and Material (Silicon or IIIV

Semiconductor) on Variation for Logic and SRAM Applications ,” IEEE Transactions onElectron Devices, vol. 60, no. 10, pp. 3298–3304, 2013.



pp. 1–2, 2012.

[4] Y. Morita, R. Tsuchiya, T. Ishigaki, N. Sugii, T. Iwamatsu, T. Ipposhi, H. Oda, Y. Inoue,

K. Torii, and S. Kimura, “Smallest Vth Variability Achieved by Intrinsic Silicon on Thin

BOX (SOTB) CMOS with Single Metal Gate,” in IEEE Symposium on VLSI Technology,

pp. 166 – 167, 2008.








[6] Y. Yang, S. Markov, B. Cheng, A. Zain, X. Liu, and A. Cheng, “Back-Gate Bias Depen-

dence of the Statistical Variability of FDSOI MOSFETs With Thin BOX,” IEEE Transac-tions on Electron Devices, vol. 60, no. 2, pp. 739–745, 2013.





ficient multi-Vt FDSOI technology with UTBOX for low power circuit design,” in IEEESymposium on VLSI Technology, pp. 65–66, 2010.

37

BIBLIOGRAPHY 38


O. Faynot, and S. Cristoloveanu, “Multibranch mobility analysis for the characterization

of FDSOI transistors,” IEEE Electron Device Letters, vol. 33, no. 8, pp. 1102–1104, 2012.









vol. 88, pp. 15–20, 2013.

[11] D. D. Lu, “Compact models for future generation CMOS,” UC Berkeley PhD dissertation,

2011.


B. Y. Nguyen, O. Rozeau, O. Faynot, A. M. Niknejad, and C. C. Hu, “BSIM-IMG: A

Compact Model for Ultra-Thin Body SOI MOSFETs with Back-Gate Control,” IEEETransactions on Electron Devices, vol. 59, no. 8, pp. 2019–2026, 2012.




[14] S. Jandhyala and S. Mahapatra, “An Efficient Robust Algorithm for the Surface-Potential

Calculation of Independent DG MOSFET,” IEEE Transactions on Electron Devices,

vol. 58, no. 6, pp. 1663–1671, 2011.

[15] P. Sebah and X. Gourdon, “Newtons method and high order iterations,” 2001.

[16] C. McAndrew, H. Gummel, and K. Singhal, “Benchmarks for compact MOSFET models,”

1995.

[17] G. Gildenblat, Compact Modeling: Principles, Techniques and Applications. Springer,

2010.

[18] S. Takagi, A. Toriumi, M. Iwase, and H. Tango, “On the universality of inversion layer

mobility in Si MOSFET’s: Part I-effects of substrate impurity concentration,” IEEE Trans-actions on Electron Devices, vol. 41, no. 12, pp. 2357–2362, Dec 1994.

[19] S. Cristoloveanu, N. Rodriguez, and F. Gamiz, “Why the universal mobility is not,” IEEETransactions on Electron Devices, vol. 57, no. 6, pp. 1327–1333, June 2010.

BIBLIOGRAPHY 39

[20] H. Yoshimoto, N. Sugii, D. Hisamoto, S. I. Saito, R. Tsuchiya, and S. Kimura, “Extension

of universal mobility curve to multi-gate MOSFETs,” pp. 703–706, Dec 2007.

[21] A. Ohata, N. Rodriguez, C. Navarro, L. Donetti, F. Gamiz, F. C. Fenouillet-Beranger,

and S. Cristoloveanu, “Impact of back-gate biasing on effective field and mobility in ul-

trathin silicon-on-insulator metal-oxide-semiconductor field-effect-transistors,” Journal ofApplied Physics, vol. 113, pp. 144–514, 2013.

[22] M. J. Sherony, L. T. Su, J. E. Chung, and D. A. Antoniadis, “SOI MOSFET effective

channel mobility,” IEEE Transactions on Electron Devices, vol. 41, no. 2, pp. 276–278,

1994.

[23] H. Zenitani, H. Kikuchihara, U. Feldmann, H. Miyamoto, H. J. Mattausch, M. Miura-

Mattausch, T. Nakagawa, and N. Sugii, “Mobility model for advanced SOI-MOSFETs

including back-gate contribution,” Japanese Journal of Applied Physics, vol. 54, no. 4S,

p. 04DC03, 2015.

[24] O. Nier, D. Rideau, A. Cros, F. Monsieur, G. Ghibaudo, R. Clerc, J. C. Barb, C. Tav-

ernier, and H. Jaouen, “Effective field and universal mobility in high-k metal gate UTBB-

FDSOI devices,” in Proc. of International Conference on Microelectronic Test Structures(ICMTS), pp. 8–13, 2014.

[25] “BSIM3 Technical Manual.” [Online]. Available: http://www-device.eecs.berkeley.edu/

bsim/?page=BSIM3

[26] D. Esseni, M. Mastrapasqua, G. K. Celler, C. Fiegna, L. Selmi, and E. Sangiorgi, “An ex-

perimental study of mobility enhancement in ultrathin SOI transistors operated in double-

gate mode,” IEEE Transactions on Electron Devices, vol. 50, no. 3, pp. 802–808, March

2003.

[27] S. C. Akiko. Ohata and M. Cass, “Mobility comparison between front and back chan-

nels in ultra-thin silicon-on-insulator transistors by the front-gate split capacitance-voltage

method.” Appl Phys Lett, vol. 89, 2006.

[28] J. Chen, R. Solomon, T. Y. Chan, P. K. Ko, and C. Hu, “Threshold voltage and C-V

characteristics of SOI MOSFET’s related to Si film thickness variation on SIMOX wafers,”

IEEE Transactions on Electron Devices, vol. 39, no. 10, pp. 2346–2353, 1992.

[29] B. J. Sheu and P. K. Ko, “A capacitance method to determine channel lengths for conven-

tional and LDD MOSFET’s,” IEEE Electron Device Letters, vol. 5, no. 11, pp. 491–493,

1984.

[30] A. Ortiz-Conde, F. G. Snchez, J. Liou, A. Cerdeira, M. Estrada, and Y. Yue, “A review

of recent MOSFET threshold voltage extraction methods,” Microelectronics Reliability,

vol. 42, no. 4-5, pp. 583 – 596, 2002.

BIBLIOGRAPHY 40

[31] H. Agarwal, C. Gupta, P. Kushwaha, C. Yadav, J. P. Duarte, S. Khandelwal, C. Hu, and

Y. S. Chauhan, “Analytical modeling and experimental validation of threshold voltage in

BSIM6 MOSFET model,” IEEE Journal of Electron Devices Society, vol. 3, no. 3, pp. 240

– 243, 2015.

[32] T. Rudenko, V. Kilchytska, S. Burignat, J.-P. Raskin, F. Andrieu, O. Faynot, Y. L. Tiec,

K. Landry, A. Nazarov, V. Lysenko, and D. Flandre, “Experimental study of transconduc-

tance and mobility behaviors in ultra-thin SOI MOSFETs with standard and thin buried

oxides,” Solid-State Electronics, vol. 54, no. 2, pp. 164 – 170, 2010.

[33] P. Kushwaha, N. Paydavosi, S. Khandelwal, C. Yadav, H. Agarwal, J. P. Duarte, C. Hu,

and Y. S. Chauhan, “Modeling the impact of substrate depletion in FDSOI MOSFETs,”

Solid-State Electronics, vol. 104, no. 0, pp. 6 – 11, 2015.

[34] K. Chain, J. hui Huang, J. Duster, P. K. Ko, and C. Hu, “A MOSFET electron mobility

model of wide temperature range (77-400 k) for IC simulation,” Semiconductor Scienceand Technology, vol. 12, no. 4, p. 355, 1997.

[35] Y. Tsividis, Operation and Modeling of the MOS Transistor., 2013. Oxford, 2013.

Chapter 3

Modeling the Impact of SubstrateDepletion in FD-SOI MOSFETs

Threshold voltage tuning through back-biasing in FD-SOI MOSFETs becomes effective due

to thin BOX beneath the channel which makes it suitable for multi-threshold (Vth) applications

[1–4]. A doped thin layer of silicon (back-plane or BP) is used below the BOX to create different

Vth flavors, i.e, low-Vth and high-Vth (see Fig. 3.1). The doping level of the substrate is used to

be tuned to adjust the threshold voltage of the device [5–8]. Some fraction of the applied back-

gate bias drops in the substrate region and creates depletion in the substrate which changes

the threshold voltage of the device [9]. For ultra-thin BOX, when the electrostatic coupling

is increasing from the back-gate, it is important to include the effect of substrate depletion in

the compact model. In this chapter, we will describe the substrate depletion modeling and its

validation against measured data for a wide range of back-gate biases.

3.1 Modeling of Substrate Depletion Effect

In this section, we have modeled the substrate depletion effect. The proposed model is then

incorporated into the surface-potential based BSIM-IMG model accounting for the shift in the

threshold voltage via the correction factor, VTbg. The concept of poly depletion effect is used to

derive VTbg. We assume the back interface (thin BOX/substrate) analogous to the poly-Si gate

with silicon channel [10]. After applying Gauss’s law and the substrate depletion effect at the

thin BOX/substrate interface, we get

εoxEbox = εSiEsubdep =√2εSiqNsubVsubdep (3.1)

41

3.1 Modeling of Substrate Depletion Effect 42

(a)

(b)

Figure 3.1: (a) Schematic of a fully depleted silicon on insulator (FD-SOI) MOSFET [11]. To have back-

baising, the front side contact is used to the substrate/well [12]. A shallow p++/n++ implant is performed

below BOX to form a thin back-plane (BP) layer over a p-type substrate. Doping level difference between

the BP and silicon body is used for a desired dynamic VT shift. (b) An illustration of four regions where

the back-gate potential drops: (i) workfunction difference between the back-gate and n+ source junction

(Δφ2), source is taken as common terminal; (ii) substrate depletion below the BOX (Vsubdep); (iii)

potential drop across the back-oxide (Vbox); (iv) back-gate surface potential (ψs2).

where q is the electron charge, εSi and εox are relative permittivity of silicon and the oxide

respectively, Nsub is the substrate doping and it can be n-type or p-type, Esubdep is the electric

field, Vsubdep is the potential drop in the substrate just below the BOX due to the back-bias,

Ebox = Vbox

Tboxis the electric field, Vbox is the potential drop across the back-oxide, and Tbox is

the back-oxide (BOX) thickness. Fig. 3.1b shows four regions where the applied back-gate

potential (Vbg) drops.

Vbg = Δφ2 + Vbox + ψs2 + Vsubdep (3.2)

After solving (3.1) and (3.2), the potential drop in the substrate due to the back-bias is


calculated to be

Vsubdep = Vsubdep0

⎛⎝√

1 +(V ∗

bg − ψs2)

Vsubdep0− 1

⎞⎠

2

(3.3)

where Vsubdep0 = qεSiNsub

2C2box

, V ∗bg = Vbg −Δφ2 is the back gate voltage. To have more flexibility

during parameter extraction, we have replaced ψs2 by a fitting parameter VKNEE1 in (3.3) as

shown below:

Vsubdep = Vsubdep0

⎛⎝√

1 +(V ∗

bg −VKNEE1)

Vsubdep0− 1

⎞⎠

2

(3.4)

Parameter VKNEE1 captures the back gate voltage at which the substrate depletion takes

place below BOX. Using (3.4), the shift in threshold voltage due to the substrate depletion is

calculated as follows:

VTbg = γL[V ∗bg − (BPFACTOR · Vsubdep)

](3.5)

where γL = γ0 · KVbg is the gamma factor and is used to capture the length scaling with the

substrate depletion effect. γ0 = − Csi·Cbox

(Csi+Cbox)·Coxis the capacitive coupling ratio between the

body and the back-gate capacitance with the front-gate capacitance. Parameter BPFACTOR is

used to invoke the effect of BP doping in the model.

KVbg = min

(KBG2,

(KBG0+

0.5 ∗KBG1

cosh(DBG∗Leff

λ)− 1

))(3.6)

where KBG0, KBG1, KBG2 and DBG are fitting parameters, λ is the characteristic length

[13], and Leff is the effective front-gate channel length. Equation (3.6) shows that the term

cosh(DBG∗Leff

λ) has higher value when Leff > λ in comparison to the case when Leff < λ. It

results in higher γL value for long channel devices as compared to short channel devices (Fig.

3.2) which implies that the shift in the threshold voltage decreases as the gate length scales

down. The effective front-gate voltage can be written as

Vfgeff = V ∗fg − VTbg (3.7)

where V ∗fg = Vfg − Δφ1 is the front-gate voltage and Δφ1 is the work function differences be-

tween the front-gate and n+ source junction. The substrate depletion effect in the BSIM-IMG

model is captured by using a modified front-gate voltage from (3.7) into the front-gate surface-

potential calculation [14]. Fig. 3.3 shows that the substrate depletion effect reduces when a


Figure 3.2: Gamma factor γL at various gate lengths for FD-SOI at Vbg = 0 V and Vds = 0.05 V. Symbols:

TCAD Data, Line: the BSIM-IMG model.

highly doped back-plane is used in place of lightly doped back-plane. The threshold voltage

deviates from straight line behavior with the lightly doped back-plane due to the substrate de-

pletion effect (i.e the effective BOX thickness increases which increases threshold voltage in

comparison to a highly doped back-plane). Parameter VKNEE1 is used to set the back-gate

voltage at which measured data starts deviating from straight line behavior as shown in Fig. 3.3.

Fig. 3.4 shows the threshold voltage shift as a function of the back-gate bias for different BP

combinations. It indicates that an NMOS device (or a PMOS device) with an n-type back-plane

has a lower threshold voltage in comparison to an NMOS device (or a PMOS device) with a

p-type back-plane due to the workfunction difference between the channel and BOX/substrate

interface [10]. Fig. 3.5 shows the impact of substrate biasing on channel region. For an NMOS

device, with 0V < Vbg < Vdd (-Vdd < Vbg < 0V for a PMOS device), the BOX/substrate

interface gets depleted and for Vbg < 0V (Vbg > 0V for a PMOS devices), the BOX/substrate

interface gets inverted, both the former cases delay inversion in the channel which increases

the threshold voltage of the device. For Vbg > Vdd (Vbg < −Vdd for a PMOS device), the

BOX/substrate interface gets accumulated which assists inversion in the channel and lowers

the threshold voltage of the device [15, 16]. The impact of substrate depletion effect increases

with reduction in BOX thickness due to the increment of back-side coupling. The model has

captured substrate depletion effect with BOX thickness variation as shown in Fig. 3.6.

3.2 TCAD Calibration Against Experimental Data 45

Figure 3.3: Threshold voltage shift vs. the back-gate voltage Vbg, for three NMOSs, one with a highly

doped n-type back-plane (1018cm−3) and other two with a moderately (1017cm−3) and lightly doped

(1016cm−3) n-type back-plane. The substrate depletion effect reduces with increase in back-plane dop-

ing. Symbols: TCAD Data, Lines: the BSIM-IMG model.

3.2 TCAD Calibration Against Experimental Data

To study the substrate depletion effect in FD-SOI MOSFETs, we have done two dimensional

(2D) technology computer aided design (TCAD) simulations using Silvaco-ATLAS tool [18]

as shown in Fig. 3.7a. Lombardi CVT model [19] and Uchida’s low-field model [20] are

used to capture the mobility degradation in FD-SOI MOSFETs. Mobility model parameters

for drift-diffusion transport, and the impact of fixed oxide charges in sub-threshold region are

calibrated against the measurement data obtained from LEAP, Japan [1]. Fig. 3.7b shows the

good agreement of the TCAD results with the measurement data for a transistor with Lg = 961

nm, Wg = 10 μm.

3.3 Parameter Extraction and Model Validation

Parameter extraction and model validation is an important part of model development. In this

section, first, we will discuss parameter extraction flow and then discuss the model validation

results at different back-biases and temperatures, respectively. Fig. 3.8 shows the parameter

extraction procedure [21] adopted in this work. Agilent ICCAP tool is used to validate the model

against the measurement data. To utilize multi-threshold characteristics of FD-SOI MOSFETs,

3.3 Parameter Extraction and Model Validation 46

-1.0 -0.5 0.0 0.5 1.00.0

0.1

0.2

0.3

0.4

0.5

0.6

BP-P BP-N

Symbols - Measured DataLines - Model

Thre

shol

d V

olta

ge S

hift

(V)

Back Gate Voltage (V)

NMOSLg= 35 nm

(a)

-1.0 -0.5 0.0 0.5 1.0-0.7

-0.6

-0.5

-0.4

-0.3

-0.2

-0.1

0.0

BP-P BP-N


Thre

shol

d V

olta

ge S

hift

(V)

Back Gate Voltage (V)

PMOSLg = 35 nm

(b)

Figure 3.4: Threshold voltage shift vs. the back-gate voltage Vbg. (a) Two NMOSs, one with a p-type

back-plane BP-P and one with an n-type back-plane BP-N are shown. (b) Two PMOSs, one with a p-

type back-plane BP-P and one with an n-type back-plane BP-N are shown. The substrate depletion effect

is turned on in the model as parameter BPFACTOR �= 0. Symbols: Data [17], Lines: the BSIM-IMG

model.


Figure 3.5: Case 1: For Vbg < 0 V, the substrate goes in inversion region and shifts the channel in accu-

mulation region which results in higher device threshold voltage. Case 2: For Vbg � Vdd, the substrate

goes in accumulation region and shifts the channel in inversion region which results in lower device

threshold voltage. Case 3: For 0 V < Vbg < Vdd, the substrate goes in the depletion which delays the

inversion in the channel. Line: TCAD Data.

Figure 3.6: Threshold voltage shift vs. the back-gate voltage Vbg, for three NMOSs with p-type back-

plane (1016cm−3), two with thick BOX (300 nm, 100 nm) and one with thin BOX (10 nm). The substrate

depletion effect increases with reduction in BOX thickness. Symbols: TCAD Data, Lines: the BSIM-

IMG model.


(a)

0.0 0.2 0.4 0.6 0.8 1.0 1.210-9

10-7

10-5

10-3

10-1

NMOS

I ds (m

A)

Vfg (V)

Symbols: Measured DataLines : TCAD Data

0.00

0.25

0.50

0.75

Vds = 0.05 V Vds = 1.2 V

Ids (mA

)

(b)

Figure 3.7: (a) Calibration of TCAD models for drift diffusion transport with experimental data [1].

TCAD device parameters are: gate work function = 4.9 eV, source/ drain Doping = 1e20 cm−3, body

doping = 1e15 cm−3, interface charge = 16e10 cm−2, source resistance = 200 Ω · μm. Device dimen-

sions are: Channel length Lg = 961 nm, Gate width Wg = 10 μm, Effective oxide thickness Tox = 2.4

nm, Back gate oxide thickness Tbox = 10 nm, Channel silicon thickness Tsi = 12 nm. (b) Drain current

Ids vs front gate bias Vfg characteristics from the measurement and calibrated TCAD simulations. Bias

conditions are: Front gate voltage Vfg = 0 to 1.2 V, Back gate voltage is Vbg = 0 V, Drain voltage Vds =

0.05, 1.2 V. Lines: TCAD data, Symbols: Measured data.


Step 1: Cgg vs. Vfg character-

istics @ Vds = 0 V, Vbg = 0 V

Step 2: Ids vs. Vfg characteristics

@ Vds = 0.05 V with different Vbg

Step 3: Ids vs. Vfg characteristics

@ Vds = 1.5 V with different Vbg

Step 4: Ids vs. Vds characteristics

@ Vbg = 0 V with different Vfg

Step 5: Ids vs. Vds characteristics

@ fix Vbg with different Vfg

Figure 3.8: An illustration of DC parameter extraction flow in FD-SOI MOSFETs.

the developed model for substrate depletion effect due to back biasing in Section 3.1 is validated

against the state-of-the-art 50 nm silicon on thin box (SOTB) technology, over a wide range of

biases and temperatures and at different channel lengths, for both NMOS and PMOS devices.

The electrical data were collected by LEAP on the same wafer as in [1] fabricated by Hitachi

and Renesas. Fig. 3.9 shows the model’s C-V characteristics validation with experimental

data for NMOS and PMOS at Vbg = 0 V and |Vds| = 0 V from long L = 961 nm to short L =

52 nm device dimensions. We have extracted physical oxide thickness (EOT1P, EOT2P) and

workfunction (PHIG1, PHIG2) from Fig. 3.9. The model is showing correct behavior for all

capacitances in all regions of operation from depletion to inversion. In short channel devices,

the dominance of source-drain charge sharing and parasitic capacitance (overlap and fringing)

become necessary, as a result, gate capacitance increases in depletion region as shown in Fig.

3.9. The threshold voltage shift with length scaling at different back-biases (Vbg = 0, 1, -1 V)

for |Vds| = 0.05 V and |Vds| = 1.5 V is shown in Fig. 3.10.

It is clear from Fig. 3.10a that the threshold voltage becomes lower in NMOS device for

|Vds| = 1.5 V in comparison to the threshold voltage at |Vds| = 0.05 V due to drain induced barrier

lowering effect. For NMOS device, in the condition of reverse back-bias Vbg = -1 V, inversion

get delayed due to depletion at the back-interface, as a result the threshold voltage of the device

increases in comparison to zero back-bias (Vbg = 0 V); whereas in the case of forward back-bias

(Vbg = 1 V), inversion comes earlier in comparison to zero back bias (Vbg = 0 V), as a result

the threshold voltage of the device decreases as shown in Fig. 3.10a and vice-versa for PMOS

device as shown in Fig. 3.10b. The drain current behavior in linear and subthreshold regions


-0.5 0.0 0.5 1.00

11

22

33

NMOS


Vds

=0.0VV

bg=0.0V

Gat

e C

apac

itanc

e (p

F/μm

)


L=961 nm, 344 nm, 56 nm

(a)

-1.0 -0.5 0.0 0.50

11

22

33


Vds

=0.0VV

bg=0.0V

Gat

e C

apac

itanc

e (p

F/μm

)


L=961 nm, 344 nm, 56 nm

PMOS

(b)

Figure 3.9: Normalized total gate capacitance Cfgfg vs. Vfg at Vbg = 0.0V . (a) NMOS device and (b)

PMOS device, with device dimensions (W = 2160 μm, L = 961 nm),(W = 3360 μm, L = 344 nm) and

(W = 4800 μm, L = 56 nm) Symbols: Data [1], Lines: the BSIM-IMG model.


0.1 10.0

0.2

0.4

0.6

0.8

1.0

Vds = 0.05 V Vds = 1.5 V

|Vds

| = 1.5 V

Symbols - Measured DataSolid Lines - Model with Sub-dep effectDotted Lines - Model w/o Sub-dep effect

Vbg

=1, 0, -1 V

Thre

shol

d V

olta

ge (V

)

Gate Length (nm)

NMOS

|Vds

| = 0.05 V

(a)

0.1 1-0.9

-0.8

-0.7

-0.6

-0.5

-0.4

-0.3

-0.2

-0.1

0.0

|Vds| = 0.05 V |Vds| = 1.5 V

|Vds

| = 1.5 V

Symbols - Measured DataSolid Lines - Model with Sub-dep effectDotted Lines - Model w/o Sub-dep effect

Vbg

= -1, 0, 1 V

Thre

shol

d V

olta

ge (V

)

Gate Length (nm)

PMOS

|Vds

| = 0.05 V

(b)

Figure 3.10: (a) Threshold voltage vs. Lset characteristics for NMOS device at different back-bais

Vbg=[-1, 0, 1] V at Vds = 0.05 V and 1.5 V. (b) Threshold voltage vs. Lset characteristics for PMOS

device at different back-bais Vbg=[-1, 0, 1] V at |Vds| = 0.05 V and 1.5 V. Dotted lines are showing

that the substrate depletion effect is turned off in the model as parameter BPFACTOR = 0. Solid lines

are showing that the substrate depletion effect is turned on in the model as parameter BPFACTOR �= 0.

Symbols: Data [1], Lines: the BSIM-IMG model.


-1.0 -0.5 0.0 0.510-14

10-9

10-4

Vbg= - 1, 0, 1 V T= 25°C

PMOS

|Vds| = 50 mV

I ds (m

A)



L = 961 nmW = 10 μm

0.00

0.02

0.04

Ids (mA

)

Vbg= - 1, 0, 1 V

(a)

-1.0 -0.5 0.0 0.50.00

0.02

0.04

0.06

0.08 PMOS

|Vds| = 50 mV

g m (m

A/V

)



L = 961 nmW = 10 μm

Vbg= - 1, 0, 1 V

T= 25°C

(b)

Figure 3.11: Back-bias tuning Vbg = [-1, 0, 1] V. (a) Ids vs. Vfg characteristics for channel lengths L =

961 nm at |Vds| = 0.05 V. (b) Transconductance (gm) vs. Vfg characteristics for channel lengths L = 961

nm at |Vds| = 0.05 V. Symbols: Data [1], Lines: the BSIM-IMG model.

with respect to the front-gate voltage is shown in Fig. 3.11a and Fig. 3.12a for the different

back-gate biases at |Vds| = 0.05 V. In PMOS device, the drain current decreases with a positive

back-bias (Vbg = 1 V) due to a higher threshold voltage while it increases with negative back-

bias (Vbg = -1 V) due to a lower threshold voltage as shown in Fig. 3.11a and Fig. 3.12a. As

channel length shrinks to 52nm, the current increases due to Vt-roll off and other short channel

effects. For short channel devices, the good agreement of the model with the experimental data


-1.0 -0.5 0.0 0.510-14

10-9

10-4

T= 25°C PMOS

|Vds| = 50 mV

I ds (m

A)



L = 52 nmW = 10 μm

Vbg= - 1, 0, 1 V

Vbg= - 1, 0, 1 V

0.0

0.1

0.2

0.3

0.4

0.5

Ids (mA

)

(a)

-1.0 -0.5 0.0 0.50.0

0.2

0.4

0.6

0.8

1.0PMOS

|Vds| = 50 mV

g m (m

A/V

)



L = 52 nmW = 10 μm

Vbg= - 1, 0, 1 V

T= 25°C

(b)

Figure 3.12: Back-bias tuning Vbg = [-1, 0, 1] V. (a) Ids vs. Vfg characteristics for channel lengths L =

52 nm at |Vds| = 0.05 V. (b) Transconductance (gm) vs. Vfg characteristics for channel lengths L = 52 nm

at |Vds| = 0.05 V. Symbols: Data [1], Lines: the BSIM-IMG model.

indicates that the model incorporates short channel effects very well (see Fig. 3.12a and Fig.

3.15a). Current derivatives of a model are important for digital and analog applications. The

BSIM-IMG model has continuous behavior for the transconductance gm as shown in Fig. 3.11b

and Fig. 3.12b. The model also shows good agreement with the experimental data for higher

order current derivatives (see Fig. 3.13). Good agreement of gm and gds (see Fig. 3.14b and

Fig. 3.15b) with experimental data ensures efficient implementation of the mobility and current


-1.0 -0.5 0.0 0.5

-0.4

-0.2

0.0

PMOS

|Vds| = 50 mV

g m' (

mA

/V2 )



L = 961 nmW = 10 μm

Vbg= - 1, 0, 1 V

T= 25°C

(a)

-1.0 -0.5 0.0 0.5

-3

-2

-1

0

1

2

3 PMOS|Vds| = 50 mV

g m''

(mA

/V3 )


Lines : Our ModelSymbols: Measured Data

L = 961 nmW = 10 μm

Vbg= - 1, 0, 1 V T= 25°C

(b)

Figure 3.13: Back-bias tuning Vbg = [-1, 0, 1] V. (a) Second derivative of drain current gm′ vs. Vfg

characteristics for channel lengths L = 961 nm at |Vds| = 0.05 V. (b) Third derivative of drain current gm′′

vs. Vfg characteristics for channel lengths L = 961 nm at |Vds| = 0.05 V. Symbols: Data [1], Lines: the

BSIM-IMG model.


-1.0 -0.5 0.00.00

0.04

0.08

0.12

0.16

0.20PMOS

|Vfg| = 1.2 V

I ds (m

A)

Drain Voltage (V)


L = 961 nmW = 10 μm

Vbg= - 1, 0, 1 V

T= 25°C

(a)

-1.0 -0.5 0.0

10-3

10-2

10-1

100PMOS

|Vfg| = 1.2 V

g ds (m

A/V

)

Drain Voltage (V)


L = 961 nmW = 10 μm

Vbg= - 1, 0, 1 V

T= 25°C

(b)

Figure 3.14: (a) The drain current Ids vs. the drain voltage (Vds) for channel lengths Leff = 961 nm at

|Vfg| = 1.2 V. (b) The output conductance gds vs. Vds for channel lengths Leff = 961 nm at |Vfg| = 1.2 V.



-1.0 -0.5 0.00.0

0.4

0.8

1.2

1.6

2.0

2.4PMOS

|Vfg| = 1.2 V

I ds (m

A)

Drain Voltage (V)


L = 52 nmW = 10 μm

Vbg= - 1, 0, 1 V

T= 25°C

(a)

-1.0 -0.5 0.00.1

1

10PMOS

|Vfg| = 1.2 V

g ds (m

A/V

)

Drain Voltage (V)


L = 52 nmW = 10 μm

Vbg= - 1, 0, 1 V

T= 25°C

(b)

Figure 3.15: (a) The drain current Ids vs. the drain voltage (Vds) for channel lengths Leff = 52 nm at

|Vfg| = 1.2 V. (b) The output conductance gds vs. Vds for channel lengths Leff = 52 nm at |Vfg| = 1.2 V.



0.1 10.0

0.1

0.2

0.3

0.4

0.5

0.6

|Vds| = 50 mV |Vds| = 1.5 V

NMOS

Thre

shol

d V

olta

ge (V

)

Gate Length (nm)


T= - 40, 25, 85 °C

(a)

0.1 1

-0.60

-0.55

-0.50

-0.45

-0.40

-0.35

-0.30

|Vds| = 50 mV |Vds| = 1.5 V

PMOS

Thre

shol

d V

olta

ge (V

)

Gate Length (nm)


T= - 40, 25, 85 °C

(b)

Figure 3.16: (a) Threshold voltage vs. Lset characteristics for NMOS device at different temperatures T =

-40, 25, 85 ◦C. (b) Threshold voltage vs. Lset characteristics for PMOS device at different temperatures

T = -40, 25, 85 ◦C. Bias conditions are: |Vds| = 0.05 V and 1.5 V and Vbg = 0 V. Symbols: Data [1],



-1.0 -0.5 0.0 0.510-9

10-4

T = 85°C

T = -40°C

Vbg = 0 V

PMOS

|Vds| = 50 mVI ds (m

A)



L = 961 nmW = 10 μm

0.00

0.02

0.04Ids (m

A)

T= - 40°C,25°C,85°C

(a)

-1.0 -0.5 0.0 0.510-12

10-7

10-2

T = 85°C

T = -40°C

Vbg = 0 V

PMOS|Vds| = 50 mV

I ds (m

A)


Lines : Our ModelSymbols: Measured Data

L=52 nmW=10 μm

T= - 40°C,25°C,85°C

0.0

0.1

0.2

0.3

0.4

0.5

Ids (mA

)

(b)

Figure 3.17: (a) Ids vs. Vfg characteristics for L = 961 nm in logarithmic and linear scale with temperature

set at T = -40, 25, 85◦C. (b) Ids vs. Vfg characteristics for L = 52 nm in logarithmic and linear scale with

temperature set at T = -40, 25, 85◦C. Bias conditions are: |Vds| = 0.05 V (linear mode) and Vbg = 0 V.


3.4 Summary 59

saturation sub-modules.

Fig. 3.16 and 3.17 show the BSIM-IMG model’s scalability with temperature for the threshold

voltage and the drain current. The threshold voltage variation in NMOS and PMOS devices with

various temperatures for different channel lengths are shown in Fig. 3.16 at |Vds| = 0.05 V and

1.5 V. The bandgap of material reduces at higher temperatures (85 ◦C) thus the inversion condi-

tion occurs at lower gate voltages and vice versa at low temperature (−40 ◦C). From Fig. 3.16,

it is clear that the threshold voltage variation with temperature is in the good agreement with

data for all channel lengths except L = 344 nm in NMOS device, which shows that experimen-

tal data for L = 344 nm is a little bit poor. Fig. 3.17 demonstrates that at higher temperatures,

current decreases for higher values of the front-gate voltage due to the reduction in mobility,

while it increases for lower values of the front gate voltage due to less surface roughness scat-

tering [22]. Hence model is showing correct behavior of temperature variation on drain current

for long and short channel devices.

3.4 Summary

In this chapter, we have modeled the impact of substrate depletion in fully-depleted silicon-

on-insulator (FD-SOI) MOSFET and have extensively verified the model for both NMOS and

PMOS with geometrical and temperature scaling. The model has an accurate behavior for C-V

and I-V characteristics and preserves the smooth behavior of the high order derivatives of drain

current.

Bibliography



BOX (SOTB) CMOS with Single Metal Gate,” VLSI Technology, IEEE Symposium on,

pp. 166 – 167, 2008.










pp. 1–2, 2012.

[4] Y. Yang, S. Markov, B. Cheng, A. Zain, X. Liu, and A. Cheng, “Back-Gate Bias Depen-

dence of the Statistical Variability of FDSOI MOSFETs With Thin BOX,” IEEE TransElectron Devices, vol. 60, no. 2, pp. 739–745, 2013.





ficient Multi-Vt FDSOI technology with UTBOX for low power circuit design,” VLSITechnology Digest of Technical Papers, IEEE Symposium on, pp. 65 – 66, 2010.


O. Faynot, and S. Cristoloveanu, “Multibranch Mobility Analysis for the characteriza-

tion of FDSOI Transistors,” IEEE Electron Device Letters, vol. 33, no. 8, pp. 1102–1104,

2012.



60

BIBLIOGRAPHY 61







vol. 88, pp. 15–20, 2013.

[9] A. Kumar and P. K. Tiwari, “A threshold voltage model of short-channel fully-depleted

recessed-source/drain (Re-S/D) UTB SOI MOSFETs including substrate induced surface

potential effects,” Solid-State Electronics, vol. 95, pp. 52–60, 2014.

[10] J. Noel, O.Thomas, C. F. Beranger, M. A. Jaud, P. Scheiblin, and A. Amara, “A sim-

ple and efficient concept for setting up multi-Vt devices in thin BOX fully-depleted SOI

technology,” pp. 137–140, 2009.

[11] N. Paydavosi, S. Venugopalan, Y. S. Chauhan, J. P. Duarte, S. Jandhyala, A. M. Nikne-

jad, and C. C. Hu, “BSIM - SPICE Models Enable FinFET and UTB IC Designs,” IEEEAccess, vol. 1, no. 3, pp. 201–215, 2013.

[12] L. Grenouillet, Q. Liu, R. Wacquez, P. Morin, N. Loubet, D. Cooper, A. Pofelski,

W. Weng, F. Bauman, M. Gribelyuk, Y. Wang, B. D. Salvo, J. Gimbert, K. Cheng, Y. L.

Tiec, D. Chanemougame, E. Augendre, S. Maitrejean, A. Khakifirooz, J. Kuss, R. Schulz,

C. Janicki, B. Lherron, S. Guillaumet, O. Rozeau, F. Chafik, J. L. Bataillon, T. Wu,

W. Kleemeier, M. Celik, O. Faynot, R. Sampson, B. Doris, and M. Vinet, “UTBB FD-

SOI scaling enablers for the 10nm node,” pp. 1–2, Oct 2013.

[13] K. Suzuki, T. Tanaka, Y. Tosaka, H. Horie, and Y. Arimoto, “Scaling theory for double-

gate SOI MOSFETs,” IEEE Transactions on Electron Devices, vol. 40, no. 12, pp. 2326–

2329, 1993.


B. Y. Nguyen, O. Rozeau, O. Faynot, A. M. Niknejad, and C. C. Hu, “BSIM-IMG: A

Compact Model for Ultra-Thin Body SOI MOSFETs with Back-Gate Control,” IEEETransactions on Electron Devices, vol. 59, no. 8, pp. 2019–2026, 2012.

[15] F. Andrieu, O. Weber, J. Mazurier, O. Thomas, J. P. Noel, C. Fenouillet-Branger, J. P.

Mazellier, P. Perreau, T. Poiroux, Y. Morand, T. Morel, S. Allegret, V. Loup, S. Barnola,

F. Martin, J. F. Damlencourt, I. Servin, M. Cass, X. Garros, O. Rozeau, M. A. Jaud,

G. Cibrario, J. Cluzel, A. Toffoli, F. Allain, R. Kies, D. Lafond, V. Delaye, C. Tabone,

L. Tosti, L. Brvard, P. Gaud, V. Paruchuri, K. K. Bourdelle, W. Schwarzenbach, O. Bonnin,

B. Y. Nguyen, B. Doris, F. Boeuf, T. Skotnicki, and O. Faynot, “Low leakage and low

variability ultra-thin body and buried oxide (UT2B) SOI technology for 20nm low power

CMOS and beyond,” pp. 57–58, June 2010.

BIBLIOGRAPHY 62

[16] J. P. Noel, O. Thomas, M. A. Jaud, O. Weber, T. Poiroux, C. Fenouillet-Beranger, P. Ri-

vallin, P. Scheiblin, F. Andrieu, M. Vinet, O. Rozeau, F. Boeuf, O. Faynot, and A. Amara,

“Multi-Vt UTBB FDSOI device architectures for low-power CMOS circuit,” IEEE TransElectron Devices, vol. 58, no. 8, pp. 2473–2482, Aug 2011.

[17] C. Fenouillet-Beranger, P. Perreau, L. Tosti, O. Thomas, J. P. Noel, O. Weber, F. Andrieu,

M. Cass, X. Garros, T. Benoist, S. Haendler, A. Bajolet, F. Buf, K. K. Bourdelle, F. Boedt,

and O. Faynot, “Low power UTBOX and back plane (BP) FDSOI technology for 32nm

node and below,” pp. 1–4, May 2011.

[18] “Atlas users manual.” [Online]. Available: https://dynamic.silvaco.com/dynamicweb/jsp/

downloads/DownloadManualsAction.do?req=silen-manuals&nm=atlas

[19] C. Lombardi, S. Manzini, A. Saporito, and M. Vanzi, “A Physically Based Mobility Model

for Numerical Simulation of NonPlanar Devices,” IEEE Trans. on CAD, p. 1164, 1988.

[20] K. Uchida and S. Takagi, “Carrier scattering induced by thickness fluctuation of silicon-

on-insulator film in ultrathin-body metal-oxide-semiconductor field-effect transistors,”

Applied Phys. Lett., vol. 82, no. 17, pp. 2916–2918, 2003.

[21] “BSIM3 Technical Manual.” [Online]. Available: http://ngspice.sourceforge.net/

external-documents/models/bsim330 manual.pdf

[22] Y. Tsividis, Operation and Modeling of the MOS Transistor., 2013. Oxford, 2013.

Chapter 4

Thermal Resistance Modeling in FD-SOIMOSFETs

The bulk MOSFET has driven the semiconductor industry for decades, thanks to scaling. How-

ever, scaling in sub-micron regime is very challenging due to reduced gate control, random

dopant fluctuation and various short channel effects [1]. Thin buried oxide (BOX) fully de-

pleted silicon-on-insulator (FD-SOI) devices (see Fig. 4.1) offer good electrostatic control over

the channel region and have threshold voltage tuning facility through back-bias [2–6]. However,

they are subjected to more device heating as compared to the bulk MOSFETs [7–9] due to the

following reasons: (i) The complete isolation of the channel from the substrate via buried oxide

(BOX) and from the sides by shallow trench isolations (STI). (ii) The lower thermal conductiv-

ity of BOX and STI materials. These reasons lead to higher device temperature and hence de-

grades device parameters like bandgap, intrinsic carrier concentration, threshold voltage, carrier

mobility and carrier saturation velocity, etc. [10]. This degradation in device parameters gets

reflected in the reduction of the drain current. Thus, there is an urgent need for a robust thermal

resistance (Rth) model for FD-SOI MOSFETs. Work [11] has developed a compact model for

FD-SOI MOSFETs which assumes constant Rth with length scaling in its self-heating network

(i.e., Rth − Cth equivalent circuit). From TCAD simulations, we observed that with channel

length scaling, the heat dissipation in the channel increases which further increases Rth. Thus,

in this chapter, we have extended our work and proposed a model for the geometrical depen-

dence of Rth (see Fig. 4.2) after extensive analysis of 3D TCAD simulation data. We close this

chapter with the discussion on the model validation results after including the proposed model

in the BSIM-IMG model [12, 13].

63

4.1 Device Structure and Simulation Setup 64

(a) FD-SOI MOSFET: 3D View

(b) Cross section view of 3D-Device

Figure 4.1: Fully Depleted Silicon On Insulator (FD-SOI) MOSFET structure using Sentaurus Technol-

ogy Computer Aided Design (TCAD) Tool [14].

4.1 Device Structure and Simulation Setup

We have investigated the self heating behavior of FD-SOI MOSFET using Sentaurus technol-

ogy computer aided design (TCAD) tool [14] (see Fig. 4.1). Mobility model parameters for

drift-diffusion transport, confinement of carrier distributions near Si/SiO2 interfaces (due to

thin oxide, Tox1 = 1.9 nm) and the impact of fixed oxide charges in sub-threshold region are

calibrated with experimental data received from LEAP Japan’s FD-SOI technology [15] in our

TCAD simulations. The calibration result with experimental data for Lg = 52 nm, Wg = 10

μm is shown in Fig. 4.3. The thermal boundary resistance (TBR) influences the temperature

4.2 Thermal Resistance behavior and Modeling 65

Figure 4.2: Rth − Cth Network for modeling of Self-Heating effect [18]. Rth and Cth are the thermal

resistance and capacitance of the thermal network, respectively. ΔT = TDEV ICE − TNOM is the

temperature rise where TDEV ICE and TNOM are the device and ambient temperature, respectively. P

is the power dissipated (P = IdsVds) in the device where Ids and Vds are the drain current and drain

voltage, respectively [19].

distribution in FD-SOI MOSFETs. Thus we have calculated TBR (layer thickness / thermal

conductivity) at each interface (Si/SiO2, Si/contact) as discussed in [16]. The device un-

der test has channel silicon thickness Tsi = 12 nm and therefore, thermal conductivity ksi =

15 W/mK is used for TCAD simulations [17].

4.2 Thermal Resistance behavior and Modeling

Fig. 4.4 and Fig. 4.5 show heat flux in the long and wide channel device with Lg =Wg = 10 μm,

and short channel device with Lg = 30 nm, Wg = 10 μm, respectively. In long channel device,

heat dissipation through the top contacts (i.e., source/drain and gate contacts) is negligible as

compared to the substrate because of large channel area [20, 21]. However, at shorter channel

length, heat flow through the top contacts becomes significant as compared to the heat flow

from the substrate because channel area shrinks at shorter channel length while the contacts do

not. Fig. 4.6 compares the rise in temperature (ΔT ) at the same power dissipation level for

two channel lengths. It is clearly observed that thermal resistance, which is the slope of ΔT vs.

power characteristics, is larger for shorter length device as compared to longer channel length

device. Different dominant paths for heat flow at different channel lengths lead to geometrical

dependence of Rth [22]. To capture this geometrical dependency of Rth, we have developed a

behavioral model based on the results obtained from TCAD and experimental data.


Figure 4.3: Calibration of TCAD models for drift diffusion transport with experimental data of FD-SOI

MOSFET. Device dimensions are: Channel length Lg= 52 nm, Gate width Wg= 10 μm, Front gate oxide

thickness Tox= 1.9 nm, Back gate oxide thickness Tbox= 10 nm, Channel silicon thickness Tsi= 12 nm.

Bias conditions are: Front gate voltage Vfg= 0 to 1.1 V, Back gate voltage Vbg= 0 V, Drain voltage Vds=

0.05, 1.2 V. Symbols: Experimental Data, Lines: TCAD Data. Experimental Data is from LEAP Japan’s

FD-SOI technology [15].

Figure 4.4: Device dimensions are: Lg = Wg = 10 μm. For long channel length devices, the heat

dissipates more through the substrate. Long channel length/width device is studied to show that the

self-heating effect is negligible in such MOSFETs. Bias conditions are: Vds= 1.0 V, Vfg= 1.2 V, Vbg= 0

V.


Figure 4.5: Device dimensions are: Lg = 30 nm, Wg = 10 μm. For short channel length devices, substrate

heat dissipation becomes comparable to the top contacts dissipation. Bias conditions are: Vds= 1.0 V,

Vfg= 1.2 V, Vbg= 0 V.

Figure 4.6: ΔT vs. power dissipation (P) normalized by gate width. For same power dissipation level,

short channel length device experiences more ΔT as compared to long channel length device, indicating

higher Rth. TNOM and TDEV ICE are the ambient and device temperatures, respectively. Device dimen-

sions are: Gate width Wg= 10 μm, Front gate oxide thickness Tox= 1.9 nm, Back gate oxide thickness

Tbox= 10 nm, Channel silicon thickness Tsi= 12 nm. Lines: TCAD Data.


Figure 4.7: Rth variation with channel length (Lg). Rth1 = 21, RTHL = 0.0031, ΔLth = 0.07. Symbols:

Experimental Data [23], Solid Line: Model.

4.2.1 Thermal Resistance with Length Scaling

Self-heating models [18, 24–29] available till date are length independent and modeled as

Rth ∝ 1

Wg

(4.1)

We have seen from TCAD simulations that as channel length (Lg) decreases, channel area

decreases which results in more temperature rise at a given power level (see Fig. 4.6) and

therefore Rth increases. The impact of channel area on thermal resistance can be modeled

using a first hand model as Rth ∝ 1LgWg

. Thus modified Rth becomes

Rth =Rth1

Wg

[1 +

1

Lg

](4.2)

where Lg and Wg are the normalized (to 1 μm) channel length and width, respectively and

Rth1 is the model parameter. Rth has non-linear dependence on Lg as dominant heat flow

paths are different at different channel lengths. This behavior is also observed in experimental

data [23, 30] as shown in Fig. 4.7 (NMOS devices) and Fig. 4.8 (both NMOS and PMOS

devices). This non-linearity in Rth is captured by a parameter β, and the modified Rth model

reads as

Rth =Rth1

Wg

[1 +

1

Lβg

](4.3)


Figure 4.8: Rth vs channel length (Lg) characteristic for NMOS and PMOS devices. The model shows

excellent agreement with the experimental data [30] for both NMOS and PMOS devices. For NMOS

parameter values are Rth1 = 2.75, RTHL = 0.03, ΔLth = 0.24 and β = 0.78. For PMOS parameter

values are Rth1 = 2.15, RTHL = 0.03, ΔLth = 0.0748 and β = 0.5. Symbols: Data [30], Lines: Model.

Figure 4.9: Importance of parameter ΔLth in Rth modeling is illustrated. Rth vs channel length (Lg)

characteristic for NMOS device with channel width Wg = 10 μm, oxide thickness Tox1 = 1.9 nm, buried

oxide thickness Tbox = 10 nm and body thickness Tsi = 12 nm. Parameter values are: Rth1 = 13, ΔLth =

0.170 and β = 1. Blue Line: the BSIM-IMG model without ΔLth parameter, Red Line: the BSIM-IMG

model with ΔLth parameter.


Figure 4.10: Importance of parameter RTHL in Rth modeling is illustrated. Rth vs channel length (Lg)

characteristic for NMOS device with channel width Wg = 10 μm, oxide thickness Tox1 = 1.9 nm, buried

oxide thickness Tbox = 10 nm and body thickness Tsi = 12 nm. Parameter values are: Rth1 = 13, ΔLth

= 0.170 and β = 1, α = 0.95. Symbols: TCAD Data, Lines: the BSIM-IMG model.

Rth shows weaker Lg dependence at short channel lengths because contacts do not scale with

Lg (see plateau in Region-1 of Fig. 4.7) which is captured by another parameter ΔLth as

Rth =Rth1

Wg

[1 +

1

ΔLth + Lβg

](4.4)

The channel length below which Rth shows weaker Lg dependence is decided by parameter

ΔLth (see Fig. 4.9): For ΔLth >> Lβg , Rth becomes

Rth =Rth1

Wg

1

ΔLth

(4.5)

At short channel lengths, Rth is function of ΔLth and Rth1 as shown in (4.5). Since ΔLth

is already extracted, Rth1 is fine tuned to shift thermal resistance magnitude in short length

regime. To make the model more robust to capture other experimental as well as TCAD data, a

parameter RTHL is introduced in (4.4) to give

Rth =Rth1

Wg

[RTHL +

1

ΔLth + Lβg

](4.6)

RTHL is extracted at very long channel lengths characterized by RTHL >> 1

ΔLth+Lβg

, for

which Rth becomes:


Figure 4.11: Rth vs channel length (Lg) characteristic for NMOS device (Tox1 = 1.9 nm, Tbox = 10 nm,

Tsi = 12 nm) for different channel widths (0.1, 0.24, 0.48, 1, 5, 10 μm). Rth1 = 13, RTHL = 0.8, ΔLth

= 0.170 and β = 1, α = 0.95. Symbols: TCAD Data, Lines: the BSIM-IMG model.

Rth =Rth1

Wg

RTHL (4.7)

Importance of parameter RTHL in Rth modeling is shown in Fig. 4.10.

4.2.2 Thermal Resistance with Width Scaling

The heat flow plane from the silicon island into the BOX is like a half cylinder for large widths

(i.e., heat flows through substrate) and half sphere for narrow widths (i.e., heat flow from sub-

strate/gate and source/drain are comparable to substrate) for same channel length [31]. Thus,

Rth varies as 1/W for large widths but deviates from this dependence for narrow width de-

vices [32]. We modeled it by using power dependence on width (i.e., W αg ) as shown in Fig.

4.11 and Fig. 4.12. Thus the final model for geometry dependent thermal resistance is given as

Rth =Rth1

Wαg

[RTHL +

(1

Lβg +ΔLth

)](4.8)

Fig. 4.11 shows Rth vs Lg at different channel widths. Without α, wide channel width devices

can be accurately modeled while Rth for narrow width devices are overestimated. Fig. 4.12

shows Rth vs 1/Wg at different channel lengths. The proposed model accurately captures the

width dependence of Rth for a wide range of channel lengths.

4.3 Impact of Ambient Temperature on Thermal Resistance 72

Figure 4.12: Rth vs 1/Wg characteristic for NMOS device for different channel lengths (0.03, 0.05, 0.1,

0.5, 5, 10 μm). Rth1 = 13, RTHL = 0.8, ΔLth = 0.170 and β = 1, α = 0.95. Symbols: TCAD Data,


4.3 Impact of Ambient Temperature on Thermal Resistance

Right, y-axis in Fig. 4.13 shows that power dissipation decreases with increase in ambient

temperature due to mobility reduction (i.e., increased scattering mechanism). Silicon material

thermal conductivity also decreases with ambient temperature [33] which does not allow heat to

flow out quickly. This obstruction in heat flow raises the device temperature (ΔT = TDEV ICE−TNOM ) and leads to increment in Rth with ambient temperature. Left y-axis of Fig. 4.13 shows

that Rth is almost a linear function of ambient temperature (from −40 ◦C to 125 ◦C) [34]. Thus

the ambient temperature dependency in the Rth is modeled as

RTHTemp = Rth [1 +RTHT ∗ΔT ] (4.9)

where RTHT is the slope of the rise in Rth vs. temperature (T) characteristic and is used as

a fitting parameter for capturing the dependence of ambient temperature on Rth. Rth is the

thermal resistance at T = 300 K. To quantify the effect of self-heating on device characteristics,

we have simulated the device for different ambient temperatures ranging from −40◦C to 125◦C.

Fig. 4.14 shows Ids vs. Vds characteristics of FD-SOI MOSFET with and without self-heating

effect. The model can accurately capture the self-heating effect on drain current at different

ambient temperatures and shows excellent agreement with TCAD data as demonstrated in Fig.

4.14.

4.4 Summary 73

Figure 4.13: Rth variation with ambient temperature (from −40 ◦C to 125 ◦C). Lines: TCAD Data.

Figure 4.14: Ids vs Vds characteristic with temperature set at T = −40◦C, 25◦C, 125◦C. Bias conditions

are: Vfg = 1.2 V and Vbg = 0 V. Device dimensions are: Channel length Lg = 30 nm, Gate width Wg = 10

μm, Front gate oxide thickness Tox = 1.9 nm, Back gate oxide thickness Tbox = 10 nm, Channel silicon

thickness Tsi = 12 nm. Symbols: TCAD Data, Lines: the BSIM-IMG model.

4.4 Summary

Geometrical scaling of thermal resistance has been analyzed using extensive 3D TCAD simu-

lations. A new behavioral model for Rth geometrical scaling has been proposed and validated

for FD-SOI MOSFETs using both TCAD and experimental data.

Bibliography



in Proc. of SOI Conference, pp. 1–2, 2012.



“Multi-Vt UTBB FDSOI device architectures for low-power cmos circuit,” IEEE Trans-action on Electron Devices, vol. 58, no. 8, pp. 2473–2482, 2011.



and O. Faynot, “Low power UTBOX and back plane (BP) FDSOI technology for 32nm

node and below,” in Proc. of IEEE International Conference on IC Design Technology,

pp. 1–4, 2011.

[4] Q. Liu, A. Yagishita, N. Loubet, A. Khakifirooz, P. Kulkarni, T. Yamamoto, K. Cheng,

M. Fujiwara, J. Cai, D. Dorman, S. Mehta, P. Khare, K. Yako, Y. Zhu, S. Mignot,

S. Kanakasabapathy, S. Monfray, F. Boeuf, C. Koburger, H. Sunamura, S. Ponoth,

A. Reznicek, B. Haran, A. Upham, R. Johnson, L. F. Edge, J. Kuss, T. Levin, N. Berliner,

E. Leobandung, T. Skotnicki, M. Hane, H. Bu, K. Ishimaru, W. Kleemeier, M. Takayanagi,

B. Doris, and R. Sampson, “Impact of back bias on ultra-thin body and BOX (UTBB) de-

vices,” in Proc. of Symposium on VLSI Technology (VLSIT), pp. 160–161, 2011.

[5] J. Colinge, FinFETs and Other Multi-Gate Transistors. Springer, 2007.


Channel Effects in Ultrathin SOI MOSFETs,” IEEE Transaction on Electron Devices,

vol. 60, no. 6, pp. 1814–1819, 2013.

[7] L. McDaid, S. Hall, P. Mellor, W. Eccleston, and J. Alderman, “Physical origin of negative

differential resistance in SOI transistors,” Electronics Letters, vol. 25, no. 13, pp. 827–828,

1989.

[8] R. Tu, C. Wann, J. King, P.-K. Ko, and C. Hu, “An ac conductance technique for measuring

self-heating in SOI MOSFET’s,” IEEE Electron Device Letters, vol. 16, no. 2, pp. 67–69,

1995.

74

BIBLIOGRAPHY 75

[9] E. Pop, R. Dutton, and K. Goodson, “Thermal analysis of ultra-thin body device scaling

[SOI and FinFet devices],” Tech. Digest of IEDM,, vol. 12, pp. 36.6.1–36.6.4, 2003.

[10] “BSIM4 Technical Manual.” [Online]. Available: http://www-device.eecs.berkeley.edu/

bsim/?page=BSIM4

[11] W. Jin, W. Liu, S. Fung, C. Chan-Philip, and C. Hu, “SOI thermal impedance extraction

methodology and its significance for circuit simulation,” IEEE Transaction on ElectronDevices, vol. 48, no. 4, pp. 730–736, 2001.

[12] S. Khandelwal, Y. S. Chauhan, D. D. Lu, S. Venugopalan, M. Ahosan Ul Karim, A. B.

Sachid, B. Y. Nguyen, O. Rozeau, O. Faynot, A. M. Niknejad, and C. Hu, “BSIM-IMG:

A Compact Model for Ultra-Thin Body SOI MOSFETs with Back-Gate Control,” IEEETransaction on Electron Devices, vol. 59, no. 8, pp. 2019–2026, 2012.




[14] “Sentaurus Device User Guide, Synopsys, Inc., Mountain View, CA, Version Z-2007.03,

Mar. 2007.”



BOX (SOTB) CMOS with Single Metal Gate,” in Proc. of Symposium on VLSI Technology(VLSIT), pp. 166 – 167, 2008.

[16] M. Shrivastava, M. Agrawal, S. Mahajan, H. Gossner, T. Schulz, D. K. Sharma, and V. R.

Rao, “Physical insight toward heat transport and an improved electrothermal modeling

framework for finfet architectures,” IEEE Transaction on Electron Devices, vol. 59, no. 5,

pp. 1353–1363, 2012.

[17] K. Etessam-Yazdani, R. Hussin, and M. Asheghi, “Impact of scaling on thermal behavior

of Silicon-on-Insulator transistors,” in Proc. of the Tenth Intersociety Conference on Ther-mal and Thermomechanical Phenomena in Electronics Systems, pp. 1257–1264, 2006.

[18] “BSIMSOIv4.5.0 Technical Manual.” [Online]. Available: http://www-device.eecs.

berkeley.edu/bsim/?page=BSIMSOI LR

[19] S. Khandelwal, J. Watts, E. Tamilmani, and L. Wagner, “Scalable thermal resistance model

for single and multi-finger silicon-on-insulator MOSFETs,” in Proc. of IEEE InternationalConference on Microelectronic Test Structures (ICMTS), pp. 182–185, 2011.

[20] K. Oshima, S. Cristoloveanu, B. Guillaumot, H. Iwai, and S. Deleonibus, “Advanced SOI

MOSFETs with buried alumina and ground plane: self-heating and short-channel effects,”


BIBLIOGRAPHY 76

[21] M. Berger and Z. Chai, “Estimation of heat transfer in SOI-MOSFETs,” IEEE Transactionon Electron Devices, vol. 38, no. 4, pp. 871–875, 1991.

[22] T. Takahashi, T. Matsuki, T. Shinada, Y. Inoue, and K. Uchida, “Comparison of self-

heating effect (SHE) in short-channel bulk and ultra-thin BOX SOI MOSFETs: Impacts

of doped well, ambient temperature, and SOI/BOX thicknesses on SHE,” Tech. Digest ofIEDM, pp. 7.4.1–7.4.4, 2013.

[23] E. Pop, “Energy dissipation and transport in nanoscale devices,” Nano Research, vol. 3,

no. 3, pp. 147–169, 2010.

[24] “BSIMIMG102.7.0 Technical Manual.” [Online]. Available: http://www-device.eecs.

berkeley.edu/bsim/?page=BSIMIMG LR

[25] “BSIMCMG110.0.0 Technical Manual.” [Online]. Available: http://www-device.eecs.

berkeley.edu/bsim/?page=BSIMCMG LR

[26] “BSIM6.1.1 Technical Manual.” [Online]. Available: http://www-device.eecs.berkeley.

edu/bsim/?page=BSIM6 LR

[27] H. Agarwal, S. Venugopalan, M. A. Chalkiadaki, N. Paydavosi, J. P. Duarte, S. Agnihotri,

C. Yadav, P. Kushwaha, Y. S. Chauhan, C. C. Enz, A. Niknejad, and C. Hu, “Recent en-

hancements in BSIM6 bulk MOSFET model,” in Proc. of IEEE International Conferenceon Simulation of Semiconductor Processes and Devices, pp. 53–56, 2013.

[28] W. Wu, X. Li, G. Gildenblat, G. Workman, S. Veeraraghavan, C. McAndrew, R. v.

Langevelde, G. Smit, A. Scholten, D. Klaassen, and J. Watts, “PSP-SOI: An advanced

surface potential based compact model of partially depleted SOI MOSFETs for circuit

simulations,” Solid-State Electronics, vol. 53, no. 1, pp. 18–29, 2009.

[29] “HiSIM-SOI 1.0.0 Users Manual.” [Online]. Available: http://www.hisim.hiroshima-u.ac.

jp/

[30] S. Lee, R. Wachnik, P. Hyde, L. Wagner, J. Johnson, A. Chou, A. Kumar, S. Narasimha,

T. Standaert, B. Greene, T. Yamashita, J. Johnson, K. Balakrishnan, H. Bu, S. Springer,

G. Freeman, W. Henson, and E. Nowak, “Experimental analysis and modeling of self

heating effect in dielectric isolated planar and fin devices,” in Proc. of Symposium on VLSITechnology (VLSIT), pp. T248–T249, 2013.

[31] P. Canfield, S. Lam, and D. Allstot, “Modeling of frequency and temperature effects in

GaAs MESFETs,” IEEE Journal of Solid-State Circuits, vol. 25, no. 1, pp. 299–306, 1990.

[32] R. Howes and W. Redman-White, “A small-signal model for the frequency-dependent

drain admittance in floating-substrate MOSFET’s,” IEEE Journal of Solid-State Circuits,

vol. 27, no. 8, pp. 1186–1193, 1992.

BIBLIOGRAPHY 77

[33] D. J. Walkey, T. J. Smy, T. Macelwee, and M. Maliepaard, “Compact representation of

temperature and power dependence of thermal resistance in Si, Inp and GaAs substrate

devices using linear models,” Solid-State Electronics, vol. 46, no. 6, pp. 819–826, 2002.

[34] C. Anghel, R. Gillon, and A. Ionescu, “Self-heating characterization and extraction

method for thermal resistance and capacitance in HV MOSFETs,” IEEE Electron DeviceLetters, vol. 25, no. 3, pp. 141–143, 2004.

Chapter 5

A Unified Flicker Noise Model for FD-SOIMOSFETs including Back bias Effect

MOS transistor has severe 1/f noise, which sets a lower limit on the level of signal that can

be processed by a low power radio frequency integrated circuit (RFIC) [1, 2]. Fully depleted

silicon on insulator (FD-SOI) MOSFET has emerged as a better option over bulk MOSFET

due to its higher immunity against short channel effects (SCE) [3] and lower threshold voltage

variability [4]. FD-SOI MOSFET faces carrier fluctuations from the front and back interfaces

(i.e., different front and back interface quality and bias conditions) which ultimately affect cur-

rent transport [5–7]. Low frequency (LF) noise is sensitive to the interface defects and the

quality of the dielectric layer. Therefore the LF noise measurement is used as a reliable tool

to evaluate a new technology [8]. A detailed and careful analysis of LF noise measurement

can give us information about noise sources and related parameters [9, 10]. Although industry

standard models have unified model for flicker noise [11, 12], these models are derived only for

the single Si − SiO2 interface (i.e., bulk MOSFET). The same model may not be accurate for

FD-SOI MOSFET due to the presence of two different interfaces. Flicker noise model specific

to the FD-SOI MOSFET presented in literature [13–16] till date are valid only in the linear

region. Normalized drain current spectral density in [13–16] is nothing, but the similar expres-

sion proposed by K. K. Hung [11, 12] for a bulk MOSFET in the linear region. Hence, there

is a need of a flicker noise model for all bias conditions. In this chapter, first, we will derive

a unified flicker noise model which accurately captures the low-frequency behavior of FD-SOI

transistors in all regions of operation. Then we will report electrical characterization setup used

for low-frequency noise measurements. The model is validated against noise measurement data

performed on the device in 28 nm technology node received from CEA-LETI.

78

5.1 Proposed Flicker Noise Model 79

Figure 5.1: A section of the transistor channel with width W and length Δx is illustrated.

5.1 Proposed Flicker Noise Model

FD-SOI MOSFET shown in Fig. 5.1 has different front and back gate biases (Vfg, Vbg), dielec-

tric or effective oxide thicknesses (Tox, Tbox) and interface qualities, which lead to the follow-

ing changes in FD-SOI MOSFET’s physics as compared to the bulk MOSFET: 1) different bias

conditions across the front and back gates cause different carrier concentrations at respective in-

terfaces. 2) different interface quality leads to different carrier trapping/de-trapping mechanism

at both the interfaces [13]. Thus, conventional bulk MOSFET’s unified flicker noise model may

not be valid for FD-SOI MOSFETs. Here, we propose a unified flicker noise model for FD-SOI

MOSFETs, which accounts for both the interfaces. The proposed model is implemented in the

surface potential-based BSIM-IMG model, which is the latest industry standard compact model

for FD-SOI transistors [17–22].

Fig. 5.2 outlines the proposed methodology to calculate the drain current noise power spec-

tral density (Sid). To calculate total Sid, it is important to know the carrier fluctuations at each

interface, which can be obtained by calculating the total number of charge carriers at the front

and back interfaces (Nf and Nb), respectively. In current BSIM-IMG model, total charges at

source (qtots) and drain (qtotd) terminals are calculated as a function of the front and back sur-

face potentials (ψ1, ψ2) [23] as shown in step 1 and 2 in Fig. 5.2. There is no direct expression

available for Nf and Nb. Here, we propose a method to calculate Nf and Nb (see step 3a and

3b of Fig. 5.2) as follows: inversion charge contribution from the front and back gates are

the functions of the oxide capacitance (Cox/box) and biases applied to the front and back gates

(Vfg/bg). Based on this assumption, we have proposed two coupling coefficients (Θ12 and Θ21),

which represent the ratio of inversion charges at the front and back interfaces.


Step 1:

Calculation of front and back

surface potentials (ψf , ψb)

Assuming back-side is in weak inversion

Step 2:

Calculation of Source and

Drain charges (qtots, qtotd)

Step 3a: Number of

carriers at front interface

Nf = (qisf + qidf )/q

Step 3b: Number of

carriers at back interface

Nb = (qisb + qidb)/q

Step 4a: Calculate

drain current noise

power spectral density

(Sidf ) at front interface

Step 4b: Calculate

drain current noise

power spectral density

(Sidb) at back interface

Step 5: Total drain

current noise power

spectral density

Sid = Sidf + Sidb

Figure 5.2: An illustration of flicker noise modeling in FD-SOI transistors.

Θ12 =Cox · f(Vfg)

Cox · f(Vfg) + Cbox · f(Vbg)(5.1)

Θ21 =Cbox · f(Vbg)

Cox · f(Vfg) + Cbox · f(Vbg)(5.2)

The hyperbolic smoothing function f (x) used in (5.1) and (5.2) provides smooth transition,

when the gate biases switch from negative to positive values as

f(Vfg/bg) =1

2·[Vfg/bg +

√V 2fg/bg + 4 · c2

](5.3)


where c is a smoothing parameter (typically 0.01). f (Vfg/bg) ensures that only positive values of

Vfg/bg will contribute to the inversion charge at the front and back gates. The sum of Θ12 and

Θ21 is always unity implying charge conservation. For higher Vfg, almost all the charges will be

at the front gate and vice-versa for higher Vbg. For symmetrical gate operation (i.e., FinFETs),

Cox = Cbox and Vfg = Vbg , Θ12 and Θ21 become 0.5, representing the equal contribution from

both sides. Thus, these ratios satisfy all asymptotic conditions. Using (5.1) and (5.2), the source

charge density at the front interface becomes qisf (= qtots ∗ Θ12), while at the back interface it

becomes qisb(= qtots ∗ Θ21). Similarly, the drain charge density at the front interface becomes

qidf (= qtotd ∗ Θ12) and at the back interface, it becomes qidb(= qtotd ∗ Θ21). Thus, source side

number of channel carriers per unit area at the front and back interfaces are Nsf =qisfq

and Nsb

= qisbq

, respectively. Drain side number of channel carriers per unit area at the front and back

interfaces (Ndf and Ndb) are calculated in the similar manner. We have used this information in

calculating noise PSD at each interface as follows: the drain current in FD-SOI MOSFET can

be expressed as

Ids = WμeffqNEx (5.4)

where N (= Nf + Nb) is the total number of channel carriers per unit area, Ex is the horizontal

channel field and μeff is the surface mobility. The corresponding fluctuations in the drain

current can be expressed as [11]

1

Ids

δIdsδΔNtf

=1

ΔNf

δΔNf

δΔNtf

± 1

μeff

δμeff

δΔNtf

(5.5)

1

Ids

δIdsδΔNtb

=1

ΔNb

δΔNb

δΔNtb

± 1

μeff

δμeff

δΔNtb

(5.6)

where ΔNf/b = Nf/b WΔx, ΔNtf/tb = Ntf/tbWΔx. Nf/b and Ntf/tb are the number of channel

carriers and occupied traps per unit area at the front and back interfaces, respectively. ΔNf/b

and ΔNtf/tb are considered in a section of the transistor channel with width W and length

Δx. These fluctuations in the drain current give rise to different Sid at each interface. To

solve the first right term in (5.5) and (5.6), we can relate ΔNf/b and ΔNtf/tb, considering that

the fluctuation in δΔQtf/tb (i.e., ΔQtf/tb= -q ΔNtf/tb) of the trapped charge density causes a

variation in the front and back gate surface potentials, which results in change of all the charges

that depend on surface potential [24]. Thus, capacitive coupling between δΔNf/b and δΔNtf/tb

at the front and back interfaces are given as follows:

Rf =δΔNf

δΔNtf

= − Cinvf

Cinvf + Cox + CITF=

Nf

Nf +N∗1

(5.7)


Rb =δΔNb

δΔNtb

= − Cinvb

Cinvb + Cbox + CITB=

Nb

Nb +N∗2

(5.8)

where Cinvf (= q2

kTNf ) and Cinvb (= q2

kTNb) are the inversion layer capacitances at the front and

back interfaces, respectively; N∗1 = kT

q2(Cox + CITF), and N∗

2 = kTq2

(Cbox + CITB); CITF and

CITB are the model parameters for the front and back interfaces trap coupling capacitance. To

evaluate the second right term in (5.5) and (5.6), we have used Matthiessen’s mobility model to

acknowledge the dependence of the carrier mobility on the front and back oxide charge densities

as1

μeff

=1

μn

+1

μox

+1

μbox

=1

μn

+ αfNtf + αbNtb (5.9)

where μox, μbox are the mobilities limited by the front and back oxide charge scattering [25] and

μn is the mobility limited by other scattering mechanisms. αf , αb are the scattering coefficients

to capture the influence of the front and back oxide trap charges on mobility. Differentiating

(5.9) with respect to ΔNtf and ΔNtb, we get

δμeff

δΔNtf

= − αfμ2eff

W ·Δx (5.10)

δμeff

δΔNtb

= − αbμ2eff

W ·Δx (5.11)

Using (5.7) and (5.10) in (5.5) for front interface and; (5.8) and (5.11) in (5.6) for back interface,

we can write δIdsIds

for both interfaces as follows:

δIdsIds

=

(Rf

Nf

± αfμeff

)δΔNtf

W ·Δx (5.12)

δIdsIds

=

(Rb

Nb

± αbμeff

)δΔNtb

W ·Δx (5.13)

Thus, the power spectrum density of the local current fluctuation at the front and back interfaces

become

SΔIdf (x, f) =

(Ids

W ·Δx)2 (

Rf

Nf

± αfμeff

)2

SΔNtf(x, f) (5.14)

SΔIdb(x, f) =

(Ids

W ·Δx)2 (

Rb

Nb

± αbμeff

)2

SΔNtb(x, f) (5.15)

where SΔNtf/tb(x, f) is the power spectral density of the mean square fluctuations in the number

of occupied traps at the front/back interface [12, 26] over the area W · Δx. Following similar


Figure 5.3: The schematic of the electrical characterization setup used for low-frequency noise measure-

ments. The device under test (DUT) is having ground-signal-ground pads for connection. The FD-SOI

wafer is provided by CEA-LETI.

methodology, as discussed in [11, 12], for the front and back interfaces separately, we get the

front and back interface noise spectral densities, Sidf and Sidb, respectively, as

Sidf (f) =1

L2

∫ L

0

SΔIdf (x, f)Δx · dx

=kTqIdsμeff

γfEF1L2

∫ Vds

0

N∗tf (Efn)

R2f

Nf

dV

(5.16)

Sidb(f) =1

L2

∫ L

0

SΔIdb(x, f)Δx · dx

=kTqIdsμeff

γfEF2L2

∫ Vds

0

N∗tb(Efn)

R2b

Nb

dV

(5.17)

whereN∗tf/tb(Efn) = NOIAf/b+NOIBf/b∗Nf/b+NOICf/b∗N2

f/b. Parameters EF1 and EF2 are

used to capture the process induced variability in flicker noise behavior [6]. NOIAf/b, NOIBf/b

and NOICf/b are the technology-dependent model parameters. V is the channel potential (i.e., 0

V at the source end, while Vds at the drain end). After calculating the drain noise power spectral

density at each interface, we get a final expression for Sid in FD-SOI MOSFET as

Sid(f) = Sidf (f) + Sidb(f) (5.18)

5.2 Electrical Characterization Setup 84

(a) (b)

Figure 5.4: Electrically shielded (Faraday Cage) probe station is illustrated. (a) Outside view. (b) Inside

view.

5.2 Electrical Characterization Setup

The devices under study have effective oxide thickness (EOT) of 1.2 nm, ultra-thin silicon film

thickness of 8 nm and thin buried oxide thickness of 25 nm. The schematic of the experimental

setup and the electrically shielded (Faraday Cage) probe station used for low-frequency noise

measurements are shown in Fig 5.3 and Fig. 5.4, respectively. Keysight’s I-V analyzer E5270B

is used to bias the device and monitor the drain current. The substrate bias is applied by con-

necting the substrate to another programmable voltage source. The noise in the drain current

is amplified by a low-noise current pre-amplifier, before feeding it into a Keysight’s spectrum

analyzer 35670A. Later, it will compute the fast Fourier transform of the noise signal and av-

erages the calculated power spectra over ten measurement cycles to obtain a smooth spectrum.

The frequency range under study is 1 Hz-65 kHz. The device under test is shown in Fig 5.3

is received from CEA-LETI. All the measurements and analyses are done using Keysight’s IC-

CAP software, which gives output referred voltage noise spectral densities at the gate and drain

terminals, Sg and Sd, respectively. Input referred voltage noise spectral densities at the gate

and drain terminals (Svg, Svd) are then calculated by dividing Sg and Sd by the square of gain,

respectively. Subsequently, the current noise spectral density (Sid) is calculated by multiplying


(a)

(b)

Figure 5.5: Impact of back bias on noise power spectral density (a) Sid vs frequency characteristics for

Vbg = -3, 0, 3 V. Device dimensions are: length Lg = 100 nm, channel width Wg = 0.5 μm, number of

fingers NF = 80. (b) Sid vs frequency characteristics for Vbg = -3, 0, 3 V. Device dimensions are: length

Lg = 50 nm, channel width Wg = 0.25 μm, number of fingers NF = 80. All the devices have Tox = 1.2

nm, Tbox =25 nm and Tsi = 8 nm.


(a)

(b)

Figure 5.6: (a) Sid vs Ids characteristics for different back bias. Device dimensions are: length Lg = 100

nm, channel width Wg = 0.5 μm, number of fingers NF = 80. (b) Sid vs Ids characteristics at Vbg = -3, 0,

3 V. Device dimensions are: length Lg = 50 nm, channel width Wg = 0.25 μm, number of fingers NF =

80. All the devices have Tox = 1.2 nm, Tbox =25 nm and Tsi = 8 nm.

5.3 Results and Discussions 87

Svd by square of outputconductance (i.e, g2ds), where gds is obtained from the DC measurements.

5.3 Results and Discussions

Low-frequency noise behavior with back bias is illustrated in Fig 5.5. For negative back bias

(Vbg = -3 V), the charge centroid gets shifted towards the front interface, which results in in-

creased scattering as front gate stack includes high-k dielectric material and therefore, higher

Sid. For positive back bias, the charge centroid gets shifted towards back interface where, carri-

ers face less scattering as back gate has thermally grown buried oxide and this results in lower

Sid [27]. Fig. 5.6 shows Sid vs. Ids characteristics for different back-gate biases at 10 Hz for

two different geometries. It shows that for a fixed Vfg value, Sid is proportional to the drain

current, as expected. Fig. 5.6a and Fig. 5.6b demonstrate that the proposed model has excellent

agreement with the measured Sid for a wide range of back biases as well as channel lengths and

widths.

5.4 Summary

A unified flicker noise model for FD-SOI transistors is proposed for the first time. The model

captures the correct flicker noise behavior from weak to strong inversion region for a wide

range of the front and back gate biases. Flicker noise power spectral densities at the front

and back interfaces are calculated using the carrier number and correlated surface mobility

fluctuation models. The model is implemented in the industry standard BSIM-IMG model for

circuit simulations.

Bibliography

[1] M. Koyama, M. Casse, R. Coquand, S. Barraud, G. Ghibaudo, H. Iwai, and G. Reim-

bold, “Influence of device scaling on low-frequency noise in SOI tri-gate N- and P-type

Si nanowire MOSFETs,” in Proc. of IEEE Solid-State Device Research Conference (ESS-DERC), pp. 300–303, 2013.

[2] C. Theodorou, E. Ioannidis, S. Haendler, E. Josse, C. Dimitriadis, and G. Ghibaudo, “Low

frequency noise variability in ultra-scaled FDSOI n-MOSFETs: Dependence on gate bias,

frequency and temperature,” Solid-State Electron, vol. 117, pp. 88–93, 2016.


Channel Effects in Ultrathin SOI MOSFETs,” IEEE Transactions on Electron Devices,

vol. 60, no. 6, pp. 1814–1819, 2013.



in Proc. of IEEE International SOI Conference, pp. 1–2, 2012.

[5] B. Cretu, E. Simoen, J.-M. Routoure, R. Carin, M. Aoulaiche, and C. Claeys, “Low fre-

quency noise characterization in n-channel UTBOX devices with 6 nm Si film,” in Proc.of IEEE International Conference on Noise and Fluctuations (ICNF), pp. 1–4, 2013.

[6] S. D. dos Santos, T. Nicoletti, J. A. Martino, M. Aoulaiche, A. Veloso, M. Jurczak,

E. Simoen, and C. Claeys, “On the variability of the front/back-channel LF noise in UT-

BOX SOI nMOSFETs,” IEEE Transactions on Electron Devices, vol. 60, no. 1, pp. 444–

450, 2013.

[7] J. A. Babcock, D. K. Schroder, and Y.-C. Tseng, “Low-frequency noise in near-fully-

depleted TFSOI MOSFETs,” IEEE Electron Device Letters, vol. 19, no. 2, pp. 40–43,

1998.

[8] B. Jones, “Electrical noise as a measure of quality and reliability in electronic devices,”

Academic Press, vol. 87, pp. 201–257, 1993.

[9] M. V. Haartman, “Low-frequency noise characterization, evaluation and modeling of ad-

vanced Si and SiGe-based CMOS transistors,” Doctoral Thesis, 2006.

88

BIBLIOGRAPHY 89

[10] C. Theodorou, E. Ioannidis, F. Andrieu, T. Poiroux, O. Faynot, C. Dimitriadis, and

G. Ghibaudo, “Low frequency noise sources in advanced UTBB FDSOI MOSFETs,”


[11] K. Hung, P. Ko, C. Hu, and Y. Cheng, “A physics-based MOSFET noise model for circuit

simulators,” IEEE Transactions on Electron Devices, vol. 37, no. 5, pp. 1323–1333, 1990.

[12] K. K. Hung, P. K. Ko, C. Hu, and Y. C. Cheng, “A unified model for the flicker noise in

metal-oxide-semiconductor field-effect transistors,” IEEE Transactions on Electron De-vices, vol. 37, no. 3, pp. 654–665, 1990.

[13] C. G. Theodorou, E. G. Ioannidis, S. Haendler, N. Planes, F. Arnaud, F. Andrieu, T. Poirou,

O. Faynot, J. Jomaah, C. A. Dimitriadis, and G. Ghibaudo, “Front-back gate coupling

effect on 1/f noise in ultra-thin si film FDSOI MOSFETs,” in Proc. of SemiconductorConference Dresden-Grenoble (ISCDG), pp. 223–226, 2012.

[14] C. G. Theodorou, E. G. Ioannidis, F. Andrieu, T. Poiroux, O. Faynot, C. A. Dimitriadis,

and G. Ghibaudo, “Low-frequency noise sources in advanced UTBB FD-SOI MOSFETs,”


[15] E. G. Ioannidis, C. G. Theodorou, T. A. Karatsori, S. Haendler, C. A. Dimitriadis, and

G. Ghibaudo, “Drain-current flicker noise modeling in nMOSFETs from a 14-nm FDSOI

technology,” IEEE Transactions on Electron Devices, vol. 62, no. 5, pp. 1574–1579, 2015.

[16] L. Zafari, J. Jomaah, and G. Ghibaudo, “Low frequency noise in multi-gate SOI CMOS

devices,” Solid-State Electronics, vol. 51, no. 2, pp. 292–298, 2007.




[18] S. Khandelwal, Y. S. Chauhan, D. D. Lu, S. Venugopalan, M. Ahosan Ul Karim, A. B.

Sachid, B. Y. Nguyen, O. Rozeau, O. Faynot, A. M. Niknejad, and C. C. Hu, “BSIM-

IMG: A Compact Model for Ultra-Thin Body SOI MOSFETs with Back-Gate Control,”


[19] P. Kushwaha, N. Paydavosi, S. Khandelwal, C. Yadav, H. Agarwal, J.-P. Duarte, C. Hu,


Solid-State Electronics, vol. 104, pp. 6 – 11, 2015.


of FDSOI transistors using industry standard BSIM-IMG model,” IEEE Transactions onMicrowave Theory and Techniques, vol. PP, no. 99, pp. 1–7, 2016.

[21] P. Kushwaha, A. Dasgupta, Y. Sahu, S. Khandelwal, C. Hu, and Y. S. Chauhan, “Charac-

terization of RF noise in UTBB FD-SOI MOSFET,” IEEE Journal of the Electron DevicesSociety, no. 99, pp. 1–1, 2016.

BIBLIOGRAPHY 90

[22] Y. Sahu, P. Kushwaha, A. Dasgupta, Y. Sahu, C. Hu, and Y. S. Chauhan, “Compact model-

ing of drain current thermal noise in FDSOI MOSFETs including back-bias effect,” underreview in IEEE Transactions on Microwave Theory and Techniques, 2016.

[23] “BSIM-IMG Technical Manual.” [Online]. Available: http://www-device.eecs.berkeley.

edu/bsim/?page=BSIMIMG

[24] G. Reimbold, “Modified 1/f trapping noise theroy and experiments in MOS transistors

biased from weak to strong inversion influence of interface states,” IEEE Transactions onElectron Devices, vol. 31, no. 9, pp. 1190–1198, 1984.

[25] S. C. Sun and J. D. Plummer, “Mobility in inversion and accumulation layers on thermally

oxidized silicon surfaces,” IEEE Journal of solid-state circuits, vol. 15, no. 4, pp. 562–573,

1980.

[26] S. Christensson, I. Lundstrm, and C. Svensson, “Low frequency noise in MOS transistors-I

theory,” Solid-State Electronics, vol. 11, no. 9, pp. 797–812, 1968.

[27] L. Zafari, J. Jomaah, G. Ghibaudo, and O. Faynot, “Low frequency noise performance in

TiN/HfO2 fully depleted SOI nMOSFET,” in Proc. of IEEE International SOI Conference,

pp. 35–36, 2006.

Chapter 6

RF Modeling of FD-SOI MOSFETs

Radio-frequency (RF) market is seeing exponential growth due to increased demand for wire-

less high data bandwidth applications. The substrates on which RF ICs are manufactured have

significant contribution in achieving this level of performance. Radio-frequency silicon-on-

insulator (RF-SOI) MOSFETs on high resistivity (HR) substrates have emerged as the best

substrate choice over other substrates for low cost RF solutions [1] (see Fig. 6.1). Mixed-signal

system-on-chip devices and integration of complex, high-power devices are now possible be-

cause of RFSOI’s high linearity substrate, electrical isolation and low insertion loss over a wide

frequency range. These technologies have offered us to integrate multiple RF/analog functions

(e.g., the RF switches, Multimode and multiband power amplifiers, antenna tuners and power

controllers) in a smaller space [3]. For battery-life limited wireless applications, fully depleted

silicon-on-insulator (FD-SOI) has emerged as a promising candidate for sub-micron technol-

Figure 6.1: Schematic of a fully depleted silicon on insulator (FD-SOI) transistor [2] with the high

resistivity (HR) substrate without trap rich layer below BOX. Device dimensions are: Channel length

Lg = 100 nm, Gate width Wg = 0.5μm, Number of fingers NF = 60, Front gate oxide thickness Tox =

1.2 nm, Back gate oxide thickness Tbox = 10 nm, Channel silicon thickness Tsi = 8 nm.

91

6.1 RF Characterization 92

ogy nodes due to better control over short channel effects [4] [5], performance enhancement

capability via back-bias tuning [6] [7], better thermal properties [8] and reduced random dopant

fluctuations [9]. With continuous channel length scaling, FD-SOI based CMOS transistors are

now becoming an appropriate choice in the millimeter wave range due to the achievement of

higher trans-conductance and cut off frequency (fT ) with the additional advantage of area and

cost over III-V technology [10]. To achieve higher fT by scaling the RFSOI MOSFET is a chal-

lenging task because of increased fringing capacitance between the gate and the source/drain

contacts [11]. Optimized multi-fingered transistor layouts are widely used to reduce gate resis-

tance and to increase the maximum frequency of oscillation (fmax). RFSOI’s market trends for

production designs show that there is an urgent requirement for a robust, compact model which

can capture FD-SOI transistor behavior accurately at high-frequency ranges [12].

For FD-SOI transistors, there is a limited qualitative discussion on RF behavior [13] (i.e., the

impact of substrate [14] and self-heating [15]) in the literature. However, with great potential

for high-frequency applications, a complete compact model for RF-FDSOI is urgently required.

This chapter addresses this need. Recently, BSIM-IMG has been declared as the industry stan-

dard model for FD-SOI transistors [2, 16, 17]. FD-SOI transistor’s characteristic has frequency

dependence via several inherent phenomena like self-heating effect [18], substrate effect [14]

and gate resistance effect [19]. The DC compact model is not sufficient to predict correct device

behavior of measured data over a wide frequency range [20–24]. To capture the high-frequency

behavior of FD-SOI transistor, we have enhanced the BSIM-IMG model for RF applications by

incorporating parasitic components like gate resistance, substrate resistance and thermal resis-

tance networks. We will start this chapter with the discussion on RF characterization followed

by the RF modeling and a parameter extraction procedure.

6.1 RF Characterization

The FD-SOI wafer with extremely thin 8 nm channel FD-SOI transistors in ultra-thin-BOX

of 10 nm was obtained from CEA-LETI. Both DC and RF measurements are performed on

the ground-signal-ground (G-S-G) pad set as shown in Fig. 6.2. The transistors gate terminal

is assigned as port-1 while drain terminal is assigned as port-2. Source terminal is common

and connected to the ground. The DC measurements are performed using Keysights B1500

parameter analyzer. The Keysights E5071C vector network analyzer with the capability of

measuring frequencies from 100 kHz - 8.5 GHz is used to measure the two-port S-parameters

(see Fig. 6.3). All the parasitics up to pad including wires and probes are removed using

calibration substrate via the short-open-load-through (SOLT) method. The pad to ports parasitic

element is de-embedded using open-short structures available along with the DUT.

6.2 RF Modeling and Parameter Extraction 93

(a) (b)

Figure 6.2: N-channel MOSFETs for two-port RF characterization. (a) Setup picture. (b) Picture of the

actual DUT.

Figure 6.3: Photograph of experimental setup used to perform RF measurements under different bias

conditions. Wafer is visible on chuck along with RF probes.

6.2 RF Modeling and Parameter Extraction

First, we have extracted DC parameters like series resistance, mobility using DC measured

data. Fig. 6.4 and 6.5 show drain current behavior with the gate voltage and drain voltage

variation, respectively for channel length 100 nm with channel width Wg = 0.5μm and number

of fingers NF = 60. The model shows good agreement with experimental data in all regions

of operation which implies accurate modeling of sub-modules like mobility, current saturation.


0.0 0.2 0.4 0.6 0.8 1.00

3

6

9

12

15

Vbg = 0.0 V

Vds = 50 mV Vds = 1.1 V

I ds (m

A)


Symbols: Experimental DataLines: Model

N-channel

(a)

0.0 0.2 0.4 0.6 0.8 1.00

5

10

15

20

25

30

Vds = 50 mV Vds = 1.1 V


g m (m

A/V

) N-channel

Symbols: Experimental DataLines : Model

Vbg=0.0V

(b)

Figure 6.4: (a) Drain current (Ids) vs. front gate voltage Vfg characteristics. (b) Trans-conductance (gm)

vs. front gate voltage Vfg characteristics for Lg = 100 nm. Bias conditions are: Vds = 50 mV and 1.1 V,

Substrate is grounded Vbg = 0 V. Symbols: Experimental Data, Lines: BSIM-IMG model.

FD-SOI transistors have a severe self-heating effect (SHE) at low-frequency levels, which af-

fects device’s characteristic such as output conductance gds. We have extracted the frequency

dependent parameters (i.e., gds, gate capacitance CGG and gate resistance Rg) which affect de-

vice’s Analog/RF figure of merit (FoM). The frequency response of gds and CGG are obtained

from the real part of Y22 and imaginary part of Y11, respectively. In this Section, we have dis-

cussed the variation of Real Y22, CGG and Rg in a wide frequency range and their impact on

Analog/RF FoM.


0.0 0.5 1.00

3

6

9

12

15

18

N-channel

I ds (m

A)

Drain Voltage (V)


Vfg= 0.9 to 1.1 V

(a)

0.0 0.5 1.01

10

N-channel

g ds (m

A/V

)

Drain Voltage (V)


Vfg= 0.9 to 1.1 V

(b)

Figure 6.5: (a) Ids vs. drain voltage Vds characteristics. (b) Output conductance gds vs. drain voltage

Vds characteristics for Lg = 100 nm. Bias conditions are: Vfg = 0.9 V to 1.1 V in steps of 0.1 V, Substrate

is grounded Vbg = 0 V. Thermal resistance Rth value extracted from step 2 shown in Figure 6.15 is used

here. Symbols: Experimental Data, Lines: BSIM-IMG model.

6.2.1 Thermal Resistance Network

As the frequency of the applied small-signal increases, the device temperature gradually stops

following the applied signal and remains effectively constant for frequency, fiso >1

Rth∗Cth[25].

Here fiso is the isothermal frequency, Rth and Cth are the thermal resistance and capacitance of

thermal network [26] [27]. The isothermal frequency is used to determine the device thermal

time constant. From our previous work [28], we know that the isothermal frequency of this


Exp. Data 1st Order Thermal N/W

105 106 107 108 109 1010

2.4

2.6

2.8

3.0

3.2

3.4

DC value of gDS

ΔGSHE

f (Hz)

Rea

l (Y

22),

mS

Thermal N/W

(a)

20 40 60 80 100

14

15

16

16

17 Hot-Chuck Measurement Result

Exp. Data

Vfg= Vds= 1.1 V

I ds (m

A)

T (°C)

N-channel

(b)

Figure 6.6: (a) Measured and extracted real part of Y22 for Lg = 100 nm. 1st order thermal network

is used for fitting till 20 MHz range. Bias conditions are: Vfg = Vds = 1.1 V and Vbg = 0 V. Symbols:

Experimental Data, Lines: BSIM-IMG model. (b) Hot-chuck measurement result is used to determine

the slope of Ids versus temperature (T) for Lg = 100 nm, Wg = 0.5μm, NF = 60. A line is drawn to

show trend. Bias conditions are: Vfg =Vds = 1.1 V.

device is around 20 MHz. We have achieved 1st transition in Real Y22 curve around 20 MHz,

hence parameters related to SHE are extracted in the following frequency range 105 − 107Hz

(i.e., below the isothermal frequency, where thermal contribution dominates over electrical con-

tribution). Fig. 6.6a shows 1st-order thermal network is accurately capturing Real Y22 variation

with frequency upto 20 MHz. We have extracted device’s thermal resistance (Rth) by small-

signal ac conductance technique [15]: ΔGSHE is the difference of Real Y22 value between the

isothermal frequency [28] and low frequency asymptotes [15] and the slope of Ids versus tem-


Exp. Data 1st Order Thermal N/W Substrate Resistor N/W

105 106 107 108 109 1010

2.4

2.6

2.8

3.0

3.2

3.4

Substrate N/W

DC value of gDS

ΔGSHE

f (Hz)

Rea

l (Y

22),

mS

Thermal N/W

(a)

(b)

Figure 6.7: (a) Measured and extracted real part of Y22 for Lg = 100 nm. Five resistor-capacitor substrate

network is used to validate the BSIM-IMG model in the medium frequency range. Bias conditions are:

Vfg = Vds = 1.1 V and Vbg = 0 V. Symbols: Experimental Data, Lines: BSIM-IMG model. (b) Substrate

network: Five R’s and five C’s along with three capacitances (Csbox/Cdbox are capacitances between

source/drain to BOX and Cox2 is BOX capacitance.) are used to validate the model for the wide frequency

range. We have neglected deep well junction capacitances. Gate parasitic network: Two resistors (gate

resistance Rg, gate terminal to contact-pad resistance Rc) in the series along with front gate capacitance

Cox1 are used to validate model above GHz range.


(a) (b)

Figure 6.8: Measured and simulated S-parameter: (a) Smith chart validation for S11 and S22 for channel

lengths Lg = 30 nm, 100 nm. (b) The phase of S11 and S22 for Lg = 100 nm. Bias conditions are: Vfg =

Vds = 1.1 V and Vbg = 0 V. Symbols: Experimental Data, Lines: BSIM-IMG model.

Figure 6.9: Current gain |H21| variation with frequency for Lg = 100 nm. Current gain reduces as

frequency increases (| iLiin | =gm

wT ∗CGG, wT = 2 ∗ π ∗ freq). Here iL/iin are output/input currents. Bias

conditions are: Vfg = Vds = 1.1 V and Vbg = 0 V. Symbols: Experimental Data, Lines: BSIM-IMG model.

perature is determined from the hot-chuck measurement as shown in Fig. 6.6b. As dynamic self

heating is more pronounced below the isothermal frequency, we have extracted Cth by fitting

the Real Y22 data till isothermal frequency. Extracted DC values of Real Y22 shown in Fig. 6.5b

is smaller than RF values of Real Y22, because at a higher frequency range dynamic self heating

is removed [18].


(a)

(b)

Figure 6.10: (a) Measured and extracted imaginary part of Y11/(2π · freq) vs. front gate voltage char-

acteristic for Lg = 100 nm. Note that CGG can also be measured using C-V measurements of large area

devices, which is not shown here. Bias conditions are: Vds = 0 V and Vbg = 0 V. (b) Measured and ex-

tracted imaginary part of Y11 for Lg = 100 nm. Low frequency measured data is not shown here. Bias

conditions are: Vfg = Vds = 1.1 V and Vbg = 0 V. Symbols: Experimental Data, Lines: BSIM-IMG model.

6.2.2 Substrate Parasitic Network

Fig. 6.6a shows that the model has a deviation from measured data above 100 MHz even after

using self-heating (SHE) network. Because after 40-50 MHz, dynamic self-heating reduces or

disappears [28]. The substrate related transition in the real part of Y22 occurs at frequencies

between 100 MHz and few GHz [13] [14] as shown in Fig. 6.7a. This effect comes into picture

due to the majority carrier relaxation time of the silicon substrate which is nothing but the


Figure 6.11: Measured and extracted real part of H11 (gate resistance) vs frequency characteristic for Lg

= 100 nm. Symbols: Experimental Data, Lines: BSIM-IMG model.

Exp. Data 1st Order Thermal N/W Substrate Resistor N/W Gate Parasitic N/W

105 106 107 108 109 1010

2.4

2.6

2.8

3.0

3.2

3.4

Gate N/W

Substrate N/W

DC value of gDS

ΔGSHE

f (Hz)

Rea

l (Y

22),

mS

Thermal N/W

Figure 6.12: Measured and extracted real part of Y22 for Lg = 100 nm. Above GHz range, gate resistor

plays major role in predicting device behavior correctly due to its lower time constant. Excellent fitting

with experimental data shows the importance of thermal, substrate and gate networks. Bias conditions

are: Vfg = Vds = 1.1 V and Vbg = 0 V. Symbols: Experimental Data, Lines: BSIM-IMG model.

silicon resistivity (ρ) multiplied by its permittivity (ε0 ·εSi). Substrate under BOX has resistivity

around 20 Ω-cm. The relaxation frequency for silicon substrate is 12π·ρ·ε0·εSi

. The relaxation

frequency is in order of 100 MHz for high resistivity substrate. For frequencies lower than ∼100 MHz the substrate will behave as a conductor and can be modeled by a resistor. But for

frequencies higher than 100 MHz the substrate will behave as a dielectric and is modeled by

a capacitor. Hence the substrate related transition occurs corresponding to its dielectric cutoff

frequency around 100 MHz.


(a)

(b)

Figure 6.13: RF Fitting results are demonstrated for two channel lengths, named as device A and B.

Device A dimensions are Lg = 30 nm, Wg = 1μm, NF = 30 and Device B dimensions are Lg = 100 nm,

Wg = 0.5μm, NF = 60. Both devices have similar front/back gate oxide thickness and channel thickness

as follows: Tox = 1.2 nm, Tbox = 10 nm, Tsi = 8 nm. (a) Real Y22 vs. frequency characteristic. (b) The

imaginary part of Y11/(2π · freq) vs. frequency characteristic. Symbols: Experimental Data, Lines:

BSIM-IMG model.

In GHz range, parallel substrate resistance (R1 to R5) and capacitances (C1 to C5) start

affecting two-port parameter behavior of MOSFET [29]. Literature [30] [31] shows that a single

resistor substrate network is sufficient to predict correctly Real Y22 behavior till few GHz. The

proposed substrate network is shown in Fig. 6.7b is used to validate the BSIM-IMG model for

several GHz frequency range. The substrate network is shown in Fig. 6.7b is important for

accurate fitting of S22 in all bias ranges [32]. Fig. 6.8a shows the S11 (the input impedance


(a)

(b)

Figure 6.14: RF Fitting results are demonstrated for two channel lengths, named as device A and B.

Device A dimensions are Lg = 30 nm, Wg = 1μm, NF = 30 and Device B dimensions are Lg = 100 nm,

Wg = 0.5μm, NF = 60. Both devices have similar front/back gate oxide thickness and channel thickness

as follows: Tox = 1.2 nm, Tbox = 10 nm, Tsi = 8 nm. (a) Real H11 vs. frequency characteristic. (b) |H21|vs. frequency characteristic. Symbols: Experimental Data, Lines: BSIM-IMG model.

when the output port (drain) is terminated with 50 Ω) and S22 (the output impedance when the

input port (gate) is terminated with 50 Ω) on the smith chart as final validation of an RF model

for a wide frequency range. The phase of S11 and S22 are shown in Fig. 6.8b. The model

has shown good agreement with phase data which implies that the input port components (i.e.,

gate resistance and gate capacitance) and the output port components (i.e., substrate network

resistance and substrate capacitance) have been optimized well. Fig. 6.9 shows the current gain

(|H21|) vs. frequency, where model has good fitting with the measured data at Vbg = 0 V. By

extrapolating |H21| characteristic, we can get fT [33].


Step 1:

CGG vs. Vfg characteristic

Step 2:

Ids vs. Vfg@Vds = 50mV ,

Ids vs. Vfg@Vds = 1.1V ,

Ids vs. Vds characteristic

Step 3: Thermal network

Real Y22 vs. frequency

Step 4: Substrate network

Substrate resistance (RSUB)

extraction, S22 vs. frequency

Step 5: Gate network

Rg vs. frequency, CGG vs.

frequency, S11 vs. frequency

Step 6: RF figure of merit

Current gain vs. frequency

DC

par

amet

erex

trac

tio

nR

Fp

aram

eter

extr

acti

on

Figure 6.15: An illustration of RF parameter extraction flow in FD-SOI MOSFETs.

6.2.3 Gate Parasitic Network

High-k metal gate transistors are gaining momentum for RF applications due to the high tran-

sient frequency achievement [11] [34]. High-k metal gate transistors suffer from gate resistance

which reduces maximum frequency of oscillation [35] [36]. At high frequencies, parasitic resis-

tances/capacitances start playing an important role and affect the high-frequency performance

of the device. We will discuss here gate capacitance and resistance extraction in detail.

6.2.3.1 Gate Capacitance Network

Fig. 6.10a shows CGG = Imag(Y11)2πfreq

vs. front gate voltage at low frequency. Fig. 6.10b shows

Imag (Y11) vs. frequency characteristic. It shows the frequency behavior of Imag (Y11) for high

gate and drain voltages (Vfg = Vds = 1.1V ), where the model shows excellent fit.

6.3 Summary 104

6.2.3.2 Gate Resistance Network

Gate resistance consists of distributed gate resistance (Rg) and distributed contact resistance

(Rc). In strong inversion, contribution from source/drain series resistance (Rs/Rd) can be ne-

glected, hence contribution from gate resistance becomes dominant [37] [38]. Thus, effective

gate resistance (Rg) is extracted from real part of H11(=1

real(Y11)) as shown in Fig.6.11. As

described earlier, at low and medium frequency ranges thermal network and substrate networks

comes into the picture while at very high frequency gate resistor network plays important role

due to its lower time constant [19] as shown in Fig. 6.12. We have also compared the model

results for short channel length Lg = 30 nm data in Fig. 6.13 and Fig. 6.14. Fig. 6.8a also

shows S11 and S22 for channel lengths Lg = 30 nm, 100 nm. Fig 6.13a shows the impact of

gate and the substrate network on Real Y22. Higher fT (|H21| intercept on frequency axis) is

achieved from Lg = 30 nm transistor due to higher drain current as shown in Fig.6.14b. The

complete RF parameter extraction flow is shown in Figure 6.15.

6.3 Summary

Industry standard BSIM-IMG model has been enhanced to capture the high-frequency behavior

of FD-SOI MOSFETs. The impact of self-heating, gate and substrate on RF characteristics are

discussed in detail, and R-C networks in the same are proposed. The step-by-step DC and RF

parameter extraction procedure are proposed and validated on the measured characteristics of

30 nm and 100 nm channel length transistors for a wide range of biases and frequencies. The

BSIM-IMG model shows an excellent match with measured data showing model’s readiness

for high-frequency circuits using FD-SOI technology.

Bibliography

[1] D. Wang, R. Wolf, A. Joseph, A. Botula, P. Rabbeni, M. Boenke, D. Harame, and J. Dunn,

“High performance SOI RF switches for wireless applications,” in Proc. of IEEE Interna-tional Conference on Solid-State and Integrated Circuit Technology, p. 611614, 2010.



Solid-State Electronics, vol. 104, pp. 6 – 11, 2015.

[3] J.-O. Plouchart, “Applications of SOI technologies to communication,” in Proc. of IEEESymposium on Compound Semiconductor Integrated Circuit, pp. 1–4, 2011.

[4] H. Van Meer and K. De Meyer, “Ultra-thin film fully-depleted SOI CMOS with raised

G/S/D device architecture for sub-100 nm applications,” in Proc. of IEEE InternationalSOI Conference, pp. 45–46, 2001.

[5] Q. Liu, A. Yagishita, N. Loubet, A. Khakifirooz, P. Kulkarni, T. Yamamoto, K. Cheng,

M. Fujiwara, J. Cai, D. Dorman, S. Mehta, P. Khare, K. Yako, Y. Zhu, S. Mignot,

S. Kanakasabapathy, S. Monfray, F. Boeuf, C. Koburger, H. Sunamura, S. Ponoth,

A. Reznicek, B. Haran, A. Upham, R. Johnson, L. F. Edge, J. Kuss, T. Levin, N. Berliner,

E. Leobandung, T. Skotnicki, M. Hane, H. Bu, K. Ishimaru, W. Kleemeier, M. Takayanagi,

B. Doris, and R. Sampson, “Ultra-thin-body and BOX UTBB fully depleted FD device in-

tegration for 22nm node and beyond,” in Proc. of IEEE Symposium on VLSI Technology,

pp. 61–62, 2010.



“Multi-Vt UTBB FDSOI device architectures for low-power CMOS circuit,” IEEE Trans-actions on Electron Devices, vol. 58, no. 8, pp. 2473–2482, 2011.



and O. Faynot, “Low power UTBOX and back plane BP FDSOI technology for 32nm

node and below,” in Proc. of IEEE International Conference on IC Design Technology,

pp. 1–4, 2011.

105

BIBLIOGRAPHY 106

[8] T. Takahashi, T. Matsuki, T. Shinada, Y. Inoue, and K. Uchida, “Comparison of self-

heating effect (she) in short-channel bulk and ultra-thin BOX SOI MOSFETs: Impacts of

doped well, ambient temperature, and SOI/BOX thicknesses on SHE,” in Proc. of IEEEInternational Electron Devices Meeting (IEDM), pp. 7.4.1–7.4.4, 2013.

[9] O. Weber, O. Faynot, F. Andrieu, C. Buj-Dufournet, F. Allain, P. Scheiblin, J. Foucher,

N. Daval, D. Lafond, L. Tosti, L. Brevard, O. Rozeau, C. Fenouillet-Beranger, M. Marin,

F. Boeuf, D. Delprat, K. Bourdelle, B. Y. Nguyen, and S. Deleonibus, “High immunity

to threshold voltage variability in undoped ultra-thin FDSOI MOSFETs and its physical

understanding,” in Proc. of IEEE International Electron Devices Meeting (IEDM), pp.

1–4, 2008.

[10] T. C. Lim, O. Rozeau, C. Buj, M. Paccaud, G. Dambrine, and F. Danneville, “High fre-

quency performance of sub-100nm UTB FDSOI featuring TiN/HfO2 gate stack,” Solid-State Electronics, vol. 53, no. 4, pp. 433 – 437, 2009.

[11] C. H. Jan, M. Agostinelli, H. Deshpande, M. A. El-Tanani, W. Hafez, U. Jalan, L. Janbay,

M. Kang, H. Lakdawala, J. Lin, Y. L. Lu, S. Mudanai, J. Park, A. Rahman, J. Rizk, W. K.

Shin, K. Soumyanath, H. Tashiro, C. Tsai, P. VanDerVoorn, J. Y. Yeh, and P. Bai, “RF

CMOS technology scaling in high-k/metal gate era for RF SoC (system-on-chip) appli-

cations,” in Proc. of IEEE International Electron Devices Meeting (IEDM), pp. 27.2.1–

27.2.4, 2010.

[12] F. Zarate-Rincon, R. Murphy-Arteaga, R. Torres-Torres, A. Ortiz-Conde, and F. Garcia-

Sanchez, “Modeling the impact of multi-fingering microwave MOSFETs on the source

and drain resistances,” IEEE Transaction on Microwave Theory and Technique, vol. 62,

no. 12, pp. 3255–3261, 2014.

[13] S. Makovejev, V. Kilchytska, M. K. M. Arshad, D. Flandre, F. Andrieu, O. Faynot,

S. Olsen, and J. P. Raskin, “Self-heating and substrate effects in ultra-thin body ultra-

thin BOX devices,” in Proc. of 12th International Conference on Ultimate Integration onSilicon (ULIS), pp. 1–4, 2011.

[14] V. Kilchytska, D. Levacq, D. Lederer, J. P. Raskin, and D. Flandre, “Floating effective

back-gate effect on the small-signal output conductance of SOI MOSFETs,” IEEE Elec-tron Device Letters, vol. 24, no. 6, pp. 414–416, 2003.

[15] W. Jin, W. Liu, S. Fung, P. C. Chan, and C. Hu, “SOI thermal impedance extraction

methodology and its significance for circuit simulation,” IEEE Transactions on ElectronDevices, vol. 48, no. 4, pp. 730–736, 2001.




BIBLIOGRAPHY 107




[18] S. Makovejev, B. K. Esfeh, V. Barral, N. Planes, M. Haond, D. Flandre, J. P. Raskin, and

V. Kilchytska, “Wide frequency band assessment of 28 nm FDSOI technology platform

for analogue and RF applications,” Solid-State Electronics, vol. 24, no. 6, pp. 414–416,

2015.

[19] A. J. Scholten, G. D. J. Smit, R. M. T. Pijper, L. F. Tiemeijer, H. P. Tuinhout, J. L. P. J.

van der Steen, A. Mercha, M. Braccioli, and D. B. M. Klaassen, “Experimental assessment

of self-heating in SOI FinFETs,” in Proc. of IEEE International Electron Devices Meeting(IEDM), pp. 1–4, 2009.

[20] P. Kushwaha, C. Yadav, H. Agarwal, Y. S. Chauhan, J. Srivatsava, S. Khandelwal, J. P.

Duarte, and C. Hu, “BSIM-IMG with improved surface potential calculation recipe,” inProc. of IEEE India Conference (INDICON), pp. 1–4, 2014.

[21] J. P. Duarte, S. Khandelwal, A. Medury, C. Hu, P. Kushwaha, H. Agarwal, A. Dasgupta,

and Y. S. Chauhan, “BSIM-CMG: Standard finfet compact model for advanced circuit

design,” in Proc. of European Solid-State Circuits Conference (ESSCIRC), pp. 196–201,

2015.

[22] P. Kushwaha, H. Agarwal, S. Khandelwal, J. P. Duarte, A. Medury, C. Hu, and Y. S.

Chauhan, “BSIM-IMG: Compact model for RF-SOI MOSFETs,” in Proc. of IEEE 73rdInternational Conference on Device Research Conf. (DRC), pp. 287–288, 2015.

[23] S. Khandelwal, H. Agarwal, P. Kushwaha, J. P. Duarte, A. Medury, Y. S. Chauhan,

S. Salahuddin, and C. Hu, “Unified compact model covering drift-diffusion to ballistic

carrier transport,” IEEE Electron Device Letters, vol. 37, no. 2, pp. 134–137, 2016.

[24] Y. S. Chauhan, D. Lu, S. Venugopalan, S. Khandelwal, J. P. Duarte, N. Paydavosi,

A. Niknejad, and C. Hu, FinFET Modeling for IC Simulation and Design: Using theBSIM-CMG Standard. Academic Press, 2015.

[25] S. Makovejev, B. K. Esfeh, J. P. Raskin, V. Kilchytska, D. Flandre, V. Barral, N. Planes,

and M. Haond, “Variability of UTBB MOSFET analog figures of merit in wide frequency

range,” in Proc. of 44th European Solid State Device Research Conference (ESSDERC),pp. 222–225, 2014.

[26] S. Makovejev, S. Olsen, and J. Raskin, “RF extraction of self-heating effects in FinFETs,”

IEEE Transaction Electron Devices, vol. 58, no. 10, pp. 3335–3341, Oct 2011.

[27] B. Tenbroek, M. Lee, W. Redman-White, R. Bunyan, and M. Uren, “Self-heating effects

in SOI MOSFETs and their measurement by small signal conductance techniques,” IEEETransaction Electron Devices, vol. 43, no. 12, pp. 2240–2248, Dec 1996.

BIBLIOGRAPHY 108

[28] M. A. Karim, Y. S. Chauhan, S. Venugopalan, A. B. Sachid, D. D. Lu, B. Y. Nguyen,

O. Faynot, A. M. Niknejad, and C. Hu, “Extraction of isothermal condition and thermal

network in UTBB SOI MOSFETs,” IEEE Electron Device Letters, vol. 33, no. 9, pp.

1306–1308, Sept 2012.

[29] D. Pehlke, M. Schroter, A. Burstein, M. Matloubian, and M. Chang, “High-frequency ap-

plication of MOS compact models and their development for scalable RF model libraries,”

in Proc. of IEEE Conference on Custom Integrated Circuits, pp. 219–222, 1998.

[30] C. Enz, “MOS transistor modeling for RF integrated circuit design,” in Proc. of IEEEConference on Custom Integrated Circuits, pp. 189–196, 2000.

[31] S. F. Tin and K. Mayaram, “Substrate network modeling for CMOS RF circuit simulation,”

in Proc. of IEEE Conference on Custom Integrated Circuits, pp. 583–586, 1999.

[32] W. Liu, R. Gharpurey, M. Chang, U. Erdogan, R. Aggarwal, and J. Mattia, “RF MOSFET

modeling accounting for distributed substrate and channel resistances with emphasis on

the BSIM3v3 SPICE model,” in Proc. of IEEE International Electron Devices Meeting(IEDM), pp. 309–312, 1997.

[33] S. Lee, B. Jagannathan, S. Narasimha, A. Chou, N. Zamdmer, J. Johnson, R. Williams,

L. Wagner, J. Kim, J. O. Plouchart, J. Pekarik, S. Springer, and G. Freeman, “Record RF

performance of 45-nm SOI CMOS technology,” in Proc. of IEEE International ElectronDevices Meeting (IEDM), pp. 255–258, 2007.

[34] J. Costa, “Passing the plateau of productivity: Development of RFSOI technologies on

HR silicon substrates for reconfigurable wireless solutions,” IEEE Microwave Magazine,

vol. 15, no. 7, pp. S61–S73, 2014.

[35] S. Voinigescu, S. Tarasewicz, T. MacElwee, and J. Ilowski, “An assessment of the state-

of-the-art 0.5 μm bulk CMOS technology for RF applications,” in Proc. of IEEE Interna-tional Electron Devices Meeting (IEDM), pp. 721–724, 1995.

[36] L. Tiemeijer and D. Klaassen, “Geometry scaling of the substrate loss of RF MOSFETs,”

in Proc. of 28th European Conference on Solid-State Device Research, pp. 480–483, 1998.

[37] B. Dormieu, P. Scheer, C. Charbuillet, H. Jaouen, and F. Danneville, “Revisited RF com-

pact model of gate resistance suitable for high-k/metal gate technology,” IEEE Transac-tions on Electron Devices, vol. 60, no. 1, pp. 13–19, 2013.

[38] X. Jin, J.-J. Ou, C.-H. Chen, W. Liu, M. J. Deen, P. R. Gray, and C. Hu, “An effective

gate resistance model for CMOS RF and noise modeling,” in Proc. of IEEE InternationalElectron Devices Meeting (IEDM), pp. 961–964, 1998.

Chapter 7

Characterization of High frequency (RF)Noise in UTBB FD-SOI MOSFETs

Ultra-thin body fully depleted (FD) silicon on insulator (SOI) MOSFETs are being used at 28

nm and below due to their excellent electrostatic control [1–9]. Apart from digital applications,

FD-SOI MOSFETs are also getting strong interest from RF circuit designers for high-frequency

applications [10, 11]. At RF frequencies, thermal noise becomes an important factor in the

design of circuits as it decides the noise floor for the signal. It is well known that thermal noise

is a function of the temperature and the conductivity of the channel. FD-SOI MOSFETs have

higher thermal noise compared to bulk MOSFETs due to high lattice temperature originating

from the poor thermal conductivity of the buried oxide (BOX). Hence, careful analysis and

measurements of thermal noise in such devices are of utmost importance.

Although RF noise characterization for thick BOX FD-SOI MOSFETs has been presented

[12–14]; there is no work reporting the same for thin BOX FD-SOI MOSFETs. In this chapter,

we report the measured data for an FD-SOI MOSFET with 8 nm thin channel and 25 nm thin

BOX and discuss the impact of the drain and the front/back gate biases on the high-frequency

noise. Fig. 7.1 shows the UTBB FD-SOI structure used in this study. The dependence of

noise on the back gate bias is especially important as the back gate bias is often used to tune

the threshold voltage (Vth) of these devices. Also, the substrate below the thin BOX plays an

important role at RF frequencies and shows significant impact on the thermal noise. Hence, we

also present an analysis of the impact of substrate resistivity and BOX thickness on the thermal

noise.

We will start this chapter with the discussion on thermal noise and related parameters. Then

we discuss the TCAD calibration and measurement setup used for the thermal noise charac-

terization. We close this chapter with a discussion on secondary effects inherent with FD-SOI

MOSFETs and their impact on noise parameters.

109

7.1 Thermal noise and related parameters 110

Figure 7.1: Schematic of the ultra-thin body and thin buried oxide fully depleted silicon on insulator

(UTBB FD-SOI) MOSFET. The Device under test (DUT) is from 28 nm technology node fabricated at

CEA-LETI.

7.1 Thermal noise and related parameters

Since noise is a random event with zero average, it is measured and analyzed using specific

parameters that highlight the device behavior accurately. One such parameter is the Noise

figure (NF), which is the ratio of the signal to noise ratio at the input port to that at the output

port. NF50 denotes the Noise Figure measurement performed with a source impedance of 50

Ω (see (7.1)), and NFmin denotes the minimum achievable noise figure (see (7.2)) for a device

under fixed bias conditions. NFmin and NF50 are given as [15]

NF50 =1 +RnGs +

(f

fT

)2S2id

16k2BT2g2mRnGs

(7.1)

NFmin = 1 + 2[(ωCgg)2Rgs(Rn −Rgs + r − r(RgsωCgs)

2)

+ωCgg(Rn(Rn −Rgs + r − r(RgsωCgs)2)

−(Rn −Rgs − r(RgsωCgs)2)2)1/2]

(7.2)

where Gs = (1/50)Ω−1 is the source admittance, kB is the Boltzmann constant, T is the

temperature, Sid is the noise power spectral density and r = 415gm

with gm denoting the trans-

conductance. Rgs = Rg +Rs, where Rg and Rs are the gate and the source resistances, respec-

tively. Gate capacitance Cgg = Cgs + Cgd, where Cgs is the gate-to-source capacitance and Cgd

is the gate-to-drain capacitance; while ω (= 2 π f ) is the frequency of operation in rad/second

and fT is the cutoff frequency. It should be noted that the equations presented here for NF50

and NFmin do not take the induced gate noise into account because it is not as significant as the

channel thermal noise for the frequency range under consideration [16]. The noise resistance

7.2 TCAD Calibration 111

(Rn) is an effective representation of the channel thermal noise which is extracted from NF50

as [15]

Rn =(NF50 − 1)− (ωCgg)

2 (r −Rgs − r(RgsωCgs)2)RA

(ωCgg)2(2Rgs +

1Gs

)+Gs

(7.3)

where RA =(2Rgs +

1Gs

). Another important parameter is the source side reflection co-

efficient, Γopt (=Zopt−Zo

Zopt+Zo). Zo is the characteristic impedance of the system while Zopt (= 1

Yopt)

is the optimum source impedance and Yopt (= Gopt + jBopt ) is the optimum source admittance

which results in minimum noise figure [16]. Gopt and Bopt are given as [16]

Gopt =ωCgg

Rn

(Rn(Rn −Rgs + r − r(RgsωCgs)2)−(

Rn −Rgs − r(RgsωCgs)2)2)1/2 (7.4)

Bopt =− ωCgg

Rn

(Rn −Rgs − r(RgsωCgs)

2)

(7.5)

7.2 TCAD Calibration

We have investigated the thermal noise behavior of FD-SOI MOSFET using Silvaco-ATLAS

technology computer aided design (TCAD) tool [17] as shown in Fig. 7.2a. Lombardi CVT

model [18] is used to capture the mobility degradation that occurs inside inversion layers due to

surface scattering. Uchida’s low-field model for ultra-thin SOI [19] is used to limit the mobility

according to SOI thickness. Mobility model parameters for drift-diffusion transport, and the

impact of fixed oxide charges in sub-threshold region are calibrated with the measurement data.

The characterization setup used to obtain the measurement data is discussed in Section 7.3. Fig.

7.2b shows the good agreement of the TCAD results with the experimental data for a transistor

with Lg = 100 nm, Wg = 40 μm.

7.3 Measurement Setup

Fig. 7.3a and Fig. 7.3b show the noise measurement setup used in this work. It includes a vector

network analyzer, a noise figure meter (NFM) to measure noise power, a source-pull tuner to

vary the impedance seen by the DUT and a noise source. The measurement setup is controlled

by Keysight’s IC-CAP tool. The low noise amplifier (LNA) is used before the NFM to boost the

7.3 Measurement Setup 112

(a)

(b)

Figure 7.2: (a) Calibration of TCAD models for drift diffusion transport with experimental data of FD-

SOI MOSFET. TCAD device parameters are: gate work function = 4.9 eV, source/ drain Doping = 1e20

cm−3, body doping = 1e15 cm−3, interface charge = 7e10 cm−2, source resistance = 200 Ω · μm. Device

dimensions are: Channel length Lg = 100 nm, Gate width Wg = 40 μm, Effective oxide thickness Tox =

1.2 nm, Back gate oxide thickness Tbox = 25 nm, Channel silicon thickness Tsi = 8 nm. (b) Drain current

Ids vs front gate bias Vfg characteristic for different back gate biases (Vbg) from the measurement as well

as calibrated TCAD simulations. Bias conditions are: Front gate voltage Vfg = 0 to 1.2 V, Back gate

voltages are Vbg = -3, 0, 3 V, Drain voltage Vds = 1.2 V. Symbols: Measured Data, Lines: TCAD Data.

weak noise signal, which increases the accuracy of the measurement [16]. In this work, we have

measured the Noise figure (defined later) keeping a fixed source impedance of 50 Ω. The DUTs

belongs to the 28 nm technology node from CEA-LETI (see Fig. 7.3b). We have performed the

measurements on two channel lengths (Lg = 50 nm and 100 nm). Other device dimensions are:

channel width Wg = 1 μm, number of fingers NF = 40, effective oxide thickness Tox = 1.2 nm,

back gate oxide thickness Tbox = 25 nm and silicon channel thickness Tsi = 8 nm.

7.4 Secondary Noise Sources in FD-SOI MOSFET 113

(a) (b)

Figure 7.3: (a) Bench synopsis for RF noise figure measurement. A separate DC power supply (not

shown here) is used for applying back-gate bias through substrate. (b) Photograph of the experimen-

tal setup for the noise figure measurement. Picture of the actual DUT along with the probes is also

illustrated. The noise measurements were performed at IMS lab in University of Bordeaux1, France.

Figure 7.4: Schematic of the substrate network showing substrate induced noise source in FD-SOI MOS-

FET. Rsub is the equivalent substrate resistance while Csub is the substrate capacitance. Vfg/Vbg are the

applied front/back gate voltages and Vd/Vs are the drain/source voltages. The substrate coupling results

in higher NFmin due to Rsub induced thermal noise at the drain [20].

7.4 Secondary Noise Sources in FD-SOI MOSFET

FD-SOI MOSFETs have secondary noise sources which get coupled with the channel thermal

noise and result in higher NFmin than expected from the channel thermal noise alone. The

majority carriers in the substrate also impact the device performance at high frequencies [21],

as they dictate the substrate loss. The doping of the silicon substrate below the BOX plays

a major role in increasing (or decreasing [22]) this substrate loss and the channel noise [20].

FD-SOI MOSFETs with the high substrate resistivity (or lightly doped substrate) are preferred

for RF applications due to their high integration capabilities along with the advantages of lower

7.5 Results and Discussion 114

(a) (b)

Figure 7.5: (a) NFmin vs. substrate doping characteristic. The substrate depletion and the substrate resis-

tance Rsub induced thermal noises also contribute to the overall noise, creating fluctuations in NFmin.

(b) NFmin vs. BOX thickness characteristic. NFmin increases further with BOX thinning due to an

increase in the substrate coupled thermal noise. Line with symbol: TCAD data.

noise and lower crosstalk [23, 24]. The depletion in the substrate and the substrate resistance

act as extra noise sources (see Fig. 7.4). The substrate depletion and the substrate resistance

Rsub induced thermal noises also contribute to the overall noise. Fig. 7.5a shows the NFmin

vs. substrate doping obtained from calibrated TCAD simulations. We can see that NFmin

changes with substrate doping due to the substrate coupled thermal noise. Fig. 7.5b shows the

NFmin variation with BOX thickness, which indicates that as thickness decreases, the substrate

coupling with the channel increases, resulting in increased thermal noise.

7.5 Results and Discussion

Fig. 7.6 shows the frequency dependence of NF50 for different bias sweeps. The NF50 shown

in Fig. 7.6(a) - Fig. 7.6(c) is more or less constant with frequency, whereas (7.1) predicts a

parabolic dependence [25, 26]. This is because the frequency dependent term,(

ffT

)2S2id

16k2BT 2g2mRnGs,

is smaller than 1+RnGs for the measured device for the frequency range used here. Inset of Fig.

7.6(a) shows NF50 as a function of the front gate bias (Vfg). As Vfg increases, the total number

of charge carriers in the device increases. This results in higher drain current and more carrier

collisions in the channel which in turn increases the overall noise (i.e., higherNFmin) [27]. Fig.

7.2b shows that, with the increase in positive back-gate bias (Vbg), the threshold voltage (Vth)

decreases [28] which results in higher drain current and higher thermal noise. This increased


(a) (b)

(c)

Figure 7.6: (a) Measured NF50 vs. frequency characteristics of different front-gate biases Vfg = 0.8, 1,

1.2, 1.4 V. Frequency is swept from 1 to 18 GHz with the step size of 1 GHz. The inset figure shows

the NF50 vs Vfg characteristics for two channel lengths Lg = 50, 100 nm. (b) NF50 vs. frequency

characteristics for different back-gate biases Vbg = -3, 0, 3 V. The inset figure shows the NF50 vs Vbg

characteristic for Lg = 100 nm. (c) NF50 vs. frequency characteristics for different drain biases Vds = 1,

1.2, 1.4 V. The inset figure shows the NF50 vs Vds characteristic for Lg = 100 nm. Device dimensions

are: Wg=1 μm, NF = 40, Tox = 1.2 nm, Tbox = 25 nm, Tsi = 8 nm.

thermal noise results in higher noise figure as shown in the inset of Fig. 7.6(b). To the best

of our knowledge, the behavior of NF50 with changing back-gate bias for thin BOX FD-SOI

MOSFETs is being reported for the first time. The inset of Fig. 7.6(c) shows thatNF50 is nearly

constant with drain bias (Vds) as the noise does not change with Vds in the saturation region due

to the phenomenon of velocity saturation [29]. A similar trend has been reported by Adan

et.al. [30] for SOI MOSFETs. It is well known that the accurate measurement of noise param-


(a) (b)

(c)

Figure 7.7: (a) Measured NFmin vs. frequency characteristics. (b) NFmin vs. frequency characteristics

from TCAD simulations. (c) NFmin vs. frequency characteristics extracted from s-parameter measure-

ments for an FD-SOI MOSFET (Lg = 100 nm) with highly doped substrate below the BOX. Frequency

is swept from 1 to 18 GHz with the step size of 0.5 GHz. Bias conditions are: Vfg = 1.2 V and Vds = 1.2

V. Parameter values used to calculate NFmin for the device are: Rgs = 37.47 Ω and Rn = 1.7, 2.02, 2.35

kΩ for Vbg = -3, 0, 3 V, respectively. Cgs = Cgg - Cgd, where Cgg and Cgd are shown in Fig. 7.11b.

eters is difficult (see measured data in Fig. 7.7a and Fig. 7.9a) for short channel devices [31].

Also, in our case, the channel width of the measured device is small, making measurements

susceptible to other noise sources in the measurement setup. Hence, we have also measured

the S-parameters and have used these, along with the NF50 measurements, to extract the noise

parameters Rn, NFmin, Bopt, Gopt and Γopt as defined from (7.1) to (7.5). Fig. 7.7 shows the

frequency dependence of the minimum noise figure for Vfg = 1.2 V and Vds = 1.2 V for different


(a) (b)

Figure 7.8: (a) The top figure shows Gopt vs. frequency characteristics while the bottom figure shows

Bopt vs. frequency characteristics, both from TCAD simulations. (b) The top figure shows Gopt vs.

frequency characteristics while the bottom figure shows Bopt vs. frequency characteristics extracted

from S-parameter measurements. Bias conditions are: Vfg = 1.2 V and Vds = 1.2 V. Parameter values

used to calculate the noise parameters for Lg = 100 nm device are: Rgs = 37.47 Ω and Rn = 1.7, 2.02,

2.35 kΩ for Vbg = -3, 0, 3 V, respectively. Cgs = Cgg - Cgd, where Cgg and Cgd are shown in Fig. 7.11b.

back-gate biases Vbg = -3, 0, 3 V. Fig. 7.7c shows that the NFmin extracted from S-parameter

measurements increases with frequency as expected [26, 32].

From (7.4) and (7.5), we can see that Gopt (∝ f) and Bopt (∝ - f) are proportional to fre-

quency. As a result Fig. 7.8 shows an increase in the magnitude of Gopt and Bopt with positive

and negative slopes, respectively. Fig. 7.9 shows the variation in the magnitude and the phase of

Γopt with the changing frequency. These trends of NFmin, Gopt, Bopt and Γopt (magnitude and

phase) are in good agreement with TCAD simulations as well as with the literature [16, 25, 26].

Fig. 7.10a shows the behavior of the noise resistance with front gate bias for three different back

gate biases. The extracted Rn does not change significantly with frequency because it depends

on gm and Cgg (see (7.1) and (7.3)), which are independent of frequency (see Fig. 7.11a and

Fig. 7.11b).

Although noise resistance Rn is defined in (7.3) in terms of the device parameters, it can

also be expressed as [16]:

Rn = Rgs +Sid

g2mIds (7.6)

From Fig. 7.11a, we observe that for higher Vfg (= 1.2 V), the transconductance, gm(= Re(Y21)),

does not vary much with back gate bias while Fig. 7.10a shows larger variation of Rn with back


(a)

(b)

(c)

Figure 7.9: (a) Measured Γopt vs. frequency characteristics. (b) Γopt vs. frequency characteristics from

TCAD simulations. (c) Γopt vs. frequency characteristics extracted from S-parameter measurements.

Bias conditions are: Vfg = 1.2 V and Vds = 1.2 V. Parameter values used to calculate the Γopt are: Rgs =

37.47 Ω and Rn = 1.7, 2.02, 2.35 kΩ for Vbg = -3, 0, 3 V, respectively. Cgs = Cgg - Cgd, where Cgg and

Cgd are shown in Fig. 7.11b.


(a) (b)

Figure 7.10: (a) Rn vs. Vfg characteristics for different back-gate biases: Vbg = -3, 0, 3 V. (b) Noise

power spectral density Sid from TCAD simulations vs. frequency characteristics for different back-gate

biases: Vbg = -3, 0, 3 V. Bias conditions are: Vfg = 1.2 V and Vds = 1.2 V. Device dimensions are: Lg =

100 nm, Wg=1 μm, NF = 40, Tox = 1.2 nm, Tbox = 25 nm, Tsi = 8 nm.

(a) (b)

Figure 7.11: (a) Real part of Y21 extracted from S-parameter measurements, vs. frequency for different

back-gate biases: Vbg = -3, 0, 3 V. Inset shows gm (DC measured data) vs. Vfg characteristics for

different back-gate biases: Vbg = -3, 0, 3 V. (b) Cgg and Cgd extracted from S-parameter measurements

vs. frequency characteristics for different back-gate biases: Vbg = -3, 0, 3 V. Bias conditions are: Vfg =

1.2 V and Vds = 1.2 V.

7.6 Summary 120

gate bias. From (7.6), this larger sensitivity of Rn with back bias can be attributed to the signif-

icant change in Sid with Vbg [27] as shown by TCAD simulation, in Fig. 7.10b.

7.6 Summary

High-frequency noise characterization of UTBB-SOI MOSFET is reported for the first time.

At high frequencies, substrate resistance induced thermal noise gets coupled with the channel

noise and results in higher than expectedNFmin. Using calibrated TCAD simulations, we show

that the noise figure changes with the substrate doping and buried oxide thickness. We observe

that thermal noise increases with positive back-bias due to an increase in the number of channel

carriers and their collisions. Also, noise figure does not vary significantly with drain bias due

to the dominance of the velocity saturation phenomenon in the saturation region.

Bibliography

[1] Y.-K. Choi, K. Asano, N. Lindert, V. Subramanian, T.-J. King, J. Bokor, and C. Hu,

“Ultrathin-body SOI MOSFET for deep-sub-tenth micron era,” IEEE Electron Device Let-ters, vol. 21, no. 5, pp. 254–255, 2000.

[2] Y.-K. Choi, Y.-C. Jeon, P. Ranade, H. Takeuchi, T.-J. King, J. Bokor, and C. Hu, “30

nm Ultra-Thin-Body SOI MOSFET with selectively deposited Ge raised S/D,” in Proc. of58th Device Research Conference, Conference Digest., pp. 23–24, 2000.

[3] V. Kilchytska, D. Levacq, D. Lederer, J.-P. Raskin, and D. Flandre, “Floating effective

back-gate effect on the small-signal output conductance of SOI MOSFETs,” IEEE Elec-tron Device Letters, vol. 24, no. 6, pp. 414–416, 2003.

[4] S. Makovejev, B. Kazemi Esfeh, V. Barral, N. Planes, M. Haond, D. Flandre, J.-P. Raskin,

and V. Kilchytska, “Wide frequency band assessment of 28 nm FDSOI technology plat-

form for analogue and RF applications,” Solid-State Electronics, vol. 108, pp. 47–52,

2015.

[5] Q. Xie, C. J. Lee, J. Xu, C. Wann, J. Sun, and Y. Taur, “Comprehensive analysis of

short-channel effects in ultrathin SOIMOSFETs,” IEEE Transactions on Electron Devices,

vol. 60, no. 6, pp. 1814–1819, 2013.




delle, B. Y. Nguyen, F. Boedt, S. Denorme, F. Boeuf, O. Faynot, and T. Skotnicki, “Effi-

cient multi-VT FDSOI technology with UTBOX for low power circuit design,” in Proc.of IEEE Symposium on VLSI Technology, pp. 65–66, 2010.

[7] F. Andrieu, O. Weber, J. Mazurier, O. Thomas, J.-P. Noel, C. Fenouillet-Beranger, J.-P.

Mazellier, P. Perreau, T. Poiroux, Y. Morand, T. Morel, S. Allegret, V. Loup, S. Barnola,

F. Martin, J. Damlencourt, I. Servin, M. Casse, X. Garros, O. Rozeau, M.-A. Jaud,

G. Cibrario, J. Cluzel, A. Toffoli, F. Allain, R. Kies, D. Lafond, V. Delaye, C. Tabone,

L. Tosti, L. Brevard, P. Gaud, V. Paruchuri, K. Bourdelle, W. Schwarzenbach, O. Bonnin,

B. Nguyen, B. Doris, F. Buf, T. Skotnicki, and O. Faynot, “Low leakage and low variabil-

ity ultra-thin body and buried oxide (UT2B) SOI technology for 20 nm low power CMOS

and beyond.” in Proc. of IEEE Symposium on VLSI Technology, pp. 57–58, 2010.

121

BIBLIOGRAPHY 122

[8] S. Khandelwal, Y. S. Chauhan, D. D. Lu, S. Venugopalan, M. A.U. Karim, A. B. Sachid,



[9] P. Kushwaha, H. Agarwal, S. Khandelwal, J. P. Duarte, A. Medury, C. Hu, and Y. S.

Chauhan, “BSIM-IMG: Compact model for RF-SOI MOSFETs,” in Proc. of IEEE 73rdAnnual Device Research Conference, pp. 287–288, 2015.


of FDSOI transistors using industry standard BSIM-IMG model,” IEEE Transactions onMicrowave Theory and Techniques, no. 99, pp. 1–7, 2016.

[11] A. Larie, E. Kerherv, B. Martineau, L. Vogt, and D. Belot, “2.10 A 60GHz 28nm UTBB

FD-SOI CMOS reconfigurable power amplifier with 2118.2dbm p1db and 74mw PDC,”

in Proc. of IEEE International Solid-State Circuits Conference (ISSCC), pp. 1–3, 2015.

[12] R. Rengel, J. Mateos, D. Pardo, T. Gonzalez, M. J. Martin, G. Dambrine, F. Danneville,

and J.-P. Raskin, “High-frequency noise in FDSOI MOSFETs: a monte carlo investiga-

tion,” in Proc. of SPIE, Noise in Devices and Circuits, vol. 5113, 2003.

[13] R. Rengel, M. J. Martn, T. Gonzlez, J. Mateos, D. Pardo, G. Dambrine, J.-P. Raskin, and

F. Danneville, “A microscopic interpretation of the RF noise performance of fabricated

FDSOI MOSFETs,” IEEE Transactions on Electron Devices, vol. 53, no. 3, pp. 523–531,

March 2006.

[14] C. Raynauda, O. Faynota, J.-L. Pelloiea, C. Tabonea, A. Grouilleta, F. Martina,

G. Dambrineb, M. Vanmackelbergb, L. Pichetab, E. Mackowiakc, H. Brutc, P. Llinaresc,

J. Sevenhansd, E. Compagnee, G. Fletcherf, D. Flandreg, V. Dessardg, D. Vanhoenackerg,

and J.-P. Raskin, “70 GHz fmax fully-depleted SOI MOSFETs for low-power wireless

applications,” in Proc. of 30th European Microwave Week GaAs 2000, pp. 65–66, 2010.

[15] R.-A. Pucel, H. Statz, and H.-A. Haus, “Signal and noise properties of gallium arsenide

microwave field-effect transistors,” Academic Press, Advances in Electronics and ElectronPhysics, vol. 38, no. 12, pp. 195 – 265, 1975.

[16] S. Asgaran, M. Deen, and C.-H. Chen, “Analytical modeling of MOSFETs channel noise

and noise parameters,” IEEE Transactions on Electron Devices, vol. 51, no. 12, pp. 2109–

2114, Dec. 2004.

[17] “Atlas users manual.” [Online]. Available: https://dynamic.silvaco.com/dynamicweb/jsp/

downloads/DownloadManualsAction.do?req=silen-manuals&nm=atlas

[18] C. Lombardi, S. Manzini, A. Saporito, and M. Vanzi, “A physically based mobility model

for numerical simulation of nonplanar devices,” IEEE Transactions on CAD, p. 1164,

1988.

BIBLIOGRAPHY 123

[19] K. Uchida and S. Takagi, “Carrier scattering induced by thickness fluctuation of silicon-

on-insulator film in ultrathin-body metal-oxide-semiconductor field-effect transistors,”

Applied Phys. Lett., vol. 82, no. 17, pp. 2916–2918, 2003.

[20] A. O. Adan., Y. Toshihiko, S. Shitara, N. Tanba, and M. Fukumi, “Linearity and low-

noise performance of SOI MOSFETs for RF applications,” IEEE Transactions on ElectronDevices, vol. 49, no. 5, pp. 881–888, 2002.

[21] S. Makovejev, J.-P. Raskin, M. M. Arshad, D. Flandre, S. Olsen, F. Andrieu, and

V. Kilchytska, “Impact of self-heating and substrate effects on small-signal output con-

ductance in UTBB SOI MOSFETs,” Solid-State Electronics, vol. 71, pp. 93–100, 2012.

[22] D. Lederer and J.-P. Raskin, “New substrate passivation method dedicated to HRSOI wafer

fabrication with increased substrate resistivity,” IEEE Transactions on Electron Devices,

vol. 26, no. 11, pp. 805–807, 2005.

[23] D. Wang, R. Wolf, A. Joseph, A. Botula, P. Rabbeni, M. Boenke, D. Harame, and J. Dunn,

“High performance SOI RF switches for wireless applications,” IEEE Solid State andIntegrated Circuit Technology, pp. 611–614, 2010.

[24] J. O. Plouchart, “Applications of SOI technologies to communication,” in Proc. of IEEESymposium on Compound Semiconductor Integrated Circuit, pp. 1–4, 2011.

[25] M. J. Deen, C.-H. Chen, S. Asgaran, G. A. Rezvani, J. Tao, and Y. Kiyota, “High-

frequency noise of modern MOSFETs: Compact modeling and measurement issues,”


[26] A. Saman, J. M. Deen, C. Chih Hung, G. Ali Rezvani, K. Yasmin, and K. Yukihiro, “Ana-

lytical determination of MOSFET’s high-frequency noise parameters fromNF50 measure-

ments and its application in RFIC design,” IEEE Journal of Solid-State Circuits, vol. 42,

no. 5, pp. 1034–1043, 2007.

[27] K. Han, J. Gil, S. S. Song, J. Han, H. Shin, C. K. Kim, and K. Lee, “Complete high-

frequency thermal noise modeling of short-channel mosfets and design of 5.2 GHz low

noise amplifier,” IEEE Journal of Solid-State Circuits, vol. 40, no. 3, pp. 726–735, 2005.

[28] P. Kushwaha, N. Paydavosi, S. Khandelwal, C. Yadav, H. Agarwal, J.-P. Duarte, C. Hu,



[29] W. Jin, P. C. H. Chan, and J. Lau, “A physical thermal noise model for SOI MOSFET,”

IEEE Transactions on Electron Devices, vol. 47, no. 4, pp. 768–773, April 2000.

[30] A. O. Adan, M. Koyanagi, and M. Fukumi, “Physical model of noise mechanisms in SOI

and bulk-siliconMOSFETs for RF applications,” IEEE Transactions on Electron Devices,

vol. 55, no. 3, pp. 872–880, 2008.

BIBLIOGRAPHY 124

[31] Y. Cheng, M. Deen, and C.-H. Chen, “MOSFET modeling for RFIC design,” IEEE Trans-actions on Electron Devices, vol. 52, no. 7, pp. 1286–1303, 2005.

[32] S. Asgaran, M. J. Deen, and C.-H. Chen, “An analytical method to determine MOSFET’s

high frequency noise parameters from 50 ohm noise figure measurements,” in Proc. ofIEEE Radio Frequency Integrated Circuits RFIC Symposium, pp. 4–304, 2006.

Chapter 8

Conclusion

The aim of this thesis was to develop a compact model for FD-SOI MOSFETs for a wide range

of back-biases and frequencies. For a robust compact model, it is important to incorporate all

real device effects inherent in the device. The thesis described the physics and modeling of

five real device effects (flicker noise, substrate depletion, self-heating, high-frequency effects

and thermal noise). All the proposed models are developed within the framework of the BSIM-

IMG model, which is the latest industry standard surface potential based model for FD-SOI

MOSFET.

To improve the computational efficiency of the BSIM-IMG model, new approaches are pro-

posed in this thesis to calculate the surface potential and effective mobility. The flicker noise

behavior of independent double gate MOSFET is different from bulk MOSFET due to the pres-

ence of different interface qualities and bias conditions. Thus, flicker noise model derived for

bulk MOSFET (i.e., single Si-SiO2 interface) is not sufficient to predict correct flicker noise

behavior of FD-SOI MOSFET. Thus, a unified flicker noise model dedicated to FD-SOI MOS-

FETs is proposed in this thesis. Previously reported flicker noise models are valid only in the

linear region, while proposed model captures the correct flicker noise behavior from weak to

strong inversion region for a wide range of the front and back gate biases. The model is vali-

dated against noise measurement data from 1 Hz to 65 kHz.

Although FD-SOI MOSFET is famous due to its threshold voltage tuning facility via back-

biasing, yet it faces substrate depletion issue as some fraction of the applied back-bias drops in

the substrate region. This in turn changes the effective back-bias and causes shift in threshold

voltage. Thus, we have modeled the substrate depletion effect for different back-bias conditions

and the model validation is done against the state-of-the-art data. Also, the FD-SOI MOSFET

is more prone to self-heating as compared to bulk MOSFET. This device heating in FD-SOI

MOSFET further increases with the length scaling. From TCAD electro-thermal simulations,

it is observed that, the device heat flow paths change with length and width scaling. In this

125

126

thesis, a new behavioral model for thermal resistance is developed which captures the impact

of length/width scaling on device characteristics.

FD-SOI MOSFET with high resistivity substrate is gaining momentum in RF market due

to its high linearity substrate, electrical isolation and low insertion loss over a wide frequency

range. However, literature has a limited qualitative discussion on RF behavior of FD-SOI MOS-

FET. Thus, we have discussed various device characteristics which have frequency dependence

via several inherent phenomena like self-heating effect, substrate effect, and gate resistance ef-

fect. From these frequency dependent device characteristics, it is clear that solely DC compact

model is not sufficient to predict correct device behavior. This is the first time, when a complete

compact model for RF-FDSOI MOSFET is proposed. The step-by-step DC and RF parameter

extraction procedures are proposed and validated on the measured characteristics of 30 nm and

100 nm channel length transistors for a wide range of biases and frequencies.

FD-SOI MOSFET also suffers from substrate resistance-induced thermal noise as this sec-

ondary noise gets coupled with the channel noise at high frequencies. This noise coupling

increases with reduction in BOX thickness and results in higher NFmin. In this thesis, for the

first time we have reported the noise measurements in RF frequency range for ultra thin body

and thin BOX FD-SOI MOSFET. We observe that thermal noise increases with positive back

gate bias due to an increase in the number of channel carriers and their collisions. Also, noise

figure does not vary significantly with drain bias due to the dominance of the velocity saturation

phenomenon in the saturation region.

One future research direction is to enhance the BSIM-IMG model to support quantum me-

chanical confinement for all regions of operations. Including the physics of 2D materials and

the validation of BSIM-IMG model for different channel materials like MoS2 and graphene

can improve the model further for flexible and RF electronics, respectively. Enhancement of

the BSIM-IMG model to support the independent gate FinFET is also an interesting topic of

research as independent gate FinFET can be used for many applications like single transistor

mixer and dynamic feedback SRAM.

Appendix A

List of Publications

A.1 Journal Papers

• P. Kushwaha, H. Agarwal, C. Hu, and Y. S. Chauhan, “A Unified Flicker Noise Model

for FDSOI MOSFETs Including Back-bias Effect”, under revision in IEEE Transactions

on Electron Devices, Oct. 2016.

• Y. Sahu, P. Kushwaha, A. Dasgupta, C. Hu, and Y. S. Chauhan, “Compact Modeling of

Drain Current Thermal Noise in FDSOI MOSFETs Including Back-Bias Effect”, under

revision in IEEE Transactions on Microwave Theory and Techniques, Sept. 2016.

• P. Kushwaha, A. Dasgupta, Y. Sahu, S. Khandelwal, C. Hu, and Y. S. Chauhan, “Charac-

terization of RF Noise in UTBB FD-SOI MOSFET”, IEEE Journal of Electron Devices

Society (in press), Oct. 2016.

• P. Kushwaha, Bala Krishna K, H. Agarwal et.al, “Thermal Resistance Modeling in FD-

SOI Transistors with Industry Standard Model BSIM-IMG”, Microelectronics Journal,

Vol. 56, pp. 171 - 176, 2016.

• B. K. Kompala, P. Kushwaha, H. Agarwal, S. Khandelwal, J. P. Duarte, C. Hu and Y. S.

Chauhan., “Modeling of Nonlinear Thermal Resistance in FinFETs”, Japanese Journal

of Applied Physics, Vol. 55, pp. 04ED11, 2016.

• P. Kushwaha, S. Khandelwal, J. P. Duarte, C. Hu, Y. S. Chauhan, “RF Modeling of

FDSOI Transistors Using Industry Standard BSIM-IMG Model,” IEEE Transactions on

127

A.2 Conference Papers 128

Microwave Theory and Techniques, Vol. 64, Issue 6, pp. 1745-1751, June 2016.

• S. Khandelwal, H. Agarwal, P. Kushwaha, J. P. Duarte, A. Medury, Y. S. Chauhan, S.

Salahuddin, and C. Hu, “Unified Compact Model Covering Drift-Diffusion to Ballistic

Carrier Transport”, IEEE Electron Device Letters, Vol. 37, Issue 2, pp. 134-137, 2016.

• H. Agarwal, P. Kushwaha, C. Gupta, S. Khandelwal, C. Hu, and Y. S. Chauhan, “Anal-

ysis and Modeling of Flicker Noise in Lateral Asymmetric Channel MOSFETs”, Solid

State Electronics, Vol. 115, Part A, pp. 33 - 38, Jan. 2016.

• H. Agarwal, C. Gupta, P. Kushwaha, C. Yadav, J. P. Duarte, S. Khandelwal, C. Hu, and

Y. S. Chauhan, “Analytical Modeling and Experimental Validation of Threshold Voltage

in BSIM6 MOSFET Model”, IEEE Journal of Electron Devices Society, Vol. 3, Issue

3, pp. 240-243, 2015.

• P. Kushwaha, N. Paydavosi, S. Khandelwal, C. Yadav, H. Agarwal, J. P. Duarte, C. Hu,

Y. S. Chauhan, Modeling the Impact of Substrate Depletion in FDSOI MOSFETs in Solid

State Electronics, Vol. 104, Issue 2, pp. 6-11, 2015 .

• C. Yadav, P. Kushwaha, S. Khandelwal, J. P. Duarte, Y. S. Chauhan, and C. Hu, “Model-

ing of GaN based Normally-off FinFET”, IEEE Electron Device Letters, Vol. 35, Issue

6, June 2014.

A.2 Conference Papers

• C. K. Dabhi, P. Kushwaha, A. Dasgupta, H. Agarwal, and Y. S. Chauhan, “Impact of

Back Plane Doping on RF Performance of FD-SOI Transistor using Industry Standard

BSIM-IMG Model”, submitted in IEEE International Conference on Emerging Elec-

tronics (ICEE), Mumbai, India, Dec. 2016.

• H. Agarwal, P. Kushwaha, S. Khandelwal, J. P. Duarte, Y. K. Lin, H. L. Chang, H. Wu,

P. D. Ye, C. Hu, and Y. S. Chauhan, “Modeling of GeOI and Validation with Ge-CMOS

Inverter Circuit using BSIM-IMG Industry Standard Model”, IEEE International Con-

ference on Electron Devices and Solid-State Circuits (EDSSC), Hong Kong, Aug.


2016.

• P. Kushwaha, R. Agarwal, H. Agarwal, C. Gupta, S. Khandelwal, J. P. Duarte, Y. K. Lin,

H. L. Chang, C. Hu, and Y. S. Chauhan, “Modeling of Threshold Voltage for Operating

Point using Industry standard BSIM-IMG Model”, IEEE International Conference on

Electron Devices and Solid-State Circuits (EDSSC), Hong Kong, Aug. 2016.

• P. Kushwaha, H. Agarwal, Y. S. Chauhan, M. Bhoir and N. R. Mohapatra, S. Khandel-

wal, J. P. Duarte, Y.-Kai Lin, H.-Lin Chang and C. Hu, “Predictive Effective Mobility

Model for FDSOI Transistors using Technology Parameters”, IEEE International Con-

ference on Electron Devices and Solid-State Circuits (EDSSC), Hong Kong, Aug.

2016.

• J. P. Duarte, S. Khandelwal, P. Kushwaha, Y. S. Chauhan, and C. Hu, “Modeling Inde-

pendent Multi-Gate MOSFET”, Workshop on Compact Modeling (WCM), Washing-

ton D.C., USA, May 2016. (Invited)

• Y. Sahu, P. Kushwaha, J. P. Duarte, S. Khandelwal, C. Hu and Y. S. Chauhan, “Compact

Modelling of Drain Current Thermal Noise in FDSOI MOSFETs”, International Work-

shop on Physics of Semiconductor Devices (IWPSD), Bangalore, India, Dec. 2015.

• P. Kushwaha, S. Khandelwal, C. Hu and Y. S. Chauhan, “Recent Updates in Indus-

try Standard BSIM-IMG Model for FDSOI Transistors”, International Workshop on

Physics of Semiconductor Devices (IWPSD), Bangalore, India, Dec. 2015.

• J. P. Duarte, S. Khandelwal, A. Medury, C. Hu, P. Kushwaha, H. Agarwal, A. Dasgupta,

and Y. S. Chauhan “BSIM-CMG: Standard FinFET Compact Model for Advanced Circuit

Design”, IEEE European Solid-State Circuit Conference (ESSCIRC), Graz, Austria,

Sept. 2015

• P. Kushwaha, H. Agarwal, S. Khandelwal, J. P. Duarte, A. Medury, C. Hu and Y. S.

Chauhan, “BSIM-IMG: Compact Model for RF-SOI MOSFETs”, IEEE Device Re-

search Conference (DRC), Columbus, USA, June 2015.

• P. Kushwaha, C. Yadav,H. Agarwal, J. Srivatsava, S. Khandelwal, J. P. Duarte, S. Khan-


delwal, Y. S. Chauhan, C. Hu, “BSIM-IMG with Improved Surface Potential Calculation”

in IEEE Indicon, Pune, India, 2014.

• C. Yadav, P. Kushwaha, H. Agarwal, Y. S. Chauhan, “Threshold Voltage Modeling of

GaN Based Normally-Off Tri-gate Transistor” in IEEE Indicon, Pune, India, 2014.

• Y. S. Chauhan, P. Kushwaha, S. Khandelwal, C. Yadav, N. Paydavosi, J. P. Duarte, and C.

Hu, “BSIMIMG: Compact Model for UTBBSOI MOSFETs”, Workshop on Compact

Modeling (WCM), Washington D.C., USA, June 2014. (Invited)

• J. R. Sahoo, H. Agarwal, C. Yadav, P. Kushwaha, S. Khandewal, R. Gillon, Y. S. Chauhan,

“High Voltage LDMOSFET Modeling using BSIM6 as Intrinsic-MOS Model”, IEEE

PrimeAsia, Visakhapatnam, India, Dec. 2013.

• H. Agarwal, S. Venugopalan, M. Chalkiadaki, N. Paydavosi, J. P. Duarte, S. Agnihotri,

C. Yadav, P. Kushwaha, Y. S. Chauhan, C. C. Enz, A. Niknejad and C. Hu, “Recent

Enhancements in BSIM6 Bulk MOSFET Model”, IEEE International Conference on

Simulation of Semiconductor Processes and Devices (SISPAD), Glasgow, Scotland,

Sept. 2013.

• Y. S. Chauhan, S. Venugopalan, N. Paydavosi, P. Kushwaha, S. Jandhyala, J. P. Duarte,

S. Agnihotri, C. Yadav, H. Agarwal, A. Niknejad and C. Hu, “BSIM Compact MOS-

FET Models for SPICE Simulation”, IEEE International Conference Mixed Design of

Integrated Circuits and Systems (MIXDES), Gdynia, Poland, June 2013.

Modeling of Substrate Depletion, Self-heating, Noise and...

Documents

Transcript of Modeling of Substrate Depletion, Self-heating, Noise and...