Modeling and schedulability analysis of AFDX networks in ...sfischme/rate/JavierGutierrez...AFDX...

UNIVERSIDADDE CANTABRIA

Modeling and schedulability analysis of AFDX networks in MAST 2

J. Javier Gutiérrez ([email protected])

Computers and Real-Time Group, University of Cantabriawww.ctr.unican.es

Funded in part by Spanish Government and FEDER funds(TIN2011-28567-C03-02-HI-PARTES)

1st Workshop on Real-Time Ethernet (RATE)Vancouver (Canada), December 2013

GRUPO DE COMPUTADORES Y TIEMPO REAL By: J. Javier Gutiérrez 1UNIVERSIDAD DE CANTABRIA 3/Dec/13


Introduction to MAST
MAST (Modeling and Analysis Suite for Real-Time Applications)
• is a long-term project led by Michael González Harbour

• defines a model to describe the timing behavior of distributed real-time systems

• model supports different scheduling policies, and is used by different tools- schedulability analysis- sensitivity analysis- assignment of scheduling parameters- simulation

Available at http://mast.unican.es



Overview of the MAST model

Real-time situation view

Platform view

EventHandler

Step

TimingRequirement

Operation

MutualExclusion

SchedulableResource

Scheduler

SchedulingParameters

Event Event

Event

Reference

ProcessingResource

Operations view

Concurrent architecture view

Resources

StepEvent

End-to-end flow



Evolution to MAST 2
The MAST model is now aligned with the model defined in MARTE
• the standardized UML profile for real-time embedded systems

MAST 2 also includes new modeling elements

• network switches and routers- IEEE 802.1p switches with prioritized traffic- ARINC-664 standard (part 7): a hard real-time network known as

AFDX (Avionics Full-Duplex Switched Ethernet)

• network links: AFDX elements and communication channels

• timetable-driven scheduling- allows modeling partitioned systems based on ARINC-653

standard



Main characteristics of AFDX
Switched ethernet network
• based on the use of point to point full duplex ethernet links

• and special purpose switches

• UDP/IP protocol is used for transmission

The routing of messages is preconfigured

• there is no delay in the discovery of routing addresses

Traffic regulation at the sending end via Virtual Links (VL)

The switches have two FIFO queues at each output port

• high and low priority traffic

• the priority is configured on a VL basis



Virtual Links
Each VL has two parameters
• Lmax: the largest Ethernet frame in bytes

• BAG: the Bandwidth Allocation Gap (BAG)- a power of 2 in the range [1,128] ms- the BAG is the minimum interval between Ethernet frames

transmitted on the VL

Each virtual link has a FIFO queue for all the fragmented packets to be transmitted through it

A virtual link can be composed of up to 4 Sub-Virtual Links

• a dedicated FIFO queue per sub-VL

• a round robin algorithm working over IP fragmented packets



The AFDX architecture

END SYSTEM

VL1 Queue

VLn Queue

...VL Scheduler

Transmitting AFDX Section

High Priority Queue

Low Priority Queue

AFDX Switch Output PortAFDX Switch

END SYSTEM END SYSTEM

END SYSTEM

AFDX Switch

SWITCHED NETWORK

of an End System

Sub-VLm Queue

...Sub-VL1 QueueRR Sched.

VL Q.



Networks in MAST 2

Network

Packet_Based_Network

Transmission_KindMax_Packet_SizeMin_Packet_SizeMax_Blocking

Driver

0..* Driver_List

Processing_Resource

Clock_Synchronization_Object

0..1 Synchronization_SourceSpeed_Factor

Throughput

RTEP_Network

...



AFDX networks

Network

Packet_Based_NetworkDriver

0..* Driver_ListThroughput

AFDX_Link

Max_Packet_SizeMin_Packet_SizeMax_HW_Tx_LatencyMax_W_Rx_LatencyEhernet_OverheadProtocol_Oerhead

Also Min, Avg



AFDX Virtual Links

Scheduling_Parameters

...

AFDX_Virtual_Link

Lmax : Bit_CountBAG : Time

Schedulable_Resource

...

Communication_Channel

0..1



Network switches and routers

Network_Switch

Processing_Resource

Clock_Synchronization_Object

0..1 Synchronization_SourceSpeed_Factor

Max_Fixed_Fork_Latency

AFDX_Switch

...

Max_Variable_Fork_LatencyMax_Delivery_Latency

Also Min, Avg

Regular_Switch

...Network_Router

Max_Fixed_Branch_LatencyMax_Variable_Branch_Latency



A simple example

Sender Data Receiver

CPU1 CPU2AFDX Switch

Task TaskMessage

Data

Ethernet

Message

Data

Ethernet

Message

SenderData Receiver

CPU1 CPU2AFDX Network

Task TaskMessage



Modeling the AFDX network

Real-Time situation view

Platform view

Concurrent architecture view

Net_Sched2: Primary_Scheduler

Policy = AFDX_Policy

...

Net_Sched: Primary_Scheduler

Policy = AFDX_Policy

...

M2: Fixed_Priority_Params

Priority = 1

...

Switch: AFDX_Switch

Max_Delivery_Latency = 10e-6

...

Stream1: Communication_Channel

...


...

M1: AFDX_Virtual_Link

LMax = 1200

BAG = 4e-3

Link1: AFDX_Link

TThroughput = 1e8

...

Link2: AFDX_Link

TThroughput = 1e8

...Host Host


Step_Schedulable_Resource

Scheduler

Step_Schedulable_Resource

Sw itchScheduler




Modeling the AFDX network (cont’d)

Real-Time situation view

Operations view

M2: Fixed_Priority_Params

Priority = 1

...


...


...

M1: AFDX_Virtual_Link

LMax = 1200

BAG = 4e-3

Data: Message

Max_Message_Size = 1600

...

MD: Message_Delivery

...

E22: Internal_Event

...

E23: Internal_Event

...

E2: Internal_Event

...

E3: Internal_Event

...

S2: Step

...

S1: Step

...

Output_Event

Step_Operation

Input_Event


Output_Event

Step_Schedulable_ResourceStep_Schedulable_Resource

Step_Operation

Input_Event

Input_Event

Output_Event




MAST for schedulability analysis
The MAST model is transformed into internal models for schedulability analysis or simulation based on the end-to-end flow
• processors and networks are treated in a similar way

i1

ei i2 i3

di2Di2

Di3=Di

CPU-1 CPU-2Network

i2

Ji3



Schedulability analysis for heterogeneous systems
A holistic analysis can be applied by dealing with each step separately
• fixed priorities or EDF (either with local or global clocks) can be mixed in the same distributed system

ij

Pij SDij | Sdij

Rbij

Rijij

Jij

Activation conditions

Scheduling parameters

Response times



Holistic schedulability analysis technique for AFDX
Can be integrated in the analysis for heterogeneous systems
• calculates the worst-case and the best-case latencies, and thus the output jitter

• manages multipacket messages and input jitter

• useful for multicast messages and multiple switches with any number of priority levels (2 for AFDX switches)

• includes the analysis of VLs and sub-VLs

Recently published online in the Real-Time Systems Journal

Compatible with a new analysis technique for ARINC-653 systems (to be published soon)



Validation of the technique
The analysis technique is an adaptation of the holistic analysis initially developed by Tindell and Clark
• it is well known that this analysis is pessimistic

Obtains results

• similar to other techniques, e.g., Network Calculus

• less accurate than the Trajectory approach

• but these techniques consider the network in isolation and work over a more simplified model

It is scalable and can be applied to real systems

• exact calculation of latencies (e.g., model-checking) is intractable except for small systems



Results for a real size example
Architecture:
• 16 switches

• 1000 VLs crossing up to 6 switches

0

10

20

30

40

50

60

70

80

90

14 19 24 28 33 38 42 47

Executiontim

e(s)

Average output ports utilization (%)

Avg. Exec. Time

Max. Exec. Time



Current state and future of MAST 2
The model has been defined and formulated in Ecore (Eclipse/EMF) as part of a model-driven strategy to enable
• model transformations for analysis or simulation

We have developed the analysis techniques for ARINC-like partitioned systems with AFDX networks

We also have a lot of work to do to implement all of this

• strong changes are needed in the current implementation to continue to guarantee compatibility

We want to explore new analysis techniques to reduce the pessimism

• applying offsets or adapting the Trajectory approach



Questions?

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Modeling and schedulability analysis of AFDX networks in ...sfischme/rate/JavierGutierrez...AFDX...

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