Modeling and Character is at Ion of an Organic Thin Film Transistor for a Circuit Design

8/6/2019 Modeling and Character is at Ion of an Organic Thin Film Transistor for a Circuit Design

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Modeling and characterization of organic thin film transistorsfor circuit design

M. Fadlallah,a W. Benzarti, and G. BilliotCEA-LETI, 17 rue des Martyrs, 38054 Grenoble, France

W. EcclestonDepartment of Electrical Engineering, University of Liverpool, Liverpool L69 3GJ, United Kingdom

D. BarclayPlastic Logic Limited, 34 Cambridge Science Park, Milton Road, Cambridge CB4 OFX, United Kingdom

Received 15 September 2005; accepted 16 March 2006; published online 25 May 2006

In this paper, we develop a device model of an organic thin film transistor for a circuit design, more

specifically, for organic radio frequency identification applications. This model is based on variable

range hopping theory, i.e., a carrier may either hop over a small distance with a high activation

energy or hop over a long distance with a low activation energy. The model takes into account all

the operating regimes in direct current and transient mode; the transistor symmetry is also

considered. The model has been developed using a physical basis where the model parameters can

easily be extracted and it improves convergence in circuit simulations. It is also suitable for

computer aided design applications. 2006 American Institute of Physics.

DOI: 10.1063/1.2197260

I. INTRODUCTION

Organic thin film transistors OTFTs are currently gen-erating a growing interest due to the low-temperature process

and low-cost production. Therefore, their potential for a wide

application, low-cost integrated circuits and large area flex-

ible electronics is increasing.1

Their possible applications are

rf identification tags, electronic paper, flexible displays, sen-

sors, etc. Furthermore, thanks to their intrinsic structure flex-

ibility, in the case of all-polymer systems, OTFTs allow the

production of flexible integrated circuits.2

Many techniques have been used in the fabrication of

organic and polymer microelectronic devices, such as lithog-

raphy spin coating, thermal evaporation, and printing. Vari-

ous printing techniques including screen printing,3,4

micro-

contact printing,5,6

and ink-jet printing7,8 IJP are of great

interest. Among these printing techniques, the IJP has been

gaining more attention because polymer devices fabricated

by the IJP technique have the advantage of simple fabrication

methods, compatibility with different substrates, low-

temperature processing, and low cost. OTFTs used in this

study were fabricated using ink-jet printing techniques.

The efficient design of complex integrated circuits based

on OTFTs requires preliminary characterization and model-

ing. To this purpose, the availability of accurate analyticalmodels simulation program for integrated circuits emphasisSPICE-like is particularly attractive. With respect tocrystalline-silicon metal-oxide-semiconductor field-effect

transistors MOSFETs, the development of an analyticalmodel for OTFTs is complicated by the peculiar nature of the

material. In addition, OTFTs are primarily operated as accu-

mulation field-effect transistors; they normally conduct at

zero gate voltage and field-effect mobility is dependent on

gate voltage.9

In recent years several mathematical models of

the OTFTs were developed.1013

They are mainly based on

classical MOS transistors models, slightly modified by intro-

ducing fitting empirical parameters. In this paper, we present

a direct current/alternating current dc/ac model for OTFTswhere the charge transport mechanism is based on the vari-

able range hopping VRH theory.14,15

The developed model should be accurate enough in de-

vice simulations but also should present a high level of con-

vergence in circuit simulations. In fact, the model has to take

into account the physical bases of the device structure and

the material specifications. At the same time, the developedmodel should be easy to upgrade since the technology is not

yet mature and different parameters such as materials and

structure can be changed. It is therefore important to adopt a

physical approach in order to facilitate the upgrade of the

model. Using physical treatment including surface potential

variables introduces implicit equations into the model. This

technique will hardly degrade model convergence in circuit

simulations. In order to avoid such divergence, the model

should be developed using explicit equations. At this stage, it

is important to note that using explicit equations in a SPICE-

like approach will imply the use of if conditions which cause

discontinuities of equation derivatives. This situation may

influence the convergence of the model in circuit simula-

tions.

It is important to find the right compromise between a

physical approach and model convergence in circuit design.

A bottom-up approach going from a simple model using a

SPICE-like approach to many more modifications, other

equations, and parameters was adopted. The model perfor-

mance will be evaluated using the validation of the model

simulations towards device measurements and its conver-

gence in circuit design.aFAX: 33 0 4 38 78 51 57; electronic mail: [email protected]

JOURNAL OF APPLIED PHYSICS 99, 104504 2006

0021-8979/2006/9910 /104504/7/$23.00 2006 American Institute of Physics99, 104504-1

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II. MODEL STRUCTURE

The work done here is based on the cross section and the

layout of the OTFT. The model equations were also based on

the dc and ac characteristics of the device.

The layout and the cross section of the OTFT used are

shown in Fig. 1. As seen, the transistor structure uses a mul-

tifinger type, where x represents the direction parallel to the

current flow.

The basic topology of the transistor is top gate-bottom

contacts where the transistor length is located between the

source and the drain contacts. The transistor model repre-

senting this cross section is shown in Fig. 2.

Rs and Rd are, respectively, the source and the drain con-

tact resistances; Cgs and Cgd are, respectively, the gate to

source and the gate to drain capacitors; and Id is the drain

current expressing the carriers flowing between source and

drain for the different operating regimes of the transistor.

III. DC MODEL IN THE DIFFERENT OPERATING

REGIMESA. Linear regime

Unlike complementary metal-oxide-semiconductor

CMOS standard technology, OTFT is only a drift mecha-nism where the subthreshold regime and linear regime are

driven with a unique mechanism and then can be modeled

using a single equation. The equation obtained depends on

the universal mobility law UML.16 In the variable rangehopping VRH model,15,16 the conductivity and thus the mo-bility of the charge carriers increase with doping as given by

the empirical Eqs. 1 and 2,

= K1N 1

and

= K3N1 , 2

where K1, K3, and are constants and N is the carrier num-

ber.

In order to further analyze the TFT result, the general

equation incorporates dependence of the mobility on accep-

tor concentrations, such as that of VRH, rather than bandlike

mechanism. Assuming that every carrier in the bulk repre-

sents a hole in the channel, the effective mobility eff maythus be expressed as Eq. 3 assuming m = 1,

eff= K3p1 = K3p

m, 3

where p =N. The drain current density J resulting from elec-

trical field application is expressed with Eq. 4,

J= pqeffx, 4

Where p is the carrier concentration, q is the electron charge,

and x is the applied field between the source and drain con-

tact.

Using Gausss law and substituting for J=IWdz and

x = dVx/dx and integrating both sides, the current equationthen becomes

I0

L

dx = K3W

2m + 1

C02m+1

20pkTm

0

VD

VG Vx2m+1dVx,

5

where C0 is the dielectric capacitor C0 =d/Td, d is the di-

electric permittivity, Td is the thickness of the dielectric, W is

the channel width, p is the permittivity of the organic semi-

conductor, 0 is the permittivity of free space, VG is the gate

voltage, and m is a mobility model parameter. Therefore, the

general equation for the drain to source current in the linearregime is expressed with Eq. 6,

Id,lin = K3

2m + 12m + 2

W

L

C02m+1

20pkTm

Vgs VT2m+2

Vgs VT Vd2m+2, 6

where VT is the threshold voltage, Vgs is the gate to source

voltage Vgs = VG Vs, Vs is the source voltage, Vd is the drain

voltage, and k and T are, respectively, Boltzmanns constant

and the temperature.

Equation 6 of the current does not seem to have adirect dependence on the carrier concentration p. Neverthe-

less, when m = 0 i.e., the device is unsaturated, Eq. 6 issimilar to the standard conventional MOSFET equation with

K3 = and thus

Id= K3W

LC0Vgs VTVd Vd

2

2 . 7

B. Saturation regime

Based on the previous calculation, the current equation

in the saturation regime Vgs VTVds is given by

FIG. 1. Layout and cross section of the organic thin film transistor OTFT.

FIG. 2. Basic model of the OTFT.

104504-2 Fadlallah et al. J. Appl. Phys. 99, 104504 2006



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Id,sat = K32m + 12m + 2W

L

C02m+1

20pkTm

Vgs VT2m+2

1 + Vd Vgs + VT , 8

where is the conductance parameter and Vds is the drain to

source voltage.

IV. TRANSIENT MODEL

Some of the important low frequency circuit parameters

can also be obtained from the drain current Eq. 6. For ex-ample, to calculate the drain and source capacitances, the

expression C= dQ/dV can be used.15,17,18 Assuming thatthe polymer TFT is an accumulation mode transistor and all

of the current is due to drift and not diffusion, then the

threshold voltage is defined as the gate voltage that results in

an accumulation channel, i.e., the flat band voltage VFB is the

threshold voltage of the device. The total charge on the gate

electrode Qg at any gate and drain voltages may be obtained

from

Qg = W0

L

C0VGT Vxdx , 9

where VGT = Vg VT, VT= VFB and C0 is the dielectric ca-pacitance per unit area. In the last step of the calculation in

6, this integral can be evaluated explicitly using the draincurrent equation 5 to relate dx to dVx and the result is givenin 10,

Qg =C0WL2m + 2VGT Vd

2m+3 VGT Vs2m+3

2m + 3VGT Vd2m+2 VGT Vs

2m+2,

10

Where L is the channel length.

The gate to source capacitance is thus

Cgs = Qg

VgsVd = C02m + 2Vgst2m+1WL

2m + 3 2m + 2Vgdt2m+3 2m + 3Vgdt2m+2Vgst + Vgst2m+3

Vgdt2m+2 Vgst

2m+22 , 11where Vgdt= VGT Vd and Vgst= VGT Vs.

Similarly, the short circuit gate to drain capacitance is

Cgd = QgVgd

Vgs = C02m + 2Vgdt2m+1WL2m + 3 2m + 2Vgst2m+3 2m + 3Vgst

2m+2Vgdt + Vgdt

2m+3

Vgdt2m+2 Vgst

2m+22 . 12

These equations depend on the operating regime. It is

also seen from the transistor layout and cross section that theoverlapping capacitors are important in this case since the

gate electrode covers the entire source and drain fingers.

Just like drain current equations, the capacitor model

obeys the off, linear, and saturation regimes.18

In that sense,

Cgs and Cgd depend on the polarizations applied to the struc-

ture added to the overlapping capacitance Eq. 13,

Cgs = CgsovW+ Cgsoff,linear,saturation,

Cgd = CgdovW+ Cgdoff,linear,saturation, 13

where Cgsov and Cgdov are the overlapping capacitance of

source and drain, respectively.

V. MODEL PARAMETER EXTRACTION

Before starting the development of the OTFT model, full

studies in terms of electrical and technological characteriza-

tion are required.

Two primary sets of measurements are required for the

characterization of the organic transistor: the transfer charac-

teristics Id vs Vgs that allow the effective mobility andthreshold voltage VT to be determined and the output char-acteristics Id vs Vds that provide saturation and general elec-trical performance information.

Electrical characterization is started using I-V and C-V

characteristics with transistors having W=10 mm and differ-ent channel lengths.

The developed model contains only 12 parameters

Table I. Most of these parameters are physical dependingon the device structure and layout.

A. Extraction of the drain current factor in the offregime I00

As we have seen in Fig. 3, the current in off regime, i.e.,

Vgst0, is nearly independent of gate potential. At the same

TABLE I. Parameters list and signification.

Lchannel Length of the channel

Wfinger Width of the channel formed of one finger

Nbfinger Number of fingers or channel interdigitatedsource-drain technology

TOX Gate insulator thickness

VT Device threshold voltage

m Mobility parameter

K3 Mobility parameter

I00 Off regime drain current factor

RWS Source contact resistance

RWD Drain contact resistance

CT Capacitor factor

Conductance parameter




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time it is clear that this current is also independent of the

drain to source voltage. The model of the current in off re-

gime is given by Ioff=I00W, where I00 is the off current pa-

rameter depending on the current density in this regime

while W is the width of the transistor.

B. Extraction of the threshold voltage

The value of the threshold voltage VT is extracted us-ing an extrapolation method which determines where the cur-

rent starts to increase with respect to the gate voltage. The

latter is measured at low Vds to ensure that the leakage cur-

rent does not affect the value of the threshold voltage.

To extract the value of VT, the slope of the curve Idagainst Vgs starting from the point corresponding to the

maximum value of the transconductance gm

= dId

/dVgs

isplotted Figs. 4a and 4b, while the intercept yields thevalue for VT.

C. Extraction of the mobility parameters

The parameters K3 and m are obtained using the equa-

tion of drain current in saturation and plotting

logdId,sat/dVgst against logVgst Fig. 5. The equationobtained 14 is in the form of Y= aX+ b; the value of m canbe obtained from the gradient of the graph while the inter-

cept yields the value for K3,

logdId,sat

dVgst= log K3C02m+1W

20polykTmL2m + 1

+ 2m + 1logVgst. 14

D. Extraction of the series resistance of source anddrain RS and RD

Using the Id against Vds curve for different Vgs, one can

calculate the value of the resistance in the Ohmic regime byusing the Ohmic law equation R = U/I for several gate volt-

ages Vgs and different channel lengths L. After that, R isplotted against L for a high Vgs Fig. 6 ensuring that theOTFT is in the accumulation regime. The value of contact

resistance can be obtained from the gradient of the curve

while the intercept yields the value for channel resistance,

Rcontact = RS + RD, RS = RD = Rcontact/2.

FIG. 3. Drain current Id against gate voltage Vgs for different drain voltages

Vds.

FIG. 4. Drain current and the slope corresponding to the maximum of gmplotted against the gate voltage for two channel lengths, L =20 m and

L =10 m.

FIG. 5. Typical curve LogdId/dVgs plotted against logVgs for theId-Vgs characteristics.

FIG. 6. Resistance plotted against the channel length for gate voltage

Vgs =40 V.




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E. Extraction of the conductance parameter

The extraction of the value of the conductance parameter

is obtained using the output conductance gd= dId/dVds

as follows Fig. 7: gd= dId/dVds =Id,sat, where Id,sat isequal to the value of the drain current when Vds = Vgs VT and

gd is the slope of the curve Id against Vds in saturation mode,obtained by linear regression.

F. Extraction of the value of the dielectric permittivityand overlapping capacitance

The dielectric constant of the gate dielectric is extracted

from capacitance measurements on a metal-insulator-metal

MIM structure at 30.41011 F/m. The real values of Wand L are extracted via a calibrated microscope.

Concerning the extraction of the overlapping capaci-

tances Cgsov and Cgdov source and drain, respectively, the

total overlapping surfaces of the devices are calculated, arethen multiplied by the dielectric capacitance, and are finally

divided by 2.

VI. MODEL VALIDATION

The model validation is performed using the measure-

ment data. An operation is done in dc regime for different

polarizations and transistor sizes. Nonetheless, these results

are obtained with a model using simplified equations in

order to enhance circuit simulator convergence in circuit

simulations. Figures 8a and 8b show the measurement

and simulation in dc regime of two transistor sizesW/L =10 mm/20 m and W/L =10 mm/10 m. It showsthe validity of the model with different channel lengths and

different regimes in p-type OTFT.

FIG. 7. Linear regression of the drain current Id against the drain voltageVds in saturation mode for different gate voltages Vgs.

FIG. 8. Measurement and simulation characteristics of transistors in different dc operation regimes with two transistors sizes: a OTFT withW/L =10 mm/20 m and b OTFT with W/L =10 mm/10 m. Solid lines are measurements, while crossed lines represent simulation characteristics.




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Even using a simple model with 12 parameters, we can

see a fair agreement in the drain current values between mea-

surements and simulations and that the model is valuable fordifferent transistor lengths. The developed model takes into

account the transistor symmetry when Vds changes from

negative to positive.

Another validation operation is done in the transient

regime. This validation is important for the simulation of

circuits in this regime. Thus, Fig. 9 shows the measurement

and the simulation of the gate-to-channel capacitance for

Vds = 0 V. Knowing that the circuit operation frequency is

low, the validation is made at a measurement frequency of

500 Hz.

VII. MODEL TEST IN CIRCUIT DESIGN

The model is validated for device operations in static

and transient regimes. Nonetheless, it is important to test the

convergence of the model in circuit design. Two steps are

chosen: simulation of an inverter and simulation of a ringoscillator.

A. Simulation of an inverter

The simulation of an inverter Fig. 10 using a drain-gateshortcut of the load transistor is done. The transistor sizes are

T1: W/L =600 m/10 m and the load transistor T2:

W/L =300 m/10 m. The inverter is simulated using a

Vdd =40 V, Vss =0 V, and an input pulse ranging between 0

and 40 V with a rise time and fall time of Tr= Tf=100 ms.

The pulse duration is Tw

=300 ms and the total period is

P =800 ms.

The simulations are shown on Figs. 11a and 11b.While Fig. 11a shows the input and output voltages fordifferent cycles of inversion, Fig. 11b shows the inverterlinearity.

FIG. 9. Measurement and simulation of gate-to-channel capacitance Cgc for

low frequency f=500 Hz against gate voltage Vgs for drain voltageVds =0 V and transistor size W/L =10 mm/20 m.

FIG. 10. Topology of the p-type OTFT inverter.

FIG. 11. a Simulation of a p-type OTFT inverter and b transfer charac-teristic of a p-type OTFT inverter.

FIG. 12. Topology of the simulated ring oscillator.




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B. Simulation of a ring oscillator

This step of validation was the simulation of a ring os-

cillator. Figure 12 shows the topology of the circuit made of

12 inverters, a resistor and a capacitor acting as loads. The

inverters have the same topology as that simulated previ-

ously Fig. 10 with the same transistor sizes and appliedpolarizations.

The simulation results are shown in Fig. 13. Using a

500 MHz processor workstation for a total duration of

1 / 10 s of oscillation, the simulation done on Eldo lasted

19 s. The simulation is done using 26 components 24 tran-sistors using a Verilog-A model and a resistor and a capacitor

using SPICE models. The characteristics of the ringoscillator obtained are the following: Voh =4.06 V,

Vol= 27.81 V, rise time= 1.80 ms, and fall time= 4.79 ms.

The ring oscillator frequency is f=70 Hz.

VIII. CONCLUSION

The model developed for circuit design is based on a

SPICE-like approach. The development methodology is

based on a bottom-up approach making it possible to start

with simple model equations to evaluate the results obtained

and to improve this model depending on the results obtained.

Today, the developed model is valid for device simulations.

Fair agreement between simulation and measurement char-

acteristics is obtained for different transistor lengths, dc op-

erating regimes linear, saturation, and off, and in the tran-sient regime capacitor behavior. The transistor symmetryVds negative and positive and Vgs negative and positive isalso taken into account in the model. The test in circuit de-

sign is also done. Simulations of inverters and ring oscilla-

tors show good characteristics and present very acceptable

simulation timing showing the good behavior of the simula-

tor convergence during circuit simulation.

ACKNOWLEDGMENTS

We would like to thank B. Eccleston from the University

of Liverpool for endless help with modeling activities. Fur-

thermore, we thank D. Barclay from Plastic Logic Limited

for providing OTFTs measurement as well as for valuable

discussions. This work has been supported by the European

PolyApply project funded under the 6th EU-Framework Pro-

gramme No. 507143.

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FIG. 13. Simulations of an OTFT ring oscillator.


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Modeling and Character is at Ion of an Organic Thin Film Transistor for a Circuit Design

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