Model of hot-carrier degradation for lateral IGBT device on SOI substrate
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Model of hot-carrier degradation for lateral IGBT device on SOI substrate Siyang Liu, Weifeng Sun, Chunwei Zhang, Tingting Huang and Qinsong Qian A novel model for hot-carrier degradation in a lateral insulated gate bipolar transistor (IGBT) device on SOI substrate (SOI-LIGBT) is pre- sented. The setup of the model is based on the existing hot-carrier degradation mechanism in a SOI-LIGBT and assisted by a lateral DMOS device on SOI substrate (SOI-LDMOS) with completely the same structure except for the doping type in the drain area. The model parameters have been extracted by the degradation measurement results and the validity of the proposed model in a SOI-LIGBT has been also verified. Introduction: The lateral insulated gate bipolar transistor (LIGBT) is a hybrid device that combines the advantages of a MOSFET (high switch- ing speed and low power drive requirement) and a bipolar junction tran- sistor (BJT) (low conduction losses), thereby the LIGBT has been added to the family of power devices. Silicon-on-insulator (SOI) substrate can offer true dielectric isolation, which eases the integration of power devices and low voltage logic devices in power ICs. Consequently, SOI-LIGBT devices have been widely used as the power switches in the monolithic integration area, especially in the plasma display panel driver ICs and the switch-mode power supply ICs [1, 2]. However, SOI-LIGBTs usually work under high temperature, high voltage and heavy current conditions, so as to suffer seriously from the hot-carrier degradation. Our previous investigations have been reported to analyse the inner degradation mechanism of the SOI-LIGBT under different stress conditions, while the model for describing the degra- dation behaviour of the device is less documented [3, 4]. In this Letter, a novel hot-carrier degradation model of a SOI-LIGBT device is proposed based on the foregoing mechanism. Moreover, the lateral DMOS on SOI substrate (SOI-LDMOS), with completely the same structure except for the doping type in the drain area, has been also fabricated and measured to assist the setup of the hot-carrier degra- dation model of the SOI-LIGBT. Device structures: The schematic cross-sections of the modelling SOI-LIGBT and the assistant SOI-LDMOS in this Letter are shown in Figs 1a and b, respectively. The fabrication of the devices is implemented in a 0.5 μm CMOS process using SOI technology. The structure parameters are given as follows: the poly-gate length is 6 μm, the effective channel length (L ch ) is 3 μm, the length of the accumulation region (L ac ) is 1 μm, the N-drift region length (L dr ) is 14 μm, the buried oxide thickness is 1.5 μm, and the thickness of the silicon film above the buried oxide is 6.5 μm. For both devices, the threshold voltage and the off-state breakdown voltage are 1 V and 238 V, respectively. a anode gate gate cathode sub drain source sub N-buffer N-buffer N-drift L dr L ac L ch N+ P+ N-drift L dr L ac L ch HV-pwell HV-pwell box P-sub box P-sub P+ P+ N+ N+ b Fig. 1 Schematic cross-sections of modelling and assistant devices a SOI-IGBT b SOI-LDMOS Analysis and modelling: On-resistance (R on ) is very important for the SOI-LIGBT device, which will be selected as the target parameter of the hot-carrier degradation model. The R on degradation model of the LDMOS device has been proposed and verified in [5, 6]. The model is available for the SOI-LDMOS here due to the very thick SOI layer (6.5 μm). However, for the SOI-LIGBT, the substrate current (I sub ) from the impact ionisation will be submerged into the normal hole current component of the device, which is also collected by the sub- strate. As a result, the existing degradation model cannot be directly used in the SOI-LIGBT. Luckily, according to our previous investi- gations, compared with the SOI-LDMOS with completely the same structure except for the doping type in the drain area, the difference of hot-carrier degradation in the SOI-LIGBT is only focused on the enhanced influence from the hole current component, but no essential degradation mechanism difference appears. Consequently, the novel hot-carrier degradation model of the SOI-LIGBT can be given as follows: DR on = C 1 (t × h 1 × j dit ) n 1 + C 2 (t × h 1 × j dit ) n - C 3 (t × h 2 × j hhi ) m 1 + C 4 (t × h 2 × j hhi ) m (1) where C 1 and C 3 denote the magnitude of the effect of the interface state (D it ) formation and hot hole injection upon the R on degradation, respect- ively. C 2 and C 4 describe the saturation effect of both the D it formation and hot hole injection. The time dependency of the degradation is given by n and m for D it formation and hot hole injection. It is emphasised that η 1 and η 2 indicate the degradation enhancement effect from the hole current component for D it formation and hot hole injection, respectively. In addition, the minus sign in front of the second term in (1) reflects the decrease in R on from the hot hole injection. 0 2 4 degradation of R on , % stress time, s V ac = 160V V ac = 165V V ac = 170V V ac = 175V V ac = 180V V gc = 5V a b 10 100 1000 10 100 1000 0 1 2 degradation of R on , % stress time, s V gc = 1.5V V gc = 2V V gc = 2.5V V gc = 3V V gc = 5V V ac = 165V Fig. 2 Degradation of R on under different stress conditions a Various V ac with V gc =5V b Various V gc with V ac = 165 V The degradation accelerating factors ξ dit and ξ hhi , reflecting the speed of D it formation and hole injection of SOI-LDMOS with the same struc- ture except for the drain doping type, are given by j dit = I ds W I sub I ds w it,e w ii (2) j hhi = I ds W I sub I ds w it,h l e w ii l h + 1 (3) It is noted that the I ds and I sub in the above equations denote the drain and substrate current of the SOI-LDMOS, respectively. w ii is the minimum energy that a hot electron must possess in order to create the impact ionisation (1.3 eV). w it,c and w it,lt are the critical energies that electrons and holes, respectively, must have for generating damage at the interface. λ e and λ h are the corresponding mean free paths in silicon. Extracting parameters and discussion: To extract the parameters of the hot-carrier degradation model in the SOI-LIGBT, a series of degradation measurements were performed with different V gc and V ac at room temp- erature, which can be seen in Figs 2a and b. For each stress, three devices were measured to verify the reproducibility of the results. The V ac -dependency of R on -degradation is shown in Fig. 2a, where V gc is kept constant at V gc = 5 V. The hot-carrier degradation level increases for the increasing V ac , moreover, it is obvious that R on decreases for low stress time (less than 1000 s) and increases after some stress time, therefore the inflexion of R on degradation can be dis- covered. The R on degradation at V ac = const = 165 V and different V gc is depicted in Fig. 2b. The R on degradation will be much more serious for increasing V gc . The degradation changes the sign, negative for shorter stress time but positive for longer stress time. In addition, the corre- sponding stress time to the inflexion is longer for lower V gc , especially for V gc = 1.5 V, the increase of R on degradation cannot even be observed. ELECTRONICS LETTERS 28th March 2013 Vol. 49 No. 7
Transcript of Model of hot-carrier degradation for lateral IGBT device on SOI substrate
Model of hot-carrier degradation for lateralIGBT device on SOI substrate
Siyang Liu, Weifeng Sun, Chunwei Zhang, Tingting Huangand Qinsong Qian
A novel model for hot-carrier degradation in a lateral insulated gatebipolar transistor (IGBT) device on SOI substrate (SOI-LIGBT) is pre-sented. The setup of the model is based on the existing hot-carrierdegradation mechanism in a SOI-LIGBT and assisted by a lateralDMOS device on SOI substrate (SOI-LDMOS) with completely thesame structure except for the doping type in the drain area. Themodel parameters have been extracted by the degradation measurementresults and the validity of the proposed model in a SOI-LIGBT hasbeen also verified.
Introduction: The lateral insulated gate bipolar transistor (LIGBT) is ahybrid device that combines the advantages of a MOSFET (high switch-ing speed and low power drive requirement) and a bipolar junction tran-sistor (BJT) (low conduction losses), thereby the LIGBT has been addedto the family of power devices. Silicon-on-insulator (SOI) substrate canoffer true dielectric isolation, which eases the integration of powerdevices and low voltage logic devices in power ICs. Consequently,SOI-LIGBT devices have been widely used as the power switches inthe monolithic integration area, especially in the plasma display paneldriver ICs and the switch-mode power supply ICs [1, 2].
However, SOI-LIGBTs usually work under high temperature, highvoltage and heavy current conditions, so as to suffer seriously from thehot-carrier degradation. Our previous investigations have been reportedto analyse the inner degradation mechanism of the SOI-LIGBT underdifferent stress conditions, while the model for describing the degra-dation behaviour of the device is less documented [3, 4].
In this Letter, a novel hot-carrier degradation model of a SOI-LIGBTdevice is proposed based on the foregoing mechanism. Moreover, thelateral DMOS on SOI substrate (SOI-LDMOS), with completely thesame structure except for the doping type in the drain area, has beenalso fabricated and measured to assist the setup of the hot-carrier degra-dation model of the SOI-LIGBT.
Device structures: The schematic cross-sections of the modellingSOI-LIGBT and the assistant SOI-LDMOS in this Letter are shown inFigs 1a and b, respectively. The fabrication of the devices isimplemented in a 0.5 µm CMOS process using SOI technology. Thestructure parameters are given as follows: the poly-gate length is 6 µm,the effective channel length (Lch) is 3 µm, the length of the accumulationregion (Lac) is 1 µm, the N-drift region length (Ldr) is 14 µm, the buriedoxide thickness is 1.5 µm, and the thickness of the silicon film above theburied oxide is 6.5 µm. For both devices, the threshold voltage and theoff-state breakdown voltage are 1 V and 238 V, respectively.
a
anode
gate gate
cathode sub drain source sub
N-buffer N-bufferN-drift
Ldr Lac LchN+ P+
N-drift
Ldr Lac Lch
HV-pwell HV-pwell
box
P-sub
box
P-sub
P+ P+N+ N+
b
Fig. 1 Schematic cross-sections of modelling and assistant devices
a SOI-IGBTb SOI-LDMOS
Analysis and modelling: On-resistance (Ron) is very important for theSOI-LIGBT device, which will be selected as the target parameter ofthe hot-carrier degradation model. The Ron degradation model of theLDMOS device has been proposed and verified in [5, 6]. The modelis available for the SOI-LDMOS here due to the very thick SOI layer(6.5 µm). However, for the SOI-LIGBT, the substrate current (Isub)from the impact ionisation will be submerged into the normal holecurrent component of the device, which is also collected by the sub-strate. As a result, the existing degradation model cannot be directlyused in the SOI-LIGBT. Luckily, according to our previous investi-gations, compared with the SOI-LDMOS with completely the same
ELECTRONICS LETTERS 28th March 2013 Vol. 49
structure except for the doping type in the drain area, the difference ofhot-carrier degradation in the SOI-LIGBT is only focused on theenhanced influence from the hole current component, but no essentialdegradation mechanism difference appears. Consequently, the novelhot-carrier degradation model of the SOI-LIGBT can be given asfollows:
DRon = C1(t × h1 × jdit)n1+ C2(t × h1 × jdit)n
− C3(t × h2 × jhhi)m1+ C4(t × h2 × jhhi)m
(1)
where C1 and C3 denote the magnitude of the effect of the interface state(Dit) formation and hot hole injection upon the Ron degradation, respect-ively. C2 and C4 describe the saturation effect of both the Dit formationand hot hole injection. The time dependency of the degradation is givenby n and m for Dit formation and hot hole injection. It is emphasised thatη1 and η2 indicate the degradation enhancement effect from the holecurrent component for Dit formation and hot hole injection, respectively.In addition, the minus sign in front of the second term in (1) reflects thedecrease in Ron from the hot hole injection.
0
2
4
degr
adat
ion
of R
on, %
stress time, s
Vac = 160V
Vac = 165V
Vac = 170V
Vac = 175V
Vac = 180V
Vgc = 5V
a b
10 100 1000 10 100 1000
0
1
2
degr
adat
ion
of R
on, %
stress time, s
Vgc = 1.5V
Vgc = 2V
Vgc = 2.5V
Vgc = 3V
Vgc = 5V
Vac = 165V
Fig. 2 Degradation of Ron under different stress conditions
a Various Vac with Vgc = 5 Vb Various Vgc with Vac = 165 V
The degradation accelerating factors ξdit and ξhhi, reflecting the speedof Dit formation and hole injection of SOI-LDMOS with the same struc-ture except for the drain doping type, are given by
jdit =IdsW
IsubIds
( )wit,e
wii (2)
jhhi =IdsW
IsubIds
( )wit,hlewiilh
+ 1(3)
It is noted that the Ids and Isub in the above equations denote the drainand substrate current of the SOI-LDMOS, respectively. wii is theminimum energy that a hot electron must possess in order to createthe impact ionisation (1.3 eV). wit,c and wit,lt are the critical energiesthat electrons and holes, respectively, must have for generatingdamage at the interface. λe and λh are the corresponding mean freepaths in silicon.
Extracting parameters and discussion: To extract the parameters of thehot-carrier degradation model in the SOI-LIGBT, a series of degradationmeasurements were performed with different Vgc and Vac at room temp-erature, which can be seen in Figs 2a and b. For each stress, threedevices were measured to verify the reproducibility of the results.
The Vac-dependency of Ron-degradation is shown in Fig. 2a, whereVgc is kept constant at Vgc = 5 V. The hot-carrier degradation levelincreases for the increasing Vac, moreover, it is obvious that Ron
decreases for low stress time (less than 1000 s) and increases aftersome stress time, therefore the inflexion of Ron degradation can be dis-covered. The Ron degradation at Vac = const = 165 V and different Vgc isdepicted in Fig. 2b. The Ron degradation will be much more serious forincreasing Vgc. The degradation changes the sign, negative for shorterstress time but positive for longer stress time. In addition, the corre-sponding stress time to the inflexion is longer for lower Vgc, especiallyfor Vgc = 1.5 V, the increase of Ron degradation cannot even beobserved.
No. 7
a b
0
1
2
3 C1= 0.85*Vgc– 0.93C3= –0.027*Vgc+ 0.16
C1,
C3
Vgc, V Vgc, V1 2 3 4 5 1 2 3 4 5
0
1
2
3
4
m = 0.27*Vgc0.68
n = 2.58*Vgc–0.21
n, m
Fig. 3 Dependency of model parameters C1, C3 and n, m on Vgc
a C1 and C3 variations with Vgcb n and m variations with Vgc
1 2 3 4 5
0
1000
2000
3000
4000 h1 = 0.15*Vgc2.8
0
4
8
12
16
h 1h 2
h2 = 64*Vgc2.6
Vgc, V
Fig. 4 Dependency of model parameters η1 and η2 on Vgc
To determine the parameters of (1), the above measurements can bechosen to fit the hot-carrier degradation model. All fitting results havebeen shown as follows:
1. The exponents in the degradation accelerating factors ξdit and ξhhi arealmost constant over the complete range, and are, on average, given by2.8 and 5.9 for the interface state and hot hole injection, respectively.2. Parameters C2 and C4, reflecting the degradation saturation effect, areconstant ratios of C1 and C3 over the complete range. The saturationlevels, C1/C2 = 4 and C3/C4 = 1, have been observed.3. C1 and C3 strongly depend on Vgc and do not have too much relationwith Vac, the results are shown in Fig. 3a, a simple linear model has beenused to fit the data.4. n and m also only change with Vgc, the fitting results are shown inFig. 3b, a simple exponential model has been used to fit the data.5. η1 and η2, the most important parameters in the model, reflect theinfluence from the hole current in the SOI-LIGBT, their fitting resultsare shown in Fig. 4. It is obvious that η1 and η2 also strongly dependon Vgc, a simple exponential model fits the data, however, the variationsof η1 and η2 with Vac can be ignored according to our fitting results.
To check the validity of the Ron degradation model, we predicted thedegradation level of the SOI-LIGBT under Vgc = 4 V and Vac = 165 Vand Vgc = 1.5 V and Vac = 175 V. Fig. 5 shows the degradation measure-ment results and the model forecasting curves for the two stressing con-ditions. It can be seen that the novel model for Ron in the SOI-LIGBT isable to reproduce the degradation, and the lifetime of the device can beevaluated well.
ELECTRO
10 100 1000–0.5
0.0
0.5
1.0
stress at Vgc= 1.5V and Vac= 175V
measurements at Vgc= 1.5V and Vac= 175V
measurements at Vgc= 4V and Vac= 165V
degr
adat
ion
of R
on, %
time, S
stress at Vgc= 4V and Vac= 165V
model results at Vgc= 1.5V and Vac= 175V model results at Vgc= 4V and Vac= 165V
Fig. 5 Comparisons of model predicted data and experimental data
Conclusion: In this Letter, a novel hot-carrier degradation model forSOI-LIGBT device has been proposed for the first time. The modeltakes the enhanced influence upon the degradation from the holecurrent in the SOI-LIGBT into consideration, and the SOI-LDMOSwith completely the same structure except that the doping type in thedrain area has been also fabricated to assist the modelling. Accordingto the verifications, the model is feasible to predict the hot-carrier degra-dation of a SOI-LIGBT.
Acknowledgments: The authors thank the National Natural ScienceFoundation of China (61204083), and the Natural Science Foundationof the Jiangsu Province (BK2011059).
© The Institution of Engineering and Technology 201319 November 2012doi: 10.1049/el.2012.4036One or more of the Figures in this Letter are available in colour online.
Siyang Liu, Weifeng Sun, Chunwei Zhang, Tingting Huang andQinsong Qian (National ASIC System Engineering Research Center,Southeast University, Nanjing, 210096, People’s Republic of China)E-mail: [email protected]
References
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NICS LETTERS 28th March 2013 Vol. 49 No. 7
