MMIC/RFIC design and its integration in RF modules · PDF file · 2015-05-260.25u...
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MMIC/RFIC design and its integration in RF modules April 2015
Transcript of MMIC/RFIC design and its integration in RF modules · PDF file · 2015-05-260.25u...
MMIC/RFIC design and its integration in RF modules April 2015
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Keysight EDA Silicon RFIC Design Solutions
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Interoperable Flow & Solutions ADS Virtuoso
Small-scale RFIC Large-scale RFIC
0.25u 0.13u 14nm
LDMOS IPD SiGe BiCMOS RF-CMOS CMOS CMOS-SOI
ADS front-to-back ADS front-end & EM
for RFIC and beyond Virtuoso-based Flow
User performs complete
circuit design to tape-out
within ADS platform (using 3rd-party DRC sign-off tool)
User performs front-end
and EM block design in
ADS, but moves to Virtuoso
for layout implementation
User runs (Keysight) RF
circuit and EM simulation
within the Virtuoso platform
http://www.keysight.com/find/eesof-rfic-design
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MMIC/RFIC Design and Integration Flow 1. ADS – Front-to-back MMIC Design Platform
• Schematic
Entry
• Simulators
• System
• Circuit
• EM
• Data Display
• Layout
• DRC/LVS
• DFM support
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MMIC/RFIC Design and Integration Flow 1. ADS – Front-to-back MMIC Design Platform
• Selected ADS 201x.x deliverables
• Multi-Technology Innovations – side-by-side
configuration support and seamless 3D EM
component integration
• Electro-Thermal Simulation – provides accurate,
“thermally aware” simulation results
• Selected ADS 2014 deliverables
• EM/circuit co-sim – "EM-based parasitic extraction"
• New device recognition LVS
• OA standard via support – greatly improves layout
productivity!
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MMIC/RFIC Design and Integration Flow
PA
Controller
PA RF
Sw
itch
2. ADS for Small Scale Silicon RFICs – Best fit
• Si RF Components
• Front-end modules (PA, Mixer, LNA-Mixer) or Antenna switches in CMOS-SOI starting to displace discrete GaAs power components
• Si-MMICs
• Silicon components and transceivers for millimeter wave products, like Optical Networks ( 10 to 40Gb/s), Automotive Collision Avoidance, 60GHz WLAN
• IPD
• Integrated Passive Device (IPD) – silicon process technology for the production of passive devices such as baluns, filters, couplers, and diplexers that are used in portable, wireless and RF applications
• LDMOS
• RF power transistors/PAs used for basestation, broadcast / ISM and aerospace & defense applications
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MMIC/RFIC Design and Integration Flow
Inputs from System-level
Schematic Entry
Circuit Design &
Simulation
Layout
Desktop DRC/LVS
& 3rd party links
GDSII or SOC integration
EM Extraction
2. ADS for Silicon RFIC Applications – Design Flow
• Proven ADS front-end solution for RFIC
• Major advantages through integrated EM
• Connectivity-driven layout creation
• Calibre/Assura DRC support for sign-off
• EM-based extraction through Momentum
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ADS PDK Support – SiGe / BiCMOS / CMOS / IPD More details at: www.keysight.com/find/eesof-foundries
Full Front-to-Back* PDKs Front-end PDKs
SG25H3 SG13S
SG25H1 SG13G2
CMRF7SF BiCMOS5PAe BiCMOS8HP
TSL018 CA18HB
SBC18H3
SBC18HA SBC18H2 SBC18HXL
IPD 0.18um
CM013RF 018CMOS
CM090rf
CM055 SIGE018
CMOS065 RF H9SOI RF
BiCMOS6G BiCMOS9MW H9SiGe
BiCMOS7RF BiCMOS9MW
CA18QC CS13Q1
High-Q™ IPD
*) All front-to-back PDKs include layout artworks and ADS Desktop LVS support
ADS DRC interconnect rule files are only included in selected PDKs
CS18Q1
BiCMOS8XP CSOI7RF
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MMIC/RFIC Design and Integration Flow 3. RF Module / RF-SiP design
RF PA module BOM:
- GaAs HBT Power Amplifier
• Schematic and IC Layout
• Done using WIN PDK in ADS
- SOI T/R Switch
• Schematic and layout provided
- CMOS Analog Controller
• Modeled using Behavioral Components
- Multilayer Laminate + SMT Components
• 4 Layer Laminate Stack w/DRC rule deck
- Custom built stack based on FR-4 Core
• Murata (Capacitors)
• Module layout done using ADS
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Keysight EDA Silicon RFIC Design Solution Virtuoso-integrated solutions
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Interoperable Flow & Solutions ADS Virtuoso
Small-scale RFIC Large-scale RFIC
0.25u 0.13u 14n
LDMOS IPD SiGe BiCMOS RF-CMOS CMOS CMOS-SOI
ADS front-to-back ADS front-end & EM
for RFIC and beyond Virtuoso-based Flow
User performs complete
circuit design to tape-out
within ADS platform (using 3rd-party DRC sign-off tool)
User performs front-end
and EM block design in
ADS, but moves to Virtuoso
for layout implementation
User runs (Keysight) RF
circuit and EM simulation
within the Virtuoso platform
http://www.keysight.com/find/eesof-rfic-design
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MMIC/RFIC Design and Integration Flow
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• Momentum is the leading 3D planar electromagnetic (EM) simulator used for passive circuit modeling and analysis
• Momentum covers a broad range of applications like RFIC, MMIC, board, package, Signal Integrity or antennas and is integrated in ADS and Virtuoso
• It provides dedicated RFIC capabilities like process scaling, via simplification and metal fill support http://www.keysight.com/find/eesof-momentum
4. Virtuoso-based Flow
• GoldenGate is the most trusted simulation, analysis and verification solution
available for integrated RF circuit design within Cadence Virtuoso
• Widely known for its advanced harmonic balance and envelope solvers, GoldenGate also provides all traditional Spice analyses like DC, AC, SP, noise and transient, as well as advanced analysis like sensitivity, stability or X-parameter http://www.keysight.com/find/eesof-goldengate
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GoldenGate RFIC Design & Simulation Solution Best-in-class RF circuit simulator:
• The best performance, capacity and accuracy to complete your RFIC designs
• Supports all large and small signal RF and transient analyses including large signal
stability and full X-parameter modeling and simulation
– Advanced statistical analysis:
• Delivers increased manufacturability using powerful Monte Carlo, Corners and Fast
Mismatch & Yield Contributor analysis capabilities
• Unique transistor-level PLL Jitter and Noise option
– Automation and Usability:
• Built-in and easy access to multi-dimensional sweeps, Optimization, Monte Carlo or
load-pull analysis along with simulation management capabilities
• Automated EVM, ACPR, Gain Compression, IP3, and load-pull
– RF to mm-Wave design support:
• Provides access to ADS Data Display with dedicated RF templates and adsLib with
over 150 RF distributed element library components
• Handling largest S-Parameter blocks with Multi-Threaded Convolution
– Wireless standard-compliant design:
• Enables scalable system-level solutions from RF architecture exploration through
end-to-end verification with links to SystemVue & Ptolemy
• Verify full radio functionality using Keysight’s wireless libraries for LTE, WCDMA,
WiMAX, DTV, ...
DC
Envelope
Transient
Multi-Tone
Variable #1
Vari
ab
le #
2
Advanced DFM/DFY
Digital State Sweep
SystemVue Verification
GoldenGate FCE
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GoldenGate integration into Virtuoso
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ADE-L support
ADE-XL support
GoldenGate Choosing Analyses Form
ViVa support
ADS Data Display support
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GoldenGate 2014 new features
• Wireless standard-compliant design
- VTB (Verification Test Bench) – pre-defined SystemVue test benches that can be used by the
RFIC designer using GG to easily validate his circuit performance against modulated metrics
like EVM, BER, or ACPR.
- FCE noise – added noise support to the existing, popular SV link (FCE – Fast Circuit
Envelope), which is a must have for any receiver test like sensitivity/desensitization. FCE
creates a model that is used in SystemVue to represent the degradation due to the RFIC in
system-level simulations without facing much of a performance impact.
• Identify & optimize critical components
- Sensitivity Analysis – enables to quickly analyze and diagnose problem areas especially
around device noise as well as device sensitivity also in large-signal analysis.
- FYC Envelope support – adding envelope analysis support for our popular FYC capability.
FYC (Fast Yield Contributor) allows to dramatically speed-up Monte Carlo simulations for
process and mismatch variations and also provides a contributor table to identify the root cause
devices and/or blocks.
Advanced analysis support
Automation & Usability
Unique mm-Wave design support
Wireless standard-compliant design
Best-in-class RF circuit simulator
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Enabling RF System simulations for RFIC Designer Verification Test Benches (VTB)
Copyright © Keysight Technologies 2014
“Designing with 4G Modulated Signals for
Optimized Multi-standard Transceiver ICs”
4G pre-configured VTB test benches:
Also other examples are available: ACPR & EVM measurement, QAM16_SER_vs_EbNo
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VTB – RFIC Designer focused use model
Copyright © Keysight Technologies 2014
“Designing with 4G Modulated Signals for
Optimized Multi-standard Transceiver ICs”
2. Set “ET
Stimulus”
to VTB
1. Setup your ET analysis
3. Select a pre-defined
VTB testbench
4. Run Envelope simulation
5. Results display
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Momentum in ADS and Virtuoso platforms
ADS 201x Virtuoso IC 5.1.41/ 6.x
.ltd .subst
3D Viewer
Spice
Model Generator
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Keysight Momentum 3D Planar EM Analysis
Momentum Simulator
Broadband
SPICE
Model
Generator
S-parameter
Component Options
2005 2008 2010 2003
Momentum Performance Improvements
Most popular 3D planar electromagnetic simulator:
• Advanced NlogN and multi-threading solver algorithms for optimal speed,
accuracy and capacity
• Arbitrary polygonal meshing with mesh reduction
• Thick metal analysis of side wall currents and efficient via modeling, accounting
for skin and proximity effects
Silicon-accurate nanometer RFIC process support:
• Automated layout pre-processing like via array merging
• Dummy metal fill and process scaling support
• Boolean layer operation for native MIM capacitor support
Cadence Virtuoso integration:
• Seamlessly integrated into the Cadence® Virtuoso® 5.1.41 and 6.1.x platforms
• Automated stack-up file creation from Cadence technology files
• 3D Viewer with embedded visualization of surface currents or radiated fields
provides insight on problem areas in layout
• Broad-band Spice Model generation for efficient use in time-domain simulations
Going beyond 3D planar applications:
• Fast, direct bond wire support
• Through Silicon Via (TSV) modeling support
• Virtuoso link to EMPro for full 3D EM simulations
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Momentum Virtuoso Flow
6. Results display
7. Virtuoso views creation
5. Simulation options
1. Via simplification 2. Substrate setup
3. Frequency plan 4. Ports setup
12 May, 2015
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Broad foundry support for Momentum
• Momentum is supported and qualified by all
relevant RFIC foundries
• Foundries typically not just provide substrate stack-
up file, but fully qualified Momentum Modules
• Just for TSMC over 50 Momentum Modules are
available for processes down to 28 nm
• A Momentum Module includes
- Momentum substrate stack-up file (.ltd)
- Via simplification Skill routines
- Default (validated) simulation options provide
best accuracy/speed trade-off
- Pre-computed substrate database
• More info at: www.keysight.com/find/eesof-foundries
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Momentum support from TSMC
Momentum officially qualified for TSMC’s 90-, 65- and 40-nm processes:
• Momentum has passed TSMC extensive qualification tests against
measurements up to 30 GHz for different configurations
• +20 inductors on average validated with different metal stacks for symmetric,
un-symmetric and center-tapped inductors configurations
Corresponding stack-up files can be downloaded at TSMC online:
Additional Momentum Modules and ADS PDKs available:
• Over 50 Momentum Modules are available for TSMC processes down to 28 nm
• Acccess through Keysightafter TSMC approval
For further details go to:
http://www.keysight.com/find/eesof-partners-tsmc
Sample results for 40 nm:
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Keysight EDA RFIC solutions within Virtuoso
Inputs from System-level
Schematic Entry
Layout
DRC/LVS
Parasitic Extraction
GDSII or SOC integration
GoldenGate – RFIC Design and Verification
SystemVue Verification
GoldenGate FCE
Momentum Simulator
Broadband
SPICE
Model
Generator
S-parameter
Component Options
QFN Designer
Circuit Simulation
GoldenGate Inductor & Passive
Component Design
Package & Bond
wire modeling
RF-ESL Analysis &
Design support
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Keysight EDA Silicon RFIC Design Solution 5. ADS/Virtuoso Interoperable Flows
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Interoperable Flow & Solutions ADS Virtuoso
Small-scale RFIC Large-scale RFIC
0.25u 0.13u 14n
LDMOS IPD SiGe BiCMOS RF-CMOS CMOS CMOS-SOI
ADS front-to-back ADS front-end & EM
for RFIC and beyond Virtuoso-based Flow
User performs complete
circuit design to tape-out
within ADS platform (using 3rd-party DRC sign-off tool)
User performs front-end
and EM block design in
ADS, but moves to Virtuoso
for layout implementation
User runs (Keysight) RF
circuit and EM simulation
within the Virtuoso platform
http://www.keysight.com/find/eesof-rfic-design
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Target Flows & Users Bi-Directional Schematic Interoperability
‒ Designers that want to simulate RF blocks in ADS, but use Virtuoso for
layout
LNA
schematic
LNA
schematic
Layout
Open
schematic
in ADS or
Virtuoso
Connectivity-driven layout creation and LVS
RF Design and/or Simulation
in ADS:
- Schematic Entry
- Circuit Simulation
- Tuning/Optimization/Stat/D
OE…
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Target Flows & Users Bi-Directional Layout Interoperability
‒ Designers that want to run EM and/or thermal
simulations on a Virtuoso layout
‒ Designers that want to design & simulate RF
blocks in ADS and include them in a larger
Virtuoso design
‒ Designers that want to create a module in ADS
containing ICs from both ADS and Virtuoso
LNA
PA
LNA schematic LNA
schematic
Bias
Layout
Bias
layout
PA
Am
alf
i P
A m
od
ule
CMOS PA
Implemented in
Virtuoso
Simulated with
GoldenGate
RF Switch
Implemented
in ADS
PA Module
Implemented &
verified in ADS Swit
ch
ADS Virtuoso
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Silicon RFIC Interoperability Vision
OA
Schem &
Layout
CDN
PDKs,
iPDKs,
Open-
PDKs
Virtuoso ADS
SK
ILL
AE
L/lis
p,
TC
L, p
yth
on
Assura
StarRCXT
Calibre
.
.
LVS
PE
Momentum 3DEM Thermal
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What’s New for ADS 2015.01 Advanced Schematic
Interoperability • Easy transfer of schematic test bench
variables
• Interoperable analogLib support
• AEL Symbol pCells
• Library CDF
• Expanded lisp support
Basic Hierarchical Layout
Interoperability • AEL Layout pCells
• Express Pcells
OA
Schem
atic
Virtuoso ADS
Momentum
3DEM
Thermal
CDN PDK Tech File
Layers
Display
AEL/Lisp
SKILL
Circuit-sim
OA
Layout,
Express
Pcells 26
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Layout pCell Flows in ADS 2015.01
Use “createTechnology”
utility to create matching
technology for ADS
tech.db (library.tech,
display.tech)
1. No corresponding ADS layout pCells:
• Leverage Express Pcell support in Virtuoso
• Does not allow any modification to pCell-based layout
components
2. Interoperable PDK with corresponding ADS layout pCells:
• AEL layout macros for (all or subset of) pCell-based layout
components
• Layout pCell instances can be modified, e.g. sweep/optimize
spiral inductor pCell
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ADS-Virtuoso Interoperable PDK Support Available at ADS 2015.01 shipment
PDKs targeted with ADS
2015.01
SGB25V
BiCMOS5
PAe
CS13/18 SBC18H
A SBC18H3
CMOS
40nm
SOI
0.18um
SOI
0.18um
(More TSMC coverage through iPDK support in 2015)
SBCQE1
Interoperable
PDKs
available at
ADS 2015.01
shipment!!
Layout pcell
support will be
added to selected
PDKs in early
FY15!
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PDK Interoperability Overview
Open Access library
- data.dm & tech.db
- .cadence & .oalib
- display.drf & *.Cat
- …
Platform specific
initialization files
devices
data.dm
symbol cellview
spectre cellview
layout cellview
…
symbol.oa
master.tag
data.dm
layout.oa
master.tag
Callbacks and custom
netlist procedures
Parameterized Layout
cells
Standard Virtuoso
PDK
ADS-Virtuoso
Interoperable PDK iPDK
Skill Lisp or AEL TCL
Skill AEL Python
Grey boxes are common for all
Open Access PDK libraries
Typically delivered as single
“PDK” database!
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GoldenGate in ADS Brings not only your Virtuoso design, but also your favorite RFIC simulator into ADS
Provides access to GoldenGate within ADS
from an interoperable schematic.
"RFIC Cockpit" in ADS reads Virtuoso states
and provides familiar RFIC simulation control.
ADS/GG 2015.01ADS/GG 2015.01
• Platforms:
•
•
•
• Platforms:
- Linux & Windows
• Important Core Analyses:
- DC & Tran
- AC & S-Param
- HB & HB-Noise
- SSNA
- ET
• Important Analysis Controls
- Sweeps
- MC & FYC
• State Import
ADS Virtuoso
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Resources for more details
• Silicon RFIC: http://www.keysight.com/find/eesof-rfic-design
- ADS: http://www.keysight.com/find/eesof-ads
• http://edadocs.software.keysight.com/display/public/ADS+30-Second+Demos
• http://www.keysight.com/find/eesof-foundries
- GoldenGate: http://www.keysight.com/find/eesof-goldengate
- Momentum: http://www.keysight.com/find/eesof-momentum
- EMPro: http://www.keysight.com/find/eesof-empro
• Join us on LinkedIn :
- http://www.linkedin.com/groups/Agilent-Silicon-RFIC-Users-Group-5177865/about
- http://www.linkedin.com/groups/Agilent-ADS-User-Group-1320157/about
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