PB 1990-2009

Copyright Piero Belforte

DWS

H I G H P E R F O R M A N C E B O A R D

D E S I G N

FREQUENCY LIMIT

TEST

It is well known that the digital

bandwidth in terms of maximum

allowable clock frequency is a key

parameter to be evaluated during

both the design and validation

cycles of high-performance

systems.

System "soft" failures due to

electrical and timing problems are

identified by testing the system at

operating speeds exceeding those

required for nominal operation.

The margin in terms of difference

between nominal and maximum frequency is a good

figure for evaluating

system robustness and

reliability.

This application note

describes the way in

which DWS can be

effectively used for

optimizing the design of

a high speed ECL 100K

board, taking

simultaneously into

account the problems of

signal degradation due

to interconnection

effects and logic-timing

problems related to

actual behaviour of

active devices.

IN

C

50 K

ni T PWLI

TPKI

PRI

R

VRI

+

OUT

I

IN

LOGIC/TIMING CORE

nT TH

L

OUT SHAPING NET

C

no T PWLO

+

PRO

RO

LO

TPKO

OUT

Total delay = T + T + ni T + no T + n T

10

0V

V

-.9-1.7

BBV

1

PWLI

-.8

PWLOC

I

PKI PKO

VC

VI

Fig. 1: Scheme of the electrical macromodel for input-output ECL ports.

DATA OUT

DATA OUT

Vee

Vee Vee Vee

Vee Vee VeeVee

Vee

Vee

Vee VeeVee

Vee Vee

Vee

Vee

75 ohm

75 ohm

75 ohm75 ohm75 ohm75 ohm

75 ohm

75 ohm

75 ohm

75 ohm75 ohm

75 ohm

75 ohm

75 ohm

RPD13430

430RPD14

2

3

4

5

U5A

100107

TXOR2

TXOR1

300 ps

300 ps

RS3

68

68

RS1

75 ohm

TDAT

300 ps

100131FPU2C

34

5

6 7

8

RPD4330

RS468

RPD6330

100131FP 100131FP 100131FP 100131FPU4B

RPD11

RPD12

330

430

RS2

68

1

24

RPD10430

200 ps

TINT4

2

11

12

U3B24

1

11

12

RPD9

330

TINT3

100 ps

RPD7430

RPD8430

8

7

4 3

6

5

U3C

RPD5430

TINT2

200 ps

U2B11

12

24

1

RPD3430

TINT1

100 ps

2

TD

300 ps

TCK2

200 ps

TCK1

200 psRSCK1

47RSCK2

47

47

RSCK3

RPD2330

330

RPD1

TC2

100 ps

TCK3

200 ps

15

16

17

18

U1A

100102FPRPD9330

TC1

100ps

15

1617

18

U7A100114FP

RT1100

CK IN

RPD19

330

RPD20

10K

U1D

100102FP

1

2

7

8

RPD17330

RPD18330

100 ps

100 ps

TCK01

TCK02

CKOUT

TD1

75 ohm 100 ps

75 ohm 100 ps

TD2RPD16330330

RPD15

15

16

17

18

U6A

100102FPRPD21

10K

DATA OUT*

CK IN*

CKOUT*

40

30

Fig.2 : Initial pre-layout version of the 31-bit pseudo-random generator board (PN5DB).

2

Copyright Piero Belforte

HIGH SPEED BOARD

MODEL

100K logic gates and flip-flops are

accurately modelled at electrical-

timing-logic levels, including such

key issues as timing skew between

outputs, internal path delay

mismatches and input-output

electrical equivalents obtained by

taking into account package and

nonlinear effects as observed in

device characterization (Fig. 1). In

this particular case, an equivalent

electrical model for input-output

ports is used instead of the more

direct s-parameter behavioural

model used for other applications.

Despite the complexity of the

resulting model network (on the

order of a thousand elements) and

the number of calculated time-

points necessary to achieve a good

resolution (on the order of several

thousand), DWS runs require

few milliseconds on a standard PC

, so that the interactive

optimization recycles are

accomplished in a small amount of

time.

DESIGN OPTIMIZATION

Starting with an initial pre-layout

version of the pseudo-random

generator board (PN5DB)

including interconnects impedance

and length evaluation (Fig. 2),

DWS simulation easily pinpoint

the causes of failures when

working at higher clock

frequencies. To achieve this goal a

limit frequency test setup is

simulated as shown in Fig.3.

The board is connected to a sweep

frequency clock generator and the

most significant board signals are

monitored in order to observe

when a failure occurs.

Typical failures consist of an

incorrect bit sequence with respect

to a pseudo-random 31-bit

PN50PT

Data (U2A)

CK (U2A)

DATA_OUT

DATA_OUT\

CK_IN

CK_IN\

-2 V

RTERM

75

reset set

V3

V set

1.7 volt

V2

V reset

2 ns pulse

Tcable2

50 ohm

2 ns

ideal cable

Tcable1

50 ohm

2 ns

ideal cable

R

50

R

50

VCP2VCP1

VCH1.3 volt

SWGEN

300

400

500

600

100

200

501 601

Fig. 3: Electrical scheme of the test set-up used to evaluate the limit frequency of

the PRBS board.

0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00

TIME[uS]

-1.30 V

-1.30 V

-1.30 V

-1.30 V

-1.30 V

-2.00 V

-0.50 V

V(100)

layout4.g

-2.00 V

-0.50 V

V(100)

layout3.g

-2.00 V

-0.50 V

V(100)

layout2.g

-2.00 V

-0.50 V

V(100)

layout1.g

-2.00 V

-0.50 V

V(400)

layout1.g

* 218 MHz

* 235 MHz

* 239 MHz

* 245 MHz

* frequency limit

Fig. 4a: Layout impact on performance: swept freq. test (200-250 MHz)

0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00

TIME[uS]

-1.30 V

-1.30 V

-1.30 V

-1.30 V

-1.30 V

-2.00 V

-0.50 V

V(200)

layout4.g

-2.00 V

-0.50 V

V(200)

layout3.g

-2.00 V

-0.50 V

V(200)

layout2.g

-2.00 V

-0.50 V

V(200)

layout1.g

-2.00 V

-0.50 V

V(400)

layout1.g

* 245 MHz

* 239 MHz

* 235 MHz

* 218 MHz

Fig. 4b: Layout impact on performance: swept freq. test (200-250 MHz)

3

Copyright Piero Belforte

sequence expected during correct

operation (Fig. 4).

The behaviour differences

between output data signals

V(200) and V(100) are

caused by different termination schemes:

complementary output 200 has a

pull down load within the board

and no termination resistor, so that

the waveform is affected by strong

overshoots due to reflections

within device package, output trace

and connector, while output 100,

being left open for bus

applications, has a more

straightforward behaviour because

it is terminated off the board

(RTERM visible on Fig. 3).

The limit frequency for the initial

design turns out to be about

200 MHz due to setup time

violation on the first 100131 D-

type master-slave flip-flop (U2A)

causing detestable operation.

After this first result several design

modifications have been evaluated

in order to identify the best

solution and the impact on

performance is summarized in Fig.

5. The most relevant improvement

in terms of clock speed is obtained

by shortening the delay of input-

output traces of the exclusive-or

gate U5A (100107) from 300ps (~

6cm) to 100ps (~ 2cm) and trying

to increase the delay of the clock

path of U2A with respect the

other flip-flops in the chain. This

last adjustment is implemented

utilizing the clock driver gate

U1A (100102) as delay for U2A

and U2B clock inputs and

connecting the other flip-flops

directly to the output of the

differential line receiver U7A

(100114) (Fig.6). Minor speed

improvements are also obtained by

modifying the type of terminations

used on critical paths turning series

into parallel arrangements.

TRACE

ELECTRICAL

LENGTH

( ps )

F max.

( MHz )

TCK1

TCK2

TCK3

TDAT

sweep

fixed

LAYOUT VERSION

300 200 200 200

100 200 200 200

100 200 200 200

300 300 200 100

218 235 239 245

- - - 238.1

# 1 # 2 # 3 # 4 (opt)

Fig. 5: Summary of the limit frequency versus layout parameters: trace length has great

impact on performance

DATA OUT

Vee Vee

Vee Vee VeeVee

Vee

Vee Vee

Vee

Vee Vee

Vee

Vee

75 ohm

75 ohm

75 ohm75 ohm75 ohm75 ohm

75 ohm

75 ohm

75 ohm

75 ohm

75 ohm

75 ohm

RPD13

430 7

6

1

24

U5D

100107FP

TXOR2

TXOR1

100 ps

300 ps

75 ohm

TDAT

100 ps

100131FP

U2A

34

15 14

13

RPD4

330

RS4

68

RPD6

330

100131FP 100131FP 100131FP 100131FP

U4B

1

24

RPD10

430

200 ps

TINT4

2

11

12

U3B24

1

11

12

RPD9

330

TINT3

100 ps

RPD8

430

8

7

4 3

6

5

U3C

RPD5

430TINT2

200 ps

U2B11

12

24

1

RPD3

430

TINT1

100 ps

2

TD

300 ps

TCK3

200 ps

RSCK1

47

330

330

RPD1

TC2

100 ps

15

16

17

18

U1A

100102FPRPD9

Vee

330

TC1

100ps

7

81

2

U7D

100114FP

RT1

100

CK IN

RPD19

330

RPD20

10K

U1D

100102FP

1

2

7

8

RPD17

330

RPD18

330

100 ps

100 ps

TCK01

TCK02

CKOUT

TD1

75 ohm 100 ps

75 ohm 100 ps

TD2330

RPD15

15

16

17

18

U6A

100102FPRPD21

10K

DATA OUT\

CK IN\

CKOUT\

Vee

RPD12

330

-2 V

RPD11

75

RPD7

75

RPD14

-2 V

7516

20

2

50 ohm

50 ohm

200 ps

200 ps

TCIN1

TCIN2

-2 V

RPD22

10K

75 ohm

TCK2

200 ps

75 ohm

TCK1

200 ps

300

400

500

600

100

200

Fig. 6: Optimized version of the 31-bit pseudo-random generator board (PN50PT)

4

Copyright Piero Belforte

RESULTS

The final result is the PN5OPT

pre-layout version which operates

correctly up to about 238 MHz in

the fixed frequency test and up to

245 MHz in the swept frequency

set-up showing a 20% performance

improvement over the initial

design.

This result is obtained with board

implementations utilizing active

devices packaged in flat-packs. It

is interesting to evaluate the

impact on performance due to

packaging effects: substituting

larger 24-pin devices for the

original flat-packs, while leaving

pcb trace lengths unchanged,

causes a decrease in maximum

operating frequency (sweep test)

from 245 MHz to 229 MHz

showing the great importance of

packaging issues for this kind of

design (Fig. 7). An analysis

procedure similar to that

previously shown can be applied

after the board layout definition in

order to verify the way in which

the differences in the

interconnection paths (length,

impedance, via holes, trace

proximity, etc.) can affect the

performance with respect to the

pre-layout specification.

0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00

TIME[uS]

-1.30 V

-1.30 V

-1.30 V

-2.00 V

-0.50 V

V(100)

layout4.g

-2.00 V

-0.50 V

V(100)

pn5db8dil.g

-2.00 V

-0.50 V

V(400)

pn5db8dil.g

* FP

* 245 MHz

* DIL

* 229 MHz

Fig. 7: Maximum operating frequency (sweep test) comparison between flat and 24 pin

dual-in-line package.