mission

Hardware Reference Manual for Mission 10x-Unified Learning Kit

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iWave Systems Technologies Pvt. Ltd. Page 1 of 119 (Confidential)


iW-EMDBY-UM-01-R2.0-REL3.0-RMHW

12th Feb 11

Authors Rahul Karkera

APPROVAL

Name Function Organisation Date Signature

Mr. Sebikumar

Kuruvilla

Wipro

Mr. Bhagavath Project Manager iWave Systems Technologies Pvt. Ltd.

Distribution iWave Systems Technologies Pvt. Ltd

Contact Info

Name Telephone e-mail

iWave Systems Tech. Pvt. Ltd. 7/B, 29

th Main,

BTM Layout, 2nd

Stage, Bangalore 560 076, India.

+91-80-2668-3700 +91-80-2678-1643

[email protected]


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DOCUMENT IDENTIFICATION

Project Name iW-EMDBY Document Name iW-EMDBY-UM-01-R2.0-REL3.0-RMHW Document Home iWave Server

Release No 3.0 Status Engineering version Audience Wipro


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DOCUMENT REVISION HISTORY

Release Date Change Description Author

1.0 10th July. 10 Initial Draft version Rahul Karkera

2.0 10th Dec. 10 Updated version

The following tables are updated with FPGA pin-out details: Table 22 to Table 29, Table 41 to Table 44, Table 47 & Table 51.

Rahul Karkera

3.0 12th Feb. 11 Engineering Version Rahul Karkera

PROPRIETARY NOTICE: This document contains proprietary material for the sole use of the intended recipient(s). Do not read this document further if you are not the intended recipient. Any review, use, distribution or disclosure by others is strictly prohibited. If you are not the intended recipient (or authorized to receive for the recipient), you are hereby notified that any disclosure, copy or distribution or use of any of the information contained within this document is STRICTLY PROHIBITED. Thank you. iWave Systems Tech. Pvt. Ltd.


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Table of Contents

Introduction ......................................................................................................11 1.1 Purpose ........................................................................................................................... 11 1.2 About Unified Learning Kit ............................................................................................. 11 1.3 Acronyms and Abbreviations........................................................................................... 11

Functional Description ......................................................................................14 2.1 Board Architecture .......................................................................................................... 14

2.1.1 Board Features .......................................................................................................... 15 2.2 ULK Board ...................................................................................................................... 17

2.2.1 TOP VIEW ............................................................................................................... 17 2.2.2 BOTTOM VIEW ...................................................................................................... 18

Processor Interface ............................................................................................19 3.1 NAND Flash interface ..................................................................................................... 19 3.2 Mobile DDR interface ..................................................................................................... 20 3.3 3.5inch LCD interface ..................................................................................................... 22 3.4 Touch panel interface ...................................................................................................... 25 3.5 Audio interface ................................................................................................................ 26 3.6 Ethernet controller interface............................................................................................. 28 3.7 RS232 interface ............................................................................................................... 30 3.8 RTC interface .................................................................................................................. 31 3.9 USB2.0 Host interface ..................................................................................................... 32 3.10 USB2.0 OTG interface .................................................................................................. 34 3.11 VGA interface ............................................................................................................... 36 3.12 I2C EEPROM interface ................................................................................................. 38 3.13 FPGA interface .............................................................................................................. 38 3.14 JTAG interface .............................................................................................................. 40 3.15 MMC/SD1 interface ...................................................................................................... 42 3.16 SD2 interface ................................................................................................................. 43 3.17 Character LCD interface ................................................................................................ 46 3.18 TV out interface............................................................................................................. 48

FPGA interface .................................................................................................50 4.1 DDR2 SDRAM interface ................................................................................................. 50 4.2 Ethernet PHY interface .................................................................................................... 53 4.3 Serial configuration PROM interface ............................................................................... 56 4.4 RS232 interface ............................................................................................................... 57 4.5 Charater LCD interface.................................................................................................... 59 4.6 ADC interface ................................................................................................................. 61 4.7 DAC interface ................................................................................................................. 63 4.8 7 Segment LED interface ................................................................................................. 65 4.9 I2C EEPROM interface ................................................................................................... 66


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4.10 JTAG interface .............................................................................................................. 68

External Interfaces ............................................................................................70 5.1 Processor Keypad interface.............................................................................................. 70 5.2 I/O expansion connector .................................................................................................. 73 5.3 Simple digital interface .................................................................................................... 76 5.4 Control sensor interface ................................................................................................... 79 5.5 Bluetooth or Modem interface ......................................................................................... 81 5.6 External LCD interface .................................................................................................... 83 5.7 Camera interface ............................................................................................................. 86 5.8 I2C GPS interface ............................................................................................................ 88 5.9 IrDA interface ................................................................................................................. 90 5.10 FPGA Keypad interface ................................................................................................. 91 5.11 FPGA I/O connectors interface ...................................................................................... 94

5.11.1 20-Pin FPGA IO header .......................................................................................... 94 5.11.2 38-pin Mictor Connector ......................................................................................... 97 5.11.3 70-Pin Expansion connector .................................................................................... 99

Operation & Maintenance Features ................................................................. 103 6.1 Power & Reset LEDs ................................................................................................... 103 6.2 LEDs for OMAP3530 .................................................................................................. 103 6.3 LEDs for FPGA ........................................................................................................... 105 6.4 Major Test points........................................................................................................... 106

Switches & Jumpers ........................................................................................ 108 7.1 Reset Switch .................................................................................................................. 108 7.2 Toggle Switches ............................................................................................................ 110

7.2.1 Mode switch ........................................................................................................... 110 7.2.2 Power Switch .......................................................................................................... 110

7.3 DIP Switches ................................................................................................................. 111 7.3.1 System information for OMAP processor ............................................................... 111 7.3.2 Boot Configuration for OMAP processor ................................................................ 112 7.3.3 System information for FPGA ................................................................................ 113

7.4 Push button switches for OMAP processor & FPGA ..................................................... 114 7.5 Jumpers for Processor UART ........................................................................................ 115 7.6 Jumper for USB OTG .................................................................................................... 116

Dos & Donts................................................................................................. 117

Technical Support ........................................................................................... 119


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List of Figures

Figure 1: ULK board Architecture .............................................................................................. 14 Figure 2: ULK board Top View ................................................................................................. 17 Figure 3: ULK board Bottom View ............................................................................................ 18 Figure 4: OMAP3530 with NAND flash interface ...................................................................... 19 Figure 5: NAND Flash circuit schematic .................................................................................... 20 Figure 6: OMAP3530 interface with Mobile DDR ..................................................................... 21 Figure 7: Mobile DDR circuit schematic .................................................................................... 21 Figure 8: OMAP3530 interface with 3.5inch LCD ..................................................................... 22 Figure 9: 3.5inch LCD circuit schematic .................................................................................... 23 Figure 10: OMAP3530 interface withTouch panel ..................................................................... 25 Figure 11: Touch panel circuit schematic. .................................................................................. 25 Figure 12: OMAP3530 interface with Audio ............................................................................. 26 Figure 13: Headset & MIC in circuit schematic .......................................................................... 27 Figure 14: Speaker out circuit schematic .................................................................................... 27 Figure 15: OMAP3530 interface with Ethernet controller ........................................................... 29 Figure 16: Ethernet Controller circuit schematic ......................................................................... 29 Figure 17: OMAP3530 interface with RS232 interface ............................................................... 30 Figure 18: RS232 interface circuit schematic .............................................................................. 31 Figure 19: OMAP3530 interface with RTC interface .................................................................. 32 Figure 20: RTC interface circuit schematic................................................................................. 32 Figure 21: OMAP3530 Processor USB Host Interface ............................................................. 33 Figure 22: USB host circuit schematic ........................................................................................ 33 Figure 23: OMAP3530 interface with OTG transceiver .............................................................. 34 Figure 24: USB OTG circuit schematic ...................................................................................... 35 Figure 25: OMAP3530 interface with VGA ............................................................................... 36 Figure 26: VGA interface circuit schematic ................................................................................ 37 Figure 27: OMAP3530 interface with I2C EEPROM ................................................................. 38 Figure 28: I2C EEPROM circuit schematic. ............................................................................... 38 Figure 29: OMAP3530 interface with FPGA .............................................................................. 39 Figure 30: OMAP-FPGA interface circuit schematic .................................................................. 40 Figure 31: OMAP3530 interface with JTAG .............................................................................. 41 Figure 32: OMAP JTAG circuit schematic ................................................................................. 41 Figure 33: OMAP3530 interface with SD1 ................................................................................. 42 Figure 34: SD1 interface circuit schematic ................................................................................. 43 Figure 35: OMAP3530 interface with SD2 ................................................................................. 44 Figure 36: SD2 interface with transceiver circuit schematic ........................................................ 45 Figure 37: OMAP3530 interface with Character LCD ................................................................ 46 Figure 38: Character LCD circuit schematic ............................................................................... 47 Figure 39: OMAP interface with TV Out ................................................................................... 48


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Figure 40: TV Out circuit schematic ........................................................................................... 49 Figure 41: FPGA-DDR2 SDRAM interface ............................................................................... 50 Figure 42: FPGA DDR2 SDRAM circuit schematic ................................................................... 51 Figure 43: FPGA-Ethernet PHY interface .................................................................................. 53 Figure 44: FPGA Ethernet Phy Circuit Schematic ...................................................................... 55 Figure 45: FPGA-SPI PROM interface ....................................................................................... 57 Figure 46: FPGA SPI PROM circuit schematic .......................................................................... 57 Figure 47: FPGA-RS232 interface .............................................................................................. 58 Figure 48: FPGA-RS232 circuit schematic ................................................................................. 58 Figure 49: FPGA-Character LCD interface ................................................................................ 59 Figure 50: FPGA-Character LCD circuit schematic .................................................................... 60 Figure 51: FPGA-ADC interface ................................................................................................ 61 Figure 52: ADC circuit schematic .............................................................................................. 62 Figure 53: FPGA-DAC interface ................................................................................................ 63 Figure 54: DAC circuit schematic .............................................................................................. 64 Figure 55: FPGA-7segment LED interface ................................................................................. 65 Figure 56: 7 segment LED circuit schematic .............................................................................. 66 Figure 57: FPGA-I2C EEPROM interface .................................................................................. 67 Figure 58: FPGA-I2C EEPROM circuit schematic ..................................................................... 67 Figure 59: FPGA interface with JTAG ....................................................................................... 68 Figure 60: FPGA JTAG circuit schematic .................................................................................. 68 Figure 61: OMAP-FPGA JTAG interface through buffer circuit schematic ................................ 69 Figure 62: OMAP3530 interface with Keypad ............................................................................ 70 Figure 63: 6x6 Processor Keypad circuit schematic & layout ..................................................... 72 Figure 64: OMAP3530 interface with I/O expansion connector .................................................. 73 Figure 65: IO Expansion connector circuit schematic ................................................................. 74 Figure 66: OMAP3530 interface with Simple Digital Interface connector .................................. 76 Figure 67: Simple Digital Interface circuit schematic ................................................................. 78 Figure 68: OMAP3530 interface with Control Sensor header ..................................................... 79 Figure 69: Control Sensor Header circuit schematic ................................................................... 80 Figure 70: OMAP3530 interface with Bluetooth or Modem Interface ......................................... 81 Figure 71: Bluetooth or Modem interface circuit schematic ........................................................ 82 Figure 72: OMAP3530 interface with External LCD .................................................................. 83 Figure 73: External LCD circuit schematic ................................................................................. 84 Figure 74: OMAP3530 interface with Camera ............................................................................ 86 Figure 75: Camera Interface circuit schematic ............................................................................ 87 Figure 76: OMAP interface with GPS Header ............................................................................ 89 Figure 77: GPS header circuit schematic .................................................................................... 89 Figure 78: OMAP interface with IrDA Connector ...................................................................... 90 Figure 79: IrDA connector circuit schematic .............................................................................. 91 Figure 80: FPGA-Keypad interface ............................................................................................ 92 Figure 81: 4x4 FPGA Keypad circuit schematic ......................................................................... 93


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Figure 82: FPGA-I/O connectors interface ................................................................................ 94 Figure 83: 20-pin FPGA IO header circuit schematic ................................................................. 95 Figure 84: 38-pin Mictor connector circuit schematic ................................................................. 97 Figure 85: 70-pin FPGA Expansion connector circuit schematic ...............................................100 Figure 86: Power & Reset LEDs circuit schematic ...................................................................103 Figure 87: Processor LEDs circuit schematic ...........................................................................105 Figure 88: FPGA LEDs circuit schematic ................................................................................106 Figure 89: Manual Reset Circuit Schematic ...............................................................................108 Figure 90: Warm Reset Circuit Schematic .................................................................................109 Figure 91: Reset Buffer Circuit Schematic ................................................................................109 Figure 92: Mode Switch circuit schematic .................................................................................110 Figure 93: Power Switch Circuit Schematic ..............................................................................111 Figure 94: OMAP DIP Switch Circuit Schematic ......................................................................112 Figure 95: OMAP Boot Configuration Circuit Schematic ..........................................................113 Figure 96: FPGA DIP Switch Circuit Schematic .......................................................................114 Figure 97: Lab interrupt Circuit Schematic ................................................................................115 Figure 98: Push Button Switches Circuit Schematic ..................................................................115 Figure 99: UART Jumper setting Circuit Schematic ..................................................................116 Figure 100: USB OTG Jumper setting Circuit Schematic ..........................................................116


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List of Tables Table 1: Acronyms & Abbreviations .......................................................................................... 11 Table 2: 3.5inch LCD connector ................................................................................................. 23 Table 3: 4 Pin Touch panel connector ......................................................................................... 26 Table 4: 3 Pin Stereo connector for MIC IN ............................................................................... 28 Table 5: 3 Pin Stereo connector for Headset OUT ...................................................................... 28 Table 6: 3 Pin Stereo connector for left speaker Out ................................................................... 28 Table 7: 3 Pin Stereo connector for right speaker Out ................................................................. 28 Table 8: RJ 45 connector Pin Description ................................................................................... 30 Table 9: DB-9 Male connector ................................................................................................... 31 Table 10: Type A connector Pin Description .............................................................................. 34 Table 11: Type mini AB connector Pin Description.................................................................... 35 Table 12: 15 Pin VGA connector................................................................................................ 37 Table 13: 14 Pin JTAG connector for Processor ......................................................................... 41 Table 14: SD1 Connector Pin Description .................................................................................. 43 Table 15: SD2 Connector Pin Description .................................................................................. 45 Table 16: 16 Pin Character LCD connector ................................................................................ 47 Table 17: TV out connector (RCA jack) ..................................................................................... 49 Table 18: FPGA pin-out details for DDR2 SDRAM interface .................................................... 51 Table 19: RJ 45 connector Pin Description ................................................................................. 55 Table 20: FPGA pin-out details for Ethernet interface ................................................................ 56 Table 21: FPGA pin-out details for SPI PROM interface ............................................................ 57 Table 22: DB-9 Male connector ................................................................................................. 58 Table 23: 16 Pin Character LCD connector ................................................................................ 60 Table 24: 3 Pin Stereo connector for ADC input......................................................................... 62 Table 25: FPGA pin-out details for ADC ................................................................................... 62 Table 26: 3 Pin Stereo connector for DAC output ....................................................................... 64 Table 27: FPGA pin-out details for DAC ................................................................................... 64 Table 28: FPGA pin-out details for 7 segment LED ................................................................... 66 Table 29: FPGA pin-out details for I2C EEPROM ..................................................................... 67 Table 30: 14 Pin JTAG connector for FPGA .............................................................................. 69 Table 31: 15 pin Keypad connector ............................................................................................ 72 Table 32: 28-pin I/O expansion connector .................................................................................. 75 Table 33: 25-pin Simple Digital Interface connector................................................................... 78 Table 34: 15-pin Control Sensor Header ..................................................................................... 80 Table 35: Bluetooth or Modem connector .................................................................................. 82 Table 36: External LCD connector1 ........................................................................................... 84 Table 37: External LCD connector2 ........................................................................................... 85 Table 38: Camera connector ....................................................................................................... 87 Table 39: 5 pin GPS header ........................................................................................................ 90 Table 40: 6 pin IrDA Header ...................................................................................................... 91


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Table 41: 12 pin FPGA Keypad connector ................................................................................. 93 Table 42: 20-Pin FPGA IO header .............................................................................................. 96 Table 43: 38-pin Mictor connector ............................................................................................. 97 Table 44: 70-pin FPGA Expansion connector ............................................................................101 Table 45: Power & Reset LEDs ...............................................................................................103 Table 46: LEDs for OMAP3530 ..............................................................................................104 Table 47: LEDs for FPGA .......................................................................................................105 Table 48: Test Points in ULK ....................................................................................................106 Table 49: OMAP DIP Switch details .........................................................................................111 Table 50: Boot Configuration DIP Switch details ......................................................................112 Table 51: FPGA DIP Switch details ..........................................................................................114


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Introduction

1.1 Purpose

The purpose of this document is to briefly describe the user interfaces & external interfaces of the Unified Learning Kit.

1.2 About Unified Learning Kit

Unified Learning Kit is based on Texas Instruments OMAP3530 application processor & Spartan-6 FPGA. The OMAP3530 processor supports interfaces such as Mobile DDR, Nand Flash, Audio in & out, TV out, Touch screen LCD, VGA out, Ethernet, Keypad, USB OTG, 2 SD cards & external interface connectors such as Control sensor header, I/O expansion connector, I2C Header for GPS, Bluetooth & Modem Connector, Simple Digital interface connector, IrDA Connector, Camera Connector & LCD connector. The Spartan-6 FPGA supports interfaces such as DDR2 SDRAM, Ethernet, ADC, DAC, character LCD & external interfaces such as 70-pin IO expansion connector & 20-pin IO header.

1.3 Acronyms and Abbreviations

Table 1: Acronyms & Abbreviations

Term Meaning

ADC Analog to Digital Convertor ALC Automatic Level Control ALE Address Latch Enable ARM Advanced RISC Machine ASIC Application Specific Integrated Circuit BGA Ball Grid Array CAS Column Address Strobe CCD Charge Coupled Device CE Chip Enable CEA Consumer Electronics Association CLE Command Latch Enable CIR Consumer Infrared CMOS Complementary Metal Oxide Semiconductor CPLD Complex Programmable Logic Device CTS Clear To Send DAC Digital to Analog Converter DDR2 SDRAM Dual Data Rate two Synchronous Dynamic RAM DSP Digital Signal Processing EDMA Enhanced Direct-Memory-Access EEPROM Electrically Erasable Programmable Read Only Memory


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EMC Electro Magnetic Compatibility EMI Electro Magnetic Interference EPC Embedded Power Control ESD Electro Static Discharge FBGA Fine pitch Ball Grid Array FPGA Field Programmable Gate Array GPIO General Purpose Input Output GPMC General Purpose Memory Controller HD High Definition HS High Speed HTSSOP Heat sink Thin-Shrink Small Outline Package IEEE Institute of Electrical & Electronics Engineers I2C Inter-Integrated Circuit I2S Inter Ic sound IP Intellectual Property IrDA Infrared Data Association I/O Input Output JTAG Joint Test Action Group LAN Local Area Network LDO Low Drop Out LED Light Emitting Diode LPDDR Low power Double Data Rate LS Low Speed MAC Media Access Controller McBSP Multichannel Buffered Serial Port McSPI Multichannel Serial Peripheral Interface mDDR mobile Double Data Rate MDIO Management Data Input Output MII Media Independent Interface MIPS Million Instructions Per Second NC No Connect NTSC National Television System Committee

OMAP Open Multimedia Application Platform

OTG On The Go PAL Phase Alternating Line PCB Printed Circuit Board PGA Programmable Gain Amplifier PHY Physical Transceiver PLL Phase Locked Loop PMIC Power Management Integrated Chip POR Power On Reset


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PWM Pulse Width Modulator QFN Quad Flat Nolead RAM Random Access Memory RCA Radio Corporation of America RE Read Enable RoHS Restriction of Hazardous Substances RS Register Select RTC Real Time Clock RTO Real Time Out RTS Request To Send RXD Receive Data SD Secure Digital SDIO Secure Digital Input Output SDRAM Synchronous Dynamic Random Access Memory SIMD Single Instruction Multiple Data SMD Surface Mount Device SPI Serial Peripheral Interface SRAM Static Randam Access Memory TBD To Be Decided TDM Time Division Multiplexing TI Texas Instruments

TQFP Thin Quad Flat Package TSOP Thin Small Outline Package TSSOP Thin-Shrink Small Outline Package TXD Transmit data UART Universal Asynchronous Receiver Transmitter USB Universal Serial Bus ULK Unified Learning Kit ULPI UTMI+Low Pin Interface UTMI USB2.0 Transceiver Macrocell Interface VFBGA Very Fine Pitch Ball Grid Array VGA Video Graphics Array WE Write Enable # or n Active low signal

Note: Before using the ULK board, please refer to the Dos & Donts section.


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Functional Description

2.1 Board Architecture

The Block level architecture of the Mission 10x-unified learning kit is shown in Figure 1.

iWave Systems Technologies

TI OMAP3530

Spartan 6FPGA

Expansionconn(28pins)

FPGA Expansion

Conn

VideoDAC

UART Trans(x2)

PROM

JTAG

LEDs /Switch

ADC

DAC

16x2Char LCD

Mission 10x-unified learning kit

DDR2SDRAM(64MB)

UART Transceiver

NAND Flash(128MB)

MobileDDR (128MB)

RJ45 with Magnetics

MAC & PHY(Ethernet)

EEPROM(256Kb)

I2C to I/OExpander

Power regulators,Clock

& reset circuit

PMIC (TPS65930)(USB OTG Tx/Rx, Keypad, RTC, Audio)

16x2Char LCD

EthernetPHY

RJ45 with Magnetics

7 segmentLEDs (x4)

Oscillators10&100MHz

Keypad Conn(4x4)

HSUSB2

RTC

I2C1 I2C4 HSUSB0 McBsp2

SDRAMC

GPMC

MMC1

External Transceiver

MMC2

DSS[24:0]

Touchcontroller

McSPI1

Bluetooth & Modem Conn

CAM[7:0], I2C2

UART1 &3

UART2, McBSP1,I2C2

I2C2

McSPI3,CS _PWM(x4)

Simple digital IF(DB25 conn-5V)

MMC3

UART3

Mictor conn(38 pins)

USB HostULPI Phy

USB Type AConn

SD2 (X4bit)Conn

VGAConn

LCD conn(2x20=40 pins)

4pin header

Camera conn(34pins)

DB-9Conn

IrDA conn

SD1 (x4bit)conn

I2C header(GPS)

UART2, McBSP1,I2C2, MMC2

USB mini -ABConn

SpeakerBatteryConn

Headset Out

Class-D Amp

KeypadIF (6x6)

Level Tx-5V

Control sensorHeader

PWM, Mc SPI3/BSP1,I2C3

Level Tx-5V

I2C3

StereoAudio Jacksx2

StereoAudio Jacksx2

FPGA HDR220 pin Header

Level Tx-5V

DB-9conn

Major components related to processor

External Connectors

Major components related to FPGA

MMC3,UART2,BSP1

UART1 as GPIOs

Video outCVBS (RCA)

Level Tx-5V

USB OTG

DSS[17:0]

I2C3

Level Tx-3V

XDS510 JTAG

Mic

3.5 inchLCD Conn Level Tx-3V

DSS[24:0]

Level Tx3V

LEDs /Switch

Level Tx-3V

Figure 1: ULK board Architecture


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2.1.1 Board Features

The ULK board supports the following features

OMAP 3530 Processor

TIs OMAP3530 application processor with CUS package

TIs TPS65930 Power management IC

NAND Flash Memory of 128Mbytes

Mobile DDR SDRAM of 128Mbytes

Ethernet controller with 10/100Mbps PHY and RJ45 LAN connector

USB2.0 OTG interface

2no.s of SD interface

RS232 Console using UART1&3

Real Time Clock

VGA

CMOS sensor interface

24 bit RGB LCD interface

Mic in and speaker out

Touch panel controller through SPI interface

3.5inch LCD interface

I2C EEPROM of 256Kbits

IrDA support using UART3

Bluetooth & modem connector (3.3V compatible)

16x2 Character LCD using I2C to I/O bus expander

JTAG interface

6x6 Keypad interface (Using PMIC)

Simple digital interface with 5V compatible

Control sensor connector with 5v compatible

I/O Expansion connector as same as beagle board through level translators (1.8 to 3.3V/5V) for 3.3V & 5V compatible

One I2C,SPI & GPIO signals between processor and FPGA

GPMC bus between processor and FPGA

DIP switches & Status LEDs

Reset device and manual reset button

Single 5V Power Supply


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Spartan-6 FPGA

Xilinxs XC6SLX25T FPGA

SPI PROM from Atmel (2Mbyte)

DDR2 SDRAM of 64Mbytes

I2C EEPROM of 256Kbits

10/100Mbps ethernet PHY and RJ45 LAN connector

UART transceiver

4x4 Keypad interface

16x2 chracter LCD through parallel interface

10bit ADC with parallel interface

12bit DAC with parallel interface

JTAG interface

7 segment LEDs

DIP switches & Status LEDs

20-pin header with 5V compatible

70-pin I/O expansion connector


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2.2 ULK Board

Figure 2 and Figure 3 shows the TOP view & BOTTOM view of ULK board respectively.

2.2.1 TOP VIEW

GPS HEADERBLUETOOTH

CONN (3.3V)

SDI CONN

(5V)

USB OTG

CONN

RESET

SWITCH

5V

JACK

POWER ON/OFF

SWITCH

CONTROL

SENSOR

HEADER

SD2

CONN

IO EXP

CONN

16X2

CHAR LCD

PMIC

PROCESSOR

DB9 CONN

for FPGA

RIGHT

SPEAKER

LEFT

SPEAKER

FPGA

DDR2

SDRAM

NAND

FLASH

FPGA

IO

CONN (5V)

3.5 INCH

LCD

ADC

INPUT

MODE

SWITCH

FPGA

EXP

CONN

(3.3V)

EXTERNAL

LCD

CONN

CAMERA

CONN

VGA

CONN

7 SEGMENT

LEDs

EXTERNAL

TOUCH

CONN

RJ45 CONN

for FPGA

RJ45 CONN

for PROCESSOR

DAC

OUTPUT

DB9 CONN

for PROCESSORHEADSET

OUT

MIC

IN TV OUT

MDDR

DIP SWITCH for

PROCESSOR GPIOs

DIP SWITCH for

PROCESSOR BOOT

DIP SWITCH for

FPGA IOs

Figure 2: ULK board Top View


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2.2.2 BOTTOM VIEW

IRDA

CONN

SD1

CONN

6 X 6

KEYPAD

CONN

RTC

BATTERY

Figure 3: ULK board Bottom View


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Processor Interface The following sections briefs out each of the interfaces connected to the OMAP3530 processor on the ULK board.

3.1 NAND Flash interface

The 128Mbyte NAND flash (MT29F1G16ABCHC) from Micron is used to boot the OMAP3530 processor in 16-bit mode. It uses 16-bit bus to transfer data, addresses, and instructions. The five command pins (CLE, ALE, CE#, WE#, RE#) used to implement the NAND flash command bus interface protocol. The OMAP3530 processor interface with NAND flash block diagram is shown in Figure 4 & schematics is shown in Figure 5.

OMAP3530WE#

NAND Flash(128MB)

ALE

RE#

GPMC_ALE

CLEGPMC_CLE

GPMC_CS0#

GPMC_WE#

GPMC_OE#

GPMC_WAIT R/B#

CE#

IO[15:0]GPMC_D[15:0]

GPMC_WP# WP#

Figure 4: OMAP3530 with NAND flash interface


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Figure 5: NAND Flash circuit schematic

3.2 Mobile DDR interface

The mobile DDR device will be configured through SDRAM controller subsystem of OMAP3530 processor. The 128 Mbyte mobile DDR (K4X1G323PD-8GC6) from Samsung will be operating at 166MHz speed with CAS latency of 3. The device is configured in 32Mx32 organization with 13 row address (A0-A12) lines and 10 column address lines (A0-A9) and total bank of 4. The OMAP3530 interface with Mobile DDR SDRAM is shown in Figure 6 & schematics is shown in Figure 7.


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OMAP3530Mobile DDR

(128MB)

CK

CS#

SDRC_CLK

CK#SDRC_CLK#

RAS#SDRC_RAS#

CAS#SDRC_CAS#

WE#SDRC_WE#

SDRC_CS0#

CKESDR_CKE0

SDRC_DM[3:0]

SDRC_DQS[3:0]

SDRC_BA[1:0]

SDRC_A[12:0]

SDRC_D[31:0]

DM[3:0]

BA[1:0]

A[12:0]

D[31:0]

DQS[3:0]

Figure 6: OMAP3530 interface with Mobile DDR

Figure 7: Mobile DDR circuit schematic


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3.3 3.5inch LCD interface

The 24bit RGB Out signals and LCD control signals of OMAP3530 processor is taken out to interface with 3.5inch LCD. Since voltage levels of these signals are 1.8V, level translators are used to convert the 1.8V level signals to 3.3V level signals. TFT QVGA LCD KWH035ST12-F02 from Formike is used. The 3.5inch LCD interface is shown in Figure 8 & schematics is shown in Figure 9. Table 2 lists the 3.5inch LCD connector pin details.

OMAP35303.5inch

LCD Conn(54 pin)

DSS_HSYNC

DSS_PCLK

DSS_DE

DSS_VSYNC

Level Tx3.3V

Level Tx3.3V

DSS_D[15:0]

DSS_D[23:16]

DSS_HSYNC

DSS_PCLK

DSS_DE

DSS_VSYNC

DSS_D[15:0]

DSS_D[23:16]

Figure 8: OMAP3530 interface with 3.5inch LCD


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Figure 9: 3.5inch LCD circuit schematic

Table 2: 3.5inch LCD connector

Pin No. Signal Description Voltage level

1 VBL1- Back light LED ground 0V

2 VBL2- Back light LED ground 0V

3 VBL1+ Back light LED power 19.8V

4 VBL2+ Back light LED power 19.8V

5 Y1 Top electrode 3.3V

6 X1 Right electrode 3.3V

7 NC No connect

8 RESET Hardware reset 3.3V

9 SPENA SPI interface data enable 3.3V

10 SPCLK SPI interface clock 3.3V

11 SPDAT SPI interface data 3.3V

12 B0 Blue data bit 0 3.3V




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20 G0 Green data bit 0 3.3V








28 R0 Red data bit 0 3.3V








36 HSYNC Horizontal sync input 3.3V

37 VSYNC Vertical sync input 3.3V

38 DCLK Data clock 3.3V

39 NC No connect

40 NC No connect

41 VCC 3.3V power

42 VCC 3.3V power

43 Y2 Bottom electrode 3.3V

44 X2 Left electrode 3.3V

45 NC No connect

46 NC No connect

47 NC No connect

48 SEL2 Input data format 3.3V



51 NC No connect

52 DE Data enable input 3.3V

53 GND Ground 0V

54 GND Ground 0V


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3.4 Touch panel interface

The SPI interface of the OMAP processor is used to communicate with serial interface based touch screen controller (TSC2046). The touch screen analog signals from the external LCD will be interfaced with touch screen controller through 4 pin 2.54mm pitch header. The touch screen analog signals from the 3.5inch LCD will be interfaced with touch screen controller through the 54 pin LCD connector itself. The 4-wire,12bit resolution, low voltage touch screen controller TSC2046IPWR from TI is used. The OMAP3530 interface with touch panel controller is shown in Figure 10 & schematics is shown in Figure 11. Table 3 lists the Touch panel connector pin details.

OMAP3530Touch controller

(TSC2046)

McSPI1_CS0

4Pinheader

X+

X-

Y+

Y-

McSPI1_SCLK

McSPI1_Din

McSPI1_Dout

3.5inchLCD conn

Figure 10: OMAP3530 interface withTouch panel

Figure 11: Touch panel circuit schematic.


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Table 3: 4 Pin Touch panel connector

Pin No. Signal Description

1 TP_X+ Left electrode

2 TP_Y- Bottom electrode

3 TP_X- Right electrode

4 TP_Y+ Top electrode

3.5 Audio interface

To support the Audio interface, the McBSP2 interface of OMAP3530 processor will be communicating with I2S interface of the PMIC. It supports 16bit linear audio stereo DAC & ADC (48, 44.1 & 32 KHz derivatives). Analog single ended Mic configuration will be supported for audio in support. For speaker output, class-D amplifier will be used externally to drive the speaker and for headset output the ac coupled headset will be interfaced with class-D predrivers of PMIC. Audio interface support for OMAP3530 processor is shown in Figure 12, Headset & Mic in schematic is shown in Figure 13 & Speaker out schematic is shown in Figure 14. Table 4 & Table 5 lists the MIC in & headset out connector pin details and Table 6 & Table 7 lists the Left & Right speaker out pin details respectively.

PMIC(TPS65930)OMAP3530

I2C1_SDA

I2C

I2C1_SCLK

I2C4_SDA

I2C4_SCLK

I2C

Mc

BS

P2

Mc

BS

P2

MCBSP2_CLKX

MCBSP2_FSX

MCBSP2_DR

MCBSP2_DX

Po

we

r

DC

&L

DO

VDD1,VDD2

VMMC1VPLL1

VDAC,VIO_OUT

Au

dio

Mic

Speaker

Class-DAmp

(TPA2010D1)

Mic_Main_P

Mic_Main_M

PreDriv-L

PreDriv-R

Stereo jack(SJ1-3535NG)

Figure 12: OMAP3530 interface with Audio


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Figure 13: Headset & MIC in circuit schematic

Figure 14: Speaker out circuit schematic


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Table 4: 3 Pin Stereo connector for MIC IN


1 GND Ground

2 MIC_IN Mic input

3 AUXR Auxiliary audio input right or Mic input

Table 5: 3 Pin Stereo connector for Headset OUT


1 GND Ground

2 PreD.Left Predriver Left Out

3 PreD.Right Predriver Right out

Table 6: 3 Pin Stereo connector for left speaker Out


1 GND Ground

2 OUTL+ Class-D amp speaker OutL+

3 OUTL- Class-D amp speaker OutL-

Table 7: 3 Pin Stereo connector for right speaker Out


1 GND Ground

2 OUTR+ Class-D amp speaker OutR+

3 OUTR- Class-D amp speaker OutR-

3.6 Ethernet controller interface

The 10/100 Ethernet controller (LAN9220) from SMSC is a peripheral chip that performs the functions of translating parallel data from the host controller into Ethernet packets. It supports both MAC and PHY transceiver. The variable voltage I/O signals of the LAN9220 accommodate lower voltage I/O signaling without the need for the voltage level translators. The GPMC controller of processor configured in non-multiplexed mode and interfaced with Ethernet controller. The OMAP3530 processor interface with ethernet controller is shown in Figure 15 & schematics is shown in Figure 16. Table 8 lists the RJ45 Ethernet connector pin details.


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OMAP3530

WR#

LAN9220

D[15:0]

INT

GPMC_D[15:0]

A[7:1]GPMC_A[7:1]

GPMC_CS3#

GPMC_WE#

GPMC_OE# RD#

CE#

GPIO

RJ45 Conn+Mag

TX+

TX-

RX-

RX+

LED2

LED1

25MHz

Reset Out# Reset#

Figure 15: OMAP3530 interface with Ethernet controller

Figure 16: Ethernet Controller circuit schematic


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Table 8: RJ 45 connector Pin Description


1 TXD+ Transmit data+

2 TXD- Transmit data-

3 RXD+ Receive data+

4 TXD-CT

Connected to 2.5V output of Ethernet controller 5 RXD-CT

6 RXD- Receive data-

7 NC No Connection

8 GND Ground

9 LED1+ Connect to VCC_3V3

10 LED1- Speed LED

11 LED2- Link/Active LED

12 LED2+ Connect to VCC_3V3

3.7 RS232 interface

The MAX3386ECPWG4 from Texas Instruments is a three driver and two receiver RS232 Transceiver. It is capable of running at data rates up to 250kbps. It has unique VL pin that allows operation in mixed logic voltage systems. Both driver in and receiver out logic levels are pin programmable through VL (1.8V) Pin. The UART3 signals (TXD, RXD) of OMAP3530 processor is used for debugging purpose. Since UART3 signals are multiplexed with IrDA signals, when IrDA interface is used, optional UART1 signals will be used for debugging interface. The DB-9 male connector is provided on the board. The OMAP3530 processor interface with RS232 transceiver is shown in Figure 17 & schematics is shown in Figure 18. Table 9 lists the RS232 connector pin details.

OMAP3530

RS232

Transceiver

(MAX3386)

UART3_TXD

DB-9

UART3_RXDU3_TXD

U3_RXD

UART1_RXD

UART1_TXD

U1_TXD

U1_RXD

Figure 17: OMAP3530 interface with RS232 interface


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Figure 18: RS232 interface circuit schematic

Table 9: DB-9 Male connector


1 NC No connect

2 RXD Receive data

3 TXD Transmit data

4 NC No connect

5 GND Ground

6 NC No connect

7 NC No connect

8 NC No connect

9 NC No connect

3.8 RTC interface

The PMIC TPS65930 contains an RTC to provide clock and timekeeping functions and an EPC to provide battery supervision and control. It also implements backup mode in which backup battery can keep the RTC running to maintain clock and time information even if main supply is not present. RTC provides the following basic functions:

Time information (seconds/minutes/hours) directly in binary-coded decimal (BCD) code

Calendar information (day/month/year/day of the week) directly in BCD code


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Interrupt generation periodically (1 second/1 minute/1 hour/1 day) or at a precise time (alarm function)

32-kHz oscillator drift compensation and time correction

RTC interface is shown in Figure 19 & schematics is shown in Figure 20.


I2C1_SDAI2

C

I2C1_SCLK

I2C4_SDA

I2C4_SCLK

I2C

Po

wer

DC

&L

DO

VDD1,VDD2VMMC1VPLL1

VDAC,VIO_OUT

RT

C RTC battery(CR2032)

Figure 19: OMAP3530 interface with RTC interface

Figure 20: RTC interface circuit schematic

3.9 USB2.0 Host interface

The OMAP 3530 Processor of CUS package supports 2 USB host ports (HSUSB1 & HSUSB2) at high speed, full speed and low speed. The USB host port2 of OMAP3530 is interfaced with ULPI transceiver in high speed (480Mbps) operation with 8 bit mode. ULPI transceiver ISP1505ABS from NXP will be used to interface with USB host system of processor. It is offered in HVQFN24


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package. The OMAP3530 interface with USB2.0 host transceiver is shown in Figure 21 & schematics is shown in Figure 22. Table 10 lists the USB Type A connector pin details.

OMAP3530 ULPI Transceiver(ISP1505)

USB_ULPI_CLK

USB Type A

D+

D-USB_ULPI_DIR

USB_ULPI_STP

USB_ULPI_NXT

USB_ULPI_DATA[7:0]

19.2MHz

VBUS

Power Distribution

Switch

FAULT

+5V

EN

VINVBUS

Figure 21: OMAP3530 Processor USB Host Interface

Figure 22: USB host circuit schematic


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Table 10: Type A connector Pin Description

Note: Currently this interface is not supported in the Unified Learning Kit.

3.10 USB2.0 OTG interface

The OMAP 3530 Processor has high speed USB OTG subsystem HSUSB0 port. It operates either in USB host at high speed (480Mbps), full speed (12Mbps) and low speed (1.5Mbps) or in USB peripheral at high speed or full speed. The PMIC device includes USB OTG transceiver with CEA carkit interface. USB host port0 (HSUSB0) of processor is interfaced with OTG transceiver (PHY) in high speed (480Mbps) through ULPI mode. When OTG configured as Host, the power to VBUS will be generated from charge pump circuit of PMIC chip (nominal 4.8V). The OMAP3530 processor interface with OTG transceiver is shown in Figure 23 & schematics is shown in Figure 24. Table 11 lists the USB OTG connector pin details.


I2C1_SDA

I2C

I2C1_SCLK

I2C4_SDA

I2C4_SCLK

I2C

US

B

OT

G

HSUSB0_DIR

HSUSB0_CLK

HSUSB0_D[7:0]

USB Mini-AB(VSM-C-UMAB)

DP

DM

US

B

OT

GHSUSB0_STP

HSUSB0_NXT

Po

we

r

DC

&L

DO

VDD1,VDD2

VMMC1VPLL1

VDAC,VIO_OUT

PH

Y

ID

VBUS

Figure 23: OMAP3530 interface with OTG transceiver


1 VCC +5V (VBUS_HS)

2 D- Data-

3 D+ Data+

4 GND Ground


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Figure 24: USB OTG circuit schematic

Table 11: Type mini AB connector Pin Description


1 VCC +5V (VBUS_OTG or VCC_OTG)

2 D- Data-

3 D+ Data+

4 ID OTG ID signal


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5 GND Ground

3.11 VGA interface

The triple 10bit, 240MSPS speed video DAC (THS8135PHP) from TI will be used to convert the 24 bit digital parallel RGB signals into analog RGB signals to display in the VGA monitors through DB-15pin VGA cable. The Horizontal and vertical sync signals (Hsync, Vsync) of processor will be converted from 1.8 into 5V and will be given to VGA connector. The VGA interface is shown in Figure 25 & schematics is shown in Figure 26. Table 12 lists the VGA connector pin details.

OMAP3530Video DAC(THS8135B)

DSS_D[17:0]

VGA Conn(DB-15)

R

G

B

DSS_PCLK

GPIO for blank

DSS_Hsync

DSS_Vsync

Level Tx-5V

Hsync

Vsync

Figure 25: OMAP3530 interface with VGA


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Figure 26: VGA interface circuit schematic

Table 12: 15 Pin VGA connector


1 Red Red Video

2 Green Green Video

3 Blue Blue Video

4 NC No connect

5 GND Ground

6 RGND Red Ground

7 GGND Green Ground

8 BGND Blue Ground

9 NC No connect

10 SGND Sync Ground

11 NC No connect

12 SDA I2C data

13 HSYNC Horizontal Sync

14 VSYNC Vertical Sync

15 SCL I2C clock


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3.12 I2C EEPROM interface

The 32Kx8 (256Kbits) serial electrically erasable PROM (24AA256-I/SM) from Microchip is used to interface with OMAP processor through I2C interface. It operates at either 100 KHz or 400 KHz clock. For VCC


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Chip select signals (CS0-4), SPI3, I2C3 and GPIO signals will be connected to FPGA for misc communication. To generate interrupt from FPGAProcessor (GPIO127) and ProcessorFPGA (GPIO126) two dedicated GPIO signals are used. The GPMC & other interface signals between FPGA and OMAP processor is shown in Figure 29 & schematics is shown in.Figure 30.

OMAP3530SPARTAN-6

FPGA

GPMC_ADV#_ALE

GPMC_BE0#_CLE

GPMC_CS[7:4]# mux with PWM

GPMC_WE#

GPMC_OE#

GPMC_A[26:17]

GPMC_A[16:1]/D[15:0]

GPMC_Wait[3:0]

GPMC_BE1#

GPMC_CLK

McSPI3_CS0,McSPI3_Dout

McSPI3_SCLK

McSPI3_Din

I2C3_SCLK;I2C3_SDA

GPIO126 for interrupt

GPIO127 for interrupt

Reset#

Figure 29: OMAP3530 interface with FPGA


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Figure 30: OMAP-FPGA interface circuit schematic

3.14 JTAG interface

The IEEE1149.1 JTAG interface is used for software and hardware debugging. The test emulation signals of processor EMU0 & EMU1 will be pulled high at POR to configure the initial scan chain of OMAP processor to TAP router-only mode. The 2.54mm pitch dual row (7x2) 14-pin header for XDS510 JTAG IF is used on the board. The OMAP3530 interface with JTAG is shown in Figure 31 & schematics is shown in Figure 32. Table 13 lists the JTAG connector pin details.


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ARM JTAG IF

OMAP3530 XDS510 JTAG

TCK

TDI

TRST

TMS

TDO

RTCK

EMU0

EMU1

Figure 31: OMAP3530 interface with JTAG

Figure 32: OMAP JTAG circuit schematic

Table 13: 14 Pin JTAG connector for Processor


1 TMS Test Mode Select 1.8V

2 TRSTn JTAG Test Reset 1.8V

3 TDI JTAG Test Data Input 1.8V

4 GND Ground

5 PD Presence Detect 1.8V

6 NC No Connect


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7 TDO JTAG Test Data Out 1.8V

8 GND Ground

9 TCK RET JTAG Test Clock Return 1.8V

10 GND Ground

11 TCK JTAG Test Clock 1.8V

12 GND Ground

13 EMU0 Emulation Pin0 1.8V

14 EMU1 Emulation Pin1 1.8V

3.15 MMC/SD1 interface

The MMC1/SD/SDIO interface of the OMAP3530 processor is configured in 4bit SD mode to interface with SD memory cards. It supports both 1.8V & 3V without external transceiver. To support the Card detect signal, the GPIO0 of PMIC is configured as input and interrupt to the processor will be given through Sys_nIRQ. The SD signals of OMAP3530 is interfaced with SD connector as shown in Figure 33 & schematics is shown in Figure 34. Table 14 lists the SD1 connector pin details.

OMAP3530

MMC/SD1_CLK

MMC/SD1_CMD

MMC/SD1_DATA0

MMC/SD1_DATA1

MMC/SD1_DATA2

MMC/SD1_DATA3

SD1 Connector(DM1AA-SF-PEJ )

GPIO for write protect

GPIO0

For CDPMIC

Sys_nirq

Figure 33: OMAP3530 interface with SD1


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Figure 34: SD1 interface circuit schematic

Table 14: SD1 Connector Pin Description


1 MMC1_DATA3 Data3 signal 1.8 or 3.3V

2 MMC1_CMD Command signal 1.8 or 3.3V

3 VSS Ground

4 VDD 3.3V

5 MMC1_CLK Clock signal 1.8 or 3.3V

6 VSS Ground




10 CD1 Card detect signal 1.8V

11 COM Ground

12 WP Write protect 3.3V

3.16 SD2 interface

The MMC2/SD/SDIO interface of the OMAP3530 processor is configured in 4bit SD mode to interface with Wi-Fi / Bluetooth cards. The SD signals of OMAP3530 is interfaced with SD connector through external transceiver SN74AVCA406DGGR from TI to support 1.8 & 3.3V cards. To support the Card detect signal, the GPIO1 of PMIC is configured as input and interrupt


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to the processor will be given through Sys_nIRQ. The SD2 signals of OMAP3530 is interfaced with SD2 connector through transceiver as shown in Figure 35 & schematics is shown in Figure 36. Table 15 lists the SD2 connector pin details.

OMAP3530

SD2_CLK

SD2_CMD

SD2_DATA[3:0]

SD2_Dir_DATA[3:0]

SD2_CLK

SD2_CMD

SD2_DATA0

SD2_DATA1

SD2_DATA2

SD2_DATA3

Card detect

SD2 Connector(DM1AA-SF-PEJ)

Transceiver(SN74AVCA406)

SD2_CLKin

SD2_Dir_CMD

1.8V 3.3V or 1.8V

GPIO1

For CDPMIC

Sys_nirq

Figure 35: OMAP3530 interface with SD2


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Figure 36: SD2 interface with transceiver circuit schematic

Table 15: SD2 Connector Pin Description


1 MMC2_DATA3 Data3 signal 3.3V

2 MMC2_CMD Command signal 3.3V

3 VSS Ground

4 VDD 3.3V

5 MMC2_CLK Clock signal 3.3V

6 VSS Ground




10 CD2 Card detect signal 1.8V

11 COM Ground

12 WP Write protect 3.3V


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3.17 Character LCD interface

The HD44780 based character LCD will be supported by using I2C3 interface of processor through I2C to I/O expander chip (MCP23017-E/SO) from Microchip tech. The chip will be configured by using I2C3. It operates in 1.8V. The 16x2 character LCD from oriole electronics will be used to interface with processor. The supply voltage range is 5V. Character LCD interface is shown in Figure 37 & schematic is shown in Figure 38. Table 16 lists the Character LCD connector pin details.

OMAP3530

D[7:0]

R/W

RS

Clock (E)

+5V

I2C to I/OExpander

I2C3_SDA

I2C3_SCL

INT_Out

Figure 37: OMAP3530 interface with Character LCD


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Figure 38: Character LCD circuit schematic

Table 16: 16 Pin Character LCD connector


1 VSS Ground

2 VDD Power (3.3V or 5V)

3 VL Power supply for LCD drive

4 RS Register selection

5 RW Read/Write selection

6 EN Starts data read/write

7 P_D0 Data bit 0

8 P_D1 Data bit 1

9 P_D2 Data bit 2

10 P_D3 Data bit 3

11 P_D4 Data bit 4

12 P_D5 Data bit 5


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13 P_D6 Data bit 6

14 P_D7 Data bit 7

15 LED+ Back light power (5V)

16 LED- Back light ground

3.18 TV out interface

The OMAP 3530 processor has in built display subsystem that support TV out in Composite video (CVBS) & Separate video (S-Video) formats. The TV display path includes the following modules: Display controller Video encoder Dual 10-bit DAC with video amplifiers The output data to the TV set are the analog composite data from the DAC. The following video standards are supported: NTSC-J, M PAL-B, D, G, H, I, N PAL-M PAL-N PAL-Nc TV out interface is shown in Figure 39 & schematic is shown in Figure 40. Table 17 lists the TV out connector pin details.

OMAP3530TV_VFB1

TV out (RCA jack)

TV_OUT1

Discrete components

Figure 39: OMAP interface with TV Out


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Figure 40: TV Out circuit schematic

Table 17: TV out connector (RCA jack)


1 TV_OUT1 DAC1 video output (Composite output)

2 GND Ground

3 GND Ground

4 GND Ground


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FPGA interface

4.1 DDR2 SDRAM interface

The DDR2 SDRAM controller will be implemented inside the FPGA. The DDR2 SDRAM (EDE5116AJBG-8E-E) from Elpida will be operating at 200MHz speed with CAS latency of 5. The device is configured in 8Mx16x4banks. The device will be configured either through DDR2 SDRAM controller supported by FPGA or through DDR2 controller which will be implemented in FPGA. The FPGA interface with DDR2SDRAM are shown in Figure 41 & schematics is shown in Figure 42. Table 18 lists the FPGA pin-out details.

FPGADDR2

SDRAM (64MB)

CK

CS#

DDR_CLK

DDR_CLK#

RAS#DDR_RAS#

CAS#DDR_CAS#

WE#DDR_WE#

DDR_CS#

CKEDDR_CKE

DDR_DQM0

DDR_DQS[0]

DDR_BA[1:0]

DDR_A[12:0]

DDR_DQ[15:0]

LDM

DDR_DQM1 UDM

BA[1:0]

A[12:0]

DQ[15:0]

LDQS

DDR_DQS[1] UDQS

CK#

Figure 41: FPGA-DDR2 SDRAM interface


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Figure 42: FPGA DDR2 SDRAM circuit schematic

Table 18: FPGA pin-out details for DDR2 SDRAM interface

FPGA Pin

No.

FPGA Signal Description

R3 M3_DQ0 DDR2 data0

R1 M3_DQ1 DDR2 data1

P2 M3_DQ2 DDR2 data2

P1 M3_DQ3 DDR2 data3

L3 M3_DQ4 DDR2 data4

L1 M3_DQ5 DDR2 data5

M2 M3_DQ6 DDR2 data6


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