MiniProject+ReversePresentations
1
Sr. No. Name Mini-Project Reverse Presentation 1 nidhi.patel 2 karan.shah 3 mehul.thakkar 4 aman.chanpura 5 swati.chavan 6 viren.bhalala 7 anudeep.j 8 megha.brahmbhatt 9 shailesh.kavar 10 himanshu.agrawal 11 nikunj.naliyapara 12 suhas.chaudhari 13 gaurang.pandey 14 parth.rpatel 15 govind.sharma 16 priyansh.bhimani 17 ajay.chauhan 18 sharvil.desai 19 sandip.gangani 20 shyamal.pampattiwar 21 abhay.chavda 22 tejas.dalal 23 meet.thacker 24 rabinkumar.yadav 25 mittal.patel 26 jayesh.patel 27 chirag.rathod 28 sureshkumar.kyatham 29 nipul.gami 30 mercy.christial 31 abhishekkumar.sahu 32 jaykumar.jasani 33 dixita.patel 34 chandrasekhar.lanka 35 jayesh.prajapati 36 gayathri.mohanlal 37 ankitkumar.savaliya 38 chintan.shah 39 moinbaba.shaik 40 ravindra.vadi 41 vishal.prajapati 42 chandrasekhar.naik 43 nidhi.padiya 44 alay.shah 45 rishi.shah Efficient code writing for FSM in verilog, Parameters and `define Strength Modeling and Advanced Net Definitions, Multiple driver resolution SPI Slave APB Slave GPIO Slave Event Queues in Verilog, Types of Verilog Simulators and their effect on simulation and simulation timing Procedural Blocks in Verilog, Blocking vs Non-blocking statements Timing and Delay Modeling in Verilog, Tasks and Functions Synthesis vs Simulation, Synthesizable and Non-synthesizable Verilog Constructs System Tasks and Compiler directives, Races in Verilog Verilog as a Verification language Memory Design in Verilog I2C Slave APB Master I2C Master GPIO Master SPI Master JTAG
-
Upload
hardik-trivedi -
Category
Documents
-
view
1 -
download
0
description
MiniProject+ReversePresentations
Transcript of MiniProject+ReversePresentations
Sr. No. Name Mini-Project Reverse Presentation1 nidhi.patel2 karan.shah3 mehul.thakkar4 aman.chanpura5 swati.chavan6 viren.bhalala7 anudeep.j8 megha.brahmbhatt9 shailesh.kavar
10 himanshu.agrawal11 nikunj.naliyapara12 suhas.chaudhari13 gaurang.pandey14 parth.rpatel15 govind.sharma16 priyansh.bhimani17 ajay.chauhan18 sharvil.desai19 sandip.gangani20 shyamal.pampattiwar21 abhay.chavda22 tejas.dalal23 meet.thacker24 rabinkumar.yadav25 mittal.patel26 jayesh.patel27 chirag.rathod28 sureshkumar.kyatham29 nipul.gami30 mercy.christial31 abhishekkumar.sahu32 jaykumar.jasani33 dixita.patel34 chandrasekhar.lanka35 jayesh.prajapati36 gayathri.mohanlal37 ankitkumar.savaliya38 chintan.shah39 moinbaba.shaik40 ravindra.vadi41 vishal.prajapati42 chandrasekhar.naik43 nidhi.padiya44 alay.shah45 rishi.shah
Efficient code writing for FSM in verilog,Parameters and `define
Strength Modeling and Advanced NetDefinitions, Multiple driver resolution
SPI Slave
APB Slave
GPIO Slave
Event Queues in Verilog, Types of VerilogSimulators and their effect on simulation and
simulation timing
Procedural Blocks in Verilog, Blocking vsNon-blocking statements
Timing and Delay Modeling in Verilog, Tasksand Functions
Synthesis vs Simulation, Synthesizable andNon-synthesizable Verilog Constructs
System Tasks and Compiler directives,Races in Verilog
Verilog as a Verification language
Memory Design in Verilog
I2C Slave
APB Master
I2C Master
GPIO Master
SPI Master
JTAG
