Minimum Systems and the PIC 16F84A Chapter Two Dr. Gheith Abandah1.

Minimum Systems and the PIC 16F84A

Chapter Two

Dr. Gheith Abandah 1

Outline

• Review of Memory Technologies• The PIC 16 Series• PIC 16F84A• The PIC 16F84A Memory• The Oscillator• Instruction Cycle• Power-up and Reset


Review of Memory Technologies


• Read Only Memory (ROM)• Random Access Memory (RAM): Read/Write• Static RAM (SRAM): Each cell is a simple flip-flop of

six transistors, CMOS, volatile• Programmable ROM (PROM): Each cell is one

transistor, MOS, non-volatile, plastic package.• Erasable PROM (EPROM): Each cell is one transistor,

MOS, non-volatile, erasable with ultraviolet light, ceramic package with quartz window.

Review of Memory Technologies – cont.


• Electrically EPROM (EEPROM): Each cell is one transistor with additional transistors for programming, MOS, non-volatile, erasable electrically (takes time), suffers from wear.

• Flash Memory: Each cell is one transistor, MOS, non-volatile, erasable electrically (takes time) in blocks, suffers from wear, popular.

The PIC 16 Series

Device Pins Clock Memory Features

16F84A 18 ≤ 20 MHz 1 K ROM68 B RAM64 B EEPROM

1 8-bit timer1 5-bit port1 8-bit port

16LF84A Extended supply voltage range

16F84A-04 ≤ 4 MHz


The PIC 16 Series



3 parallel ports,3 counter/timers,2 capture/compare/PWM,2 serial,5 10-bit ADC,2 comparators




The PIC 16 Series







PIC 16F84A


PIC 16F84A Architecture


The 16F84A Status Register

• C: Carry/Borrow’• DC: Digit Carry/Borrow’• Z: Zero• PD’: Power Down• TO’: Time Out• RP0: Register Bank Select• RP1, IRP: Not implemented


The 16F84A Memory


Memory Technology Size Features

Program Flash 1K x 14 bits10,000

erase/write cycles

Data (File Registers) SRAM 68 Bytes Retains data

down to 1.5 V

Data (EEPROM) EEPROM 64 Bytes10,000,000 erase/write

cyclesStack SRAM 8 x 13 bits

Program Memory and Stack


Configuration Word


Allows the user to define certain configurable

features of the microcontroller, at

the time of program download.

Data memory and Special

Function Registers


FSR: File Select Register for indirect addressing.

EEADR: EEPROM AddressEEDATA: EEPROM DataEECON1: Control; RD, WREN, WR, EEIFEECON2: 55H to AAH

The Oscillator


• It is necessary to provide the ‘clock’ signal.• The clock is a continuously running fixed

frequency logic square wave.• The overall speed of the microcontroller

operation is entirely dependent on this clock frequency.

• Higher frequency -> Higher Performance and higher power consumption.

Instruction Cycle


• The main oscillator signal is divided by 4 to produce the instruction cycle time.

Pipelining

• All PIC microcontrollers implement pipelining.• Pipelining fails when one instruction changes

the contents of the Program Counter.


Power-up and Reset

• At power-up, the Program Counter is forced to zero and the SFRs are reset so that peripherals are initially in a safe and disabled state.

• There is also a master clear input MCLR’.


Summary• The PIC 16 Series is a diverse and effective family of microcontrollers.• The 16F84A architecture is representative of all 16 Series

microcontrollers, with Harvard structure, pipelining and a RISC instruction set.

• The PIC 16F84A has a limited set of peripherals, chosen for small and low-cost applications. It is thus a smaller member of the family, with features that are a subset of any of the larger ones.

• The 16F84A uses three distinct memory technologies for its different memory areas.

• A particular type of memory location is the Special Function Register, which acts as the link between the CPU and the peripherals.

• Reset mechanisms ensure that the CPU starts running when the appropriate operating conditions have been met, and can be used to restart the CPU in case of program failure.


Minimum Systems and the PIC 16F84A Chapter Two Dr. Gheith Abandah1.

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Transcript of Minimum Systems and the PIC 16F84A Chapter Two Dr. Gheith Abandah1.