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© 2008 MindTree©2010 MindTree
IP Re Engineering – Challenges
© 2010 MindTree
Agenda
Introduction IP Re Use and Challenges
IP Re-Engineering Activities
Internal IP Vs Third Party IP
Challenges and solutions Challenges
Internal Vs External Team
Capabilities of the external Team
Solutions from MindTree IP ReD
CSoC Initiative
Conclusion
Slide 2
IP Re Engineering Challenges
© 2010 MindTree
Introduction
IP Reuse Time to MarketCostOptimized area, performance
IP Re-engineeringEngineering activities that are aimed to customize, port and make the existing
IP available for new designs
Challenges: Porting to different Technology libraries (Power, Performance) Verification/Validation/Proto type (Quality) Quality Documentation Support for different teams (internal/external)
Enablers: Standard processes/methodology/Framework for Reusable IP DevelopmentIP Qualification and VerificationChip IntegrationIP Distribution and support
Slide 3
© 2010 MindTree
IP Re Engineering Activities
Design Feature Enhancements, Functionality
modifications (fixing bugs) Optimizing the design for Power,
Performance, Area Interface/Bus modifications Making the design more
DFT/implementation friendly
Verification/Validation Verification Environment optimization
for coverage improvement Modifications to reflect and test the DUT
enhancements Methodology migration (e – SV; Legacy –
HVL)
Integration/Physical Implementation/Maintenance Validating the IP for Integration Flow validation Release / Version Control User Documentation/update
Slide 4
Design
Verification
Implementation
© 2010 MindTree
Internal IP Vs Third Party IP
Internal IP IP that were developed and used
within the organization
Standard based, proprietary
More visibility to the different designs in which the IP was used
Access to the design team and details of the design, environment
Legacy environment, custom tool flow and proprietary design components
Integration issues due to insufficient documentation and validation
Support from the IP owner to re-engineer the IP is possible
Third Party IPIndependent vendor developed
IP
Mostly Standard based
Lesser visibility to the different design scenarios in which the IP was used
Better user documentation possible as the IP is to be shared with different users
Good qualification process to be in place before the reuse
Support for customization from the vendor is key for success
Slide 5
© 2008 MindTree©2010 MindTree
Challenges and Solutions
© 2010 MindTree
ChallengesEngagement ModelsFlexi Pool
Support for global teams and local centers
Issue based support
Support for external customers Scalability &
Maintenance Peak requirements handling
Support for existing IP
Multiple Target Platforms (Proc, Bus, OS..)
ExecutionPlanning and Forecasting
Resource optimization (activities Vs resources)
Legacy and third party IP
Team Preparation (training)
Quality/ProcessProcess adherence
Different flow qualification (CAD)
Metrics collection and analysis
Benchmarking & Certification
Training
Reuse Targets Optimization (power, area,
Performance)
Multiple SoC Platforms
Bus interfaces, Processors
Key Challenges
© 2010 MindTree
Internal Team Vs Design Services Team..
More often the re-engineering or customization tasks are centered around Technology Migration, Bus interface modification
Targeting different SoC platforms, resolving integration issues
Improving the quality of the IP (Performance, Power, Area)
Optimization of the design and verification environment (coverage improvement for functionality, manufacturing etc.,)
Engaging a third party team for effective use of the resources and focused IP re engineering will result inCost savings due to the effective utilization of the team that
manages the IP enhancements and improvements
Enables the customer team to focus on the domain specific activities
Becomes a central team that supports different design teams
Serves as a common knowledge platform where the project experiences are fed back and made available for different teams
Slide 8
© 2010 MindTree
Capabilities of the Partner
Slide 9
• Optimized resource management• Access to third party IP• Handling Legacy IP• Legacy Environment and porting to new methodologies
• Handling multiple IP during peask requirements
• Frameworks that will result in productivity improvemets
• Process/Methodology definition• VIP, Solution Accelerators
• End2End implementation experience
• Multiple Cad Flow• SoC Platforms• Verification flow migration• Validation/emulation and SW validation experience
• IP Development Experience• Customization to suit different architectures (SoC, Processors, Internal Bus)
• Exposure to Integration challenges (HW and SW)
• Handling legacy IP • Good experience in Optimization
IP Developmen
t & Customizati
on
Complete design cycle experience
Flexible Execution
Models
Capability to develop
Frameworks
© 2008 MindTree©2010 MindTree
IP ReD
© 2010 MindTree Slide 11
Design/Verification IP Re-Engineering Life Cycle
Customer MindTreeDeliverables
Product / Requirements Specification
Knowledge BaseData BaseDocument Standards
Specification Understanding
Feasibilty AnalysisResource AllocationExecution PlanningReview & Approval
Functional SpecificationProject Execution Plan
Review & Approval
Documents
Detail DesignValidation Plan
S/ W Driver
Modification
RTLVerification Environment
Review & Approval Data Base
DesignVerification
EnvironmentValidation
Set Up
ASIC FEFlow
FPGA FlowReview & Sign-Off Logs & Reports
Quality CheckReview & Sign-Off Logs & Reports
ValidationIntegration (SOC / Full Chip)
DFTReview & Sign-Off Data Base
Audi
ting
Phas
eEx
ecut
ion
Phas
e
(Optional)Cust
omer
Pro
cess
& In
fras
truc
ture
Sup
port M
indTree Process & Infrastructure Support
Packaging & Sign-OffAcceptance & Sign-Off Data Base
Pack
agin
g Ph
ase
© 2010 MindTree Slide 12
Design/Verification IP Re-Engineering - Auditing
Tool-SpecificTool-Specific
Data Base Analysis
Env Analysis
Data Base Analysis
Env Analysis
Methodology Compliance
Methodology Compliance
Tool UsedTool UsedDesign
Documentation
Design Documentation
Limitation on Existing
Synthesis
Limitation on Existing
Synthesis
Integration Compatibility at
System level
Integration Compatibility at
System level
Feasibility analysis
Feasibility analysis
CustomerApproval
CustomerApproval
SOW / WBSSOW / WBS
Re-engineering
requirements
Re-engineering
requirements
Customer’s estimation on
time and resources
Customer’s estimation on
time and resources Approved
by customer
Approved by
customer
Existing DIP
Database
Existing DIP
Database
Execution Phase starts
Execution Phase starts
NoNo
YesYes
RTL Checks (Lint)
RTL Checks (Lint)
Logs & QoR Report
Logs & QoR Report
Verification Reports
Verification Reports
• Auditing:• IP Re-eng schedule and schedule
confidence• IP Re-eng effort estimate – leading to
WBS• Clearly defined Customers & MindTree
role in re-eng activity, Receivable and Deliverable
• Quality of deliverables
• Entry: • Customer Requirements• Latest Data Base of the IP• Standard Specification (Optional)
• Exit: • Approved Feasibility Report -
Effort, Scope, Schedule, Current Status
• IP Auditing Checklist
© 2010 MindTree Slide 13
Design/Verification IP Re-Engineering - Execution
Re-engineering Scenario Specific Activities
Re-engineering Scenario Specific Activities
Design Document
availability?
Design Document
availability?
Code Understanding
Code Understanding
Understanding the Design
Understanding the Design
Creating / Enhancing
Design Document
Creating / Enhancing
Design Document
Review & Customer approved?
Review & Customer approved?
PackagingPackaging
Re-Engineering
Requirements
Re-Engineering
Requirements
YesYesNoNo
NoNo
YesYes
• Execution:• Follow the guidelines for different
scenarios for re-eng and ensure less execution
• Different phases of execution - Design change, RTL Modification, Verification, Synthesis, DFT, STA, P&R
• Each phase is followed by an internal review and tracking
• Entry:• RTL Data Base• Feasibility Report and Guidelines• Customer Requirement
Specification
• Exit Criteria:• Re-Engineered IP Database• Updated design doc
© 2010 MindTree Slide 14
Design/Verification IP Re-Engineering - Packaging
• Packaging:• Supported by a well defined check-list
for each activity• Check IP Quality and Use version
control to track all the releases• Systematic bug tracking• Reviews and Sign-off at each stage• Package into MindTree or Customer
format• Post delivery support
• Entry:• Modified IP Database• Quality check metrics
• Exit Criteria:• Quality Passed IP packaged into a
MindTree or Customer format
Netlist(Optional)
Scripts Docs RTL
Detailed Design
Verification Plan
Test Plan
Com
pilation Script
ASIC Flow
Scripts
FPGA Flow
Scripts
© 2010 MindTree Slide 15
CSoC Infrastructure
© 2010 MindTree Slide 16
Advantages
Rapid Prototyping of SoC’s
Unified Platform from Architecture Exploration to System Development
Architecture Exploration
Virtual Prototyping
SoC Development & Verification
IP / SoC Validation
Seamless Software (Low Level Firmware, Middleware, Application) Development
GUI based Automation Framework
CSoC Uniqueness
Seamless Migration from AE, VPP, SoC Development to Prototyping
No Processor Dependencies
Adaptive Verification Environment
© 2010 MindTree Slide 17
Adaptive Verification Environment
© 2010 MindTree Slide 18
Validation Prototype
© 2010 MindTree Slide 19 © 2010 MindTree Limited
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