Mid Acd Fall2014-Solution

EE 628 UMT School of Engineering/ Department of Electrical Engineering Jameel Ahmad

Midterm Examination 1 Fall Semester, 2014

University of Management and Technology School of Engineering

Department of Electrical Engineering

EE 628: Advanced Circuit Design Midterm EXAMINATION January 2015 Jameel Ahmad

NOTE: No laptop computers, cellular telephones, Blackberries, Droids, iPods, iPads,

iPhones or any other types of smart phones or wireless devices are permitted during the conduct of this examination. Simple hand calculators can be used. Turn off all electronic equipment you have with you, save for the aforementioned simple (non-wireless) calculator. This is 120-minute, close book, close notes, close homework examination.

STUDENT NAME: ________________________________

(Please Print Clearly: First, Middle, Last)

STUDENT NUMBER: ________________________ (Student Identification Number)

LOCATION:

STUDENT SIGNATURE: _________________________________

Please hand in this header page with your examination solutions!

PROBLEM #1: _______ points out of a possible 25 points PROBLEM #2: _______ points out of a possible 25 points

PROBLEM #3: _______ points out of a possible 25 points

PROBLEM #4: _______ points out of a possible 25 points EXAM SCORE: _______

points out of a possible 100 points AVERAGE: ______ points out of a possible 100 points

CLASS RANK: out of students

DO NOT WRITE BELOW THIS LINE!

SOLUTION



Problem-1 (25 points) Part-A (10 points)

For transistor size given as ratio , a basic current mirror is shown below. The expression for Icopy

Often, in a given circuit, we need current sources and sinks. We can build them all out of a single current source. Using the same concept write expression for Iout4 for following current mirrors and sinks.

Solution:

Part-B (10 points)

1. Briefly describe the circuit function

SOLUTION



2. Draw the small signal model of the circuit and determine the voltage gain

Solution:

1. This is a source follower driven by a current mirror. The source follower or common drain amplifier provides a voltage gain close to unity, and often limited by the body effect. It can provide a large current gain and it is often used as a voltage buffer.

2. Small signal model of source follower is

rds1 and rds2 are in parallel. Rs1 = rds1 || rds2 || 1 gs1 Body effect is equivalent to a resistor 1/gs1 The equivalent model is further simplified to

SOLUTION



vgs1 = vin vout Writing Nodal equation

vout Rs1 = gm1(vgs1) = gm1(vin vout) Solving for voltage gain

Gs1=1/Rs1 Normally, gs1 is on the order of one-tenth to one-fifth that of gm1. Also, the transistor output admittances, gds1 and gds2 might be one-tenth that of the body-effect parameter gs1. Therefore, it is seen that the body-effect parameter is the major source of error causing the gain to be less than unity. Part-C (5 points) Without drawing small signal model, determine the gain of the diode-connected differential amplifier. Gain by inspection is often used by analog circuit designer.

3

1

31 3//1//

1 m

m

mm g

grorog

gGain

SOLUTION

Problem-2 (25 points)

In the single stage amplifier shown schematically in Figure 1, capacitance Cf in parallel with resistance Rf sets the bandwidth of the amplifier. Transistor M1, which likely has a larger gate aspect ratio (W/L) compared to transistor M2, operates in saturation. Channel length modulation and bulk-induced threshold modulation (body effect) can be presumed negligible in both transistors. (a) Assuming that the parallel capacitance is dominant, what is the 3-dB bandwidth of the amplifier? (20 points) (b) Does resistance Rss widen or narrow the circuit bandwidth? (5 points)

Figure-1

Solution:

For a dominant pole network possessing no finite frequency zeros, the 3-dB bandwidth is the inverse of the time constant associated with the dominant capacitance (in this case, capacitance Cf).The time constant is the product of Cf and the resistance seen by Cf. This resistance can be viewed as the parallel combination of circuit resistance Rf and the resistance, Vx /Ix, predicted by the small signal model as shown. KVL applied to the model at hand gives

SOLUTION

Figure-2 Small signal equivalent model of the circuit

Does resistance Rss widen or narrow the circuit bandwidth? Increasing Rss reduces Vx /Ix, and hence, increasing Rss reduces the net effective resistance seen by capacitance Cf. Accordingly, the time constant associated with capacitance Cf decreases, whence the bandwidth increases, albeit somewhat modestly (depending on the value of resistance Rf ) as Rss increases. Problem-3 (25 points)

Part-A

Determine the input impedance of the circuit at very high frequencies

(5 points)

SOLUTION

Solution Part-A

With a high voltage gain, the Miller effect may substantially lower the input impedance at high frequencies.

Part-B

Given the 3-stage amplifier

1) Determine the transfer function (5 points) 2) Determine the poles from the transfer function H(s). (5 points) 3) Determine the DC Gain (i.e. low frequency gain). (5 points) 4) Roughly sketch the Bode Magnitude Plot of H(s). (5 points)

Solution Part-B

1) Transfer function

2) 3 poles at

SOLUTION

3) DC Gain = (gmRD)3 by setting s=0 in H(s)

Bode Magnitude and Phase plot

Problem-4 (25 points)

Design the Common Source Amplifier stage of Fig. 3 for a voltage gain of 5, an input impedance of 50 k, and a power budget of 5 mW. Assume = 100 A/V2, VTH = 0.5V, = 0 (no channel length modulation), and VDD = 1.8 V. Also, assume a voltage drop of 400 mV across RS.

The word Design here means:

1. Determine the size of transistor e.g. (W/L ratio), (6 points) 2. Values of R1 and R2 for proper biasing, (6 points) 3. Transconductance gm for voltage amplification, (6 points) 4. Appropriate values of VGS such that transistor M1 operates in saturation and provides required gain

of 5. (7 points) 2 ; 12

Fig. 3

SOLUTION

324 Chapter 7 CMOS Amplifiers

R1

R2

V

R

DD

M 1

D

RS

outV

inVC1

R1

R2

V

R

DD

M 1

D

RS

outV

inVC1RG

R1

R2

V

R

DD

M 1

D

RS

outV

C2

(c)(a) (b)

inVC1RG

Rin

Figure 7.20 (a) CS stage with input coupling capacitor, (b) inclusion of gate resistance, (c) use ofbypass capacitor.

Thus, if the circuit is driven by a finite source impedance [Fig. 7.20(b)], the voltage gainfalls to

Av = R1||R2RG + R1||R2 RD

1gm

+ RS, (7.80)

where is assumed to be zero.As mentioned in Chapter 5, it is possible to utilize degeneration for bias point stability

but eliminate its effect on the small-signal performance by means of a bypass capacitor[Fig. 7.20(c)]. Unlike the case of bipolar realization, this does not alter the input impedanceof the CS stage:

Rin = R1||R2, (7.81)but raises the voltage gain:

Av = R1||R2RG + R1||R2 gmRD. (7.82)

Example

7.11Design the CS stage of Fig. 7.20(c) for a voltage gain of 5, an input impedance of 50 k,and a power budget of 5 mW. Assume nCox = 100 A/V2, VTH = 0.5 V, = 0, andVDD = 1.8 V. Also, assume a voltage drop of 400 mV across RS .

Solution The power budget along with VDD = 1.8 V implies a maximum supply current of2.78 mA. As an initial guess, we allocate 2.7 mA to M1 and the remaining 80 A toR1 and R2. It follows that

RS = 148 . (7.83)As with typical design problems, the choice of gm and RD is somewhat flexible so

long as gmRD = 5. However, with ID known, we must ensure a reasonable value for VGS,e.g., VGS = 1 V. This choice yields

gm = 2IDVGS VTH (7.84)

= 192.6

, (7.85)

SOLUTION

JAMEELHighlight

JAMEELHighlight

JAMEELHighlight

7.3 Common-Gate Stage 325

and hence

RD = 463 . (7.86)Writing

ID = 12nCoxWL

(VGS VTH)2 (7.87)gives

WL

= 216. (7.88)With VGS = 1 V and a 400-mV drop across RS , the gate voltage reaches 1.4 V, requiringthat

R2R1 + R2 VDD = 1.4 V, (7.89)

which, along with Rin = R1||R2 = 50 k, yieldsR1 = 64.3 k (7.90)R2 = 225 k. (7.91)

We must now check to verify that M1 indeed operates in saturation. The drainvoltage is given by VDD IDRD = 1.8 V 1.25 V = 0.55 V. Since the gate voltage isequal to 1.4 V, the gate-drain voltage difference exceeds VTH , driving M1 into the trioderegion!

How did our design procedure lead to this result? For the given ID, we have cho-sen an excessively large RD, i.e., an excessively small gm (because gmRD = 5), eventhough VGS is reasonable. We must therefore increase gm so as to allow a lower valuefor RD. For example, suppose we halve RD and double gm by increasing W/L by a factorof four:

WL

= 864 (7.92)

gm = 146.3 . (7.93)

The corresponding gate-source voltage is obtained from (7.84):

VGS = 250 mV, (7.94)yielding a gate voltage of 650 mV.

Is M1 in saturation? The drain voltage is equal to VDD RDID = 1.17 V, a valuehigher than the gate voltage minus VTH . Thus, M1 operates in saturation.

Exercise Repeat the above example for a power budget of 3 mW and VDD = 1.2 V.

7.3 COMMON-GATE STAGEShown in Fig. 7.21, the CG topology resembles the common-base stage studied inChapter 5. Here, if the input rises by a small value, V, then the gate-source voltageof M1 decreases by the same amount, thereby lowering the drain current by gmV and

SOLUTION

JAMEELHighlight

JAMEELHighlight

JAMEELHighlight

JAMEELHighlight

JAMEELHighlight

JAMEELHighlight

JAMEELHighlight

Mid Acd Fall2014-Solution

Documents

Transcript of Mid Acd Fall2014-Solution