Microwave Field-effect Transistors Theory- Design and Applications (3rd Edition)

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Microwave Field-Effect TransistorsTheory, Design, and Applications

Microwave Field-Effect Transistors is a memberof the Noble Publishing Classic Series. Titlesselected for Classic Series Membership areimportant works which have stood the test oftime and remain significant today. While manypublishers lose interest in old titles, NoblePublishing is proud to recognize classic worksand to revive their contribution.

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Microwave Field-Effect TransistorsTheory, Design, and Applications

byRaymond S. Pengelly

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Noble PublishingAtlanta

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Pengelly, Raymond S. (Raymond Sydney). 1948-Microwave field-effect transistors : theory, design, and

applications / by Raymond S. Pengelly. - 3rd ed.p. cm.

Includes bibliographical references (p. ) and index.ISBN 1-884932-50-91. Gallium arsenide semiconductors. 2. Metal semiconductor

field-effect transistors. I. Title.TK7871.15.3G3P46 1995621.381'32-dc20 95-51185

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Contents

Contents vPreface ixForeword xiBiography xv1 Introduction 1

1.1 Introduction 11.2 Semiconductor Theory 11.3 Intermetallic Compounds 51.4 Metal-Semiconductor Contacts 51.5 Semiconductor-semiconductor Contacts 101.6 Conclusions 13

2 GaAs FET Theory-Small Signal 152.1 Introduction 152.2 Materials for MESFETS 162.3 Operation Principles of the Schottky Barrier MESFETs 172.4 The Dual Gate FET 582.5 Conclusions 732.6 Bibliography 73

3 GaAs FET Theory-Power 793.1 Introduction 793.2 Principles Of Operation 803.3 Modeling GaAs FET To Predict Large Signal 833.4 Predictions Of Non-linear Performance 913.5 Intermodulation Performance 943.6 Power FET Device Performance 993.7 Power FET Results 1203.8 Conclusions 1213.9 Bibliography 121

4 Requirements and Fabrication of GaAs FETs 1274.1 Introduction 1274.2 Material Requirements 1274.3 FET Fabrication Techniques 1624.4 Conclusions 1704.5 Bibliography 170

5 The Design of Transistor Amplifiers 1775.1 Introduction 177

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VI

5.2 Low Noise Small Signal Amplifiers 1775.3 Example of Narrow Band Amplifier Design 1915.4 Example of a Broadband Amplifier Design 1945.5 Designing an Amplifier For Optimum Noise Figure 1995.6 Broadband Amplifier For Minimum Noise Figure 2035.7 Computer-Aided Design Practice 2125.8 CAD Example 2205.9 The Use Of Single Ended And Balanced Amplifiers 2265.10 Variations In Amplifier Performance 2285.11 Designing an Amplifier for a Specified Linear Output 2305.12 Feedback, Active Matching and Travelling Wave 2315.13 Power Amplifiers 2615.14 Narrow Band Power FET Amplifier Design 2685.15 Broadband Power FET Amplifier Design 2685.16 Maximum Spurious Free Dynamic Range Amplifiers 2715.17 Power Combining Techniques 2725.18 Thermal Considerations In Power Amplifier Design 2735.19 Pulsed Operation Of Power FETs 2745.20 Reflection Amplifiers 2775.21 Conclusions 2815.22 Bibliography 281

6 FET Mixers 2876.1 Introduction 2876.2 The GaAs FET As A Mixing Element 2876.3 Experimental Results on Gate Mixers 3006.4 Noise Figure 3036.5 Signal Handling of FET Mixers 3106.6 Further Mixer Configurations Using Single Gate FETs 3126.7 The Dual Gate Mixer 3156.8 Image Rejection Mixers 3176.9 Frequency Up-Conversion Using Dual-gate FETs 3206.10 Frequency Multiplication 3206.11 Conclusions 3266.12 Bibliography 329

7 GaAs FET Oscillators 3337.1 Introduction 3337.2 Induced Negative Resistance 3347.3 S-Parameter Mapping 3367.4 Oscillator Design 3397.5 Free-running Oscillators-Performance Review 3457.6 Stabilized Oscillators 3597.7 Dielectric Resonators 3617.8 Dielectric Resonator Stabilized FET Oscillators 3687.9 Electronic Tuning Of GaAs FET Oscillators 3757.10 Varactor Tuned FET Oscillators 3787.11 Yig Tuned GaAs FET Oscillators 3867.12 Pulsed RF Oscillators 3927.13 Conclusions 395

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V l l

7.14 Bibliography 3968 FET and IC Packaging 403

8.1 Introduction 4038.2 Packages and Sealing 4048.3 Package Modeling 4078.4 Prematched GaAs FETs 4108.5 Packaging and Thermal Resistance 4148.6 GaAs IC Packaging 4188.7 Conclusions 4268.8 Bibliography 426

9 Novel FET Circuits 4299.1 Introduction 4299.2 Switches 4299.3 Phase Shifters 4399.4 Discriminators 4469.5 GaAs FET Osciplier 4509.6 Pulsed Oscillators 4519.7 Transformer Coupled Circuits 4549.8 Integrated Optoelectronic Circuits 4579.9 Conclusions 4619.10 Bibliography 462

10 Gallium Arsenide Integrated Circuits 46510.1 Introduction 46510.2 Monolithic Microwave Circuit Design 46610.3 Digital Circuits 49710.4 Technology of GaAs Integrated Circuits 52610.5 Integrated Circuit Examples 54510.6 Conclusions 61610.7 Bibliography 616

11 Other III-V Materials and Devices 62911.1 Introduction 62911.2 ThelnPMESFET 62911.3 ThelnPMISFET 63511.4 Ternary and Quaternary Compounds for MESFETs 63711.5 Permeable Base Transistor 64611.6 Ballistic Electron Transistors 65011.7 Heterostructure Transistors 65511.8 Traveling Wave FETs 67311.9 Conclusions 67711.10 Bibliography 678

Index 683

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Preface

The development of solid state active microwave devices can be consid-ered as beginning with refinements of the traditional p-n junction.Examples are the varactor and parametric amplification, the amplifyingand oscillating tunnel diode, and the amplifying and oscillating Impattdevice. Prior to the arrival of these devices and their associated circuittechniques, microwave systems utilized thermonic devices such as theklystron and the magnetron, or at the lowest microwave frequenciesminiature versions of the triode.

Thus the microwave system designer-in contradistinction to the lowfrequency system designer-was deprived of the system benefits of a twoport device. In the mid 1960s, the performance of the silicon bipolartransistor was extended into the microwave region giving for the firsttime the advantages of two port techniques.

The gallium arsenide metal semiconductor field effect transistor (MES-FET) has now largely replaced the bipolar transistor as the microwavetwo port active device and is used for linear and non linear analogue aswell as digital functions at frequencies in excess of 18 GHz. The recentlydeveloped combination of lumped circuit elements on the galliumarsenide chip is a potentially powerful technique.

This monograph describes the current state of the art and is written byRay Pengelly of Plessey Research (Caswell) Ltd. who heads arguably themost forward looking research team in Western Europe on this topic.

The work detailed in this monograph will be of great interest to micro-wave device, circuit and systems designers as well as people from outsidethis field.

C.S. Aitchison

Preface to the Second Edition

Since the publication of the first edition of this monograph there havebeen exciting developments in the use of MESFET devices in microwavecircuits. These arise from further developments in the use of monolithictechniques to produce monolithic microwave integrated circuits(MMICS) and also the use of the latest MESFET devices in the moretraditional microwave integrated circuits (MICS).

This, however, is not the end of the story: there have also been significantadvances in microwave digital techniques and we now find that circuitsoperating at bit rates of 15 GBit/sec are realizable.

The second edition is published at a propitious time since, at long last,the day has arrived when the mass production of microwave circuits athigh-street prices is required in the form of front ends for the receptionof direct broadcasting of domestic TV signals from satellites. It remainsto be determined whether traditional hybrid technology, perhaps withrobot assembly, will be preferable to monolithic techniques for thismassive market.

Research, development and production engineers working with devices,circuits and systems will find this monograph an invaluable professionaltool.

Colin Aitchison

Preface to the Third Edition

This is the third edition of Microwave Field-Effect Transistors—Theory,Design, and Applications, written by Raymond S. Pengelly in 1981.Although the industry has changed over the past 15 years, this book isstill a fundamental resource for all engineers involved in the develop-ment of solid state microwave devices.

Significant efforts were made to improve the layout quality of this book;reformatting a 700 page manuscript is quite a task. We decided to leavethe text material virtually the same. There are a few updates scatteredthroughout the book, and the computer sections found in chapter 5 havebeen modernized. However, since Noble Publishing considers this booka "classic," we thought it essential to preserve the original material.

Titles selected for Classic Series membership have stood the test of timeand remain significant today. Many publishers lose interest in old titles.Noble Publishing is proud to recognize classic works and to revive theircontribution. Each Classic Series title includes a biography of its author.I encourage you to read Mr. Pengelly's biography.

Crawford Hammond

Foreword

The field effect transistor (FET) at microwave frequencies using theIII-V compound gallium arsenide (GaAs) has been one of the mostexciting devices to emerge from the solid state microwave communityover the past twenty years. This device has reached operational frequen-cies of well over 30 GHz with the expectation that O.ljum gate lengthdevices will give acceptable performance to 50 GHz. The field effecttransistor has now become an established item in microwave systemsof today in such applications as low-noise amplifiers, mixers, oscillators,power amplifiers, switches and multipliers. Indeed many microwavesystems would not be possible at their present day performance levelsif it were not for the unique solution that the FET offers in providing areliable, reproducible and flexible device. In many cases costly paramet-ric amplifiers have been replaced with compact, low cost GaAs FET unitswhilst bulky traveling wave tubes with their associated large powersupplies are giving way to power FET amplifiers albeit at lower powerlevels of up to 100W or so. This monograph attempts to give a compre-hensive introduction to the theory, design and application of field effecttransistors with most emphasis placed on gallium arsenide-based de-vices. A theoretical review of both low-noise and power FET operationis given in Chapters 2 and 3 following an introductory chapter withexamples of the agreement between theoretical predictions and practi-cal results. The requirements and growth of GaAs are detailed inChapter 4 together with a review of the fabrication methods used toproduce the devices. Chapters 5, 6 and 7 give design information andaccompanying examples from within the microwave industry on theapplications of the FET to low noise and power amplifiers, frequencyconversion circuits and oscillators respectively. Chapter 8 contains areview of the means by which microwave transistors can be packagedhermetically whilst retaining acceptable performance. Chapter 9 dealswith the increasing use of GaAs FETs in circuit applications such asswitching and phase shifting. This chapter serves as an introduction tothe use of the field effect transistor as the vital active component forGaAs integrated circuits. Both monolithic microwave analogue anddigital circuits are covered involving both normally-on, depletion modeand normally-off, enhancement mode MESFETS. Chapter 10 reviewsthe technologies being adopted for both linear and digital integratedcircuits with examples of state-of-the-art circuits (in 1981). Alongsidethe exciting progress being made in GaAs IC's is the parallel activity ofthe improvement of basic FET performance and the extension of itsuseful frequency range by the use of other III-V compounds. The final

X l l

chapter (Chapter 11) deals with this subject introducing such materialsas indium phosphide, ternary and quaternary alloys, MISFETs andIGFETs and introduces the reader to the concept of the permeable basetransistor which is heralded as the successor to the FET.

This book has only been made possible by the extensive cooperationwhich the author has received from his colleagues worldwide, particu-larly those who have given permission for the publication of heretoforeunpublished material. The LE.E.E. is, in particular, acknowledged forits cooperation-operation.

I would like to thank, in particular, my colleagues at Plessey Research(Caswell) Ltd. who include R.S. Butlin, I.R. Sanders, A. Peake, J. Arnold,H.J. Finlay, M.G. Stubbs, J.R. Suffolk, C.W. Suckling, J.Singleton, J.R.Cockrill, S.G. Greenhalgh, K. Vanner, P. Cooper, J.A. Turner, D. Wilcoxand A. Hughes. Special thanks are due to J. Joshi for his contributionto the writing of Chapter 7 and J. Arnold for reading the final manu-script. The following colleagues amongst many have supplied informa-tion for which I offer my thanks: W.R. Wisseman, R. Pucel, D. Ch'en, D.Maki, P. Harrop. J. Oakes, R.Eden, K. Weller, H. Phillips, C. Liechti, H.Huang, M. Kumar, J.Magarshak, J. Mun, W. Kellner, H.Q. Tserng, R.Zucca and R. Zuleeg.

The considerable task of typing the manuscript was undertaken by Mrs.H. Barbour to whom I offer my grateful thanks. The line drawings andphotographs were prepared by Mr. K. Jenkins of Plessey Research(Caswell) Ltd/s report section for whose meticulous work I am greatlyindebted. I would also like to acknowledge the co-operation of Drs. G.Gibbons and J. Bass in making the preparation of this book possible andC. Aitchison for his detailed editing of the various chapters.

Foreword to the Second Edition

In the four years between 1981 and 1985, the performance and versatil-ity of microwave field effect transistors and integrated circuits fabri-cated on gallium arsenide and related compounds have increased at arapid rate. The GaAs FET has, during that time, been applied success-fully to, for example, low-noise receivers at 40 GHz with noise figures ofaround 3 to 4 dB. The high electron mobility transistor employing atwo-dimensional electron gas at the interface between GaAs and AlGaAslayers has achieved 3 dB noise figures at 60 GHz. Tremendous progresshas been made in the application of GaAs MESFETs in monolithicmicrowave integrated circuits in achieved performance, levels of inte-

Xlll

gration and frequency of operation. For example, single chip low-noisereceivers for low-cost satellite television have been produced at K-Bandwhilst single chip transmitter/ receivers have been demonstrated suc-cessfully at around 20 GHz. Equally impressive has been the dramaticincrease in the level of integration of digital GaAs ICs, particularly inthe area of static random access memories, reflecting the maturing ofthe technology base.

It is for amongst these reasons that this second edition has been written.Considerable alterations and additions have been made to the firstedition to up-date the contents although the general theme remains-thatof being a text which introduces the technology and applications ofmicrowave field effect transistors with extensive examples. All chaptersfrom the first edition have been updated and certain areas clarified.Chapter 5 contains new sections on traveling wave and feedback ampli-fiers whilst Chapters 10 and 11 have been essentially rewritten. Thelatter chapter carries information on the new modulation doped heteros-tructure FETs that have come to the forefront in performance terms overthe last few years.

Much of the contents of this second edition have only been made possiblethrough the cooperation which the author has received from his col-leagues worldwide. These are too numerous to list but I would like tothank, particularly: W.F. Wisseman, R. Pucel, Y. Ayasli, K. Honjo, S. Hori,H. W. Tserng, N.T. Linh, M. Rocchi, T. Mimura, P.T. Greiling and R. Zucca.

I would like to offer special thanks to my co-workers at Plessey Research(Caswell) Ltd. who have contributed to this second edition. Theseinclude A.J. Hughes, R. Charlton, R.L. Tebbenham, I.G. Eddison, H.J.Finlay, J.R. Suffolk, P.D. Cooper, A.M. Howard, P. Saul, D.M. Brookbanks,T.B. Bambridge, A. Lane, J. Jenkins, R. Arnold, C.Saint, K. Jenkin andC.H. Oxley.

I would like to acknowledge the permission of Procurement ExecutiveDCVD, Ministry of Defence to publish various new sections of thisedition which describe work performed under their sponsorship.

The preparation of the text has been a joint experiment between twoword-processors and I am grateful to Mrs. H. Barbour for interpretingmy word-processor output and transferring it to the final version with-out losing her sanity. I would also like to acknowledge the cooperationof Drs. George Gibbons and John Bass in making the preparation of thisedition possible and to Colin Aitchison for surviving the editorship ofthe chapters.

Biography

Raymond Pengelly was born in Penzance, Cornwall, England in 1948.After studying at the Humphry Davy Grammar School he went toSouthampton University, England where in 1969 he obtained an HonorsBachelors Degree in Physics. From 1969 to 1972 he was employed as ascientist at the former Plessey Electronics Systems Research Divisionat Roke Manor, Romsey, Hampshire where he did research work in highdielectric constant microstrip circuits from L-Band to X-Band. In 1973he was awarded a Masters Degree in Electronics at SouthamptonUniversity and in that same year married his wife, Alexandra. Raycontinued to work at Roke Manor as a senior principal scientist where,together with advanced technology supplied by Plessey Central Re-search, he realized the world's first monolithic GaAs MESFET IC in1974. Until 1978 he was responsible for an expanding activity in theemployment of GaAs MESFETs in hybrid and monolithic low-noise andpower amplifiers at Plessey. During this time he gained a keen under-standing of systems' engineering having responsibility for leading pro-jects on advanced EW and IFF receivers. In 1978 he transferred fromRoke Manor to the Central Research Laboratories of the Plessey Com-pany at Caswell, Northampton, England where he managed the GaAsMMIC design department. He was responsible for the smooth transferof integrated circuit design rules and practices to the Plessey III-VGroup Ltd. as well as the development of advanced CAD and circuitconcepts for future generations of MMICs. Under Ray's guidance theGaAs MMIC department at Plessey Research grew to become worldfamous. During this time, after several years of development, thedepartment produced one of the world's first phased array radar trans-mit/receive modules to be put into a demonstration system.

In 1986 Ray was employed by Tachonics Corporation in Princeton, NewJersey where he was Executive Director of Design for analog andmicrowave GaAs MMICs. He emigrated from England with his wife andthree children in late 1986. Tachonics was one of the first companiesworldwide to successfully offer "off-the-shelf' GaAs MMIC products andintroduced a range of GaAs MMIC switches and amplifiers. He joinedCompact Software, Paterson, New Jersey in 1989 as the Vice Presidentof Marketing and Sales, where he was responsible for marketing ofstate-of-the-art computer-aided design tools to the RF, microwave andlightwave research, development and manufacturing industries. He

XVI

was also responsible for defining enhancements to software products aswell as the specifications for new CAD products including schematic andlayout editors integrated to linear and nonlinear circuit simulators.

Since 1993 Ray has been employed by the Raytheon Company inAndover, Massachusetts as MMIC Design and Product DevelopmentManager for one of the world's largest groups of MMIC designers. Hehas managed the successful introduction of a Central Design Group, atthe Advanced Device Center, which is responsible for both military andcommercial MMIC designs as well as transitioning those designs tovolume production.

He has published a large number of papers particularly in the areas ofFET modeling and GaAs integrated circuits winning the 1979 EuropeanMicrowave Conference Prize for his paper on the application of dual-gateFETs to frequency discriminators. He has served on the TechnicalProgram Committee of Military Microwaves and the European Micro-wave Conference, is a past Chairman of the Institution of ElectricalEngineers' Professional Group (E12), is a Fellow of the Institution ofElectrical Engineers, is a Senior Member of the Institution of Electricaland Electronic Engineers, a member of the editorial board of the IEEETransactions on Microwave Theory and Techniques and a member of theIEEE MTT-S Technical Committee on Computer-Aided Design. He isthe editor of two reprint volumes" Advanced FET Technology" and "CADof Devices Circuits and Systems".

Ray has three children. His eldest son, Timothy, is taking a Bachelor ofFine Arts at the Savannah College of Art and Design. His second son,Robert, is at the University of New Hampshire majoring in Civil Engi-neering. His daughter, Demelza, is a High School student in Salem, NewHampshire. His hobbies include home improvements such as buildinga full-basement, photography and computing. Ray and his family livein rural Windham, New Hampshire sharing their home with 6 cats anda dog.

Introduction

1.1 Introduction

A monograph on microwave field effect transistors would be incompletewithout an introductory chapter on basic semiconductor theory. Thus,this chapter gives a basic review of energy bands in solids and introducesthe reader to the concepts of intrinsic and impurity semiconductors andmetal-to-semiconductor contacts.

1.2 Semiconductor Theory

For many years the energy levels of electrons in solids have been treatedin discrete bands separated by gaps in which ordinarily no energy levelsoccur.

The band structure of occupied energy levels of electrons in solids havebeen extensively investigated by using X-ray emission spectroscopy.When the crystal structure of the solid is bombarded by high-energyelectrons, electrons are ejected from the innermost part of the atom thusallowing transitions to take place between the outer and inner atomicshells. Such transitions give rise to narrow discrete spectroscopic lines,except for certain lines that are broader due to the transition of certainouter electrons which have a range of energies.

In ionic crystals, such as NaCl, there are two energy bands occupied byelectrons where one energy band is due to the outer electrons of thepositive ion and the other to the outer electrons of the negative ion. Invalence-bond crystals, such as diamond, only one energy band exists andthis is attributed to the electrons in the valence bond.

The band structure of unoccupied energy levels has been investigatedby the use of X-ray absorption spectroscopy. When the crystal is irradi-ated by X-rays at certain frequencies there are more or less abrupt jumpsin the absorption spectra. This is because the X-ray quanta bringelectrons from one of the inner shells to unoccupied levels of the crystal.The minimum energy needed is that needed to transfer the electron froma given shell to the lowest unoccupied energy level of the crystal.

Microwave Field-Effect Transistors

Ionic crystals and valence-bond crystals have their highest occupiedenergy levels several electron volts lower than the highest unoccupiedenergy level. In metals no such difference, or gap, exists. In the firstmaterials if an electric field is applied to the crystal the electrons in anoccupied energy band, separated from the lowest unoccupied energyband by a gap of several electron volts, cannot gain energy from the fieldbecause there are no unoccupied energy levels to which they can go. Inmetals, however, there are unoccupied energy levels in the immediatevicinity of the occupied levels and hence electrons gain energy from theapplied electric field and move through the crystal quite freely.

If the energy gap, Eg, is less than 2 electron volts (eV), the material is agood insulator at low temperatures but becomes a conductor at elevatedtemperatures since some of the electrons can gain enough energy fromthe crystal lattice vibrations to reach the unoccupied energy levels. Thenumber of electrons that can do this varies as exp(-eEg/kT) where k isBoltzmann's constant and T is the absolute temperature. Accordinglythe conductivity increases rapidly with increasing temperature. Suchmaterials are called Semiconductors.

The band of unoccupied energy levels is called the Conduction Band.The band of occupied energy levels in valence-bond crystals is called theValence Band. The bands in ionic crystals are named after the ionsresponsible for them. In insulators the conduction band is empty attemperatures below several hundred degrees centigrade, in semiconduc-tors the conduction band is empty at low temperatures, and in metalsthe conduction band is partly occupied continuously (Figures l.l(a),(b)).

If the energy gap, Eg, between the filled band and the conduction bandof an insulator is relatively small the material will be a good insulatorat low temperatures but at high temperatures the crystal will start toconduct. This happens because the electrons in the filled band and thelattice vibrations interact causing the former to gain enough energy totransfer from the valence band to the conduction band. Conductorshaving this property are referred to as 'intrinsic semiconductors' whereintrinsic means that the semiconducting characteristic is a property ofthe pure material. However, many materials become semiconductingdue to the introduction of impurities or deviations from stoichiometry.Such materials are called 'extrinsic semiconductors.'

Table 1.1 lists, for example, Group IV elements where the gradualtransition from insulating properties through semiconductor propertiesto metallic properties are shown.

Introduction

Empty (or conduction) bandFermi level

^F i l l ed (or valence) band^

(a)

Conductionband

(b)

Figure 1.1 (a) Energy Level Diagram of an Insulator at T=0 (b)Energy Level Diagram of a Metal at T=0

The current in semiconductors is carried by two types of carriers. Onetype is the electrons in the conduction band. For every electron in theconduction band there is an electron missing in the valence band. Thesevacancies are called lioles'. A hole acts in many respects like a positivecharge-it may move and gives rise to a current.

Semiconductors in which the current is carried predominantly by holesare called p-type semiconductors, whilst those in which the current iscarried predominantly by electrons are called n-type.

n-type or p-type semiconductors can be produced in ionic crystals byintroducing slight deviations from stoichiometry. Such materials arecalled excess or defect semiconductors. Valence-band crystals can bemade n or p-type semiconductors by the additions of impurities. Thesematerials are called impurity semiconductors.

Table 1.1 Energy Gap and Properties of Group IV Materials

ELEMENT

C (diamond)

Si

Ge

Sn (grey tin)

Pb

Eg(V)

7

1.1

0.7

very small

-

PROPERTY

Insulator

Semiconductor

Semiconductor

Semiconductor

Conductor

4 Microwave Field-Effect Transistors

If a semiconductor is at absolute zero with its valence band completelyempty together with its occupied energy levels only slightly below thebottom of the conduction band, then it is only necessary to increase thetemperature in order to raise the electrons in the occupied levels to theconduction band. Such levels are called donor levels. Because suchelectrons occupy fixed positions in the crystal they are referred to aslocalized.

If a semiconductor is at absolute zero with its valence band completelyfilled and its conduction band completely empty together with its unoc-cupied energy levels slightly above the top of the valence band, then itis only necessary to raise electrons from the valence band to theseunoccupied energy levels to leave behind free holes in the valence band.These unoccupied energy levels are called acceptor levels and they arelocalized.

In impurity semiconductors the donor or acceptor levels are provided byimpurities. The most notable semiconductors such as silicon and ger-manium exist in Group IV of the periodic table and, therefore, have acrystal structure like diamond where each atom has four outer electronswhich are shared by its four nearest neighbors to form a covalent typeof bond.

If impurity atoms from group V of the periodic table that have five outerelectrons are added (such as P, As or Sb) they take the place of some ofthe regular atoms of the lattice. Four of their outer electrons are usedto form the four covalent bonds with their neighbors leaving one looselybound electron behind. Such impurity atoms give rise to occupied donorlevels close to the bottom of the conduction band-thus the semiconductorbecomes n-type.

If impurity atoms from Group III of the periodic table (B, Al, In) areadded they also will take the place of some of the regular atoms of thelattice. Their three outer electrons are used to make three covalentbonds where the electron for the fourth covalent bond is missing-thus aloosely bound hole is left forming unoccupied acceptor levels close to thetop of the filled band; the semiconductor therefore becomes p-type.

The most useful property of such impurity semiconductors is that theirproperties can be very well controlled. The type of conduction dependson the kind of impurity added where the magnitude of the conductivitydepends on the concentration of the impurity atoms.

Introduction

1.3 Intermetallic Compounds

Semiconductors such as silicon crystallize in the diamond structurewhere each atom is surrounded by four like neighbors and the four outerelectrons of each atom form electron-pair (covalent) bonds with eachneighbor.

A similar structure exists in compounds of the AB type, where A is anelement from Group III and B is an element from Group V of the periodictable. Each atom of one type is surrounded by four neighbors of the othertype-the structure showing close similarity to the diamond structurebeing known as the zinc blende (ZnS) structure. These compoundsresemble the crystals of the group IV elements in that they are semicon-ductors. Since the constituent elements are metallic the compounds arecalled intermetallic compounds.

Having four electron-pair bonds around each A atom and around eachB atom requires the transfer of one electron from a B atom to an A atom.The A-B bond is not truly covalent but is partly ionic. This results in alarger forbidden gap width than would be expected otherwise. Forexample, if we compare Si with A1P formed by its neighbors in theperiodic table, we find that the gap width of A1P is 3 eV whereas Si isonly 1.1 eV. Table 1.2 lists some of the intermetallic compounds. Thecrystals can be made p-type by replacing some of the Group III atomsby Group II atoms or made n-type by replacing some of the Group Vatoms by group VI atoms.

Much of this monograph concentrates on the application of one of theseIII-V compounds, gallium arsenide (GaAs) to an active three terminalmicrowave device.

1.4 Metal-Semiconductor Contacts

When two materials are brought into contact, a redistribution of chargeoccurs, and finally a new equilibrium condition is reached in which theFermi-levels of the two materials are at equal heights, where the Fermilevel of an n-type semiconductor is given by

Ef=--E0+-kTln^- 1.1f 2 ° 2 Nc


Table 1.2 Properties of Some Intermetallic Compounds

Compound

InSb

InAs

InP

GaSb

GaAs

GaP

AlSb

Melting Point°C

523

936

1,070

720

1,240

-

1,080

Energy Gap at300°K eV

0.17

0.4

1.25

0.75

1.35

2.2

1.6

ElectronMobility,

10~4m2/Vsec

70,000

23,000

34,000

4,000

4,000

-

100

Hole Mobility1_0~4m2/Vsec

500

100

650

200

200

-

200

where k is Boltzmann's constant, T is the absolute temperature, Nd isthe donor concentration, Nc is the carrier concentration and Eo is thebinding energy of the electrons to the donors.

Owing to the redistribution of charge, a dipole layer will form at thecontact between the two materials. In a metal to metal contact the ohmiccontact is formed by surface charges on both sides of the contact andelectrons can move freely from one metal to the other. In a metal-semi-conductor contact, the contact may be either ohmic or rectifying; in thelatter case the current flowing more easily in one direction than theother.

Consider, for example, a contact between a metal and an n-type semi-conductor where the donor concentration in the semiconductor is rela-tively large with most of the donors ionized at room temperature. LetOm be the work function of the metal and Os the work function of thesemiconductor, where in general

•v 1.2

X being the electron affinity, i.e. the energy difference between thevacuum level and the bottom of the conduction band.

Consider the case where Om > Os. The situation prior to contact is shownin Figure 1.2(a) where the Fermi level of the semiconductor is above theFermi level of the metal by (Om-Os). On contact electrons from thesurface layer of the semiconductor enter the metal, leaving ionized

Introduction

Metal

Fermi Level

f|jjP

0m

.1

VacuumLevel

Fermi Level

(a)

Semiconductor

0s *s Cond. band

^Valence band

Metal

fermi level•t

n 'Xs

isemiconductor— - T —

* v d t m \

i (0s-Xs)

^ ^ F i l l e d b a n d

(b)

Figure 1.2 Energy-Level Diagrams of a metal n-type ConductorContact (with

donors behind in the surface layer. The Fermi levels of both materialsare at the same height after the exchange of charge which results in theenergy levels in the bulk semiconductor being lowered by (Om-Os). Apotential barrier is formed at the surface where, on the semiconductorside the height of the barrier is (Om—Os) and on the metal side thebarrier height is ($m-Os) + (Os-/S) = (Om~%s) (Figure 1.2(b)). The heightof the barrier (Om-Os) is often called the diffusion potential. Thepotential difference is maintained by the electric dipole layer at thecontact.

The positive charge at the semiconductor side of the contact is causedby ionized donors having a lower density than the ionized atoms in ametal. The donors being bound to fixed positions results in the positivecharge being distributed in a so-called space-charge layer. Because ofthe potential barrier at the contact this surface layer is also known asthe barrier layer.

Owing to the thermal agitation some electrons of the metal will haveenough energy to cross the potential barrier into the semiconductor andvice versa. In equilibrium this gives rise to equal and opposite currentsIo crossing the barrier.

Applying a voltage -V to the semiconductor (Figure 1.3) results in theenergy levels in the conduction band being raised by an amount eV, such


Metal

0m

Fermi-level

semiconductor

| Fermi level

eV

Figure 1.3 Effects of Applying Negative Voltage (-V) toMetal-Semiconductor Contact

that the barrier for electrons going from right to left is lowered by anamount eV. Consequently, the corresponding current from left to rightchanges by a factor exp (eV/kT). Since the barrier for electrons goingfrom left to right remains the current from right to left is unchanged.Thus, a current characteristic

I = I0(exp(—)—l) 1-3

results which is that of a rectifying or Schottky contact since for V»kT/eI is large and positive but for V«-kT/e the current is small andvirtually equal to -Io. The first condition is called forward bias and thesecond back or reverse bias.

If Om<<I>s no rectifying barrier is formed. Before contact the energylevels are as shown in Figure 1.4(a) where the Fermi level of thesemiconductor is below the Fermi level of the metal by the amount(O8-<Dm).

On contact electrons flow from the metal into the surface layer of thesemiconductor leaving a positive surface charge behind on the metal sideof the contact and, thus, causing a negative surface charge at thesemiconductor side of the contact. The Fermi level in the semiconductorbulk material is raised by an amount (<J>s-*m) (Figure 1.4(b)). Applyinga voltage V results in the potential difference being distributed acrossthe semiconductor as shown in Figure 1.4(c),(d). If (3>s-£s) is small theelectrons can move across the barrier relatively easily and for this

Introduction

Metal

Fermi level

Vacuumsemiconductor Metal

levelCond. band

Fermi level

^FMIedband

(a) Energy-level diagram before contact

Fermi level

(b) Energy-level diagram after contact

Metal semiconductor

Fermi level

Metal Semiconductor

(c) Contact with a negative voltage applied (d) Contact with a positive voltage appliedV,

Figure 1.4 Energy-Level Diagrams of a Metal n-type SemiconductorContact

reason the contact can be considered as ohmic (i.e. linearly resistive).Thus, a contact is ohmic if (Om<^)s) and Schottky (rectifying) if (Om>Os).

One would expect that if two metals are compared with different valuesof Om that the one with the largest Om would give the smallest value ofIo. This does not necessarily happen in practice since the semiconductorcan have a natural surface barrier. The way in which this can happenis that a large number of electron energy levels, the so-called surfacestates, are located at the surface of the semiconductor. Many of thesesurface states are occupied resulting in a distributed positive charge dueto the ionized donors in the surface layer. Making contact with metalsof different work functions, Om results in a different portion of the


Surfacestates

yjs^ Conduction bandFermi level

Figure 1.5 Energy-Level Diagram of an n-type Semiconductor withSurface States

occupied surface states being emptied into the metal-thus leaving thespace-charge barrier at the surface unchanged (Figure 1.5).

An ohmic contact can also be formed by alloying the metal and semicon-ductor together resulting in a gradual transition from the one materialto the other. This occurs, for example, if Ge-Au is alloyed to n-type GaAs.It can also be shown that if the donor concentration in the semiconductorsurface is above a certain critical value then an ohmic contact can beformed.

1.5 Semiconductor-semiconductor Contacts

If n and p-type semiconductors are brought into contact, electrons willflow from the n-type material into the p-type material until the Fermilevels are equal in height.

In practice such rectifying contacts are made by diffusing n-type impu-rities into p-type material or vice versa. The structure that results ispartly p-type and partly n-type; such a structure is called a p-n junction.Figure 1.6 shows the energy level diagram of such a junction in whichthere is a sudden change from p-type to n-type material at x = 0. Thereis a region of negative space charge for -xi<x<0 due to ionized acceptorsand a region of positive charge for 0<x<X2 due to ionized donors. The nregion has a positive potential with respect to the p region due to the

Introduction 11

n-region

Fermi level

Space chargeregion

X, X == 0 \

p-region

eVd

1

<2

Figure 1.6 Potential Distribution in ap-n Junction at Equilibrium

space charge region when there is no external bias. This potential iscalled the diffusion potential, Vd.

Assuming that the direction of positive current flow is from right to leftthere will be two equal and opposite current flows Ino under equilibriumconditions. The current flowing from right to left is caused by electronsmoving from the left to the right over the potential energy barrier ofheight eVd. The current flowing from left to right is caused by electronsgenerated in the p-region going downhill into the n-region. This lattercurrent does not change if an external potential V is applied to thep-region. However, the first current obeys an exp (eV/kT) law since thepotential energy barrier is lowered by an amount eV.

Consequently the characteristic is

1.4

A similar expression occurs for the hole currents.

If different semiconducting materials are grown one on top of the otheranother form of junction is formed. An n-type or p-type compound whengrown on another p-type or n-type compound of approximately the samelattice spacing forms a so-called hetero-junction. There are four possi-bilities, n-n, n-p, p-n and p-p junctions.


x2

zzrFermi level

Vacuum 1

t levef

02

0, X,

Fermi level

(a)

Fermi levelE [0,-X,

#

X1-X2_]

(b)

Figure 1.7 (a) Two n-type Semiconductors Before Contact (b)Heterojunction Formation After Contact

n-type VacuumrztFermi Level

Level

Fermi Level

(a)

n-type p-type

V/

(b)

Figure 1.8 (a) Ap-type and an n-type Semiconductor Before Contact(b) Heterojunction Formation After Contact

Introduction 13

For example, Figure 1.7 shows two n-type semiconductors with workfunctions Oi and O2 (where O2 < $1 and #2 < %\)> On contact, electronsflow from semiconductor 2 to semiconductor 1 until the Fermi levelheights are the same (Figure 1.7(b)). There is now a potential barrier ofheight %\— X2 on the side of the semiconductor 1 and a barrier of height<J>i—O2 on the side of semiconductor 2. Such a contact can be shown tobe rectifying.

Figure 1.8 shows a p-n junction where the work functions of the n andp-type semiconductors are Oi and $2 respectively (O2 >Oi). On contact,electrons flow from the n-type to the p-type semiconductor, leavingionized donors behind on the n side of the contact and ionized acceptorson the p side. As the gap widths are different there is no match at thecontact between the bottoms of the conduction band or the tops of thevalence band. Even so this contact is also rectifying.

1.6 Conclusions

This first chapter has introduced the reader to a number of concepts andterminologies associated with semiconductor theory. Some of the follow-ing chapters will expand considerably on the basic concepts presentedabove and show in particular the importance of the metal semiconductorSchottky contact in relation to the microwave field effect transistor.

GaAs FET Theory-Small Signal

2.1 Introduction

Over twenty years ago the first gallium arsenide transistors which useda diffused-gate structure were reported by Turner et al (1967) givinguseful gains in the lower megahertz frequency bands. In 1969 Middel-hoek realized a silicon Metal Semiconductor Field Effect Transistor(MESFET) with a ljum gate length by projection masking which had amaximum frequency of oscillation of 12 GHz (Middelhoek, 1970a, b).This was comparable to the maximum frequency of oscillation, fmax, ofthe best bipolar transistors at that time.

In 1971 a significant step was made by Turner et al, when l/*m gatelength FETs on GaAs were made having fmax equal to 50 GHz and usefulgains up to 18 GHz.

The substantial improvement in FET performance over the siliconbipolar transistor is due mainly to two reasons:-

1. In gallium arsenide the conduction electrons have a six timeslarger mobility and twice the peak drift velocity of those in silicon(Ruch et al, 1970).

2. The active layer is grown on a semi-insulating GaAs substratewith resistivity larger than 107 Q cm. This compares with a typicalvalue of 30 Q cm for intrinsic silicon.

The first property results in lower parasitic resistances, larger transcon-ductances and shorter electron transit times.

The second property results in lower gate-bonding pad parasitic capaci-tance when the gate pad is on the semi-insulating (SI) substrate.

By the early 1970's it was clear that the gallium arsenide MESFET couldbe used in low noise amplifiers up to X-band and Leichti et al (1972)reported a noise figure of 3.5 dB with 6.6 dB associated gain at 10 GHz.

A scanning-electron micrograph of a typical low noise FET is shown inFigure 2.1.


Figure 2.1 Photograph of Typical 0.5jum Gate Length MESFET(Courtesy-Plessey)

2.2 Materials for MESFETS

Besides Si and GaAs, InP has been investigated as a substrate forMESFET fabrication. InP has a 50 percent higher maximum driftvelocity than GaAs (Lam et al, 1971; Fawcett et al, 1974). The frfor InPFETs is therefore expected to be higher and indeed Barrera et al (1975)has measured fr's which are 1.6 times larger than in GaAs. However,the maximum frequency of oscillation, fmax is 20 percent lower. Also,degenerate feedback resulting from a larger gate-to-drain capacitanceand a smaller output resistance degrade the overall microwave perform-ance. Further details of InP FETs are contained in Chapter 11.

A field effect transistor requires a semiconductor having large mobility,large maximum drift velocity and a large avalanche break-down field.This means that the electrons must have a small effective mass, and thematerial must have a large intervalley separation as well as a largeenergy gap. However, a large energy gap implies a large electroneffective mass. Materials which are closer to the ideal in this respectthan either GaAs or InP are the so-called quaternary crystals such as

GaAs FET Theory-Small Signal 17

InAs-InP and InAs-GaAs (Fawcett et al. 1969; Glicksman et al, 1974).Further details of such materials are examined in Chapter 11.

2.3 Operation Principles of the Schottky Barrier MESFETs

The first part of the analysis of the operation of the Schottky barrierFET deals with the characteristics of the silicon device such that thedifferences between Si and GaAs can be outlined especially in relationto short gate lengths.

Figure 2.2(a) shows the current-voltage relationship of a thin n-typesilicon layer in which the electrons are carrying the current and wherethe layer is grown on an insulating substrate. Ohmic contacts, thesource and drain, are fabricated on the surface of the conducting layer.A cross section of the device is shown in Figure 2.2(a) where bandbending at the free surface of the n-type layer and the depleted regionat the substrate-layer interface are neglected.

Applying a positive voltage Vbs between drain and source causes elec-trons to flow. For small values Of VDS the layer appears to be a linearresistor, but as larger voltages are applied the electron drift velocity doesnot increase at the same rate as the electric field, E (Ruch, 1972). Thecurrent-voltage relationship therefore falls below the initial 'resistor'line. As VDS is increased further E reaches a critical value, Ec at whichthe electrons reach a saturation velocity, vs as shown in Figure 2.3-cor-respondingly the drain to source current saturates.

By adding a metal-to-semiconductor contact between the source anddrain, the so-called gate, a layer is created in the semiconductor whichis depleted completely of free-carrier electrons depending on the barrierheight between the gate stripe and the n-type layer (Figure 2.2(b)). Thisso-called depletion layer has the same action as an insulating layerrestricting the current flow in the n-layer. The width of this depletionregion is related to the voltage applied between the gate and the sourceelectrodes. By connecting the gate to the source as in Figure 2.2(b) thedepletion layer will have a finite width and the conducting channelbeneath has a smaller cross section d than in Figure 2.2(a)-the sourceto drain distance being larger.

The drain to source current, IDS, can be determined by considering a'sheet' of charge (of dimension W by d(x)) moving at the drift velocityv(x), thus

IDS=Wqn(x)v(x)d(x) 2.1


Source Drain

^Ohmic contact

-n-type GaAs

substrate

(a) Current — Voltage relationship of a thinn-type GaAs layer

i Source

r~i i—]

d

Gate

1 1

7//,

- Depletion layer

(b) Gated thin n-type layer with V^ = C\

do

7ZZZZZ/ZZZ/ZZA

X,

(c) Gated thin rvtype layer with V K = V«

No Gate

No Gate

Figure 2.2 (a). Current-voltage relationship of a thin n-type GaAslayer (b). Gated thin n-type layer with VGS = OV (c). Gated thinn-type layer with VDS = VDSAT


s/ZZZZZZZZZZZ d,>do

Xo X, X*X»

I I II I I

Constant n Constant Vn = No V s VSAT

(d) Gated thin n-type layer with Vos > VQSAT

/ZZZ//ZZZZ////

(e) Gated thin n-type layer with VM and Vos < a

No Gate

Figure 2.2 (d). Gated thin n-type layer with VDS > VDSAT (e). Gatedthin n-type layer with VDS and VGS < OV


Figure 2.3 The Equilibrium Electron Drift Velocity in Si and GaAs

where W is the gate width (Figure 2.6), q is the electronic charge, n isthe density of conduction electrons, v is the electron drift velocity, d isthe conducting layer thickness and x is the distance from the source todrain. The electron density n is equal to ND, the doping density, forvalues of field E less than the critical value, Ec.

The metal-to-semiconductor junction becomes increasingly reverse bi-ased from the source towards the drain with a corresponding wideningof the depletion region. Since the device is taking constant currentthrough the channel region the electric field increases as the channelregion narrows and there is therefore a related increase in electronvelocity, v. Increasing the drain voltage results in the electrons reachingtheir maximum limiting velocity, vs at the drain end of the gate. This isshown in Figure 2.2(c) where the channel is restricted to a cross-sectiond0 at the drain end of the gate. By increasing the drain to source voltagebeyond VDSAT the depletion region widens towards the drain contact andthe point xi where the electrons reach saturation velocity moves towardsthe source as in Figure 2.2(d). As xi moves towards the source the voltageat xi decreases and the conducting channel widens resulting in morecurrent being injected into the velocity-saturated region. The IDS curvehas a positive slope in this region with a finite drain-to-source resistancebeyond current saturation (Grebene et al, 1969; Lehovec et al, 1975).


Beyond xi the channel potential increases towards the drain wideningthe depletion layer with a corresponding decrease in the conductingchannel cross section to less than di. The electron velocity being satu-rated in this region results in a change in carrier concentration tomaintain constant current. Thus from equation 2.1 an electron spacecharge layer must form between xi and X2 where d < di. At X2, d—di andthe negative space charge becomes a positive space charge again topreserve constant current.

Electron velocity is still saturated between X2 and X3 due to the fieldadded by the negative space charge.

Now consider a negative voltage applied to the gate such that the gateto channel junction is reverse biased (Figure 2.2(e)). Under such condi-tions the depletion region becomes wider. Again under small values ofVDS the channel acts as a linear resistor-larger than in the previous casedue to the narrower cross section beneath the depletion region.

The critical field is reached at a lower drain current than when Vgs =0.

In gallium arsenide the analysis in the high-field region is more compli-cated than in silicon due to two reasons:-

1. The equilibrium electron velocity versus electric field reaches apeak value at 3 kV/cm, then decreases and levels off at a saturatedvelocity that is about equal to the limiting velocity in Si (Figure 2.3).

2. For gate lengths shorter than about 3/*m, a non-equilibriumvelocity-field characteristic has to be considered (Maloney et al,(1975)).

Various analytical solutions for the voltage-current characteristics ofshort gate length MESFETs have been developed. Many use a onedimensional analysis based on the gradual-channel approximation ofShockley (1952).

Considerable work has taken place in the development of accuratetwo-dimensional numerical solutions for GaAs and other materials (Moet al, 1970; Alley et al, 1974; Shur et al, 1978). *

Recently more emphasis has been placed on very short gate length GaAsFETs where the electrons do not reach equilibrium transport in the highfield region of the channel.

Experimental data and two dimensional calculations (Englemann et al,1976; Yamaguchi et al, 1976) show that the formation of a stationary


Gunn domain at the drain side of the gate (rather than a channelpinch-off) is responsible for the current saturation in GaAs MESFETs.

Current saturation is assumed to occur when the average electric fieldunder the gate reaches the Gunn domain sustaining field, Es:

2.2

where ju is the low field mobility.

2.3.1 Analytical Expressions For FET DC Parameters

Pucel et al (1975) has shown that the pinch-off voltage, Vpo, of a fieldeffect transistor is given by :

v = ^ u

P° 2sos

and the saturated drain current, ISAT, by:

2.3

2.4

where Vpo is the pinch-off voltage when the channel is completelydepleted of carriers, £0£ is the permittivity, A is the channel thickness, Lis the gate length and W is the gate width (Figure 2.4).

Substituting

-* L

Source |_ -u—* Gate

?VD

•* | Drain

JCH

!SUB

Figure 2.4 MESFET Geometry


q=1.6x 10~19C

fO = 8.85xl0~14F/cm

e = 12.5 for GaAs

and Vs=1.4 X 107 cm/sec into Equations 2.3 and 2.4 gives

V^ = 723NDA2 = Vp +VBi volts 2.5

and

ISAT=0224WNa amps 2.6

where N is in units of 1016cm~3, A is in^m and W is in mm.

The maximum channel current, Imax, is higher than the saturated draincurrent owing to a factor called the maximum channel opening factor,/?.

i-e-Imax^PhAT 2.7

Imax plays an important role in determining the maximum capability oflarge signal operation of the device. Parameter/? is given by

P ml-°J* ± 2.8H AN

Another approximate expression for Imax is given by

0J8NuA15Wlmax = -ToTs

Le

2 ' 9

where Le is the effective gate length, defined as the physical gate lengthplus an additional length accounting for depletion layer spread.

The zero gate bias channel current, Io, (often termed Idss) is given by

/, = r W 2.10

where

y ~l+o-yld+2o +o2 2.11

where


= Vbi+0.234L

and

a =0.0155^- 2 1 3

where Rs is the source series resistance.

Another approximate expression for Y is given by

2.14

2.15

Vc being a correction voltage which depends on the configuration of thechannel structure.

If any of the basic channel parameters, ND, A, or L is known, the othertwo can be calculated from known values of Vp, VBI and (Imax/W). Forexample, if the ND value is known, A is determined by using

A VP+VB' 9 1«

A = — wm 2.167.23ND

with a maximum channel opening factor of

(1= .12I^/W 2.17

r

L > Iwhere

Vpo'=Vpo+Vc

2yJ PO

Using this value of /?

L = 4.27(Vp+VBi)(l-p2) fim 2.18

For example, if Vp = -3V, Vbi = 0.7V, and ND = 1017 cm-3.

A , 3 + 07 I 3.7A =

7.23(10) \72.3


.-. A = 0.22/fm.

If Imax= 120 mA

= 4.27(3.7X1-079)2

= 0.72.19

If none of the three basic channel parameters (ND, A or W) are knownthen the secondary d.c. parameters are used to determine the basicchannel parameters.

If the zero gate bias channel current, Io (Idss), is known then by rearrang-ing equations 2.10 and 2.14 we can write

vp+vBi+v 1+ 1-jvp+vBi+vc-i

2.20

After calculating ISAT, ND and A can be determined from equations 2.5and 2.6 respectively, as follows:

°12

. } 'SAT 2.21

where ND is in units of 1016 cm"3 and

W= 0.03l{Vp+VBi)-

SAT

Using equation 2.19 with 2.9 gives

L = 4.27(Vp+VBi)[l-Imax/ISAT]2

jum

jUTCl

2.22

2.23

2.3.1.1 Determination of Gate Barrier Built in Voltage and IdealityParameter

Sze (1969) has shown that the forward current density, J, of a Schottkybarrier junction for V > 3 kT/q is approximately given by


2.24

where A* is the effective Richardson constant, T is the junction tempera-ture in °K, k is Boltzmann's constant, n is the ideality parameter and Vis the applied forward bias voltage.

The extrapolated value of current density to zero bias gives the satura-tion current density, JSAT. The barrier built-in voltage is then given by

2.25Q I JSAT

and the ideality parameter,

n = J.—IX— 2.26JcTdQnJ)

Fukui (1979) has given a method of determining various GaAs FETparameters by a series of d.c. measurements. The first of these is tomeasure the forward I-V characteristic of the gate junction at roomtemperature. A plot of gate forward-bias voltage, VG versus gate current,IG is then plotted. An example of such a plot is show in Figure 2.5. Athigh values of gate bias the gate current tends to saturate. At low valuesof VG, IG is often disturbed by a leakage current around the gateperiphery. In the middle range of VG, log IG versus VG is linear. Fromthe slope and location of this linear region it is possible to calculate theideality parameter, n, of the Schottky junction and the gate built-involtage, VBI, respectively.

2.3.1.2 VpO Determination

By measuring the drain I-V characteristics at low values of Ids a plot ofdrain current versus Vgs, gate-to-source voltage can be produced. Theterminal pinch-off voltage, Vpo can be determined by extrapolating theplot to the abscissa as shown in Figure 2.6.

2.3.1.3 Rs and Rn determination

The drain to source resistance RDS, at a very low drain to source voltage(say 50 mV) can be plotted as a function of a parameter X defined by


io-'

10-2

DU

Si

10"6

10"7

r-

-

-

- f

0.4

/

i

0.5

/

/

i

/

Aluminium gate atroom temperature

i i 1 i

0.6 0.7 0.8 0.9 1.0Gate forward-bias voltage (Vg, V)

Figure 2.5 Forward I-V Characteristic of an Aluminum Schottkygate diode at room, temperature

1-,-Vn

2.27

It should be pointed out that RDS is not constant with frequency. Thismay be due to electron trapping at the active layer-substrate interface(Camacho-Penalosa, 1985).

The plot will be a straight line provided the value of Vp previously foundis accurate. Figure 2.7 shows such a plot. By linearly extrapolating theline to the ordinate a value for the parasitic (gate to source and gate todrain) resistances, RS+RD, can be found. The slope of the line is Rowhereby RoX represents the effective value of the active channel resis-tance at a given VGS.


4

I3cu

rren

t,D

rair

0

-

-

i

0.4

\ . Vds= 0.05 volt

\

\ Vp= 0.36 volt

0.2 0 -0.2 -0.4 -0.6Gate bias voltage, Vgs(V)

Figure 2.6 Drain Current as a Function of Gate Bias Voltage forForward and Reverse Drain-Source Bias Conditions

Also by measuring the gate current versus gate to source voltage at highcurrent levels (VDS = 0 volt) with either the source and drain, or sourceonly, or drain only, connected to ground it is possible to determine Rs-RD.Thus because RS+RD is known from the experiment described above Rsand RD can be evaluated separately.

2.3.1.4 Transconductance determination

To a first order approximation the magnitude of the transconductanceof a FET device can be assumed to remain constant up to the cut-offfrequency, fr. The d.c. transconductance can, to a first order approxima-tion, be considered the same as the microwave transconductance.

The measured transconductance, gm(obs) is lower than the intrinsictransistor gm owing to the gate-to-source resistance, Rs. The intrinsictransconductance is given by

6m ~~8m(°bs)

l-gm(obs)Rs

2.3.1.5 Expressions derived from experimental results

2.28

Fukui (1979) has shown that it is possible to use basic FET channelparameters to calculate their d.c. parameters such as maximum channel


32

26

E

820

.55

u5812O

c

! •

4

_

-

-

-

//

U Rs+

-

10 2

>

//

//

///f

RD*5.5n

1 I

4 6

/

/

0

16

gT]"1

/ V p - 0.36 volt

n

i i

10 12

Figure 2.1 Derivation of the Open Channel Resistance, RoandParasitic Series Resistance Rs and RD.

current, Imax, zero-gate bias channel current, Idss and transconductancegm.

Further the built-in voltage of an aluminum gated Schottky barrier gatejunction at room temperature can be expressed by

VBi = 0706 + 0.06 log ND volt 2.29

where ND is in units of 1016 cm"3.

The small signal measured transconductance of a GaAs FET, gm(obs),agrees well with the predicted value using the expression


091

where Ich is the channel current.

The parasitic series resistance, Rs or RD, actually consists of the ohmiccontact resistance, Rco, of the source and drain contacts on the GaAsand the series channel resistance RDS between the source and draincontacts. The resistances have been separately expressed (Macksey andAdams (1975)) as

T T T

where pi is the specific resistivity of the GaAs layers under the sourceand drain contacts (regions 1-Figure 2.4), ai is the thickness of the GaAscontact layer, Lc is the length of the contacting metal electrode and Reis the specific contact resistance. Parameters pi, and Re are bothfunctions of the doping concentration, ND (in the simplest case thechannel doping and ohmic contact doping are equal). The doping de-pendence of p can be written in an analytical form as

p s 0.11 ND~0-82 ohm—cm 2.32

An empirical expression for Re has been found by Hewitt (1977) as

Rc s 4ND-°'5 x 10~5 ohm—cm2 2.33

The series channel resistance, RDS, can be divided into two components,one between gate and source, R2, and one between gate and drain, R3(Figure 2.4). i.e.

RDS = R2+R3 2.34

where

and


(Figure 2.4) 2.36

where L2 and L3 are the lengths of GaAs between gate and source andgate and drain. By substituting Equation. 2.32 and 2.33 into 2.31, 2.35and 2.36 we obtain

D 21co ~ JXT 05A 7 066 ohms 2.37

Wo,! ND

* 2 " ^ 7 ^ ohms 2-38

and

Rs ~ w ^oja ohms 2.39Wa3ND

In a common source connected FET the input signal is applied to thefeed point of the gate and then travels along the gate metallization tothe other end. At microwave frequencies the gate has to be consideredas a distributed network.

Wolf (1970) has analyzed the effective value of the gate metallizationresistance, Rg, at microwave frequencies as one third the-end-to-end d.c.resistance to a first order approximation

where pg is the specific resistivity of the gate metallization, Lg is the gatelength, cog is the unit gate width (i.e. the gate width per cell), t is the gatemetal thickness and Wg is the total device gate width.

Comparing values of pg, derived from measured values of Rg usingEquation 2.40 with the bulk resistivity of the gate metal usually pro-duces a factor of 2 increase. This has led to a practical expression for Rg

for aluminum gated FETs given by

R^ljr ohms 2.41


From the foregoing it can be seen that many of the basic device parame-ters of the FET, which also occur in the microwave equivalent circuit,can be derived from relatively simple d.c. measurements. Some of theparameters such as gm, Rg and Rs are particularly important in deter-mining the microwave performance of the FETs. It will be seen inSection 4B how these parameters determine FET gain, noise figure etc.

Table 2.1 indicates an example of the satisfactory agreement betweenexperimental data measured using the techniques discussed and thetheory given in the foregoing.

The depletion layer width d(x) (Figure 2.4) can be expressed as

Table 2.1 Measured and Calculated Parameters ofGaAs MESFETs

Symbol

Wg

OJg

n

VBi

vP

Vpo

•max

Idss

Ro

Rs

RD

RG

gm

gm (obs)

ND

L

ND

A

Units

mm

mm

V

V

V

mA

mA

ohms

ohms

ohms

ohms

mS

mS

1016cm"3

microns

1016cm"3

microns

MeasuredValue

0.5

0.25

1.46

0.74

1.15

1.89

79.0

29.3

4.00

2.70

2.70

13.7

33.0

30.0

CalculatedValue

2.35

2.35

35.1

3.52

0.57

3.51

0.37

EquationsUsed

2.20, 2.21

2.20, 2.23

2.23, 2.7, 2.21

2.16


d(x) = 2.42

where V(x) is the potential drop between points 0 and x (V(L)=Vi). Theelectric field at x is given by

E(x)*%- (=£,)

V(x)sE,(x)

Thus

2.43

d(x) =E,x+VBi-VG

2.44PO

Since the current is continuous under the gate d(x) E(x) = constant.

The total charge Q under the gate in the linear region when Vi < Vs isgiven by

Q = qNDw\Wd(x)dxJo

±r .1 . n2.45

since the channel current is expressed by

hh = ' ' 3 V 2vpo

where Vi is the voltage drop across the gate region (Figure 2.4), VBI isthe barrier height voltage and Vgis the gate voltage.

Since

vs*(vm-vG)Q = qNDAoWL 2.46


We are now in a position to derive expressions for the drain-to-gate andgate-to-source capacitances Cdg and Cgs using the simple equivalentcircuit of the GaAs FET shown in Figure 2.8.

-(Vi+vBi-vGy2.47

and

dVr, V

For the case where V i « VBI-

2.48

Gate R.o V W V -

VG ^= ?QmVG

Source

R, Drain•AAA/V °

=t=d.

Figure 2.8 Simplified Equivalent Circuit of GaAs FET


^dg ~ ^gs - T l T

2V2 i vBi-yG.

The cut-off frequency can be calculated to be/r^r-T1 2.50

For the case where Vi «(VBi~Va) this becomes

fr- T 2.51Jt L

so that fr « 25.5 GHz for a ]jum device. This agrees well with estimatesgiven by Englemann (1976) where

2 - 5 2

where Vp is a peak electron velocity.

The characteristic switching time of the GaAs FET is given by

'SAT

Using Equation. 2.46 and the fact that Ich can be approximated by

L Ao

Thus the switching time is proportional to the transit time under thegate and the saturation velocity determines the switching time.

We can therefore decrease the switching time and hence increase thecut-off frequency by making the gate shorter.


2.3.2 Small Signal Equivalent Circuit

A simple lumped element equivalent circuit is capable of modeling theFET's S-parameters up to 20 GHz (Wolf, 1970; Dawson, 1975; Vendelin,1976; Kuvas, 1980; Vendelin, 1975). The equivalent circuit of the GaAsMESFET when operating under saturated current conditions is shownin Figure 2.8 for the case where the FET is connected in common source.Figure 2.9 shows a diagram indicating the physical origin of the circuitelements.

In the intrinsic FET model, the elements (Cdg, + Cgs) represent the totalgate-to-channel capacitance; Ri and RDS show the effects of the channelresistance and ids defines the voltage controlled current source. Thetransconductance gm relates ids to the voltage across Cgs. The extrinsic(parasitic) elements are: Rs, the source resistance, RD the drain resis-tance, Rg, the gate metal resistance and Cds the substrate capacitance.Typical element values for a ljum gate length and 30Qum gate widthdevice are listed in Table 2.2. The extrinsic elements are those causedby the fabrication of the device not being ideal, for example Rs and RDare due to the contact resistances of the 'ohmic' source and drainelectrodes.

Ohkawa (1975) has shown that the equivalent circuit shown in Figure2.8 has a critical frequency fe above which the FET is unconditionally

Drain

Figure 2.9 Physical Origin of the Circuit Elements of the MESFET


Table 2.2 Equivalent Circuit Parameters of a Low Noise GaAs FETwith a ljum by 300jum Gate

Intrinsic Elements

gm = 30 mS

To = 3 pS

Cgs = 0.4 pF

Cdg = 0.01 pF

Cdc = 0.015 pF

Ri = 3 ohms

Rds = 500 ohms

Extrinsic Elements

Cds = 0.07 pF

Rg = 2 ohms

Rd = 5 ohms

Rs = 5 ohms

d.c. bias

Vds = 5V

Vgs = 0V

Ids = 50 mA

stable (Chapter 5 includes details of stability factor etc.). fe can beapproximated by

2JZ(TO+T1+T2)

where the transadmittance,

v = P e~~J(0T°

2.55

2.56

r,=-Cdg(2Rg+Ri

2.57

and

r 9 = -

gs

R

*ds2.58

The GaAs FET detailed in Table 2.2 has an fK of 5.7 GHz. Below thisfrequency the device becomes unstable since a larger fraction of the


output voltage is fed back to the input over the Cdg-Rin voltage dividerwhere

R 2 ' 5 9

i.e.

O)

and the feedback capacitance,

The device unilateral power gain can be defined as

A 2.60

where fu is the maximum frequency of oscillation. Now the frequencyfor unity current gain, fr, is given by Equation 2.50 and

bfer)where

0 = ^ — 2.62KDS

and

T3=2jtRgCdg 2.63

For example for the device of Table 2.2, fu, is 69 GHz. To maximize fu,the frequency fr and the resistance ratio Rds/Ri must be optimized. Inaddition the extrinsic resistances Rg and Rs and the feedback capaci-tance Cdg must be minimized. The maximum available gain at a fre-quency f of the FET is given by


)\ 2.64

where Ls is the inductance in the common source lead of the device.

Thus it may be appreciated that in order to increase MAG the value offr must be optimized whilst Rg, Rs and Cdg are minimized.

It has been found empirically for GaAs FETs having gate lengths ofabout l//m, that

40fu—~r (GHz) where L is in microns 2.65

Li

fmax is a figure of merit for the FET and is comparable to the figure ofmerit for the microwave bipolar transistor which is given by 40/S whereS is the emitter strip width and S is in microns. In the FET, f is directlyrelated to the saturated drift velocity, Vs, by equation 2.22 and it is forthis reason that GaAs is preferred to Si, since Vs is 1.4 x 107 cm sec"1

for GaAs whereas Vs is 8 x 106 cm sec"1 for Si.

2.3.3 Noise Theory Of GaAs MESFETs

The noise properties of a linear two port can be represented by anoiseless two port with noise current generators connected across theinput and output ports. This is particularly meaningful in the case ofthe MESFET, corresponding to noise sources at gate, source and drainas shown in Figure 2.10.

The noise-current generator at the output of the FET represents theshort-circuit channel noise generated in the drain-source path. Themean square of iND can be expressed (Van der Ziel, 1962) as

i =4KTAfgmP 2.66

where K is Boltzmann's constant

To is the lattice temperature

Af is the bandwidth

gm is the transconductance

P is a dimensionless factor depending on the device geometry andthe d.c. bias conditions.


Figure 2.10 Noise Equivalent Circuit ofGaAs MESFET

For zero drain voltage, iND2 represents the thermal noise generated bythe drain conductance, Gds. It can be shown that P=Gds/gm. For positivedrain voltages the noise generated in the channel is larger than thethermal noise generated by Gds, since:

1. A thermal noise voltage generated locally in the channel modu-lates the conductive cross section of the channel resulting in anamplified noise voltage at the drain.

2. The electrons are accelerated in the electric field and are scat-tered due to interactions with lattice phonons. Their random drift-velocities and the free-carrier temperature increase with the appliedfield to values considerably higher than the lattice temperature (socalled hot electron noise (Baechtold, 1971)).

3. In GaAs the carriers undergo field dependent transitions fromthe central valley in the conduction band to satellite valleys and viceversa. Such a transferred electron suffers a dramatic velocitychange. These transitions generate so-called 'intervalley-scatteringnoise' (Baechtold, 1972).

4. For large drain voltages, the electrons reach their limiting veloc-ity on the drain side of the channel. Thus this channel section cannotbe treated as ohmic. In this region the noise is analyzed as high-fielddiffusion noise (Van der Ziel, 1971; Statz et al, 1974). The mean


square value of the noise current is proportional to the high-fielddiffusion coefficient in the semiconductor.

Noise voltages generated in the channel cause fluctuations in thedepletion-layer width. The resulting charge fluctuation in the depletionlayer induces a compensating charge variation on the gate electrode.The total induced-gate charge fluctuation is shown in Figure 2.10 by anoise generator iNG at the gate terminal where

—7 co2cjRiNG

2=4KToAf ^— 2.67om

where R is a factor depending on the FET geometry and the biasconditions. For zero drain voltage, R~gmRi.

Since the two noise currents iNG and iND are caused by the same noisevoltages in the channel partial correlation can be expected. A correlationfactor C is defined as (Van der Ziel, 1963)

jC= to'hm^ 2 6 8ATM?

where j is the imaginary unit and the asterisk denotes the complexconjugate.

C is purely imaginary since iNG is caused by the capacitive coupling ofthe gate circuit to the noise source in the drain circuit.

The minimum noise figure for the intrinsic MESFET can be expressedby

Fmin =7 + 2^P/?(7-C2)^ + 2g m ^pf7-C^Y^j 2.69

For actual GaAs MESFETS, however, this expression is no longereffective. With an exhaustive treatment using the equivalent circuit ofFigure 2.10, Pucel et al (1975) obtained an expression for the minimumnoise figure as:


^Kg[Kr+gm{Rg+Rs)]

2.70

where

K =R{l-C2)

['-egand

K =

where Rg is the gate resistance; Rs is the source series resistance and gm

is in Siemens.

In Equation 2.70 Rg and Rs are parasitic and remain unchanged undernormal operating conditions.

2.3.4 Minimum Noise Figure Of The GaAs FET

Consider the case where the FET is operating at a frequency below itscut-off frequency at room temperature.

A simple expression for the minimum noise figure, Fmin, can be foundfrom the equivalent circuit elements of the device from Equation 2.70.

4* RQ -3XlO

&2.71


where Kf is a fitting factor approximately equal to 2.5 representing thequality of the channel material. Essentially Equation 2.71 is a specialcase of Equation 2.70 where R=0 and or C=l neglecting higher orderterms. Since

2nCgs

Equation 2.71 can be rewritten as

2.72

TTAlso since ft- is related to the gate length L (see Equation 2.78) we have

2.73

where Ki ~ 0.27 when L is in microns.

Consider Table 2.3 where the parameters of five GaAs FETs are shownfor the purposes of noise figure calculations. These devices had opti-mized gate recess structures (see Chapter 4) and as a result the effectivegate length reduces to the physical length of the gate metal when thegate is rectangular in cross section on a planar channel. Parameterssuch as L, gm, Rg and Rs can be measured using the method of Fukui(1979a).

The predicted and the measured values of Fmin for these FETs shown inTable 2.4 are in excellent agreement when measured at a frequency of6 GHz (i.e. approximately fr/3). Equation 2.73 shows that a short gatelength is essential for low noise figure as well as the minimization ofparasitic resistance Rg and Rs by paralleling gate fingers, increasing gatemetallization thickness and reducing ohmic contact resistances. Thiscan be most conveniently achieved by narrowing the unit gate widththrough a gate paralleling scheme even though there is an increasedfabrication complexity.

From the circuit design viewpoint the GaAs FET can be treated as ablack box of noisy two ports. The noise properties of this black box canbe characterized by the use of four noise parameters (Rothe et al, 1956).A variant of this expression gives


Table 2.3 Design Parameters ofGaAs MESFETs used for NoiseCalculations

Parameter

Symbol

L

Lg

L2

L3

h

ND

N I

N2

N3

a

ai

a2

a3

W

Wi

Units

^m

//m

/urn

jum

jum

1016/cc

1016/cc

1016/cc

1016/cc

fim

//m

ywm

^m

mm

nm

Device

1

0.9

0.9

1.0

0

0.5

7

7

7

-

0.3

0.3

0.17

-

0.25

0.24

2

0.9

1.2

0.75

0.4

1.0

40

200

200

4

0.27

0.15

0.12

0.27

0.25

0.23

3

0.5

0.8

0.75

0.3

0.65

8

200

200

8

0.15

0.15

0.12

0.15

0.25

0.14

4

0.5

0.8

0.75

0.3

0.65

8

200

200

8

0.15

0.15

0.12

0.15

0.1

0.14

5

0.25

0.4

0.4

0.2

0.4

18

200

200

18

0.1

0.15

0.12

0.1

0.065

0.065

Table 2.4 Comparison of the Predicted Value of Minimum NoiseFigure for the Devices having the Parameters of Table 2.3 with theMeasured Values

Parameters

Symbol

Predicted

Measured

Fmin

Fmin

Fmin

Units

dB*

dB**

dB

Device

1

1.72

1.77

1.75

2

1.8

1.85

1.76

3

2.12

2.18

2.22

4

1.56

1.62

1.51

5

1.7

1.76

1.74

using Equation 2.83 ** using Equation 2.88


'min —R0P + X0P

2.74

where

Fmin is as previously defined

Rn is the equivalent noise resistance

Rss is the signal source resistance

ROP is the optimum signal source resistance

Xss is the signal-source reactance and

XOP is the optimum signal source reactance.

In this expression Fmin, Rn, ROP and XOP are the characteristic noiseparameters of the device.

As explained in Chapter 5 Equation 2.74 can be represented on thesource impedance Smith Chart as a family of circles each of whichcorresponds to a constant value of F.

A small Rn is essential for a device to be used in a broadband amplifierwhere a large tolerance is required in the input match. Furthermore,the smaller the value of Rn the higher the gain in a given gate structure.

The four noise parameters can be expressed as

{Rg+Rs)

Jom

8m 2.75

2.76

2.77

where Ki, K2, K3 and K4 are fitting factors.


Figures 2.11 to 2.14 show the fits obtained for six different FET struc-tures having different channel carrier concentrations, gate lengths andchannel thicknesses.

Good fits are obtained for values of

Ki = 0.016 K3 = 2.2

K2 = 0.03 K4 = 160

Where Rn, ROP, XOP, Rg and Rs are in ohms, gm in mhos and Cgs inpicofarads with f in gigahertz.

In order to design a GaAs FET conveniently it is advantageous to haveexpressions for gm, Cgs and fi\

We have already seen that the maximum frequency of oscillation isapproximately related to the gate length L by Equation 2.65. Similarly

fr_103gm_9A

2nCa

8m=l

= — GHz

mhos

pFr2ll

2.78

2.79

2.80

0.80.7

0.6

| 0.5LL

0.4

0.3y

2

> ^

o

3

fCgs[(Rg + Rs)/(

4

o

5 6

Figure 2.11 Correlation Between the Minimum Noise Figure Fminand Equivalent Circuit Elements CgS, gm, Rs, and Rg (after Fukui)


200

100

70

g 50c 40* 30

20

1010 20

gm(n

30

125)

40 50 60

Figure 2.12 Correlation Between the Equivalent Noise Resistance Rn

and the Transconductance gm (after Fukui)

where ks and k6 are found to be 0.02 and 0.34 respectively.

Figure 2.15 and 2.16 show the agreement between the measured valuesof gm and Cgs and the empirical results of Equations 2.79 and 2.80.

Simplified expressions for the gate metallization resistance Rg and thesource resistance Rs can be found as

17W/8 hLW

7060

50

a •£ 30

20

ohms

7 10 20V4 gm + Rg + Rs (12)

2.81

30

Figure 2.13 Correlation Between the Optimum Source ResistanceRQP and Equivalent Circuit Elements Rg, Rs and gm


200

100

70

a>! ^

30

2 0 0.5 0.7 1

Cgs(pF)

2 3

Figure 2.14 Correlation Between the Optimum Source ReactanceXOP and the Gate-to-Source Capacitance CgS.

and

5 W2.1 LlLsg

(a-as)ND0.82 ohms 2.82

where h is the gate metallization thickness in microns,

LSg is the distance between source and gate in microns,

as is the depletion layer thickness in microns at the surface in thesource-gate gap and

Wi is the unit gate width for a multi-parallel gated FET.

GaAs FET Theory - Small Signal 49

t

60

50

40

30

20

100.7 1

^ ^ No

W:

2

W ( N 0 / a L p

1016

im

mm

cm~3

3 4

Figure 2.15 Transconductance gm as a Function of ChannelParameters

Figure 2.16 Gate-Source Capacitance as a Function of ChannelParameters W, L, a and ND


2.3.5 Practical Equations for Noise Parameters

We cam now substitute Equations 2.78 to 2.82 together with the fittingfactors k l , k2, k6 into Equations 2.73, 2.75,2.76, 2.77 giving

Fmin =1 + 0.038/NnL

5

ITWi | 2J | 1JLsg

hL066

\a — as)ND°82

2.83

R=75W~2 aL

N D _

R0P = 22W -l

X0P -450

fW

ohms

2.1 1.1

hL J W (a-as)ND082

ohms

2.84

2.85

2.86

where f is in gigahertz; Wi and W are in millimeters; a, as, h, L and Lsg

are in microns and ND is in 1016 cm"3. (Fukui, 1979b).

Fmin is invariant to the total device width but varies with the unit gatewidth.

As the operating frequency increases, the skin effect on the gate metal-lization can no longer be ignored and Equation 2.83 becomes:

Fmin=l = 0.038 f

1.1U'sg0.82

2.87

Consider now a practical device as shown in Figure 2.17 which has arecessed gate structure with the geometrical parameters as shown.

Equation 2.87 can be extended to cover this practical case by theexpression (Fukui, 1979c)


Source

I

Gate

"W-ih\

\ Yi—i vt- - - - - - - a ~'

Buffer

^ _

Drain

N

Figure 2.17 Optimized Low-Noise MESFET Structure

Fmin=l+0.038f NnL5

1\l7Wf 2.1

0.5 AT 0.661 -*V 7

2.88

where Lg is the average gate metallization length in microns, L2 and L3are the effective lengths of each sectional channel between the sourceand gate electrodes in microns; a is the effective channel thickness underthe source electrode, a2 and a3 are the effective thicknesses of thesectional channel in microns; Ni is the effective free carrier concentra-tion in the channel under the source electrode and N2 and N3 are theeffective free carrier concentrations of the sectional channel, all in 1016

cm"3.

For the case where an n+ GaAs layer exists between the ohmic metaland n-GaAs, L2 can be approximated to the distance of the n layerbetween the edge of the n+ layer and the effective edge of the gateelectrode.


2.3.6 Example Of Low Noise GaAs FET Design

First let us examine the variation of Fmin and noise resistance, Rn as afunction of the carrier concentration ND and the active channel thickness

a.Consider a l//m GaAs FET where the source-to-gate separation Lsg isalso ljum. The source resistance is assumed to be 4 ohms and f = 3.8GHz. as is assumed to be approximately equal to the gate depletion layerthickness, a0. Fukui (1979a) has shown that this parameter is given by

\ 0.706 + 0.06 logNDa ° \ 7.23 ND

for aluminium devices.

Thus Equation 2.83 reduces to

2.89

Figure 2.18 shows the values of Fmin as a function of ND and a. It maybe seen that Fmin is lowest for the highest values of a/N consistent withthe avoidance of drain-source breakdown at around 10 volts. This

1

0.7

0.5

0.3

0.2

0.12 3 4 5

N

VB =

— • _ _

" * - —

7

o(10M

10v

\

10

cm- 3 )

n,n = 1.5dB

^ — 1 7

ISM.9

\

20 30

W = 0.5mm, W, -0.25mm

No Gate recessf = 3.8 GHz

Figure 2.18 Contours of Fmin as a Function ofND and a for a ljumGate Length FET


condition implies a non-optimum value for Rn by Equation 2.84 so thereis clearly a compromise value of a/ND.

Let us examine this a little more closely. Consider two devices with thefirst device having ND = 1.25 X 1017 cm"3 with a = 0.2/um and the seconddevice having ND = 5 X 1016 cm"3 and a = 0.5jum.

The noise performance of these devices can be plotted on the SmithChart (Figure 2.19) following equations 2.83 to 2.86.

As may be seen the second device, even though having a smaller Fmin,has a larger R, leading to the fact that the 50 ohm noise figure is over 1dB higher than the first device.

Referring to the 50 ohm noise figure as

50(50-ROP)2

R0P +X OP

it is possible to calculate the variation of both Fmin and F50 with the totaland unit gate widths W and Wi. Again for the two devices used asexamples previously Figure 2.20 results where it has been assumed that

No = 1.25 x 1017/cc a = 0.;

• ND = 5 x 1016/cc a = 0.5Mm

L = l_6G = 1fim

W = 0.5mmW1 = 0.25mm

f = 3.8GHzZo = 50fi

Figure 2.19 Constant Noise Figure Circles for two lfim Gate LengthMESFETs


oL_0.1 0.2 0.3 0.5 0.7 1

W(mm)

L = LSG = tyW = 2W,Rg = 8Wfif = 3.8GHZ

-N D = 1.25 x 1017/cc;a

-N D = 5 x 1016/cc;a =

Figure 2.20 Fmin and F50 as a Function of Total Device Width fortwo ljum Gate Length MESFETs

the gate metallization resistance is related to the total gate width by thesimple expression

Rs = 8W W being in millimeters

As may be seen F50 is a strong function of W and indicates that theoptimum value for the total gate width is approximately 450/*m for thefirst device and 90Qam for the second FET.

The maximum value of unit gate width Wimax can be defined as the limitabove which Rg becomes greater than Rs. Thus equating 2.81 and 2.82and accounting for Equation 2.88 we obtain

Wlmax=0.25yjhLg

a1

2.90

when Wi = Wimax Equation 2.88 reduces to


Fmin=l + 0.057f

1.9

NDL5

L3

a2N20'82 a3N3

0'82

2.91

where

is the perturbation due to the skin effect.

Figure 2.21 shows the calculated minimum noise figures versus fre-quency for the devices of Table 2.3 (Fukui, 1979).

Four of the devices have n+ layers under the ohmic contacts. Device ahas a Cr-Au gate metallization with a resistivity of 2.5 x 10~6 Q cm whilstthe remaining devices have aluminum gate metal of resistivity 5 x 10"6

Qcm. Device bis an optimized design for a gate length of 0.9//m. Devicec has a Wi value greater than Wimax negating the effect of the 0.5/^mgate length. Device d is an improved version of device c with a Wi oflOQams. Device e is a 0.25/nn gate length device with a unit gate widthof 65/jms.

CO

o

I

2 3 4 6 10 20 30 40

Frequency, GHz

W(mm)09 5!25 Ro0.9 0.25 Yes0.5 0.25 Yes0.5 0.1 Yes0.25 0.065 Yes

Figure 2.21 Calculated Minimum Noise Figure as a Function ofFrequency for the Devices of Table 2.3


0.25 micron gate length MESFETs in practice have achieved noisefigures of less than 3.0dB at 35 GHz. Figure 2.22 shows the best noisefigure results that have been produced as of 1985. Gains of over 6 dBhave also been obtained at 60 GHz but no noise figures have beenpublished. Predictions based on modified Fukui noise analysis (Oxley,1985) suggest that noise figures of less than 4 dB should be possible atthis frequency. In the first edition of this book (Figure 2.19) noise figuresof around 2dB were being obtained at 20 GHz but noise figures at 30GHz were in the region of 5 dB. Optimization of device structures andmaterial have lowered this figure to 2.5 dB in the intervening threeyears.

2.3.7 Noise Modeling of FETs

Podell et al (1979) have shown that the noise performance of GaAs FETscan be adequately described by two effectively Uncorrelated noisesources-one at the input of the FET due to thermal noise generated inthe various resistances in the gate-source loop and the other in theoutput of the FET due to the Gunn domain between the gate and thedrain of the device.

The input conductance gi of the FET can be approximated by

2.92

Podell et al has found that RN in a GaAs FET can be approximated bythe expression

6

•o

ft*4

l 3in

I2

1

•0a

0 10

TlPlesseyAvantekTRW

DO

20 301 1

40 50Frequency,

Predicted

1 1

60 70GHz

* '

1

80i

90

Figure 2.22 Noise Figure of MESFETs as a Function of Frequency


^ = I ? T K V 2.93

where I = IDS/IDSS and Ko, K2 are empirical constants.

Ko is approximately 1 for 0.5 micron FETs and 0.5 for 1 micron FETswhilst K2 has a value of 2.5. Both these constants are independent offrequency.

The optimum source admittance (gsopr + COPT) can be calculated withthe following equations

2.94

where * denotes the complex conjugate and Qi equals

2.96

From the above equations, once the equivalent circuit of one FET andits noise figure at one frequency are known, the optimum noise sourceimpedance and noise figure at any frequency can be calculated.

The equation for FMIN above relates the noise factor to the parameter A.It is desirable to minimize both the noise and the input Q of the FET,particularly at low microwave frequencies where the input Q is ex-tremely high, and losses in the input matching network can be asimportant as losses in the input of the FET itself. This is particularlytrue in monolithic microwave integrated circuits where the Q of thematching networks is low (usually around 50).

The reader is referred to the original paper for details and examples.


2.3.8 The GaAs FET Versus The Bipolar Transistor As A Low NoiseDevice

It was mentioned earlier in this chapter that the improved maximumcut off frequency of a GaAs FET when compared to a silicon BJT forsimilar geometries was due to the larger saturated drift velocity of GaAs.

The minimum noise figure for the bipolar junction transistor at roomtemperature is given approximately by

2.97

where

= 40Ic-\f

rb being the parasitic base resistance in ohms and Ic being the collectorcurrent in amperes. An equivalent figure for the GaAs FET is

where

m = —— Jg (R +R) 9 Qftr A/ O ITl\ £ S / ^J.t/VJ

/rIt may be appreciated therefore that the minimum noise figure for theGaAs FET increases linearly with frequency compared with a quadraticfunction for the BJT. Thus, the GaAs FET not only has a better intrinsicnoise performance but also degrades much more slowly with frequencythan the bipolar device.

2.4 The Dual Gate FET

Although the single gate structure has become the most widely manu-factured and used device the dual gate FET has the advantages of anincreased capability due to the ability of the two independent gates toperform such functions as gain control and mixing as well as reducedfeedback and improvement in signal gain. The dual gate FET, however,is in general much less well understood than the single gate FET mainlydue to the r.f. interaction which can occur between its three accessible


ports when it is used in a particular configuration, usually commonsource. The applications of the dual gate FET are numerous. It has beenused in up and down converters, modulators, pulse regenerators, phaseshifters, and discriminators as well as in oscillator applications. Itsmajor use in mixers and multipliers is covered in Chapter 6, whilst itfigures considerably in Chapters 8 and 10.

The first GaAs dual gate MESFETs were made in 1971 by Turner et albut it was some time before this pioneering work was followed up by thefirst serious attempt at analysis of the device by Liechti in 1975.

The dual gate device can be considered as two separate FETs connectedin cascade as shown in Figure 2.23(a) where the current characteristicsof the bottom FET are determined by the top device. Figure 2.23(b)shows a representation of a dual-gate device where the first and secondSchottky gates Gi and G2 are formed between the source and drainohmic contacts.

The operation and characteristics of the dual-gate FET can be analyzedby combining the analyses of the two single gate FETs. As we havealready seen in this chapter the performance of such single gate deviceshas been extensively examined.

Consider the analytic model of the dual gate MESFET shown in Figure2.24. It is composed of 2 single gate FETs and three parasitic resistors,i.e. FET1, FET2, a source series resistor Rs, the intergate resistance Risand the drain resistor, RD.

0—G2

0—G1

D

I— FET2

I— L _ FET1

1-(a)

Source

V///////A

First Secondgate gate

Active layer

Buffer layer

S.I. substrate

(b)

Drain

Y/////////

Figure 2.23 (a). Equivalent Circuit Configuration of Two SingleGated FETs (b). Cross Section of Dual-Gate MESFET


Figure 2.24 Analytical Model of the Dual-Gate FET

Using the model of Statz et al (1974) it is possible to calculate

1. The drain currents IDI and ID2 of F E T S 1 and 2.

2. The channel lengths Lui and Lu2 where the carriers move at theunsaturated velocity.

3. The regions Lsi and Ls2 where the carriers have reached satu-ration velocity.

These 3 quantities are calculated as functions of the gate-source biasesVGIS and VG2S and the applied voltages across each single gate FET, i.e.V D I - V S I and VD2-VS2.

Thus by setting IDI = ID2 = IDS for given bias conditions VGIS, VG2S andVDS. The voltage drops across the 2 FETs and the 3 resistors will equalVDS.

Figure 2.25 shows calculated and measured I-V characteristics for a dualgate FET having the parameters:

LGI = LG2 = 1/Jm

LIG = l/*m

Wi = W2 = 300/*m

ND = 2.5 x 1017 cm 3 and a = 0.14jum


1J

60

40

20

nc

VGJS = OV

• Measured

/

S* *)

\\\A

•1

^f * *

/^\ . .

\\

\• • w \

V o s (Volts)

VG1S

• • • •

\\

\

2

= 0•

-0.0

-1.0

-1.5

-2.0

3

Figure 2.25 Drain Current-Drain Voltage Characteristic as aFunction of First Gate Bias for a Dual-Gate MESFET

where LGI, LIG, Wi, VPi, ND and a are the gate lengths, intergate spacing,gate widths, pinch-off voltages, and the carrier concentration in theactive region of layer thickness, a. (i = 1 or 2).

Various other parameters were as used by Statz (1974) or Pucel (1975).It may be seen from Figure 2.25 that the agreement between measuredand theoretical characteristics is satisfactory.

2.4.1 Equivalent Circuit Parameters

The equivalent circuit of the GaAs dual gate MESFET is somewhat morecomplicated than the single gate device. Figure 2.26 shows the equiva-lent circuit where parasitic circuit elements and noise sources have alsobeen included.

The intrinsic circuit elements of the two FETs, FET1 and FET2, enclosedby dotted lines in Figure 2.26 have been analyzed using Statz's model(Furutsuka et al, 1978).

The gate resistance RGI (i = 1 or 2) can be estimated using the equation

Rrri= — 2.99


FEJ2

Figure 2.26 Equivalent Circuit ofGaAs Dual-Gate FET

where two unit gate widths, each Wi /2, are assumed, and where p is theresistivity of the gate metal (2.75 x 10~6 Q cm for aluminum).

The source series resistances is given by

USG12.100

where LSGI, is the spacing between the first gate and source and pc isthe specific ohmic contact resistance. The drain series resistance isgiven by a similar expression. (Furutsuka et al, 1978).

The electrical characteristics of the dual gate FET can thus be expressedin terms of all the circuit elements of FET1 and FET2. For example, thetransconductance associated with the first gate is given by:

Smol

2.101omol

gmoi being the d.c. transconductance of FET1


where both FETs are operating under current saturation. Also, forexample, the drain conductance gd Of the dual-gate FET is given by:

\8d22.102

where both FETs are in current saturation.

The variation of gm with VGIS is shown in Figure 2.27 as a parameter ofVG2S for the same MESFET structure used in Figure 2.25. As bothdevices in the cascade enter the current saturation region the gm risesto a maximum value.

The dual gate FET is usually characterized as a 3-port device with thesource connected to ground. Table 2.5 shows the S-parameters of asingle gate FET and a dual gate FET where the dual gate FET is similarin geometry to the single gate device with LGI = LG2 = ljum and LIG =1.5/um.

30

20

10

Z5

A• / V-2.0

U ir

y-1.5

—

Device parameters are those of Figure 2.22

^ N.VG2S (VOltS)

•v \-0.5 \

\-1.0 \ \

-1 0

VG,S (VOltS)

Figure 2.27'First Gate Bias Dependence of Transconductance onSecond Gate Bias, VG2S

Tab

le 2

.5 C

ompa

riso

n of

S-P

aram

eter

s of

Sin

gle

and

Dua

l Gat

e F

ET

s at

12

GH

z

Dev

ice*

Sin

gle

gate

dG

AT4

Dua

lga

ted

DU

GA

T10

-000

S11

.55

180°

.6

170°

S21

1.39

22

°

1.49

-7

2°

S31

1.12

30

°

S12

.08

42°

.06

-.16

°

S22

.67

-.86°

.69

-81°

S32

.24

-21°

S13

.06

-13°

S23

.61

12°

S33

.85

-83°

s icrowa CO

ield-Effect Transisto


It may be seen that, as with a single gate FET, there is a high transmis-sion coefficient between gate 1 and drain. However, there is also consid-erable transmission from gate 1 to gate 2. The reverse scatteringparameters are small, that between drain and gate 1 being lowered withrespect to the single gate FET due to the shielding effect of gate 2.

The forward transmission coefficient between gate 2 and drain is lowerthan gate 1 to drain because the output impedance of FET1,1/gdi + Rs+ wLsi is in series with the second gate capacitance Cgs2 and theintergate resistance RIG, thus lowering the transconductance of thesecond gate. The output impedance of the first FET also acts as a seriesfeedback impedance increasing the reverse transmission coefficientfrom drain to gate 2.

We have already seen that the dual-gate FET equivalent circuit isconstructed from a cascode connection of two single-gate FETs. A newmodel has been suggested by Scott and Minasian (1984) which contains14 elements and is derived from a design-oriented equivalent circuitdeveloped for single-gate FETs. The dual-gate MESFET representationas a cascode connection of two single-gate FETs is shown in Figure 2.28.

Figure 2.28 Wideband Model of GaAs Dual Gate MESFET (afterTsironis, 1982)


The equivalent circuit is deduced by combining two single-gate FETmodels. Such a full equivalent circuit contains 28 circuit elements(Tsironis et al, 1982). Thus, when combined with other active andpassive devices in a CAD program the resulting data file would becomeuntractable especially during optimization. The simplified form ofequivalent circuit shown in Figure 2.29 can be used with little loss inaccuracy up to 12 GHz. The application of these constituent FET modelsto obtain a circuit model for the dual-gate FET is shown in Figure 2.29.This model contains only 14 elements. Scott et al have shown that theS-parameters derived from such a model compare within 4% in magni-tude and 3 degrees in phase in all 9 S-parameters of the 3-port dual-gateFET in common source configuration up to 11 GHz.

2.4.2 Gain Versus Second-Gate Terminations

When the dual gate FET is used as an amplifier the device is convertedinto a 2 port by terminating the second gate with an impedance ZG2. ASwith a single gate FET gate 1 is the input and the drain is the output.The S-parameters of this 2 port Sue' are related to the original 3 portS-parameters Sue by the relationship (Bodway, 1968)

SiK' ~ 2.103

where FG2 is the reflection coefficient of the load ZG2 with respect to thecharacteristic impedance Zo, i.e.

Figure 2.29 Simplified Model ofGaAs Dual-Gate MESFET (afterMinasian and Scott)


,, (ZG2-Z0)

2.104

The maximum available gain, MAG, and associated reverse isolation,RI, between the matched input and output ports can be calculated as

2.105\°]2 |L J

and

RI =

where

2.106

? > C ' C ' C 'I IC 'I _ IC 'I' ; ; •i>22 ^n • J 2 ; I P ; ; I P22 I

For an RF shorted second gate the dual gate MESFET is essentially acascode connection with a common source input and a common gateoutput. The properties of such a connection are:

1. Sn' and |S2l'| are similar in value to those of an equivalentsingle gate device.

2. The phase angle of S21' is smaller than that of the single gateFET due to the increased length between gate 1 and drain.

3. IS12' I is smaller than in the single-gate FET because of secondgate shielding.

4. I S22; I is somewhat higher than in the single gate device.

A map of forward gains (Figure 2.30) has been computed for the devicein Table 2.5 (Plessey DUGATlO-000) at a frequency of 12 GHz for varioussecond gate terminations. It may be seen that with the second gategrounded (rG2 = -1) the maximum available gain is 13.4 dB with 20 dBreverse isolation between drain and gate 1. Up to 20.5 dB forward gaincan be obtained from the dual gate FET with an inductive termination.The reverse S-parameters decrease however and the limits are set bythe boundary k = 1 beyond which the transistor is potentially unstable.Also, there is a region where the transistor will yield forward loss.


20 dB

15.4 dB14.3 dB, 7

13.8 dBf / 1 3 d B

13.4 dB

10 dB

f = 12GHz

Figure 2.30 Forward Gain Mapping for (DUGAT10-000) l/um DualGate FET when VG2S = 0 volts (Courtesy-Plessey) as a Function ofSecond Gate Impedance

Figure 2.30 shows this area where the signal flowing via gate 2 to thedrain interferes destructively with the signal flowing from gate 1 todrain.

2.4.3 Gain Control With Second-Gate Bias

At 12 GHz, for the device above, the second gate termination effect onthe forward transmission coefficient can be mapped when the secondgate bias is increased negatively to the point where the channel underthe second gate is completely depleted and the drain current is cutoff.

Essentially the dual gate FET then behaves like a passive, reciprocaldevice, i.e. the forward loss equals the reverse loss in which the drain tofirst-gate capacitance Cgd, dominates the coupling between the 3 ports.However, there is still a signal component present in the second gatecircuit which interferes with the gate 1 to drain signal causing theoff-isolation of the device to vary according to FG2. This is shown inFigure 2.31.

Figure 2.31 is a mapping of forward insertion loss for the same dual gateFET when VG2S = Vp and can be compared with Figure 2.30 showing thatthere is a termination which will produce an acceptable forward gain,


-lOdBM

' f = 12GHZ

Figure 2.31 Forward Insertion Loss Mapping for (DUGAT10-000)ljum Dual Gate FET when VG2S = Vpasa Function of Second Gate

when gate 2 bias is zero and also an acceptable insertion loss at a valuesuch that the channel under gate 2 is pinched-off. The input impedanceversus VG2S stays within close limits because the reverse couplingcoefficients S12 and S13 remain small in the bias range. Figure 2.32(a)demonstrates this whilst Figure 2.32(b) shows that the forward trans-mission phase of the dual gate FET can vary considerably as the secondgate voltage is changed. Again a second gate termination exists whichminimizes the phase and input impedance variations. For the device ofTable 2.5 a variation in gain from a maximum of 10 dB to below —20 dBcan be produced whilst keeping the input VSWR below 1.5:1.

2.4.4 Noise Performance

As with the noise analysis of the single gate FET, the dual gate FETnoise figure can be predicted by evaluating the equivalent noise conduc-tances and correlation factors within the intrinsic FETs 1 and 2 andincludes the effects of the parasitic resistances shown in the equivalentcircuit of Figure 2.26. Denoting each noise current which appears at thedrain Tx , the noise figure of the dual gate FET is given by


cr 2

>

I rG2 = u-45 0

-2 0 2

Second gate voltage, VG2S (Volts)

(a)

0 2

Second gate voltage, VG2S (Volts)

(b)

Figure 2.32 (a). Input VSWR Versus Second Gate Voltage for TwoSecond Gate Terminations (after Liechti (1975). (b). TransmissionPhase Versus Second Gate Voltage for Two Second Gate Terminations

IRS + IRGI + 1 RIG + IGI + Idi + IRG2 + IRD + IG2 )2.107

where Tin is the noise current at the drain generated by the input signalsource at a standard temperature. The correlation coefficients betweenthe various noise sources must also be determined.

Figure 2.33 shows the calculated and measured dependence of theminimum noise figure on drain current (i.e. on VGIS) for a device havingthe same parameters as those used to compute the I-V characteristicsof Figure 2.25. Again it is seen that there is good agreement betweentheoretical and measured results. The large increase in Fmin for IDS/IDSS>0.9 is due to FETl working in the unsaturated regime and thereforehaving a low gm.

As has been detailed earlier in this chapter for the single gate FET it ispossible to produce analytical solutions for the dependence of noisefigure and maximum available gain on parasitic resistances, carrierconcentration and first and second gate lengths, LGI and LG2.


10

s~ 5z

vG2S = o vLGI = I_G2 = liimVP, = VP? = - 2 . 5 V

0.5IDS/IDSS

1.0

Figure 2.33 Computed Drain Current, IDS/IDSS Dependence ofMinimum Noise Figure, Fmin

Figure 2.34(a), (b) and (c) show the results for a dual gate FET havingthe material and geometry parameters used in previous figures.

In summary the dual gate FET can be optimized in its design by

a) Producing an optimum pinch-off voltage (i.e. thickness of theactive layer) to minimize noise figure and maximize gain. Forexample, for FETs with equal gate 1 and gate 2 lengths and equalactive region thicknesses this optimum pinch-off voltage is approxi-mately - 1.5V for n = 8 x 1016/cc.

b) Producing a longer second gate and wider second channel (Asaiet al, 1975). This leads to a further improvement in both Fmin andMAG. The increased gm of the dual-gate FET is due to the fact thatFET2 will have a higher pinch-off voltage than FET1 thus supplyingmore current to the pair and thus increasing the voltage applied toFET1. In terms of device fabrication further processing is neededto produce a channel with two thicknesses thus lowering yields andraising costs.

c). Lowering the parasitic resistances Rs and RG by using betterohmic contact technology, or an n+ layer and employing parallelgates.

d). Keeping LG2 < LGI .


4.0

CD

3.0

2.0

2

(b)

CO

0.5

(c)

10

Rs + RGI (fl)

20

1020

(after Furutsuka(ref. 44))

-130

f = 10GHzVG2S = OVVP, = V w = - 2 V

5 10 20

ND(1016/cc)

MAGCO

S

f = 10GHz

VG2S = OV

1.0 1.5

Figure 2*34 (a). Computed Parasitic Resistance Dependence ofFminand MAG at VG2S = OV (b). Computed Carrier Concentration, NdDepencences ofFmin and MAG at VG2S = OV (c). Computed SecondGate Length Dependences ofFmin and MAG at VG2S = OV


e). Increasing the carrier concentration, ND, the upper limit beingset by the required breakdown voltage of the drain to the Schottkygate.

2.5 Conclusions

This chapter has given an introduction to the theory of small signalGaAs MESFETs with particular emphasis on the models used to predictthe FET gain and noise figure performance. Such calculations have ledto better FET structures and geometries being introduced as a meansto exploit the intrinsically superior properties of GaAs over Si. Theproperties of the dual-gate FET have also been covered in some depthas this particular type of device has proved itself to be especially usefulin microwave circuit applications.

2.6 Bibliography

Alley, G. and Talley, H. A theoretical study of the high frequencyperformance of a Schottky barrier field effect transistor fabricated on ahigh-resistivity substrate. IEEE Trans. Microwave Theory and Tech-niques, Vol. MTT-22, pp.183-139, March 1974.

Asai, S., Murai, F. and Kodera, H. GaAs dual-gate Schottky barrier FETsfor microwave,frequencies. IEEE Trans. Electron Devices, Vol. ED-22,pp.897-904, October 1975.

Baechtold, W. Noise behaviour of Schottky barrier gate field-effect tran-sistors at microwave frequencies. IEEE Trans. Electron Devices Vol.ED-18, pp.97-104, February 1971.

Baechtold, W. Noise behaviour of GaAs field effect transistors with shortgate lengths. IEEE Trans. Electron Devices, Vol. ED-19, pp.674-680.

Barrera, J. and Archer, R. InP Schottky gate field effect transistors.IEEE Trans. Electron Devices, Vol. ED-22, pp. 1023-1030, November1975.

Bodway, G. Circuit design and characterisation of transistors by meansof three port scattering parameters. Microwave Journal, Vol. 11, pp.55-63, May 1968.

Butlin, R.S., Hughes, A.J., Bennett, R.H., Parker, D. and Turner, J.A.J-band performance of 300 nm gate length GaAs FETS. 1978, Int.Electron. Devices Meeting, Dig. Tech. Papers, pp.136-139.


Camacho-Penalosa, C. and Aitchison, C.S. Modeling frequency depend-ence of output impedance of a microwave MESFET at low frequencies.Electronics Letters. Vol. 21, No. 12, June 1985, pp.528-529.

Dawson, R. Equivalent circuit of the Schottky-barrier field effect tran-sistor at microwave frequencies. IEEE Trans. Ilicrowave Theory andTechniques, Vol. MTT-23, pp.499-501, June 1975.

Englemann, R.W.H. and Liechti, C.A. Gunn domain formation in thesaturated current region of GaAs MESFETS. IEDM Tech. Digest, pp.351-354, Dec. 1976.

Fawcett, W., Hilsum, C. and Rees, H. Optimum semiconductors formicrowave devices. Electronics Letters, Vol. 5, pp.313-314, July 1969.

Fawcett, W. and Herbert, D. High-field transport in gallium arsenide andindium phosphide. J. Phys. C: Solid State Phys., Vol. 7, pp. 1641-1654,May 1974.

Fukui, H. Determination of the basic device parameters of a GaAsMESFET. BellSyst. Tech. J. Vol. 58, pp.771-797, March 1979.

Fukui, H. Design of microwave GaAs MESFETs for broadband low-noiseamplifiers. IEEE Trans. Microwave Theory and Techniques, Vol. MTT-27, No. 7, July 1979, pp.643-650.

Fukui, H. Optimal noise figure of microwave GaAs MESFETS. IEEETrans Electron Devices, Vol. ED-26, No. 7, July 1979, pp. 1032-1037.

Furutsuka, T, Ogawa, 14. and Kawariua, N. GaAs Dual-gate MESFETS.IEEE Trans. Electron Devices, Vol. ED-25,No.6,pp.580-586,June 1978.

Glicksman, M., Enstrom, R., Ilittleman, S. and Appert, J. Electronmobility in InxGal-xAs alloys. Phys. Rev. B., Vol. 9, pp.16211626, Feb.1974.

Grebene, A. and Ghandi, S. General Theory for pinched operation of thejunction-gate FET. Solid State Electron. Vol.21,pp.573-589, July 1969.

Grove, A.S. Physics and technology of semiconductor devices. New York,Wiley, 1967.

Hewitt, B.S., Cox, H.M., Fukui, H., DiLorenzo, J.V, Schlosser, W.O., andIglesias, D.E. Low noise GaAs MESFETS: Fabrication and performance.Gallium arsenide and related compounds. Conf. Series No. 33a, TheInstitute of Physics, pp.246-254,1977.


Kuvas, R.L. Equivalent circuit model of the GaAs FET including distrib-uted gate effects. IEEE Trans. Electron Devices, Vol. ED-27 No. 6, June1980.

Lam, H. and Acket, G. Comparison of the microwave velocity fieldcharacteristics of n-type InP and n-type GaAs. Electronics Letts, Vol. 7,pp.722-723, Dec. 1971.

Lehovec, K. and Miller, R. Field distribution in junction field effecttransistors at large drain voltages. IEEE Trans. Electron Devices, Vol.ED-22, pp.273-281, May 1975.

Liechti, C, Gowen, E. and Cohen, J. GaAs microwave Schottky-gate FET1972 Int. Solid State Circuits Conf. Digest of Tech. Papers, pp.158-159.

Liechti, C.A. Performance of dual gate GaAs MESFETs as gain control-led amplifiers and high-speed modulations. IEEE Trans. Microwavetheory and techniques, Vol. MTT-23, pp.461-469, June 1975.

Macksey, H. and Adams, R. Fabrication processes for GaAs power FETSProc. 5th Cornell Conf. on Active Semiconductor Devices for Microwaveand Integrated Optics, pp.255-264,1975.

Maloney, T. and Frey, J. Frequency limits of GaAs and InP field effecttransistors. IEEE Trans. Electron Devices, Vol. ED-22, pp.357-358,July 1975, and Vol. ED-22, p.620, August 1975.

Middelhoek, S. Projection masking, thin photoresist layers and interfaceeffects. IBM J. Res. Develop. Vol. 14, pp.117-124, March 1970.

Middelhoek, S. Metallization processes in fabrication of Schottky barrierFETs. IBM J. Res. Develop. Vol. 14, pp. 148-151, March 1970.

Mo, D. and Yanai, H. Current-voltage characteristics of the junctiongatefield effect transistor with field dependent mobilitv. IEEE Trans. Elec-tron Devices, Vol. ED-17, pp.577-586, August 1970.

Ohkawa, S., Suyama, K. and Ishikawa, H., Low noise GaAs field effecttransistors. Fujitsu Sci. Tech. J., Vol. 11, pp.151-173, March 1975.

Podell, A.F. A functional GaAs FET noise model. IEEE Trans, onElectron Devices, Vol. ED-28, No. 5, May 1981, pp. 511-517.

Pucel, R., Haus, H. and Statz, H. Signal and noise properties of galliumarsenide microwave field effect transistors. Advances in Electronics andElectron Physics, Vol. 38, New York: Academic Press, 1975, pp. 195-265.

Rothe, H. and Dahlke, W. Theory of noisy fourpoles. Proc. IRE Vol. 44,pp.811-818, June 1956.


Ruch, J. and Fawcett, W. Temperature dependence of the transportproperties of gallium arsenide determined by a Monte Carlo method.J.Appl. Phys. Vol. 41, pp.3843-3849, August 1970.

Ruch, J. Electron dynamics in short channel field effect transistors.IEEE Trans. Electron Devices, Vol. ED-19, pp.652-654, May 1972.

Scott, J.R. and Minasian, R.A. A simplified microwave model of the GaAsdual-gate MESFET. IEEE Trans. Microwave Theory and Techniques,Vol. MTT-32, No. 3, pp.243-8, March 1984.

Shockley,W. A unipolar field effect transistor. Proc. IRE, Vol. 40, p. 1365-1367, November 1952.

Shur, M.S. and Eastman, L.F. Current-voltage characteristics, smallsig-nal parameters and switching times of GaAs FETS. 1978 IEEE MTT-5Int. Microwave Symp. Digest, June 1978, pp. 150-152.

Statz, H., Haus, H. and Pucel, R. Noise characteristics of galliumarsenide field effect transistors. IEEE Trans. Electron Devices, Vol.ED-21, pp.549-562, September 1974.

Sze, S.M. Physics of Semiconductor Devices, New York, Wiley-Inter-science, p.393,1969.

Tsironis, C. and Beneking, H. Avalanche noise in GaAs MESFETS.Electron Lett. Vol. 13, No. 15, pp.438-439,1977.

Tsironis, C. and Meierer, R. Microwave wide-band model of GaAs dualgate MESFETS. IEEE Trans. Microwave Theory and Techniques, Vol.MTT-30, No. 3, pp.243-251, March 1982.

Turner, J.A., 1967 Gallium Arsenide (Inst. Phys. Conf. Ser. 3).

Turner, J., Waller, A., Bennett, R. and Parker, D. An electron beamfabricated GaAs microwave field effect transistor. 1970 Symp. GaAs andRelated Compounds (Inst. Phys. Conf. Serial No. 9, London 1971)pp.234-239.

Turner, J.A., Waller, A.J., Kelly, E. and Parker, D. Dual-gate galliumarsenide microwave field effect transistor. Electronics Letters, Vol. 7,pp.661-662, November 1971.

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Van der Ziel, A. Gate noise in field effect transistors at moderately highfrequencies. Proc. IEEE Vol. 51, pp.461-467, March 1963.


Van der Ziel, A. Thermal noise in the hot electron regime in FETS. IEEETrans. Electron Devices, Vol. ED-18, p.977, October 1971.

Vendelin, G. and Omore, M. Circuit model for the GaAs MESFET validto 12 GHz. Electronics Letts., Vol. 11, pp.60-61, February 1975.

Vendelin, G.D. Feedback effects in the GaAs MESFET model. IEEETrans. Microwave Theory and Techniques, Vol. MTT-24, No. 6, June1976, pp.383-385.

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Yamaguchi, K., Asai, S. and Kodera, H. Two-dimensional numericalanalysis of stability criteria of GaAs FETS. IEEE Trans. ElectronDevices, Vol. ED-23, pp. 1283-1290, December 1976.

GaAs FET Theory-Power

3.1 Introduction

The low noise and small signal properties of GaAs MESFETs have beenthe subject of the previous chapter. In contrast to the low noise devicethe power FET has only recently started to receive attention fromtheoreticians. The outcome of such studies is now beginning to show inthe results of power, efficiency and reliability of power FETs at frequen-cies up to 20 GHz.

For example the progress of power obtained from GaAs FETs as afunction of time is shown in Figure 3.1 where the results of severalcompanies have been collected together.

25

20

ja-3| 10

+

+

/ +

1976 1977 1978 1979 1980Year

Figure 3.1 Progress of Power Obtained from GaAs FETs as aFunction of Time


Power FETs with output powers in excess of 2 watts at 12 GHz areavailable commercially and over 5 watts has been achieved in thelaboratory.

This chapter will review the operating principles of the power GaAs FETand discuss the various structures that are being used to increase deviceperformance. The large signal performance of the device will be ana-lyzed together with its third order intermodulation distortion and gaincompression characteristics.

3.2 Principles Of Operation

As has been seen in Chapter 2, Shur (1978) and Shur and Eastman(1978) have modeled the GaAs FET as a device where a Gunn domainforms at the drain contact thus effecting the current saturation andbreakdown voltage of the FET. Recently, Willing et al (1978) haveconsidered the power performance of the FET by calculating the largesignal performance from the experimentally observed bias dependencesof equivalent circuit model components.

Figure 3.2 shows the I-V characteristics of a power FET having a 1 mmwide gate. From this figure two important static characteristics can beseen

500

400

? **M ° 200

100

0C

V,

r ^ +0.5

/ -2

If "4

> 5

- " I f

- - l o s s

- • —

10Vos (Volts)

(after Di Lorenzo)

15

Figure 3.2 I-V Characteristics ofal mm wide Gate Power GaAs FET

GaAs FET Theory-Power 81

1. The values of the saturated drain current, IDSS, with VGS = OVand the maximum forward drain current IF with VGS > OV

2. The behavior of the drain current IDS with applied gate voltageVGS at a fixed drain voltage VDS.

When VDS is approximately 9V and VGS, is approximately - 8 volts, i.e.VDG = 17 volts there is a significant change in gradient of IDS indicatingthat there is avalanche breakdown between the gate and drain.

Figure 3.3 shows the I-V characteristics of Figure 3.2 displayed in asomewhat simpler form where a representation of the maximum draincurrent IF is shown for a forward gate bias of VF.

The load line for a load resistance RL is also shown as well as VK- a kneevoltage at which current saturation is deemed to have occurred.

VL is the limiting source-drain voltage given by

VL=VGD-VP 3.1

where VGD is the gate-drain avalanche breakdown voltage for a FETbiased to its pinch-off voltage Vp. Beyond VL excess current flowsbetween drain and source which cannot be modulated by the r.f. voltageon the gate and thus is a limiting value of VDS for further output power.

It is possible to calculate the output power of the device from this I-Vcharacteristic.

Load line for RL

Figure 3.3 Simple Representation of the ID-VDS Characteristic of aPower FET


Assuming that the d.c. bias points are VDS and IDS and that the totaloutput power is made up of harmonics as well as the fundamentalfrequency, the output power available to the load is

3.2

where

h"" h

and I1-I2 is the current swing associated with the voltage swing VL—VI(Di Lorenzo et al, 1979).

The maximum output power Pm is given by

Pm = ^(VGD-VP-VK) 3.4

where

T O.D

and

vGD-vP-vK_ yGD3.6

For example, consider a device with an IDS = 350 mA, VGD = 30V, Vp = 5V,VK = 2V, where the channel of the FET is not thermally limited. Thus

Pm = ^-(30-5-2) = ! wattO

This result corresponds closely to the best output powers found experi-mentally for lmm gate width FETs having power gains of approximately4 dB up to frequencies approaching 18 GHz.

Thus the important device parameters for power FETs are:


1. IF, the maximum drain current available with a forward biasedgate, VF;

2. VK, the knee voltage at which IF saturates;

3. VGD, the gate to drain avalanche voltage;

4. Vp, the pinch-off voltage; and

5. VL, the limiting drain-source voltage at which the gate can nolonger modulate the channel current effectively.

Unfortunately, some of the above variables are inter-related. For exam-ple increasing IF by increasing the carrier concentration ND generallydecreases the breakdown voltage, VGD. However we shall see later inthis chapter that the geometrical design of the device plays a major rolein its power handling and efficiency.

3.3 Modeling Of GaAs FET To Predict Large Signal Performance

For large signal performance evaluation it is necessary to derive anonlinear circuit-type device model. In order to achieve such results thebias and frequency dependences of the device S-parameters have to bemeasured. The model thus derived is then used in a time domainanalysis computer program to produce large-signal waveforms. These

\ 5 0 B Load line

N 1

-3

-4

0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0

(a) Vos (Volts)

(b)Cp.U.UandLo

are package parasitics

Figure 3.4 (a). Static I-V Characteristic (b). Equivalent Circuit ofPower GaAs FET


results can be transformed into the frequency domain by the usualFourier analysis.

Consider, for example, the measured I-V characteristics of a TexasInstruments power MESFET shown in Figure 3.4(a) together with theFET model of Figure 3.4(b).

In this model the package parasitics are Ls, LG, LD and Cp representingthe source common lead inductance, gate wire bonds, drain wire bondsand shunt parasitic capacitances due to the package respectively. Thebias dependent elements in this equivalent circuit are:

CFB the gate to drain feedback capacitance

CGS the gate-to-source capacitance

gm the transconductance

Rl the intrinsic channel resistance

RGD the Gunn domain resistance

Ro the output resistance.

The equivalent circuit is the same as that used for small signal FETanalysis which included the formation of a Gunn domain at the draincontact (Willing et al, 1977).

(after Willing)

c

— Modelled—i

4 6 8 10 12 14 16 18Frequency (GHz)

2 4

MeasuredModelled

6 8 10 12 14 16 18Frequency (GHz)

Figure 3.5 S-Parameters for a Power GaAs MESFET


0.7

0.6

0.5

0.4

0.3

0.2

0.1

50 Ohm load line ^trajectory ^ 3 ^ ^

• / ^ ^ ^ ^ ^ ^ ^

I f 50

!o? 30oa? 20

I 101.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0

Drain-to-source voltage Vos (VDC)

(a)

1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0


(d)

1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0


1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0


(b) (e)

1OOO

900

If800700

£500

400

3001.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0


1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0

Drairvto-source voltage V * (VDC)

(c)

Figure 3.6 Bias Dependences ofCGS, gm, CFB, Rl, RO and RGD (afterWilling, 1978)


Figure 3.5 shows the dependence of the small signal S-parameters of thedevice as a function of frequency for both the model and the measureddevice at a VDS = 6V and VGS = — 2V. It is seen that there is a goodagreement over the 1 to 18 GHz frequency range. The components inthe model having the most significant bias dependences are thosementioned above and the relationship of their values to drain to sourcevoltage is shown in the plots of Figure 3.6(a) to (f). Each curve showsboth the measured results and the computer-fitted small signal modelelement values as a function of both drain to source voltages and gateto source voltages.

3.3.1 Channel Capacitance (CGS)

The influence of bias on the active layer or channel capacitance is shownin Figure 3.6(a). CGS initially decreases with increasing VDS at a con-stant VGS due to the depletion width increasing. CGS approaches aminimum close to the value of VDS at which the device drain to sourcecurrent saturates. Further increase in VDS results in an increase in CGSdue to the charge accumulation effects as described in Chapter 2(Engelmann et al, 1976).

The total input capacitance of the FET is made up of CGS, CEX and CG.This can be calculated using the analytical techniques of Lehovec andZuleeg (1970) at the onset of saturation. Table 3.1 shows the calculatedvalue of CTOT and the fitted value of CTOT for the set of bias conditionsgiven where CTOT = CGS + CEX + CG.

Table 3.1 Dependence of FET Equivalent Circuit Parameters on DCBias at Onset of Current Saturation

Gate toSourceVoltage

Vgs(volts)

0

- 1

- 2

- 3

Drain toSource

SaturationCurrent

Vds(volts)

2.3

2.0

1.65

1.2

gm*(calc) mS

50

37

31

25

gm**(fitted)

mS

47

40

32

22

gm (DC)mS

45

41

35

25

Cgs*(calc) pF

0.76

0.65

0.49

0.35

Ugs(fitted) pF

0.76

0.63

0.53

0.4k After Lehovec and Zuleeg (1970) ** After Willing et al (1978)


3.3.2 Transconductance (gm)

The transconductance can be calculated using the expressions given inChapter 2 and compared to the computer fitted gm (gm(FiT)) and the gm(DC)calculated from the static I-V characteristics. Table 3.1 compares thevalues of gm( CALO, gm(FiT) and gm(DC) at the indicated bias conditions. Itmay be seen that there is good agreement.

Figure 3.6(b) shows that as Vbs is increased gm reaches a maximumaround the knee voltage and then decreases for values of VDS greaterthan VK.

Engelmann and Liechti (1976) have attributed this effect to a reductionin charge accumulation.

3.3.3 Feedback Capacitance (CFB)

Charge accumulation also accounts for the decrease in the feedbackcapacitance seen in Figure 3.6(c) as VDS is increased. Charge accumu-lation at the drain edge of the gate is seen in the sharp reduction in thevalue of CFB as VDS approaches VK. Above VK the feedback capacitanceincreases slightly with increasing VGS.

3.3.4 Intrinsic Channel Resistance Ri And Output Resistance Ro

Figure 3.6(d) shows the variation of Ri with VDS and VGS. For smallvalues of VDS, RI initially increases at a greater rate for values of VGSclose to the pinch-off voltage. At higher values of VDS the value of Ridecreases and approaches a constant value which depends on the initialopen channel conductance as well as the ratio of the channel width atthe drain edge of the gate when biased at VK to the undepleted channelwidth.

Figure 3.6(e) indicates that the Ro of the device increases from the d.c.resistance of the channel to a final value dependent on | VGS | •

3.3.5 Gunn Domain Resistance RGD

Willing and De Santis (1978) have reported the bias dependence of theGunn domain resistance.

As | -RGD | becomes the same order as Ro the magnitude of the outputreflection coefficient S22 may approach or even become greater than


unity. Normally | S221 increases monotonically with increasing VDS butthe influence of the Gunn domain resistance results in a nonmonotonicvariation of | S221, the effect being most noticeable in the region whereVDS = VK and when | VGS | « Vp, i.e. when the drain current is high.The relative magnitudes of | -RGD | and Ro can be seen by comparingFigure 3.6(e) and (f).

3.3.6 FET Model

A circuit model that can be used for the MESFET under large-signalconditions is shown in Figure 3.7. There are five non-linear elementsCGS, CGD, DGS, DGD and IDS and a non-linear parametric resistor, Ricontrolled by VGS, the voltage across CGS.

Both the capacitances CGS and CGD can be described by the relation

C(V) =

vBi

Go—VW—<^i^-

V G S "

RD LD

CGD

UGS

I—w—itJ R, C,

'T

vi>s

-OS

Figure 3.7 Non-Linear Equivalent circuit of MESFET


where Co is the value of the capacitance at V = 0 and Vm is the built-inbarrier voltage of either the gate-source or the gate-drain Schottkybarrier diodes, DGS and DGD.

The currents through DGS and DGD are given by

where Io is the saturation current at - V » V T where VT is the thresholdvoltage.

The non-linear controlled source IDS is a function of the delayed voltageVG = VGs(t—r) and the voltage, VDS.

IDS is given by

IDS(VGyDS) = BT(VG)E(l + LVDS)tanh{AVDSD(VG))Gun 3.8

where

) %L 3.9

3.10

and

( [ 2 ^ 3.11

Gunn (VG,VDS) is present to simulate the Gunn effect on the staticcharacteristics.

The parametric resistor, Ri, is a function of the voltage, VGS

3.12

VBI can be calculated from

VBi= 0.706+ 0.06 loge(ND(l06)) Volt 3.13

where ND is the channel doping density in cm~3.


For a typical FET, ND is 2 x 1017 cm"3.

Io is calculated from 3.395 x 10~2LG(WG) microamps

where LG and WG are the gate length and width in microns respectively

T7 nkTVT= 3.14

where n is the ideality factor of the Schottky diode

Typical figures for the constants in the above equations are given inTable 3.2.

In order to use such a non-linear MESFET model in a non-linearanalysis program such as ANAMIC (Sobhy, 1984) or harmonic balanceCAD (Rizzoli et al, 1983) it is necessary to evaluate the constants, VT, A,B, L, E, R, F and G, so that the measured static I-V characteristics agreewith the calculated ones.

The small signal S-parameters of the device will be already known withthe corresponding equivalent circuits as described in Chapter 2.

A complete set of data is thus available for the design of non linearcircuits such as amplifiers working in the non-linear regime.

Table 3.2 Complete Non-linear Model Parameters for 1 micron, 300micron FET

RG = 0.3 ohm

RD = 2 ohm

Rs = 2 ohm

LG = 0.06 nH

LD = 0.03 nH

Ls = 0.07 nH

CDS = 0.06 pF

CGSO = 0.25 pF

CGDO = 0.03 pF

VBI = 0.79 volt

Rio = 5 ohm

VR = 0.9 volt

IDGSO = IDGSO= 10//A

VT = nkT/q = 0.04 volt

Vt = 1.4 volt

A=1V"1

B = 28 mA/V2

L = 0.07V"1

E = 1.9

R = 0.35

F = - 0 . 5 7 volt

G = 0.018 V"2

D = 1 + VG/Vt


3.4 Predictions Of Non-linear Performance Of GaAs Power FETs

Large signal circuit models simulating nonlinear device performancedepend on the use of expressions which relate the current-voltagerelationships for each of the nonlinear elements.

Instantaneous currents through each of the nonlinear elements can beexpressed as the product of an instantaneous element value and aninstantaneous voltage.

Consider, for example, the simplified equivalent circuit of a tuned GaAspower FET amplifier (Higgins et al, 1980). As has already been shownthe dominant contributions to nonlinear response come from the vari-ations in transconductance, gm, with gate voltage, in the drain conduc-tance, GD, with drain voltage, and the voltage dependence of thegate-source capacitance, CGS.

The variation in the equivalent circuit elements is most convenientlyrepresented by a Taylor series. Thus, for example the transconductancecan be expressed as

I = a + a Vrq + g Vr<s + ff Vrq + 3 15

Thus the FET r.f. drain current is given by:

3.16

whereVG(,)=VGS(,)-VGO 3.17

specifies the instantaneous deviation of the gate-source voltage from thegate bias VGO.

The expansion coefficients gmi are derived from the polynomial fit to thecharacteristic of Figure 3.6(b), for example. The variation in gm withdrain bias is neglected in the simplest calculations by assuming anaverage value for the typical drain voltage range.


An expression for the drain conductance Go (= 1/Ro) as a function of thedrain voltage is given by:

= G01+G02VDS +GO3VDS2+GO4VDS

3+... 3.18

where

VD(t)=VDS(t)"VDO 3.19

represents the instantaneous deviation in the drain voltage from thequiescent value of VDO. The dependence of Go on gate bias has beenneglected by using an average value for the gate voltage range.

The active channel capacitance, CGS, as a function of the instantaneousgate voltage VGH) can be expressed as

CG(V) = CGS] + CGS2VGS + CGS3VGS2 + CGS4VGS

3+... 3.20

The resulting impedance associated with CG(V) is derived from

/ =±Git) i+

v' at

VGS(t)

J CGS(V)dVo

3.21

gmn, Gon and CGn are dependent on the doping profile of the active layer.All the expansion coefficients such as gmn, Gon and CGn, are used tocalculate the IMD products using the methods of Tucker and Rauscher(1977).

Let us consider the typical results of such a nonlinear model followingtime-domain analysis. A 60Qam gate width device with a 1.7jum gatelength and an epitaxial thickness of 0.32//m was used where the dopingdensity ND = 7.5 x 1016/cc. Pinch-off voltage was calculated to be -5.1Vwith a built-in potential VBI of 0.7V resulting in a channel pinch-offvoltage of —5.8V.

Now consider the device to be biased at VGS = -2V and VDS = +6V withr.f. inputs at a frequency of 2 GHz with drive levels up to the point where6 dB gain compression occurs. The sequence of steps leading to thefundamental and harmonic output powers with input power Pin is shownin Figure 3.8.

Figure 3.9 shows the excellent agreement between the measured fun-damental output power and that calculated.


Measurement of S-parametersfor VGS.VDS conditions

Simulation of device characteristics by model

tDetermine model element values for VGS, VDS values by least

square fit of computed to measured S-parameters.

Expressions for instantaneous element values in terms ofinstantaneous voltages.

Time domain analysis |

Fourier transformation

Figure 3.8 Simulation of Non-Linear Power GaAs FET Performance

30

I2,<£ 20

|

§ 10o

f = 2GHz / '

yS

i i •

0 10 20

Incident power P,NC (dBm)

6dB Compressionpoint

measured

modelled

30

Figure 3.9 Measured and Modelled Fundamental Output PowerVersus Input Power of GaAs FET


0

.10

§-20

-40

(a) 2nd Harmonic

P,NC(dBm)

0 10 ^ 30

(c) 4th Harmonic

-40

; -20

"-30

-40

PINC (dBm)

6 10/20 30

(b) 3rd HarmonicPINC(dBm)

0 10 * 30

(d) 5th Harmonic

measuredmodelled

Fundamentalfrequency = 2GHz

Figure 3.10 Measured and Modelled Harmonic Output PowerLevels Versus Power for a GaAs Power FET

Figure 3.10(a)-(d) shows the excellent agreement between the modeledand measured results for harmonic powers up to the 5th order.

3.5 Intermodulation Performance

In Equation 3.18 the drain coefficients are greatly reduced if the drainvoltage level is increased so that the instantaneous drain voltage neverapproaches the saturation drain voltage. This is a commonly observedeffect of power GaAs FETs where intermodulation levels can be reducedby increasing the drain to source voltage. The coefficients of both gm andGo are dependent on the carrier profiles of the GaAs active layer.

Most of the modeling of GaAs FETs use expressions derived fromShockley's work (1952) but recently Pucel et al (1975) have included theeffects of velocity saturation. Most of the analytical work assumes thatthe carrier profile from the surface immediately beneath the gate to thesemi-insulating GaAs is flat.

Figure 3.11 represents the model used to calculate the effects of a nonflat profile (Higgins, 1978). The model divides the active layer into 150layers. The electrons' motion under the gate region is assumed to be


150 layers of fixed thickness. Gate but variable carrier level

Source Drain

Depleted material Fixed static dipole

Figure 3.11 Layer Model used in the Model of GaAs FETs withVariable Carrier Concentration Profile

such that they reach saturation velocity after an initial short channelsection where the velocity is proportional to electric field. As explainedin Chapter 2 the necessary boundary conditions in the directions alongand normal to the charge flow establish the current at a given biascondition.

The numerical integration adaptation of Pucel's model is extremelyuseful in predicting the way in which the intermodulation distortion(IMD) of a GaAs FET depends on the carrier profile.

Figure 3.12 shows the profiles for three different layers:

1. An idealized epitaxial profile described by Williams and Shaw(1978);

2. A flat epitaxial profile with an abrupt doping transition at thesubstrate; and

3. An ion implanted layer where a 500 keV Se implant has beenpurposely compensated at the surface with a shallow 40 keV Beimplant (see Chapter 4).

The devices modeled were 500/im gate width, l/jm gate length FETswith specific ohmic contact resistances of 10~6 Q cm2.

In calculating the third order intermodulation products it is normallyassumed that the third order coefficient (gm3, for example) is much largerthan the fifth or seventh order coefficients (gm5 and gm7). From Table


101 8

5

101 7

I 5

? 2

5

2

1015

Fliit Ideal epitaxial

_ _ - — ^*\ Improved linearityx

r - - Ion implanted\\\\\\\

o-» 1a1

Depth (microns)

10

Figure 3.12 Three Different Profiles used in CalculatingIntermodulation Characteristics of Power GaAs FETs

(3.3 it may be appreciated that gm5 and gm7 can, in fact, be comparablein magnitude or larger than gm3. The gm5 and gm7 coefficients are leastfor the ion-implanted profile, promising a better IMD performance.

In fact, for moderate to high signal levels the transconductance contrib-utes mainly from its fifth order (gms) term. The analysis therefore takesaccount of the contributions to third order IMD products due to thehigher order terms in the nonlinear device model.

The two tone intermodulation products are given at frequencies 2fi—f2,3fi-2f2 and 4fi-3f2 where fi and f2 are the two input tones to the FET.gm3 contributes to the 2fi-f2 product whilst gm5 and gm7 contribute tothe 2fi-f2 and 3fi-2f2 products and the 2fi-f2, 3fi-2f2 and 4fi-3f2

products respectively. For example, it may be shown that if we neglectthe gmn terms for n greater than 5, the intermodulation current is givenby

I2fl.h =0.25gm3A2B+0.25gm5A

4B

+0.375gm5A2B3

where

V =


Table 3.3 Polynomial Coefficients ofTransconductance* and DrainOutput Conductance**

Coefficient

9m1

gm2

gm3

9m4

gm5

gm6

gm7

gm8

G01

G02

GO3

GO4

Gos

GO6

GO7

Gos

Flat EPI

3.5 x 10~2

5.8 x 10"3

-4.5 x 10~4

3.3 x 10~4

1.46 x 10"3

5 x 10~5

- 2 x 10"4

5 x 10"6

1.64 X10"4

-3.07 x 10"5

1.13 x 10~5

-1.37 x 10"6

-3.92 x 10"7

5.8 x 10"8

6.2 X 10"9

-8.21 x 10"10

Profile ImprovedEPI

3.55 x 10"2

4 x 10"3

- 7 x 10"4

5.8 x 10~4

9 x 10"4

- 1 x10 " 4

- 1 x10 " 4

1.5 x 10~5

1.99 x 10"4

-4.19 x 10"5

5.18 X 10"6

7.62 x 10"7

-2.25 x 10~7

-8.47 x 10~9

5.4 x 10~9

-3.4 x 10"10

Ion Implant Se + Be

3.1 x 10~2

3.3 x 10"3

7.5 x 10"4

-5.4 x 10~5

- 2 x 10"4

4.2 x 10"5

4.48 x 10"5

-4.7 x 10~6

4.28 x 1 0 " 4

-4.9 x 10"5

-2.23 x 10~6

1.23 x 10"7

1.26 x 10~7

-2.02 x 10"8

2 x 10~9

-1.08 x 10"10

*gm(V) =gml

** Go(V) = Goi + G02V+G03V2 + G04V3 + . . .

Calculated IMD products are based on the usual two tone method. Thirdorder products have been calculated by Higgins and Kuvas (1980).Several conclusions have been drawn:

1. Optimum tuning and loading conditions change with signal powerlevel because of the corresponding changes in the admittance matrixof the device.

2. The IMD products are sensitive to tuning and loading since thepeak RF voltage levels will change with these two parameters.


3. At low r.f. input powers the IMD contributions from the Go(V)polynomial dominate.

4. At higher r.f. input powers the IMD products are due to both thegm(V) and Go(V) terms. A correlation exists between the gate anddrain voltage which are effective in the respective polynomials andthis results in a decrease in the IMD versus input level relationshipaccompanied by a steep rise in the IMD power output.

5. The sign of the fifth order coefficient relative to the third ordercoefficient contributes to the determination of the low signal levelIMD products. Cancellation effects can occur in third order IMDproducts from the drain (or gate) alone due to sign differences of thedifferent coefficients.

Figure 3.13 shows the calculated gain and third order intermodulationproducts versus input power using the active layer profiles of Figure3.12.

These IMD products have three regions. At very low signal levels thethird order products rise with a gradient of 3. In the second region thecancellation effects of 4. above are seen. In the region where the signallevels are becoming large the contribution from the gm(V) polynomial

15,

Sf 10CO

« 2 -20

40II -«S -60

-80

I -100

Idealized epitaxial• Implant• Flat profile

-30 -20 -10 0 +10

Input power (dBm)

Figure 3.13 Calculated gain and Third Order IntermodulationProducts Versus Input Power for the Three Profiles of Figure 3.12


COG

ain

rin

term

od

.W

.R.T

. car

rior

dele

veTh

ird

Pro

duct

15

10

5

u

20

40

60

80

lUO 40 -30

VDS = 6 V / ^ V ^^ ^ ^ ' ^ = 10V

-20 -10 0

Input power (dBm)

/J

+ 10

-

/

+ 20

Figure 3.14 Dependence of Gain and Intermodulation Distortion onDrain Voltage

dominates and the rate of rise of the IMD product is greater than 3. Thisis because gm5 > gm3 as shown by Table 3.3.

The dependence of IMD on drain bias level has also been calculated forthe implanted profile of Figure 3.12. The result of a rise in the drainbias level is a reduction in the Go coefficients with the resulting gainand third order intermodulation products of Figure 3.14.

3.6 Power FET Device Performance

The performance of GaAs power FETs is dominated by four items:-

(a) Gate width.

(b) Minimization of electrical parasitics, particularly the commonlead inductance.

(c) Reduction of the device thermal impedance.

(d) A device structure capable of high drain to source and gate todrain potentials.


Devices with excessive common lead inductance, for example, exhibitnarrow bandwidth capability, low gain and spurious oscillations at lowfrequencies.

3.6.1 Structures Used To Increase Gate Width

There are basically three techniques available for increasing total gatewidth. The first approach involves the parallelling of a number of gatefingers by the use of crossover structures which can utilize

(a) Dielectric crossovers

(b) Air bridge overlays

(c) Wrap around or edge plating.

Fujitsu (Fukata et al, 1976) and NEC (Higashisaka et al, 1980) usedielectric crossovers with SiO2 as the insulating material. The advan-tage of this technique is that it leads to a compact structure but resultsin additional parasitic capacitances at the crossover points. Deviceswith up to 26 mm total gate width have been fabricated using such atechnique (Figure 3.15). The source electrodes are all connected to alarge grounding electrode. The SiC>2 insulates the overlaid gate conduc-tors from the sources.

The air bridge overlay shown in Figure 3.16 is superior to the dielectriccrossover in that it has a lower capacitance/unit area. The air bridge isformed by first depositing a thick resist layer and then evaporating athin gold film. A second resist layer follows to define the bridge areawhich is then electroplated for strength. Finally the resist is removedleaving the bridge suspended in air as shown in Figure 3.16. Hence forthe same parasitic capacitance the air bridge overlay can have a largerarea leading to a reduced inductance per unit length as well as anincreased current handling capability. The processing requirement ofsuch a connection is also less than the dielectric crossover since bothdielectric deposition and vias (holes) through the SiC>2 to make sourceto source contact are no longer needed. Wrap around or edge plating ofthe chip is a low inductance approach because of the large peripheryconnection occurring between the source area and the ground plane.However, a crossover technique is still required to interconnect thevarious gate and drain fingers as shown in Figure 3.17.

The second approach simply involves wire bonding a number of FETcells in parallel. The device in Figure 3.18 has multiple source bondingpads and drain and gate pads. Devices as large as 9.6 mm for operation


DrainSource Gate Metal

Drain

Figure 3.15 Power GaAs FET Incorporating Crossovers (afterFukuta)

•

1•

1Figure 3.16 Air-Bridge Source Interconnections (Courtesy Plessy Co)


Figure 3.17 Wrap Around or Edge Plated Power FET

Figure 3.18 Wire Bonded 4 Cell Q3FET in BMH60 Package(Courtesy Plessy Co.)


Plated source Gate Drain

Figure 3.19 Flip Chip Mounted Power GaAs FET

at 9 GHz (Macksey et al, 1977) and 24 mm for operation at 4 GHz(Wemple et al, 1978) have been constructed in this way. Although themultiple bond approach uses a simpler processing technology, withplated-up drain contacts to remove the possibility of wire bonds touchingthe gate fingers, the device assembly is difficult.

The third approach is that first attempted by RCA (Drukier et al, 1975)and now used by MSC (Drukier et al, 1979) and Mitsubishi (Mitsui et

Figure 3.20 SEM Photographs showing "Via'Holes beforeMetallization (Courtesy Plessy Co. Ltd.)


Source Drain Gate VIAS

Figure 3.21 (a). Via Hole Source Connections for Power GaAs FET(b). Device Structure (Via Plating Technology) (CourtesyPlessy Co.Ltd.)


al, 1979) amongst others. This is the 'flipchip' mounting of the chip toproduce a very low inductance connection since the source pads areattached directly to the ground plane. The source pads are plated-up toprevent the ground plane contacting the channel areas (Figure 3.19).

D'Asaro et al (1977) introduced the Via-FET' approach where the sourceconnections to the ground plane are made through the semi insulatingsubstrate. Several laboratories are now using this technique, the gen-eral conclusion being that the Via-FET' gives significant increases inoutput power and gain although the saturated output power is un-changed. Figure 3.20 shows an array of'vias' approximately 50/* m indiameter, etched through a GaAs substrate which is of the order of 5Qamthick. Figure 3.21(a) shows the cross section of a typical via-FET whilstFigure 3.2l(b) shows a top view of an experimental device made byPlessey.

3.6.2 The Minimization Of Parasitics

The parasitic inductances in the gate, LG and drain LD of Figure 3.4(b)do not degrade the gain of the FET as much as the common source leadinductance Ls. Hence the maximum available gain under small signaldrive conditions can be approximated by

QQ

2.

§

Gai

nd

0

-1

-2

-3

-4

-5

-6

N. N. f = 4GHz

\ W = 300fym^ V U = 1.5Mm

0.05 0.1

Common-source inductance, U (nH)

^ ^

0.15

Figure 3.22 Effect of Common Lead Source Inductance on theMaximum Available Gain of a Power GaAs FET


Table 3.4 Effect of Source Lead Inductance on CombiningEfficiencies of Power FETs (Di Lorenzo et al, 1979)

Gain dB

4

One

chip 6

4

Four

chips 6

No. of Cells

1

4

1

4

1

4

1

4

POUT(watts)

0.91

2.88

0.83

2.14

0.96

3.72

0.87

3.39

PowerAdded

EfficiencyV(%)

25.6

24.1

31.8

19.9

39.3

36.8

45.3

40.0

VDS (volts)

8

8

8

8

8

8

8

8

CombiningEfficiency

(%)

79.1

64.5

96.9

97.4

f-I

' ! \ S + S +4jtfTCFB{2(RG + Rt + Rs +27ifTLs)

3.22

where fr is the cut-off frequency and f is the operating frequency, and allthe other parameters are defined in Figure 3.4(b).

For given device parameters, MAG falls off at a theoretical value of 6 dBper octave increase in frequency. Consider the effect of several shortbonding wires approximately 0.4 mm long which are typical of thelengths associated with the source bonds on power FET chips. Figure3.22 shows the result of calculating the effect of common lead inductanceon gain for a power FET of 3000/^m total gate width made up of twelvegates of 250/jm unit width (D'Asaro et al, 1977) at 4 GHz. It may be seenthat an inductance of only 0.1 nH degrades the MAG by over 4 dB.

The cell combining efficiencies (Macksey et al, 1978) of power FETsdepends significantly on the common lead inductance, Ls. This can beseen by inspection of Table 3.4 (Di Lorenzo et al, 1979) where 4 cell FETs


Test conditions

Symbol

•

•

a

Connection

Conventional

Conventional

VIA

VIA

V» =

Gatelength(Mm)

2

1.5

2

1.5

12V. f

Total

width(mm)

3

3

3

3

= 4GH2

Saturationoutputpower

(W)

1.65

185

1.65

1.65

-12 ^10 ^8 ^6 =4 ^2 6

Output power relative to saturation (dB)

(after DiLorenzo)

Figure 3.23 Power Gain for Conventional Wire Bonded andVia-Source Power GaAs FET

° § 29Q. ^

98

-o

Rn

0- —

= 24 dBm

50 100 150 200 250

Gate fingerwidth (microns)

50 %4 0 ?30 320 ©10 |0

300

• f = 6.4 GHz o —

(after Higashisaka.)

>f = 8.3 GHz

Figure 3.24 Microwave Performance of Power GaAs FETs VersusGate Finger Width


have been constructed either as one complete chip or as four bondedseparately, the latter giving reduced source lead inductance due to theeffectively shorter electrical path between the source electrode andground.

The via technique described in the previous section achieves this in amost efficient manner demonstrated by Figure 3.23 where a comparisonis made between a conventional power FET and a FET using via sourceconnections. It is seen that the measured power gain can be increasedby over 2 dB when the output power is 3 dB below saturation.

The effect of common lead inductance increases as the gate length isdecreased. This can be appreciated by inspecting equation 3.22 since asgate length is reduced fr becomes greater (fr « 1/LG) and thus theproduct of 2jrfrLs becomes more significant in comparison to the otherterms.

A gate much greater than A/10 in width will suffer from transmissionline effects and therefore it seems intuitive that such effects will reducedevice performance. Fukata et al (1976) have suggested, for example,that a ljum long gate should have a width no greater than 5Qum at 10GHz and 100/jm at 5 GHz. This assumption has, in fact, been found notto be true in practice. For example, measured performance for powerFETs with different unit gate widths where unit gate width is equal tototal gate width divided by the number of gate fingers is shown in Figure3.24 at 6.4 and 8.3 GHz (Higashisaka et al, 1980) for devices with a totalgate width of 3 mm. It may be seen that no significant degradationoccurs in power gain until unit gate widths approach 200/im at 8 GHz,i.e. a factor of 5 wider than the intuitive approach. Such a factor isextremely useful in keeping the overall FET chip width low.

The disagreement between the simple theoretical approach and experi-mental results is due to the difference between the assumed gatecapacitance and the real device capacitance, as discussed below.

Consider the propagation constants a and /} along the gate electrode tobe given by the following equations (Aono et al, 1979):

3.23

and

GaAs PET Theory-Power 109

tio

n(d

B)

Gai

n d

egra

da

0

-0.5

-1.0

-1 5C

\ 1 5

50 100 150 200

Gate finger width (microns)

(pF I^m)

^0.5

f :

250

x 10 3

= 6GHz= 1.4pH/nm= 4 x 10-2fi/Mm

Figure 3.25 Gain Degradation Versus Unit Gate Width as aFunction of Gate Capacitance

J + rJ/w2

3.24

where lg and rg are the inductance and resistance per unit gate width.

CGS dominates both equations 3.23 and 3.24. Fukata et al (1976) andAono et al (1979) have employed a CGS of 0.5 x 10~3 pF/jum, which wasobtained theoretically from Wolf's model (1970). However measuredvalues for ljum gate length devices puts CGS = 1.5 x 10~3 pF///m. Figure3.25 shows the way in which the gain of a device is degraded with unitgate width as a function of the CGs/unit gate width parameters.

It may be seen that there is a considerable difference between the twovalues quoted. This knowledge has, therefore, led to the design of FETswhich produce the same power and gain as previous devices but in achip area which is one half the area of the best previous device givingthe same performance.


Power gain of a power FET does not appear to be particularly sensitiveto gate length. For example, devices designed to operate at X band withtotal gate widths of 2.4 mm have virtually indistinguishable maximumoutput powers and gains with gate lengths of 1.8 or 2.6/jm. This maywell be due to the fact that there are many other effects masking theadvantages to be gained in reducing gate length some of these have beendiscussed in this chapter, including common lead inductance and unitgate widths.

3.6.3 Thermal Impedance

The GaAs MESFET, like many electronic devices, shows a deterioratingperformance as its operating temperature is increased. This operatingtemperature is determined not only by the ambient temperature butalso by the d.c. driving conditions and to a certain extent by the level ofthe microwave signal input to the FET. The temperature rise in the FETis treated by considering the thermal impedance between the channeland the heat-sink. This heat-sink might either be the package to whichthe FET chip is attached, the package then being attached to a part ofthe microwave circuit, or a carrier, for example, if the power FET is beingused in bare chip form.

The thermal properties of power FETs have until recently received littletreatment. A thermal model of a GaAs FET with a single gate fingerhas been shown by Cooke (1978) to be given by

3 - 2 5

where w is the unit gate width, K and K' are the complete ellipticalintegrals of the first kind, K* is the thermal conductivity of GaAs, and

where L is the gate length and t is the GaAs substrate thickness.Of course, L is much smaller than t so that K(k) and K'(k) can beapproximated to n/2 and ln(16t/;rL). As a result, equation 3.26 reducesto

3.27


gW - 6 m m

80 120 160 200 240 280 320 360Channel temperature (°C)

Figure 3.26 Measured Thermal Impedance of Power FET (afterFukui)

The thermal conductivity of GaAs for a doping level of around the mid1016cm"3 can be approximated by

= 5.6T-0.87 —1Z—mm)

3.28

in a temperature range of 70 to 220°C.

Substituting equation 3.28 into equation 3.27 yields

0.87 -1

L 3.29

Most modern FETs utilize a number of unit gate fingers. The overallthermal resistance would then be greater than (w/W) times the unit FET.(W is the total gate width). The total thermal resistance can be ex-pressed as:

3.30

The expression in equation 3.30 can be compared with experimentaldata. Figure 3.26 shows a typical result of plotting thermal resistanceof a FET chip in a microwave package against the operating channeltemperature. The thermal impedance increases as the channel tern-


I9I

io

Equ.(3.30)for

|t=«21/im

300 400 500 600 700Channel temperature (°K)

Figure 3.27 Channel Temperature dependence of ThermalResistances as a Function of Substrate Thickness

perature, Tch, increases as would be expected from equation 3.25 but asthe channel temperature continues to rise the thermal resistance startsto decrease. This is due to a substantial increase in the leakage currentflowing through the buffer layer (if present) and the substrate. Thedevice effective electrical volume is increased thereby causing redistri-bution of heat flow resulting in an apparent decrease in thermal resis-tance. Referring to Figure 3.27 the theoretical magnitude for thethermal resistance resulting from equation 3.30 is greater than themeasured results. This implies that the heat source adopted in Cooke'smodel is too small. Fukui (1980) has compared the theoretical treatmentwith experimental results and concludes that the effective heat sourcearea is actually about twice the gate barrier area. Figure 3.27 also showsthe measured values for three FETs having the same geometries (2micron gate length, 500 micron unit gate width, 6 mm total gate widthand 100 micron gate to gate separation).

The expression in equation 3.30 can be modified to fit the practicalresults with minor changes to its mathematical form. The thermalresistance can be expressed as


15 r

Equ.(3.32)

20 30 40 50 60 70Substrate thickness

Figure 3.28 Thermal Resistance as a Function of SubstrateThickness

3.31

where Tch is in degrees Kelvin, W is in millimeters, and L,t, and d are inmicrons, d being the gate to gate separation.Figure 3.28 shows the thermal resistance of a typical power FET havinga total gate width of 6 mm as a function of GaAs substrate thickness ata channel temperature of 200°C. The thermal resistances are measuredby taking FETs from the various parts of the same wafer which havebeen individually thinned down from the starting thickness. The dashedline in Figure 3.28 shows the agreement between equation 3.31 andexperiment. A much simpler expression can be used which is based onan empirical fit to measured results. This expression is

9 ^3.32

ch

which is applicable for t/d ratios of up to one.


FETs with different unit gate widths have been investigated by Fukuiand the results can be accommodated in an improved version of equation3.31

T 0.87— T 3.33

This last expression can be used for most power FETs of conventionalgeometries. It indicates that besides the utilization of thin substratesto decrease t, the thermal resistance of the FET can be reduced byincreasing the area of GaAs the device consumes and/or increasing thenumber of unit cells. These latter two techniques are particularly usefulwhen there is some reason for not decreasing the thickness of the GaAsfurther-for example, in a monolithic circuit where substrate thicknessaffects transmission line losses.

The thermal resistance of power FETs can be measured in a variety ofways:

(a) By using an infra-red microscope (Sechi et al, 1977);

(b) Nematic liquid crystals (Abbott et al, 1976); or

(c) Electrical pulse method (Fukui, 1980).

The first two methods are particularly useful as diagnostic tools. Forexample, infra red microscopy can be used to check whether the FET die

| o . 7

.j.0.6

| 0 . 5

5 0.4

•5 0.3

ate

! » • '

o 0

V s v Ig=1.2mA

\

1 1 1 1 1 1 1 1 1

) 40 80 120 160 200 240 280 320 360Channel temperature, TCH, °C

Figure 3.29 Gate Voltage of a Power FET as a Function of ChannelTemperature


has been effectively soldered to a package base for low thermal resis-tance by comparing with a reference device. However, such a techniqueneeds careful calibration. The third method determines FET channeltemperature by an electrical method by using the forward I-V charac-teristic of the gate Schottky barrier diode (Siegal (1977) and Fukui(1980)).

The I-V characteristic of a Schottky barrier diode can be related to itsoperating temperature by thermionic emission theory

^V> 3.34

where A* is the effective Richardson constant, T is the absolute tempera-ture, q the electronic charge, k is Boltzmann's constant, n the diodeideality factor, VBI the built-in barrier voltage and V the applied voltage.

Equation 3.34 can be expressed as

)

Figure 3.29 shows a typical measured variation of gate voltage, Vg versuschannel temperature, Teh, for a 6 mm wide FET with a nominal gatelength of two microns.

If the FET is driven at its drain by a pulsed voltage, Vds, with a dutycycle F, then the power dissipation, Pd, is given by

Pd = FVdsIs 3.36

where Is is the measured source current.

The channel temperature is determined from the value of Vg during thetime the drain pulse is off. If the temperature, Tp, of the package to whichthe FET is attached is also monitored n the total thermal resistance ofthe FET-to-package is given by


Source uaiei F I t

Drain

* —

- —

(a) Alloyed contacts

(b) Selective implantation

(c) Epitaxial with n+ contacts

(d) Recessed channel

- Active layer- Buffer layer

- S.I. substrate

\ \ \ \ \ \ \ \ - n* region

- n* layer

(e) Recessed channel with flat-source area

Figure 3.30 Various GaAs MESFET Structures


3.6.4 Source-to-Drain Burnout and Gate-to-Drain Avalanching

Equation 3.4 has shown the importance of gate to drain voltage on thepower handling capability of a power GaAs FET. Thus the performanceof the device in this respect will be determined by the gate-to-drain andsource-to-drain breakdown voltages. Much effort has been concen-trated, therefore, on the improvement of the breakdown characteristicsof power FETs by optimizing the structures, and materials used. Break-down voltages of over 70 volts have been obtained (Tiwari et al, 1979) todate with the theoretical promise of further improvements being possi-ble.

Figure 3.30 shows five kinds of GaAs MESFET structures that havebeen fabricated. The role of ohmic contacts in the drain-source burnoutis well established (Wemple, 1976). Carrier densities in the active layer

Table 3.5 Various Power FET Technologies Used to Produce HighBurnout Voltages

Company

NEC

Plessy

Mitsubishi

HP

Fujitsu

Bell

Technology

Recessed channel,No N+ EPI, EPIchannel

Recessed channel,N+ source anddrain, EPI channel

Recessed channel,graded profile

N+ inlaid sourceand drain islandsformed by ionimplantation,channel formed byimplantation

N+ inlaid sourceand drain islandsformed by selectiveepitaxial regrowthEPI channel

N+ EPI planarsource and draincontacts, EPIchannel

Ohmic Contact

AuGe/Ni

AuGe

Au/Ni/AuGe

NiCr/Ge/Au

AuGe

AuGe / Ag / Au

Burn out Voltage

22 to 25 Vat 100mA/mm

23 volts at 176mA/mm

>20V

>30Vat100mA/mm

>26Vat100mA/mm

Up to 52V at 100mA/mm


and the n+ contact layer are typically 1017 and 1018/cc respectively, witha buffer layer which has a carrier level of less than 1014/cc.

Figure 3.30(a) shows a planar structure having alloyed ohmic contacts.Figure 3.30(b) shows a similar structure but with n+ areas producedusing ion implantation under the source and drain contacts to decreasethe problem of avalanching and the resultant thermal runaway in thesubstrate. Figure 3.30(c) is an epitaxial version of Figure 3.30(b) withan n+, n, n~ layer system.

The structures in Figures 3.30(d) and (e) are of the recessed channeltype but do not have the n+ contact layer (Furutsuka et al, 1978). Figure3.30(e) allows closer source to gate spacing, than the fully recessedstructure of Figure 3.30(d) thus decreasing the source resistance andallowing simpler fabrication. Table 3.5 lists a summary of the contacttechnologies being used to improve source-drain burnout.

Bell Laboratories use the n+ contact technology achieving 52 volt source-drain breakdown at a current density of 100 mA/mm gate width whilstNEC who use the recessed channel technique of Figure 3.30(d) and (e)have achieved breakdown voltages of 25V at the same current rating.

However, not only does the source-drain burn-out voltage have directconsequences on the power handling capabilities of a FET structure but

IDS(mA)

150

125

100

75

50

25-k°0 2 4

V9.=0

s* ^-1

-2

T~-

-4

6 8 10 12 14 16VDS (Volts)

0

-1

— . "2

-3

-4

18 20 22

Slow-Sweep

Pulsed

Figure 3.31 Slow Sweep and Pulsed Characteristics of ShallowRecess Power GaAs FET


also the voltage at which the gate-drain avalanche process takes placeas seen by inspecting equation 3.4.

Wemple et al (1980) have recently shown that there is a correlationbetween the pulse gate-drain avalanche and the power added efficiencyof a power FET which is related to three parameters:

1. Avalanche current can be reduced by reducing the charge per unitarea in the active epitaxial layer;

2. By maintaining the smoothest possible gate edge structure; and

3. Reducing the drain bias voltage.

The first requirement implies that the gate metallization should beplaced in a recess etched to the zero-bias depletion depth. This alsoimproves the source-drain breakdown voltage provided the materialparameters are optimum.

Figure 3.31 shows the drain characteristics of a shallow recess powerFET measured with 8Qasec pulses.

Under such pulsed conditions these devices (White, 1980, private com-munication) typically withstand drain-source voltages of 35 volt beforefailure. Using a slow bias sweep, however, the drain current starts toincrease in the region where gate voltages would ordinarily pinch-off thechannel. This drain current increase is usually accompanied by lightemission. This breakdown phenomenon is not only due to gate-to-drainavalanching but is also due to current multiplication in the channel in

o0.5Q.

a

O

^ a• •

a

•

I

•

X9

a

•

O

m

0

1

GETIPlesseyMitsubishiFujitsuBell LabsRCA

x

10 20 30Frequency, GHz

Figure 3.32 Output Power per unit Gate Periphery ofFETs as aFunction of Frequency


the presence of deep electron traps in the buffer layer and also at then-layer to buffer interface. Ladbrooke et al (1980) have shown that theelectron trap densities (of the order of 1016 cm"3) found in the bufferlayers of VPE material based power FETs gave theoretical limitingoutput powers of 1 watt mm"* at gate-to-drain voltages of 40 volts whichis in reasonable agreement with the performance of good X-band powerFETs (Hughes, 1981, private communication).

3,7 Power FET Results

Considerable output powers have been achieved at frequencies up to 60GHz at which frequency Texas Instruments, for example, have achieved100 mW CW. At lower frequencies much greater powers have beenachieved with single-chip figures of greater than 20 watts CW.

Greater output powers can be obtained by prematching and combiningFET chips using internally matched structures within individual ce-ramic packages much as is done with bipolar transistors at lowerfrequencies. The frequency performance of power FETs tends to belimited by the ability to either match or uniformly feed the physicallylarge transistors as the frequency increases. In order to compare intrin-sic FET performance Figure 3.32 shows the figure of merit of outputpower per unit gate periphery as a function of frequency where it isindicated that the best reported power per millimeter of gate widthshows a factor of two decrease between 10 and 30 GHz at the time ofwriting. The average figure of merit is around 0.6 watts/mm. Withimprovements in layer growth, including the introduction of AlGaAslayers for higher frequency operation it is expected that 0.5 watts/mm

Table 3.6 Power Output Versus Total Gate Width for Power FETsOperated at 24V Source-Drain Bias (Di Lorenzo et al, 1979)

Gate Width(mm)

4

6

8

16

Output Powerat 3 dB gain

(watts)

4.2

5.4

7.2

13.5

Power/mm at3 dB gain

(watts/mm)

1.05

0.9

0.9

0.84

Gain at 106mW/mm Imput

(dB)

9.4

8.7

8.6

8.1

Output powerat 106

mW/mm Imput(watts)

3.6

4.7

6.2

10.7


will be achievable at 40 GHz in the near future. Recently Smith et al(1985) have reported 0.25 /im gate length MESFETs with 0.36watts/mm, power added efficiencies of 33% and power gains of 6 dB at30 GHz.

In Table 3.6 the results of a detailed study of the effect of overall gatewidth done by Wemple et al (1978) are shown. This table indicates thepower/mm gate width, the gain at approximately 100 mW/mm inputpower and the corresponding output power at that gain. It may be seenthat the degradation in gain is 1.3 dB when comparing the 16 mm and4 mm total gate width devices whilst the output power/mm gate widthfor 3 dB gain is reduced by approximately 1 dB. This dependence ontotal gate width observed at 4 GHz has also been noted on smaller gatewidth devices at 10 GHz (Wemple et al, 1977). The reasons for thegradual decrease in power added efficiency with device size at a givenfrequency is undoubtedly due to a combination of effects including thecommon lead effect, the inability to feed large transistors uniformly inphase and amplitude and the effect of circuit losses on the very lowdevice impedances presented by the very large gate width FETs.

3.8 Conclusions

Some remarkable strides have been made in power FET design andperformance over the last few years (Schellenberg et al, 1981, Pengelly,1985). Single FET chips with output powers of 25 watts CW have beenproduced at 10 GHz and a number of these have been contained withinsmall modules to produce 50 to 100 watt output powers. Power FETamplifiers are now being used in satellite applications to provide usefullives of 10 years or more. For example, Czec et al (1984) recentlydescribed 3.7 to 4.2 GHz 10 watt amplifier with over 60 dB gain and anoverall efficiency of 24%. Material profile improvements (White et al,1984) and the use of ion implantation into GaAs have also led toimproved intermodulation performance which is particularly useful formulticarrier communications systems applications. The power GaAsFET is now a firmly established member of the microwave solid statedevice porfolio and has been integrated successfully with other devicesinto GaAs monolithic microwave circuits (see Chapter 10).

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Aono, Y., Higashisaka, A. Ogawa, T. and Masegawa, F. X and Ku-bandperformance of submicron gate GaAs power FETs. Japan J. Appl. Phys.,Vol. 17, Supplement 17-1, pp. 147-152,1979.

Cooke, H.F. Microwave field effect transistors in 1978, Microwave J, Vol.21, No. 4, pp. 43-48, April 1978.

Czech, J., Khilla, A.M. and Schiinzel, M. A 10 watt C-Band GaAs FETpower amplifier for satellite down-link communications systems. Pro-ceedings of 14th European Microwave Conference, Liege, September1984,pp.lO6-lll.

D'Asaro, L.A., Di Lorenzo, J.V. and Fukui, H. Improved performance ofGaAs microwave field effect transistors with via-connections throughthe substrate. Int. Electron. Devices Meeting Tech. Digest, pp.370-371,December 1977.

Di Lorenzo, J.V. and Wisseman, W.R. GaAs Power MESFETs: design,fabrication and performance. IEEE Trans, on Microwave Theory andTechniques, Vol. MTT-27, No. 5, May 1979, pp. 367-378.

Drukier, I., Camisa, R., Jolly, S., Huang, H. and Narayan, W. Mediumpower GaAs field effect transistors. Electronics Letters, Vol. 11, pp. 104-104, March 1975.

Drukier, I., Wade, P.C. and Thompson, J.W. A high power 15 GHz GaAsFET. Proceedings of the 1979 European Microwave Conference,Brighton, England, pp.282-286.

Engelmann, R.W.H. and Liechti, C.A. Gunn domain formation in thesaturated region of the GaAs MESFET. IEEE Int. Electron DevicesConf. Digest, 1976, pp.351-354.

Fukata, M., Suyama, K, Suzuki, H. and Ishikawa, H. GaAs microwavepower FET. IEEE Trans. Electron Devices, Vol. ED-23, pp.388-394,April 1976.

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Fukui, H. Thermal resistance of GaAs field effect transistors. IEEEInternational Electron Devices Meeting Digest, 1980, pp.118-121.

Furutsuka, T, Tsuji, T. and Hasegawa, F. Improvement of the drainbreakdown voltage of GaAs power MESFETs by a simple recess struc-


ture. IEEE Trans. Electron Devices, Vol. ED-25, No. 6, June 1978,pp.563-567.

Higashisaka, A., Takayama, Y. and Hasegawa, F. A high-power GaAsMESFET with an experimentally optimized pattern. IEEE Trans, onElectron Devices, Vol. ED-27, No. 6, June 1980, pp. 1023-1029.

Higgins, J.A. Intermodulation distortion in GaAs FETS. IEEE MTT-SInternational Microwave Symposium Digest, 1978, Ottawa, Canada,pp.138-141.

Higgins, J.A. and Kuvas, R.L. Analysis and Improvement of Inter modu-lation distortion in GaAs power FETS. IEEE Trans, on MicrowaveTheory and Techniques, Vol. MTT-28, No. 1, January 1980, pp.9-17.

Hughes, A.J. private communication, 1981.

Ladbrooke, P.H. and Martin, A.L. Material and structure factors affect-ing the large-signal operation of GaAs MESFETS. Semi insulating III-VMaterials, Nottingham 1980, Shiva Publishing 1980, pp.313-320.

Lehovec, K. and Zuleeg, R. Voltage-current characteristics of GaAsJ-FETs in the hot electron region. IEE Solid State Electron. Vol. 13,pp. 1415-1429,1970.

Macksey, H.M., Adams, R.L., McQuiddy, D.N., Shaw, D.W. and Wisseman,W.R. Dependence of GaAs power MESFET Microwave performance ondevice and material parameters. IEEE Trans. Electron Devices, Vol.ED-24, pp. 113-122, Feb. 1977.

Macksey, H.M., Blocker, T.G. and Doerbeck, F.H. GaAs power FETs withelectron beam defined gates. Electronics Letters, Vol. 13, p. 312, May1977.

Macksey, H.M., Blocker, T.G., Doerbeck, R.H. and Wisseman, W.R. Opti-misation of GaAs power FET performance. 1978 Workshop on Com-pound Semiconductor Microwave M a t e r i a l s and Devices(WOCESEMMAD) Feb. 1978.

Macksey, H.M., Tserng, H.Q. and Nelson, S.R. GaAs power FET forK-band operation. ISSCC 1981 Digest of Technical Papers, New York,Feb. 1981, pp. 70-71.

Mitsui, Y., Otsubo, M., Ishii, T, Mitsui, S. and Shirahata, K. Flip-chipmounted GaAs power FET with improved performance in X to Ku band.Proceedings of the 1979 European Microwave Conference, Brighton,England, pp. 272-276.


Pengelly, R.S. Advanced FET technology. Microwave Exhibitions andPublishers Ltd. 1985, ISBN No. 09468215OX, pp.239-302.

Pucel, R.A., Hans, H.A. and Statz, H. Signal and noise properties ofgallium arsenide microwave field effect transistors. Advances Electronand Electron. Physics, Vol. 38, New York: Academic Press, 1975, pp.195-265.

Rizzoli, V., Lipparini, A. and Marazzi, E. A general-purpose program fornon-linear microwave circuit design. IEEE Trans. Microwave Theoryand Techniques, Vol. MTT-31, pp-762-770, September 1983.

Schellenberg, J.M. and Yamasaki, H. An FET chip-level cell combiner.ISSCC 1981 Digest of Technical Papers, New York, Feb. 1981, pp.76-77.

Sechi, F, Perlman, B.S. and Cusak, J.M. Computer controlled infraredmicroscope for thermal analysis of microwave transistors. IEEE Inter-national Microwave Symposium Digest 1977, pp. 143-146.

Siegal, B.S. A proposed method for testing thermal resistance of MES-FETS. Microwave Systems News, pp-66-70, Nov. 1977.

Shockley, W. A unipolar field effect transistor. Proc. IRE, Vol. 40, pp. 1365-1376,1952.

Shur, M.S. and Eastman, L.F. Current voltage characteristics, smallsignal parameters and switching times of GaAs FETS. IEEE Trans.Electron Devices, Vol. ED-25, pp.606-611, June 1978.

Shur, M.S. Analytical model of GaAs MESFETS. IEEE Trans. ElectronDevices, Vol. ED-25, pp.612-618, June 1978.

Smith, P.M., Chao, P.C., Mishra, U.K., Palmateer, S.C., Duh, K.H.G. andHwang, J.C.M. Millimeter wave power performance of 0.25jum HEMTsand GaAs FETS. Abstracts of Tenth Biennial IEEE Cornell Conferenceon Advanced Concepts in High Speed Semiconductor Devices and Cir-cuits, July 1985.

Sobhy, M.I. and Jastrezebski, A.K. Computer-aided design of non linearmicrowave integrated circuits. Digest of the International Solid-StateCircuits Conference, San Francisco, pp.80-87, February 1984.

Tucker, R.S. and Rauscher, C. Intermodulation distortion properties ofGaAs FETS. Electronics Letters, Vol. 13, p.509,1977.

Tiwari, S., Woodard, D.W. and Eastman, L.F. Domain formation inMESFETs-Effect of device structure and materials parameters. Pro-


ceedings of the 7th Biennial Cornell Electrical Engineering Conference,Cornell University, New York, 1979, pp.237-248.

Wemple, S.H. and Nichaus, W.C. Source-drain burn-out in GaAs MES-FETs Gallium Arsenide and Related Compounds (St. Louis), 1976,Institute of Phys. Conf. Series No. 33b, pp. 262-270.

Wemple, S.H. Nierhaus, W.C, Schlosser, W.O., Di Lorenzo, J.V. and Cox,H.M. Performance of GaAs power IIESFETS. Electron Lett. Vol. 14,pp.104-105, March 1975.

Wemple, S.H., Steinberger, M.L. and Schlosser, W.O. Relationship be-tween power added efficiency and gate-drain avalanche in GaAs MES-FETS. Electronics Letters, Vol. 16, No. 12, June 1980, pp.459-460.

White, P.M., private communication, 1980.

White, P.M., Van Rees, B. and Leonard, M.F. The effect of profile design,bias conditions and load impedance on intermodulation distortion inC-Band GaAs power FETS. Proceedings of 14th European MicrowaveConference, Liege, 1984, pp.821-826.

Williams, R.E. and Shaw, D.W. Graded channel FETS: improved linear-ity and noise figure. IEEE Trans. Electron Devices, Vol. ED-25, p.600,1978.

Willing, H.A. and De Santis, P. Modelling of Gunn domain effects inGaAs MESFETs. Electronics Letters, Vol. 13, No. 18, pp. 537-539,1977.

Willing, H.A., Rauscher, C. and De Santis, P. A technique for predictinglarge signal performance of a GaAs MESFET. 1978 IEEE MTT-S Inter-national Microwave Symposium Digest, Ottawa, Canada, pp. 132-134.

Wolf, P. Microwave properties of Schottky-barrier field effect transistors.IBM J. Research and Development, Vol. 14, pp. 125-141, March 1970.

Requirements and Fabrication of GaAs FETs

4.1 Introduction

The subject of material growth for GaAs FETs and the fabrication ofthose devices on the material thus prepared is far too extensive to becovered in detail in this book. Indeed the subject warrants a book in itsown right. However, a review is given in this chapter of the most popularmethods of material growth. These are namely, vapor phase epitaxy,liquid phase epitaxy, ion implantation and molecular beam epitaxy.Fabrication of MESFETs can be divided broadly into two techniques-firstly using recessed channels together with gate liftoff technology andsecondly the so-called self-aligned gate technology. Such fabricationtechniques can be adopted for both mesa and planar technologies de-pending on whether the FETs are isolated from the bulk semi-insulating(SI) GaAs by an etched step or by an isolation implant respectively.

4.2 Material Requirements

The four material technologies that have been used to produce highquality epitaxial material are: chemical vapor deposition (CVD) basedeither on chloride chemistry (Knight et al, 1965) or organometallicchemistry (Manasevit et al, 1969), molecular beam epitaxy (Cho et al,1977), liquid phase epitaxy (Rosztoczy et al, 1974) and ion implantation(Stephens et al, 1978). Well over 800 papers have been written on thesubject of GaAs and InP growth since 1960, with a sharp increase in theinterest in ion implantation since 1975 due to the increased emphasisin the use of this method of producing active regions for IC exploitation.

4.2.1 Epitaxial Layers

Considering the diagram of the GaAs FET in Figure 4.1, a GaAs bufferlayer is first grown onto the GaAs semi-insulating (SI) substrate. Thislayer has a high resistivity (approximately 107 ohm cm) and containsvery few mobile electrons. Consequently it acts effectively as an exten-


Source

'/////////AGate

X/////////A\ \ \ \ \ \ \ \ \ N

\ \ Active layer(n) \ \

\\w\\\vBuffer layer (n-)

^ \ \ ^ ^\ x S.I. substrate \ \ \

^ ^

Drain

V////////.

Figure 4.1 Schematic of Buffer Layer Approach to MESFETFabrication

sion of the semi-insulating substrate but protects the subsequentlygrown active layer from any deleterious effects due to the bulk substratewhich would otherwise occur.

The buffer layer and active layer are usually grown in a continuousepitaxial growth run. The incorporation of the buffer improves thesharpness of the carrier density profile and helps to maintain a highelectron mobility right up to the layer-substrate interface. Figure 4.2(a)shows a typical buffered epitaxial n-type layer having a peak carrierconcentration of approximately 6 x 1016 cm"3 and shows that the carrierconcentration drops to below 1015 cm""3 0.25/mi further into the materialthan the epitaxial layer Tmee' which occurs at a depth of approximately0.55jum. Figure 4.2b shows the marked difference that can be obtainedbetween the mobility profile of a non-buffered and buffered layer. Theseprofiles were obtained by measuring successively etched away surfacesusing a Van der Pauw Hall mobility technique (Van der Pauw, 1958).Such buffer layers markedly improve the noise figure, gain and otherproperties of FETs.

There are two crucial parameters relevant to the active layer-the mobil-ity of the active layer as a function of depth as well as the uniformity ofthe doping and thickness across the wafer. These factors affect thetransconductance of the FET device to be fabricated on the active layerparticularly as the drain current is reduced by applying negative gatevoltage. This is because as negative gate voltage is increased the

Requirements and Fabrication of GaAs FETs 129

101J

Expanded version of0 to 1 Mm region

0 1 2 3 4 5 6 7Depth Oim)

(a)

S.I.j substrate

(b)

0.4 0.8Depth ^m)

Figure 4.2 (a). Doping Profile of FET Structure (b).MobilityProfiles of GaAs Epitaxial Layers (after Butlin et al)

depletion region starts to extend beyond the knee of the level carrierconcentration. If the 'tail' of the profile, i.e. the region in which thecarrier level is decreasing is poor, i.e. the rate of change of carrier levelwith depth is low, the transconductance of the device will be correspond-ingly low. Also, if this 'tail' characteristic is not constant over the waferthen the gm will change from device to device. It is also desirable tomaintain the steepness of the tail right down to the SI background levelsuch that the gm of the device is maintained at a high level under biascurrents considerably less than IDSS (typically at low noise bias). Thetransconductance of the device has a strong influence on both the noisefigure and gain of the FET, as we have seen in Chapter 2, when the deviceis biased for minimum noise figure.

Figure 4.3 shows the transfer characteristics of two FET devices (Butlinet al, 1976) where device A has a buffer layer and the transconductanceis maintained at a high level to very low current values. Device B hasno buffer layer and it can be seen how the transconductance drops asthe drain current is decreased. The noise figure of device A was 2.5 dB


High-noise FET gm = 14mS

Low-noise FETgm = 14mS

Poor gm at 5mA (device B)

-Good gm at 5mA (device A)

-2.0 \ -4.0\ Gate-to-source voltage (volts)

d.c. gm = .dip. 15QMm gate width F E ? ^ ^ ^d V« (courtesv Plessev) ^ ^ ~ -

Figure 4.3 Transfer Characteristics of High and Low Noise FigureGaAs FETs

at 8 GHz whilst the noise figure of device B was 3.3 dB at the samefrequency. The uniformity of active layer doping level and the layerthickness will have a marked effect on the yield of the wafer whenprocessed for FETs since these parameters control the spread in drainsaturation current IDSS, pinch-off voltage, Vp, as well as the microwaveparameters of the device.

Figure 4.4. shows, the evolution of material structures used for FETs invarious companies worldwide using the vapor phase epitaxy technique.Initial structures were grown on n-type active layers on chromium (Cr)doped substrates (Figure 4.4a). Noise performance of these devices waspoor and soon a buffer layer was introduced (Figure 4.4b) to lower noisefigure and increase gain. Even lower noise figures and higher gainswere produced by introducing an n+ contact layer (Figure 4.4c) whichapart from improving ohmic contact resistance also gives a considerabledecrease in source to gate and gate to drain resistance with recessedgate FETs (Butlin et al, 1976) (Figure 4.4d). It was later discovered thatthe undoped high-resistivity buffer layers being used were high resis-tivity due to out-diffusion of unidentified acceptors from the substrate(Cox et al, 1976). Figure 4.5 shows the evolution of the profiles used to


SourceX//////y

(a)

pa

(c)

_ Drain_ Gatp -—__—___/j vjaie Y/j/yyy//

n-Active layer

S.I. substrate (Cr doped)

n * Contact

n

Buffer

S.I.

ayer

(b)

7777^

d)

n-Active layer

Buffer layer (undoped)

S.I. substrate

7 Y////A \n

Buffer

S.I.

Figure 4.4 Evolution of GaAs FET Structures

produce low noise FETs since the introduction of the MESFET some 20years ago (Di Lorenzo, 1977).

Figure 4.5(a) shows the basic device profile the performance of whichis aided by the introduction of buffer layers (Figure 4.5(b) and (c)).

Referring again to Figure 4.2(a) the background level of the layer dropsbelow 1013 cm"3 which allows the growth of a high resistivity buffer asrequired. If the thickness of the buffer is increased by extending thebuffer layer growth time, the profile of Figure 4.6 results where themajority of the buffer layer has the correct resistivity but that closest tothe active layer has a higher carrier level of approximately 8 X1014 cm"3.

The high resistivity region is due to out-diffusion of acceptors from thesubstrate which compensate the donor population of the buffer in thevicinity of the substrate. Thus for a good high-resistivity buffer layerthe acceptor level should be approximately equal to the uncompensatedbackground level at the active-buffer interface. Thus undoped bufferlayer quality can vary with the GaAs ingot used and even within a GaAs


1017

1013

10'

10

Q 1013

ActiveSubstrate

(a)

0.1 0.2 0.3 0.4

ActiveUndoped buffer

Depth (nm)

Substrate

(b)

0 0.1 0.2 0.3 Depth ( m)

Active Undoped/Cr doped buffer Substrate(c)

0.1 0.2 0.3 0.4 Depth ( m)

Active Undoped bufferCr-0 doped

buffer Substrate

(d)

0.1 0.2 0.3 0.4 Depth ( m)

Figure 4.5 Evolution of Profile Types for GaAs FETs

ingot. Thus undoped buffer properties are not reproducible withoutcareful condition monitoring. Tuck et al (1979) have reported a seriesof radiotracer experiments which suggested that Cr was the acceptorand more recent secondary-ion mass spectrometry results (Evans et al,1979; Huber et al, 1979) have confirmed this.

Although doped buffer layers suffer from the disadvantage that thedopant that is added to the system during buffer growth is an undesir-able impurity if it reaches the active layer, the advantage is that variablesubstrate effects can be dramatically reduced (Fairman et al 1979).Chromium doping of epitaxial GaAs to form SI layers was first reportedby Mizumo, Kikuchi and Seki (1971). Resistivities in excess of 108 Q cmwere obtained. Kato et al (1979) reported results with MESFETsfabricated on Cr doped GaAs having similar performances to those madeusing undoped buffers.


10"

10 1 6

Buffer knee

Buffer layer—H\ S B u f f e r l a y e r H\ Substrate—* ^r-High resistivity-^)

2 3 4Layer depth fcm)

13 14

Figure 4.6 Doping Profile of GaAs FET with Buffer Layer ShowingKnee (After Di Lorenzo)

Drukier et al (1975) have also reported improvements in gain and poweroutput of MESFETs when Cr-doped buffers were used. Fairman (1979)has recently produced semi-insulating layers using a halide transporttechnique with final sheet resistances for the buffers in excess of 109

ohms per square exhibiting excellent thermal stability.

The effect of a Cr doped buffer layer of the correct thickness can becompared to undoped buffer layers by reverse biasing the substrate withrespect to the buffer layer. This can be achieved by using a mercuryprobe Schottky contact (Bonnet et al, 1980). The mercury contact(Figure 4.7) is reverse biased with respect to the mercury ring.

The carrier concentration is measured at 0 volts and —25 volts, forexample, and for the undoped layer where a space charge develops atthe interface between the active layer and the buffer the carrier profilechanges (Figure 4.8(a)). It may be seen from Figure 4.8(b) that the effectis reduced considerably for a 4/jm thick chromium-doped buffer layer.The main advantage of the chromium-doped buffer layer is to suppresssubstrate effects provided the buffer is greater than 3^m thick. Refer-ring to Figure 4.5(d) the latest technique reported by Di Lorenzo et al(1979) is to also incorporate an undoped buffer layer between the Crdoped buffer and the active layer to isolate the active layer from Cr traps.


cooplotter Mercury probe.

Mercury ring

S.I. substrate

ISubstrate bias

Figure 4.7 Reverse Biased Substrate C(V) Measurement

7o.

g 1017

?

'co

nce

ni

Car

riei

10*

\\

-25v\

) 0.1Depth (ym)

(a)

\ °\ov .11°17

rat

con

cen

t

o

Car

rier

0.2

V>

-18'

0.1Depth ( m)

(b)

| ,\\ov

\

\

0.2

Figure 4.8 Carrier Concentration Versus Depth of FET Structureswith (a) 0.5jum Undoped Buffer and (b) 4jum Chrome Doped Buffer


4.2.1.1 Vapor Phase Epitaxy

Epitaxy refers to the growth of a material on a substrate which in thisparticular case is the same material. Preparation of films of solidmaterial by chemical vapor transport techniques involves the transferof the material to be deposited from a source zone in the form of gaseousspecies of limited stability into a deposition zone where these gaseousproducts are made to react (by controlling the temperature of the zone)to form the compound which is deposited on the desired substrate.Various techniques have been developed which may be divided into:-

1. The use of GaAs as the source with some transport agent, and

2. The use of Ga and/or As with other elements and a carrier gas.

Chloride Transport Process. In the chloride transport techniqueGaAs is made to react with HC1 gas at a temperature of approximately800°C in a closed quartz tube so that gallium monochloride and elemen-tal arsenic are produced, thus:

4 GaAs + 4 HCl -* 4 GaCl + As4 + 2H2

These products are transported along a temperature gradient in afurnace and GaAs is deposited at the cool end, thus

6GaCl + As4 Z 4GaAs + 2GaCl3

Moest and Shupp (1962) have deposited epitaxial GaAs using such aprocess with film thicknesses up to 2jum with thickness variation lessthan 10%.

The Arsenic Trichloride Process

In the AsCl3-Ga-H2 open flow system a reaction first takes place betweenAsCl3 and H2 being accomplished at temperatures greater than 425°Cso that HCl gas is formed, thus:

4AsCl3 + 6H2 -* 12HCI + As4

HCl is made to react with a gallium source at approximately 800°Cresulting in GaCl which is transported to the deposition zone whereGaCl and arsenic react to form GaAs, thus

2Ga + 2HCI -> 2GaCl + H2 (source zone)

6GaCl + As4 Z 4GaAs + 2GaCl3 (deposited zone)


Knight et al (1965) used an open tube flow system schematically shownin Figure 4.9 and this system has become very popular (Eddolls, 1966;Bobb et al, 1966; Wolfe et al, 1970; Cairns et al 1968; Nozaki et al, 1974).The equipment is usually made from high purity quartz (for hightemperature zones) and pyrex for the auxiliary systems.

High purity material is readily grown with such a system where thebackground level of undoped layers grown (e.g. for buffer layers) is foundto decrease with increasing AsCh molecular fraction (Cairns et al, 1968).

Thermodynamic calculations of this type of transport system indicatethat the most probable source of background contamination of undopedlayers is Si from the quartz walls and other hardware transported aschlorosilanes.

As may be appreciated from Figure 4.9 the AsCl3 gas is passed througha single bubbler but considerable versatility can be produced by intro-ducing a second AsCls bubbler (Cox et al, 1976; Hewitt et al, 1976). Aschematic diagram of this system is shown in Figure 4.10.

ASCI3/H2 from the main bubbler passes over the gallium source. Theflow from the second bubbler is introduced into the reactor between thesource and the substrate at a high flow rate to produce an in-situ etchof the substrate prior to epitaxy thus improving the interface. This flowis also used at a slower rate during the growth of the undoped buffer.

v

57

t

Zoneiprimary

(optional)

*

1 Zone 2 1 Zone 3| source11

AsCk H2>ubbler purifier

substrate

H

Trap

Figure 4.9 Typical Arrangement for a Single Bubbler AsCl3-Ga-H2Open Flow VPE System


Y//////////////////////,

Substrate position

1Exhaust/

Furnace

H2S/H2

Figure 4.10 Typical Arrangement for a Two-Bubbler AsCl3-Ga-H2VPE System

H2S/H2 mixture is admitted to the reactor for doping of the active andn+ contact layer if the latter is required. Flow rates in productionequipments, for high material uniformity, are controlled by mass flowcontrollers and the control of gas valves, furnace temperatures etc. ismicroprocessor controlled. Such actions have led, for example, to largesubstrates of 40 cm2 being grown with a standard deviation of 1% or lessbeing obtained for the saturated drain current of processed FETs(Komeno et al, 1979).

The Metal Alkyl-Hydride or Organometallic Technique

Over the past few years a number of workers (Ito et al, 1973; Hallais etal, 1978; Rai-Choudbury, 1969) have developed an alternative vaporsystem using metal alkyl vapors and the group V hydrides for manyIII-V compounds. The basic reaction is an irreversible pyrolysis whichtakes place on a heated substrate, thus:

GaiCHi). + AsH3 -> GaAs + 3CH4

This is the analogue of the silane reaction used to produce epitaxialsilicon.


The alkyl system has a number of advantages over the chloride trans-port system. As all the reactants and dopants can be in the vapor phaseand only the substrate is heated the equipment is much simpler and istherefore capable of faster turn around time. Because adding smallamounts of gases in the gas stream can be readily achieved the GaAsstoichiometry can be varied. Since the system requires a lower growthtemperature than the AsCl3-Ga-H2 system, dopant diffusion is lower andn to semi-insulating interfaces are sharper. GaAs is doped n-type byadding small amounts of hydrogen sulphide into the gas stream of thebasic reactor shown in Figure 4.11. Figure 4.12 shows the doping levelas a function of sulphur temperature used to generate the H2S and theH2S partial pressure for a number of GaAs layers (Bass 1975).

Morkoc (1979) has reported 1.5/nn gate length FETs fabricated onorganometallic grown layers with noise figures of 3 dB and associatedgainsof5.5dBat8GHz.

4.2.1.2 Liquid Phase Epitaxy

All the techniques discussed so far involved deposition of the compoundfrom the vapor phase. Liquid phase epitaxy has also received consider-able attention (Holger et al, 1966; Morkoc et al, 1979) and both undopedand Cr doped high resistivity layers have been grown using this tech-nique. Low doped layers grown by LPE have high resistivity regions

Coolingwater

Inductioncoil

Water cooledenvelope

H2 + AlkylThermocouple

Liner

Graphitepedestal

Filter and exhaust

Figure 4.11 Reactor for the Epitaxial Growth of GaAs by theOrganometallic Process


Figure 4.12 Dependence ofn-type Doping on Sulphur Temperature

near the substrate, presumably caused by acceptor compensation as inVPE growth. These high resistivity regions have been successfully usedfor MESFET structures by Nanishi, Takahei and Kuroiwa (1978) andKim et al (1979) who found that the active layer mobility and deviceperformance improved with the use of buffer layers as with VPE.

In LPE a saturated solution of GaAs in gallium is brought in contactwith the substrate and allowed to cool slowly whence the GaAs isdeposited on the substrate. A simple equipment is shown in Figure 4.13.

It consists of a silica furnace containing a silica boat which has a GaAs"seed" at one end and the gallium-GaAs mixture at the other. TheGa-GaAs mixture is brought to a temperature of 850° -900°C uponwhich GaAs dissolves in gallium and a saturated solution is formed. AN2 + H2 atmosphere inside the furnace is maintained to avoid oxidationof the Ga. The molten gallium-GaAs solution is made to run onto theGaAs substrate by tilting the furnace and the furnace temperaturelowered to allow crystallization of the GaAs on the substrate. AlthoughLPE is simple in principle it requires very critical control of the condi-tions to produce reproducible layers and for this reason it has not becomepopular as a production source of GaAs.


Quartzwindow

GaAs melt

Furnace

Silica tube

Thermocoupletube

Figure 4.13 Typical Equipment for Liquid Phase Epitaxy of GaAs(After Bolger)

4.2.1.3 Molecular Beam Epitaxy

The rapid development in microwave FETs fabricated on molecularbeam epitaxial (MBE) material has come about because this methodprovides well controlled film thickness, steep doping profiles, goodcomposition and an exceedingly smooth surface (Luscher, 1977).

The basic MBE process achieves epitaxial growth in an ultra highvacuum (UHV) environment through the reaction of multiple molecularbeams of differing flux density and chemistry with a heated singlecrystal substrate. The process is schematically illustrated in Figure 4.14which shows the essential elements for MBE of GaAs.

Each furnace contains a crucible containing one of the constituentelements. For example, Sn is used as an n-type dopant whilst Mn is usedas a p-type dopant for FET buffer layers. The temperature of eachfurnace is such that the vapor pressures of the materials are highenough for free evaporation of thermal energy molecular beams to takeplace. The furnaces are so arranged that the central portions of the beamflux distributions intersect at the substrate. Choice of furnace andsubstrate temperatures as well as control of the beams by shuttersbetween the furnaces and the substrate allow epitaxial films of the


GaAsY//////

Ga

MonocrystalSubstrate

N Molecular Beam

N \ y Shutters

Furnaces

Figure 4.14 Schematic Diagram of a MBE System for the Growth ofDoped GaAs

desired chemical composition to be produced. Growth rate is determinedby the rate of arrival of the group III elements while the condition ofstoichiometry is satisfied simply by growing in an excess flux of thegroup V elements.

One of the distinguishing characteristics of MBE is the low growthrate-approximately 1/um per hour or one monolayer per second. Themolecular beam at the substrate can therefore be readily modulated inmonolayer quantities in times below one second. Because MBE takesplace in UHV 'in situ' analytical instrumentation is possible such asmass spectrometry, Auger spectroscopy for surface analysis and secon-dary ion mass spectrometry.

Epitaxial films for both low noise (Bandy et al, 1979; Cho et al, 1976;Cho et al, 1977) and power FETs (Cho et al, 1977; Wataze et al, 1978)have been grown by MBE. Noise figures of 1.5 dB with 15 dB associatedgain at 8 GHz have been reported by Bandy et al where the materialwas grown using Sn as the dopant. Wataze et al have reported powerFETs having power outputs of over 4W with linear gains of 5.4 dB at 8GHz using Si doped MBE epitaxial layers. Hysteresis is often presentin the d.c. characteristics of FETs grown by other techniques without ahigh resistivity buffer layer between the Cr doped substrate and thechannel. This hysteresis, attributed to the alternate filling and empty-


ing of interface states, is not observed in FETs fabricated on MBEmaterial indicative of a higher quality interface. MBE has some impor-tant attractions for future microwave transistor devices such as theGaAlAs FET and other structures requiring highly doped n and p-typelayers. For these reasons MBE is likely to play a more important rolein the future in ICs rather than in discrete FET production and certainlythere are no FET production facilities which use MBE to grow layers, atthe present time.

4.2.2 Liquid Encapsulated Czochralski Growth

In 1962 a simplification in the growth of GaAs was made by the use ofliquid encapsulation techniques (Metz et al, 1962). In this method themelt from which the crystal is pulled is immersed under an inertencapsulant which confines the volatile constituents and simplifies theequipment. GaAs is now grown routinely using the LEC method(Caruso et al, 1972; Au Cain et al, 1979; Ware, 1979). The LEC processessentially requires a Czochralski growth furnace which can be pressur-ized to approximately 1 atmosphere with nitrogen used as the ambient

The LEC process is represented in Figure 4.15 where the crucible andsusceptor assembly are charged with polycrystalline GaAs and encap-sulant lumps prior to heating. Also shown is an illustration of theassembly during growth.

Lumps ofpure encapsulant

Graphitesusceptor

' or cup

Polycrystalline-charge of

GaAs

Quartzcrucible

Seed holder

^Growing ingot

Encapsulant

GaAs melt

Before growth During growth

Figure 4*15 The Liquid Encapsulated Czochralski Process


The fabrication of the crucibles and susceptors is important to the purityof the ingot. The encapsulant for the growing ingot must be inert,transparent, have a low melting point, be of high purity and be less densethan the melt. For these reasons boric oxide (B2O3) has become popularas an encapsulant.

After the charge is melted at 1240°C a cooled 'seed' is lowered into themelt through the encapsulant and it is then slowly withdrawn at acarefully selected temperature at which nucleation and single crystalgrowth occur on the seed. Since the withdrawn seed and ingot are coatedin B2O3 the evaporation of arsenic from the ingot is minimized.

4.2.2.1 Dislocation free wafers

Recently it has been shown that crystal defects caused by dislocationshave the most detrimental effect on the uniformity of threshold voltagesof ion-implanted FETs.

Adding or mixing large amounts of In or InAs to GaAs (0.1 mole.% toapproximately 0.4 mole.%) is considered to be effective in suppressingthe generation of microdefects which are responsible for the formationof dislocations. Tada et al (1984), following on from work by Jacob et al(1983), have produced semi-insulating GaAs single crystals mixed withIn or InAs which showed dislocation free (DF) areas of about 40% of thewafer with a diameter of 65 mm. The threshold voltages of FETsfabricated on DF-GaAs wafers have been evaluated by a number ofworkers (Ohmori, 1984). For example, Tada et al (1984) have fabricatedFET channel layers by implanting 28Si + with 180 keV and 50 keV fordepletion mode (normally-on) and enhancement mode (normally-off)FETs respectively. The FETs had a gate length of I micron and a widthof 5 micron. The distance between the source and gate and between thegate and drain was 2 micron, with the gate direction parallel to the<110> crystal axis. The FETs were arranged in a matrix with a separa-tion of 200 microns. Figure 4.16(a) shows the mean threshold voltageand standard deviation for each cell, all of which contained 100 depletionmode FETs in a region 2 x2 mm (the total number of cells being 379).Data for conventional undoped GaAs is given in Figure 4.16(b) showingthat there is a much larger distribution of parameters than in theDF-GaAs.

The data for the uniformity of enhancement mode FETs is shown inFigure 4.17. The mean threshold voltage of 625 FETs in a 5 mm squareregion was -22 mV with a standard deviation of 13 mV which is much


D-FETs on DF-GaAs wafer

300

- 2 0 0X

b100

o

379 data points

-

-

-2.0a

-1.0VTH(volt)

E

b

D-FETs

300

2 00

100

o

379

-

- v.;'!:

-2.0b

on normal wafer

data points

-1.0VTH (volt)

Figure 4.16 VTH and dVTHfor Depletion Mode FETs on DF-GaAs(a) and Conventional LEC GaAs (b) (after Tada et al, 1984

smaller than that in conventional LEC GaAs (typically of the order of50 to 100 mV).

Thus for both depletion mode analogue and, more importantly, enhance-ment mode digital GaAs ICs where d.c. coupled circuits are employedso-called dislocation-free wafers are starting to offer significant advan-tages over conventional LEC material leading to larger levels of inte-gration.

200

- 1 0 0

0

-

-1.0

E-FETs on DF-GaAs

373 data points

i -**,-.-.'* ^-0.5 0 0.5

7^" (volt)

Figure 4.17 VTH and oVmfor Enhancement Mode FETs onDF-GaAs (after Tada et al, 1984)


4.2.3 Ion Implantation

Because of the increasing use of GaAs FETs in microwave systems andthe introduction of GaAs integrated circuits requiring large areas ofuniform material, high yield and reproducible material preparationmethods have become a primary concern. A major breakthrough hasbeen accomplished in this respect by developing ion implantation intobulkgrown substrate material as a viable approach for preparing thevery thin active layers.

Ion implantation is a process whereby controlled amounts of chosenforeign species can be introduced into the near surface regions of theGaAs in the form of an accelerated beam of ions to form active layerswith defined profiles. The principal advantages of ion implantation are:

(1) The total amount and purity of material implanted can beaccurately controlled and monitored.

(2) The concentration of impurities as a function of depth can becontrolled by means of the ions' energy.

(3) Implanted ions enter the surface usually as a well directed beamso that a very high lateral definition of the doped region can beachieved using conventional lithographic masking techniques. Thisleads to the lack of any need to produce a mesa structure for FETssince either the SI substrate produces isolation or a proton, say,implant can be used for device to device isolation in GaAs integratedcircuits.

(4) The process is very versatile and a single implantation facilitycan be used with a range of ion species.

(5) The process can be controlled automatically with a large through-put rate giving uniformities determined by the host material.

The large energy transfer of the ions as they give up their energy to theatoms of the target material occur as elastic recoils which disrupt thecrystalline structure where the distribution of damage along the iontrack varies considerably with the mass of the ion. A region of disorderoccurs but this can fortunately be restored by thermal annealing.

In order to employ ion implantation into semi-insulating GaAs sub-strates for device fabrication it is important that the doping producedby implantation not be affected by changes in the substrate. This leadsto a need to qualify the substrate material. Some SI substrates convertto either p-type or n-type following high temperature annealing even in


the absence of implanted ions. One qualification test consists of im-planting the qualification sample with argon or krypton, then annealingat, typically 800 to 900°C for 15 to 30 minutes. A qualified SI substratedoes not convert after this test.

One of the major problems of ion implantation into GaAs is that thematerial begins to dissociate at the commonly used anneal temperaturesof 800°C to 1000°C. To prevent problems caused by dissociation, it iscommon practice to use an encapsulant such as SiO2 (Foyt et al, 1969),Si3N4 (Harris et al, 1972), A12O3 (Chu et al, 1973), A1N (Pashley et al,1975) or Al (Sealy et al, 1974). Capless annealing has also become apopular method where an arsenic overpressure is maintained to preventdecomposition of the GaAs.

Development of horizontal Bridgman and gradient freeze technology forLED applications has not been found particularly advantageous for thegrowth of SI GaAs for FETs. The resulting electrical yields for ionimplantation into Bridgman grown material is low. GaAs ingots grownin the <100> direction by liquid encapsulated Czochralski methods haveshown considerable promise. Workers as early as 1965 (Mullins et al,1965) have shown the virtues of the B2O3 encapsulation technique.Weiner, Lassota and Schwartz (1971) were the first to show the relation-ship between silicon contamination and the thermal stability of undopedsemi-insulating GaAs. Recently Swiggard and Henry (1977) and Rum-sby (1979) have demonstrated the merits of the LEC method. Thedissociation of the volatile As from the GaAs melt, which is contained ina crucible, is avoided by encapsulating the melt in an inert molten layerof boric oxide (B2O3) and pressurizing the chamber with a non-reactivegas, such as nitrogen or argon, to counterbalance the As dissociationpressure.

With the recent introduction of the Melbourn high pressure LEC puller(manufactured by Metals Research, England) 'in'situ' compound synthe-sis can be carried out from the elemental Ga and As components. Theattainment of low background doping levels has led to the growth ofhighly uniform 'undoped' crystals of up to 75 mm diameter.

4.2.3.1 Carrier Concentration and Mobility

Successful ion implantation has resulted from the use of 28Si, 32S, Se and29Si for n-type layers. The choice of ion species depends to a certainextent on the implant energy available and the fluence chosen.


Figures 4.18 and 4.19 show, for example, the carrier concentration aidmobility profiles of two implanted samples, one using 200 keV 32S andthe other using 70 keV 28Si at a much higher fluence (Lui 1980).

Post implant annealing was done at 825°C for 20 minutes in both casesusing capless annealing. The profile of Figure 4.18 shows a maximumcarrier concentration of 2.4 xlO17 cm"3 with a mobility which variesfrom 3000 cm2 V"1 s"1 at the surface to over 4000 cm2 V"1 s"1 towardthe SI substrate. For the higher dose example, the average mobility andpeak carrier concentration of the wafer are 1800 cm2 V"1 s"1 and 1.8XlO18 cm-3.

The Hall mobility of the implanted layer is given by

RsVH = —

Ps4.1

where Rs is the Hall coefficient andps is the sheet resistance. The Hallcoefficient is given by

Y24

BI4.2

13

S-implant

200 KeV energy

1x1013 cm-2 fluence

825° C anneal

0.1 0.2 0.3

Depth ( m)

0.4 0.5

Figure 4.18 Carrier Concentration and Mobility Profiles of aImplanted Sample (after Liu et al)

32C


7o

ion

i=

ncer

8E8

1 0 1 9

10"

10"

10 1 6

/ \

/ ^y\

11

• i • •

0.1 0.2Depth ( tm)

•

•

•

•

In2000>

1000 o600 £•400 |200 1

0.3

Si-implant

70 KeV energy

1 x 1015cm~2 fluence

825°C anneal

Figure 4.19 Carrier Concentration and Mobility Profile of a SiImplanted Sample (after Liu et al)

where I13 is the current, B is the magnetic flux density applied perpen-dicularly to the surface of the sample and AV24 is the voltage changewith and without the magnetic field. The subscripts correspond to thefour ohmic contacts (Van der Pauw, 1958). The sheet resistance, ps isgiven by

{{l12

4.3

where F is a geometrical correction factor. Using Equation 4.1 the sheetcarrier concentration Ns is given by

14.4

where q is the electronic charge (1.6 xlO"19 coulomb). The activationefficiency for an implanted and annealed sample is given by

rj =N

4.5

where Ns' is the fiilence used.


Carrier concentration can be approximately determined using

4.6

where ARp is the standard deviation of the projected range. Table 4.1shows for example the range and standard deviation on that range for32S and 28Si ions implanted into GaAs at particular energies.

From the above equations and data it is possible to evaluate the mobilityversus carrier concentration for a particular implant. Figure 4.20 showsthe result for a 28Si implant where a carrier concentration of 1017/cccorresponds to a mobility of 4500 cm2 V"1 s"1.

The equivalent carrier concentration as a function of implant dose canalso be plotted at a given energy (Figure 4.21). It may be seen that carrierconcentration varies almost linearly with fluence for fluences between2.5 X1012 and 2 X1013 for Si implants and that the carrier concentrationincreases at a much slower rate at high fluences. Also there is noelectrical activation at fluences lower than 1012 cm"2 for 200 keVimplants the limit depending to a certain extent on substrate quality.This cut-off behavior is not fully understood.

Table 4.1 Projected Range and Straggle Statistics for 32S and 28SiIons Implanted into GaAs

32S into GaAs

Energy(KeV)

10

50

100

200

300

400

800

1000

ProjectedRange, Rp

(am)

0.0102

0.0395

0.0758

0.1515

0.2279

0.3029

0.5919

. 0.7219

StandardDeviationARP (^m)

0.0078

0.0194

0.0337

0.0578

0.0778

0.0942

0.1423

0.1580

28Si into GaAs

Energy(KeV)

10

50

100

200

300

400

800

1000

ProjectedRange, Rp

(am)

0.0111

0.0441

0.0861

0.1732

0.2582

0.3421

0.6549

0.7941

StandardDeviation,ARP (am)

0.0105

0.0221

0.0383

0.0646

0.0855

0.1024

0.1488

0.1638


in7

Mob

i8000

6000

4000

2000

-w

1015

^^v. x Experimental points

\

1016 10" 1018 1019

Free electron concentration (cm-3)

Figure 4.20 Mobility Versus Carrier Concentration for Si Implantedinto GaAs

7

cg

1

rier

con

cei

a

1 0 1 9

1 0 1 8

10 1 7

10 1 6

-

-

10 1 2

y

1 0 1 3

y •

1014

Dose (cm-2)

•

• Experimental points

10'5

Figure 4.21 Carrier Concentration as a Function of ImplantationDose for Si Implantation into GaAs


4.2.3.2 Cr-Redistribution

Conventional (i.e. Si3N4 or SiC>2) as well as capless annealing techniquescan induce Cr depletion in the region near the GaAs surface. In thisdepleted region the Cr concentration may drop below the residual donorlevel allowing them to contribute to the electrical profile of the implant.Secondary ion mass spectrometry (SIMS) has been used to determinethe atomic redistribution of sulphur and chromium, for example, in 32Simplanted SI GaAs as a function of fluence, energy and annealingtemperature Figure 4.22 shows the as-implanted sulphur profile for a300 keV, 4 X1015 cm"2 32S implant into SI GaAs as well as the 32S profileand 52Cr profile for the annealed material. This figure demonstrates thebasic results of the Cr redistribution.

After thermal processing the Cr depletes in the outer 2/*m of the GaAsand piles up in the encapsulant-GaAs interface. Cr shows two distinctpeaks in and around the projected range, Rp, of the S implant. This isthought to be due to Cr taking up positions in damaged lattices due tothe implantation. Figure 4.23 shows the effect of Cr redistribution as afunction of 32S fluence at a constant 300 keV implant energy. Concen-tration of Cr at the surface is also a function of annealing temperature.

Thus, the carrier concentration profile of implanted and annealed GaAswill depend on the substrate used. This dependence can be very dra-

o<

^S-300 KeV energy 4 x 1015crrr

52Cr after anneal

0.5 10 1.5Depth ( m)

2.0

Figure 4.22 Thermal Redistribution ofS and Cr in Si GaAs (afterEvans et al)


o

Ato

m d

ensi

ty1019

1018

1017

1016

r

1 /\/V-4x10'5cm-J

\*y<^^ X 1 2

Cm

0 0.2 0.4

-300 KeV energy

^

0.6Depth &im)

_————

i

0.8

in— —

1.0

Figure 4.23 Thermal Redistribution ofCr as a Function of SImplantation Fluence

o

11011

10"0.2 0.4

Depth ( m)

Bulk(5x10*Crcm-3)

Bulk (1016 Cr cm-3)

High purity bulk

High purity LPE

500 KeV energy6 x1012 cm-2 fluenceAnnealed at 850° C

0.6

Figure 4.24 Carrier Concentration Profiles for Various SeImplanted GaAs Samples


matic in cases where there is a high background impurity level. Figure4.24 illustrates some of the effects. The high purity bulk substrates weregrown by Hewlett Packard (For, private communication). This materialhad very low impurity concentration with no Cr added to produce thesemi-insulating properties. Profiles obtained using high purity LPEsubstrates are seen to be very similar. However, ingots containing theCr content shown exhibit a marked difference the effect being greaterthan that predicted by the level of the Cr concentration due to the Crpile-up in the implant damage region as explained above.

Figure 4.25 (Stolte, 1980) shows the results of long-term investigationson the mobility of implanted wafers from different substrates measuredat room temperature and at 77°K for standard Se implants and annealconditions.

The high purity LPE samples give mobilities greater than 4000 cm2 V"1

s*1 at room temperature and a significant increase when the sample isheld at 77°K indicating a low amount of impurities.

The LEC material with Cr added also illustrates the lower mobilityachieved with Cr doped substrates.

1

lity

(ci

lobi

- 2

6000

5000

4000

3000

2000

C

-

• 4

o • S

+o

1 1 1 1

) 1 2 3 4

Si implant500 KeV energy

850° C anneal» * *

- High purity LEC at 300° K4 High purity LEC at 70° K

• LEC withCr added at 300° K0 Commercial low Cr content at 300° K

i i \ i i i i i i

5 6 7 8 9 10 11 12 13Ingot number

Figure 4.25 Hall Mobility Measurements for a Number of GaAsIngots of Different Types


4.2.3.3 Qualification of Material and Device Results

The results of ion implantation into undoped GaAs substrates are nowbeing applied to the use of the material for discrete FET and ICfabrication. The properties required of ion implanted layers are pro-duced by:

1. High purity starting substrates with less than 5x10 cm donorand acceptor impurities.

2. Freedom from harmful crystalline defects such as inclusions,precipitates and segregates.

3. Resistivity greater than 107 ohm cm or sheet resistance greaterthan 107 ohms per square.

4. Thermal stability during an 850°C annealing process usually witha Si3N4 cap or using an arsenic overpressure capless anneal.

5. The achievement of high activation efficiency of the implantedspecies.

6. The electrical compensation by deep donors, acceptors or both.

Semi-insulating GaAs is usually qualified by:-

1. Thermal annealing where a sheet resistance greater than 107 ohm persquare is required following an anneal at 850°C.

2. Ensuring active ion implantation at a 300 keV, 3 X1012 cm'2 Se dose,for example where

a), the implanted layer shows an activation greater than 80% of thedose.

b). correlation with the range statistics used (e.g. Table 4.4)

c). uniformity in the above properties over the length of the ingot(usually by taking slices from the two ends of the ingot).

As was stated earlier the prime reasons for exploiting ion implantationinto GaAs is to produce high uniformity, large area wafers leading tohigh yield processing of discrete FETs and perhaps more importantlythe newer GaAs ICs. In this respect the use of 'undoped' substratesproduces by far the best results which are illustrated by the pinch-offvoltage variations achieved, for example, by Rockwell (Zucca et al, 1980)shown in Figure 4.26. These particular results, showing a standarddeviation of 85 mV in a mean of 1.18V, indicate the potential of ionimplantation since such a standard deviation indicates a variation of


16

10

C

Uniformity over 440mm2 area

11 Vp = 1.179V

ovp = 0.085V

iL) 1.0 2.0

Vp (volts)

18

10

(

Uniformity ov

. ,l

er 0.1mm2 area

I3 1.0

Vp (volts)

Vp = 1.204V

o^ = 0.029V

2.0

Figure 4.26 Histograms of Pinch-off Voltages of GaAs FETs onIon-Implanted Wafers

only 50A in the depth at a particular electron concentration over theentire wafer.

Table 4.2 shows some of the results achieved at Plessey (Sanders et al,1980) using selenium implants into chromium doped substrates ofvarious manufacturers. The implants used produced single Gaussianprofiles. Table 4.3 shows the same electrical measurements using siliconas the implant species where it may be noticed that the resultant sheetresistance is much more reproducible, Hall mobilities are some 10%higher than the Se implants and the activation is also consistentlyhigher. Table 4.4 summarizes some of the measurements of siliconimplants into undoped substrates showing that the mobilities are con-sistently 10% higher than the corresponding silicon implants into chro-mium doped material. The reproducibility of activity is also good.

Many FET devices have been made using undoped semi-insulatingsubstrates implanted with a single room temperature silicon implant of6 x 1012 ions cm"2 at a 240 keV energy. Resulting peak carrier concen-trations are in the 2 x 1017 cm""3 region with the profile peak occurringat approximately 0.2jum depth and sheet Hall mobility values in excessof 4000 cm2 V-isec"1.

Table 4.5 shows a summary of some of the saturated source-draincurrent measurements (Isat) after source-drain delineation and before

Tab

le 4

.2 E

lect

rica

l Mea

sure

men

ts o

f Sel

eniu

m Im

plan

ts in

to V

ario

us C

r D

oped

Ingo

ts

Ingo

tM

anuf

actu

rer

Met

als

Res

.

Met

als

Res

.

Sum

itom

o

Met

als

Res

.

Met

als

Res

.

Met

als

Res

.

Se

Impl

ant

Dos

e (c

m'2 )

4x

10

12

4x

10

12

5 x

10

12

6 x

10

12

8x

10

12

8x

10

12

Ene

rgy

(KeV

)

380

380

380

380

380

380

Pea

kC

once

ntra

tion

(cm

'3 )

1.7

X1

01

7

1.4

X1

01

7

2x

10

17

2.5

X1

01

7

2.4

x1

01

7

4x

10

17

Hal

l Mea

usre

men

ts

Sh

eet

Res

ista

nce

(Q/Q

)

1298 764

337

498

295

426

Mob

ility

cm

2 V1

s'1

3311

3571

4118

3217

3403

3178

% A

ctiv

ity

36 57 90 65 78 58

CD i

Tab

le 4

.3 E

lect

rica

l Mea

sure

men

ts o

f Sil

icon

Im

plan

ts i

nto

Var

ious

Cr

Dop

ed In

gots

Ingo

tM

anuf

actu

rer

Mon

sant

o

Sum

itom

o

Met

als

Res

.

Met

als

Res

.

Sum

itom

o

Si I

mpl

ant

Dos

e (c

m-2

)

6x

10

12

8x

10

12

7x

10

12

7x

10

12

6x

10

12

Ene

rgy

(KeV

)

240

240

240

240

240

Pea

kC

once

ntra

tion

2x

10

17

3x

10

17

2.5

x1

01

7

2.6

x1

01

7

2.7

x1

01

7

Hal

l Mea

sure

men

ts

Sh

eet

Res

ista

nce

(QA

3)

285

262

318

296

311

Mob

ility

(cm

2V

-1 S

-1)

4055

3319

4042

3936

4066

% A

ctiv

ity

90 90 69 77 82

Tab

le 4

.4 E

lect

rica

l Mea

sure

men

ts o

f Si

Impl

ants

int

o V

ario

us U

ndop

ed In

gots

Ingo

tM

anuf

actu

rer

Met

al R

es.

Met

al R

es.

Met

al R

es.

Met

al R

es.

Met

al R

es.

Impl

ant

Dos

e (c

m"2 )

6x

10

12

6 x

10

12

6x

10

12

6x

10

12

6x

10

12

Ene

rgy

(KeV

)

240

240

240

240

240

Pea

kC

once

ntra

tion

(cm

'3 )

2.3

X1

01

7

2.1

X1

01

7

2.1

x1

01

7

1.8

X1

01

7

1.6

x 10

17

Hal

l Mea

sure

men

ts

She

etR

esis

tivity

(Q

/Q)

336

376

447

372

358

Mob

ility

(cm

2

v1 o41

44

4310

4037

4323

4174

% A

ctiv

ity

75 64 58 65 70

8? •3 S' B CD I § s? O!


Table 4.5 Uniformity of Source Drain Saturated Current for FETsFabricated on Various Implanted Undoped Substrates

Run No.

1

2

3

4

5

6

7

Substrate

A

A

A

A

B

C

Cr doped

Mean (mA)

60

58

69

65

62

82

112

ISAT

STD. Dev. (%)*

15

10

8

10

6.5 (2.4)

11(6)

8(5)

Area (cm2)

3.7

2.5

2.7

2.0

3.5

3.4

0.6

* values in parenthesis refer to standard deviation over 10mm2

gate etching from six implantations taken from three different ingots.The means and standard deviation for Isat from about 200 devices oneach wafer over areas greater than 2 cm2 are shown. The mean Isatvalues represent a run-to-run variation of ± 10%. Standard deviationsare between ± 5% and ± 15%. However over small areas of the orderof 10 mm2 standard deviations are as low as 2.5%.

It is possible to study the noise and r.f. performance of recessed gate ionimplanted FETs as a function of the impurity profiles. Trew et al (1985)have investigated devices having I micron gate lengths and 300 microngate widths. Donor profiles created by implant energies ranging from70 to 150 keV were investigated where Si was the implant species. Twoseries of calculations were performed: one in which the implant dosewas held constant and one in which the peak donor concentration washeld constant. In the latter case the implant dose was increased as theimplant energy was increased. Using the device geometry, materialparameters, and bias conditions as input data the model used calculatedthe element values for the usual small-signal equivalent circuit. Theequivalent circuit was then analyzed to obtain operating characteristics.

The transconductance that results from recessing the various implantsfor the case of constant peak doping is shown in Figure 4.27.

For each implant energy an optimum recess depth exists. This optimumdepth is established when the gate length to channel depth ratio is such


E 5 0

OC

o

1 * 0§K (

90 110 1 j 0 15Q keV

^ ^ P \ \ \ NpeQk=2x1017cm-3

i i i i i 1

D 200 400 600 800 1E3 1.2E3Recess depth (£)

Figure 4.27 Transconductance Versus Recess Depth as a Function ofImplant Energies

that the gate potential is able to exercise optimum control over thechannel current. The optimum recess depth was found to increase withincreasing implant energy. The maximum value for the transconduc-tance was essentially independent of energy for devices with the opti-mized recess depth. The corresponding variation in the gatesourcecapacitance, CGS , as a function of recess depth is shown in Figure 4.28.CGS increases with recess depth since the doping increases as thechannel is etched into the implanted profile. Now, since transconduc-tance increases with increasing recess depth more slowly than CGS thefr of the FET (equal to gm/ PCGs) generally decreases for increasingimplant energy. MESFETs fabricated using implant energies ranging

a,u-0.5

o 5T o 0.4

(

-

90

)

110

1200

130

i i

150 keV

1400 600 800o

Recess depth (A)

N

11E3

\\

11.2E3

Figure 4.28 Gate to Source Capacitance Versus Recess Depth as aFunction of Implant Energies


Fluence= 2.5 x 1012ions/cm2

NT = 2x1015crrf3nce 2.5 x2x1015crr

100 130Energy (keV)

Figure 4.29 Transconductance, Gate-to-Source Capacitance andGain-Bandwidth Product Versus Implant Energy

from 70 to 150 keV wer e investigated. With a constant implant dose theresults of Figure 4.29 were obtained where it is shown that both CGS andgm decrease with implant energy. Again, however, the decrease in gm isfaster than for CGS and, hence, the gain-bandwidth product of the FETdecreases.

CD

£8

8 4E

1 2l o

GA

F m j n ^ * ' ^

1 1 1 1 t

10

NT-2x10£cm*

£ 4x1015cm-3

8 & Npeak=2x1017cm-3

"g Frequency=8GHz

07 8

U)<

* 90 110 130 150Energy (keV)

Figure 4.30 Gain and Noise Figure Versus Implant Energy as aFunction of Trap Density


The noise figure and associated gain as a function of implant energy areshown in Figure 4.30. As has been shown in Chapter 2, the minimumnoise figure of a MESFET can be expressed by the equation:

FMIN - 4.7

where P, R and C are assumed to be constant (from Pucel's theory (1975)).

According to this equation the reduction in the fr for higher implantenergies, as shown in Figure 4.29, should result in degraded noisefigures-this is clearly not the case from the results presented in Figure4.30. The improved noise figure performance at higher implant energiesis due to the manner in which the drain resistance increases withimplant energy. The P and R terms in the above equation can be shownto be proportional to the inverse of the square of the drain resistance,RD. AS RD increases, P and R decrease at a rate fast enough to compen-sate for the degradation in fr resulting in an improved noise figure. Themodel used did not include the effect of substrate conduction (whichlowers the effective drain resistance) but it does explain when MESFETsare fabricated on GaALAs buffer layers that the material constants inthe FMIN equation are lower than in MESFETs fabricated on GaAs. Thevariations in gain and noise figure as a function of frequency for deviceswith 90, 130 and 150 keV implants are shown in Fig 4.31. All deviceshad a peak donor concentration of 2 X1017 cm"3 and an IDSS of 30 mA.

Figure 4.31 Gain and Noise Figure as a Function of FrequencyImplant Energy


The degradation in noise figure is least for devices employing a deepimplant.

4.3 FET Fabrication Techniques

The two techniques used for GaAs MESFET fabrication which havegained the most popularity are the self-aligned and the etched-channeltechnologies both of which can exploit either optical or electron beamlithography to define the gate stripe depending on the transistor's gatelength. Electron beam lithography is used generally for gate lengths ofless than 0.5/jm.

In all FET technologies the aim is to minimize the source resistance andgate capacitance allowing an increase in the maximum frequency ofoperation of the device. All technologies employ 'lift-off or 'float-off'metallization processes for both the ohmic contact metal, generallyAu/Ge/Ni, and the gate metallization. Gate metals vary but commonsystems are Ti/Pt/Au, Ti/Pd/Au and Ti/W/Au, the titanium forming areliable Schottky contact to GaAs with the barrier metals, Pt, Pd or Wpreventing gold diffusion to the GaAs surface. High performance ana-logue microwave FETs employ an n+ contact layer for source and drainand an n active region. These are formed either by epitaxial growth orimplants. These devices usually employ etched channel technology.FETs for digital applications usually employ selective implantation of

Photoresist Photoresist

(a)

v uateGate metal Gate metal

V7///////////////ASubstrate

n layer

(b)

PhotoresistOhmic metal

(c)

XSource Gate Drain

V///////7/7///////

(d)

'/////// ////////A

Figure 4.32 Processing Steps of Self-Alignment Gate Technology


the channel and contact regions giving the required device pinch-offvoltage directly.

4.3.1 Self-Aligned Gate Technology

Figure 4.32 shows the basic processing steps of the self-aligned gatetechnology. The first step is that the isolation mesa is defined by etchingaway the active n-layer until the semi-insulating substrate is reached.The gate metal, say aluminum is then evaporated over the active areaas shown in Figure 4.32(a).

Source and drain areas are defined in photoresist and the exposed gatemetal is removed by etching. Over etching is used to undercut the resistas shown in Figure 4.32(b) to allow the necessary space between gateand drain and gate and source. Gold ohmic contact metallization,usually In-Ge-Au or Au-Ge-Ni is then evaporated (Figure 4.32(c)). Theresist which is protecting the gate stripe is now covered with this ohmicmetallization but this is conveniently removed by 'floating off' the goldby dissolving away the resist. Thus the remaining thin gate is leftsituated between source and drain contacts as shown in Figure 4.32(d).

There are two different methods for producing a self-aligned structure.These are normally referred to as the gate-priority and ohmics-priorityapproaches. The first approach uses a temperature stable gate tech-nique developed by Yokoyama et al (1981) in which the gate metal is firstdeposited and patterned and then acts as an implantation mask for the(self-aligned) n+ contact layers as shown in Figure 4.33. Since the gatemetal is present during the high temperature anneal of the n+ implant,its composition is carefully chosen to retain its Schottky barrier charac-teristics. Sputter deposited Ti-W alloy film was the metal first reported(Yokoyama et al, 1981). Thereafter, sputtered Ti-W silicide (Yokoyamaet al, 1982) and W-silicide (Yokoyama et al, 1983) were reported. Ta-silicide has been reported as another stable refractory gate metal (Tsenget al, 1982) and electron-beam evaporated W has also been reported tohave good thermal stability up to 950° C (Matsumoto et al, 1982). Morerecently, Nakamura et al (1983) have reported the employment ofsputtered W-Al films as stable gate metal giving the advantage of lowresistivity. The reduction in gate-source parasitic resistances due to then+ implant being completely adjacent to the n-channel have led totransconductances of 200 mS/mm at room temperature for FETs withgate lengths of 1.2 microns.


Masking metal

Selective rn-type layer

RIE etch

Stable SB.gate metal

51 GaAs

SI GaAs

n + implant

Anneal

• •• + • • • •SI GaAs

V////VY//A"' \ Y////AV//ASI GaAs

-SiNy

Ohmic/source Ohmic/drainOhmics andprotonisolation 17/nV/

IV SI GaAs

Figure 4.33 Stable Gate Self-Alignment for a GaAs MESFET

The second approach involves more complex processing, relying ondielectric lift-off using a tri-level photoresist technique to define theplacing of the gate metal at a controlled distance from the selectivelyimplanted n+ regions. Enhancement mode (normally-off) and depletionmode (normally-on) FETs have been fabricated using this self-alignedFET technology known as SAINT (Self-Aligned Implantation for N+-layer Technology). A schematic diagram of the process sequence isshown in Figure 4.34. The main feature of the SAINT FET is that itsn+-layer is embedded between the source and drain electrodes beside thegate channel region. The distance between the gate metal and then+-layer can be controlled by under-cutting the bottom layer of thetri-level resist. Gate-to-source capacitance can be reduced for highfrequency operation by reducing the distance. Any suitable Schottkygate material can be applied to the SAINT FET.


I n-implantotion

PCVD-SiNdeposition

Multilayerresistpatterning

n^-implantation

5iO2 sputterdeposition

Lift-off

±[Annealing

OHMIC contactmetal ization

| OHMIC alloying

Gatemetalization

n-implanted layer

S.I.GaAs

.Photoresist

I* \YAfi

29Si

ft \K"y/"'%

rA

Photoresist\ Multilayer/ resist

Photoresist

-PCVD-SiN

n+-implanted layer

Source Drain

Gate

Figure 4.34 SAINT Process Flow

4.3.2 Recessed Channel Technology

Rather than define the active channel thickness by the thickness of then-type epitaxial layer, a thicker layer is grown and the channel regionunder the gate is defined by etching. This removes the high tolerancein thickness required for the epitaxial layer when the channel region isnot etched. Most companies use a preferential etch that gives a flat


Ohmic metal Photoresist

(a)Substrate

n-layer

(b)

Gate metal

(c) (d)

Figure 4.35 Processing Steps of Etched-Channel Technology

bottomed recess. Source and drain contacts are deposited first as inFigure 4.35(a) and the gate is defined in photoresist.

A channel is etched in the GaAs until a specific current is measuredbetween the source and drain contacts (the so-called ISAT current). Gatemetal is then evaporated and the excess metal (Figure 4.35(c)) removedby using the 'float-off technique'. This basic method works equally wellwith both photolithographic and electron beam resist exposure tech-niques and gate lengths as low as 0.25/j,m have been produced. Figure4.36 is a scanning electron micrograph of a 0.3/zm electron beam exposedFET fabricated using the recessed channel technique by Butlin et al(1978). The SEM clearly shows the channel where it joins the mesa edgeand the gate lying between the source and drain contacts.

Adaptations of this basic technique are numerous (Vokes et al, 1977;Ohata et al, 1980; Murai et al, 1977). For example, Murai et al havereported a technique of intentional side etching of the gate metal toproduce a cross-sectional shape much as shown in Figure 4.37 where theeffective gate length is 0.5/mi but because of the mushroom shape thegate metal resistance (which, as has been seen in Chapter 2, contributessignificantly to the overall noise figure) is reduced.

As has been seen in Chapter 2 the adoption of the recessed channeltechnology can significantly improve the performance of the small signalGaAs FET since such a recess can decrease the source resistance of the


Figure 4.36 Photograph of0.3/im GaAs FET Showing the MesaEdge Area (courtesy Plesssy Co. Ltd.)

device and thereby improve the noise figure and associated gain. To-gether with the incorporation of an n+ contact layer for the source anddrain electrodes it is possible to reduce the source resistance by a factorof four over a self aligned FET with a planar geometry. Figure 4.38.

Figure 4.37 GaAs FET with Intentionally Side Etched Gate


Source Gate

j

DrainX///A

N

Source Gate Drain

AT(a) (b)

Source

N^ Gate

HIP

Drain

N

N

Y////////A

(c) (d)

Figure 4.38 Cross Sections of Various FET Recessed ChannelStructure

shows the cross sections of several types of low-noise MESFET fabri-cated using the recessed-gate technique.

In power FETs the breakdown voltage between gate and drain is ofimportance in determining the r.f. power handling capability. The re-cessed channel structure improves this breakdown voltage. Figure 4.39shows a power FET device structure which improves the breakdownvoltage. Three regions are identified where high electric fields can occur.

Source

/I Active layer

Gate| ^ ^ J , > R e g i o n 2

V///A )

Buffer layer

S.I. GaAs

i\Drain

\/Region 1

\_

Region 3 '

Figure 4.39 Power FET Geometry Showing Recessed Gate andRecessed Channels


The field in region 1 is reduced by smoothing the channel near the drainthus reducing the possibility of breakdown due to avalanching andelectron-hole pair generation (Tiwari et al, 1979). The field in region 2is reduced by recessing the gate. This recess depth has to be correct sinceif it is too deep local field enhancement will take place lowering thebreakdown voltage. The electric fields in region 3 occur because of risingfringing fields towards the active-buffer depletion region through whichsubstantial space charge limited current may be flowing. This leads tocurrent crowding of carriers as they approach the drain region of thechannel. By recessing the active layer 0.5 to l/*m away from the draincontact edge and making the thickness under the drain contact edgeequal to the breakdown depletion width these effects are avoided.

4.3.3 Ion Implanted Fet Processing

Both mesa isolation and planar isolation techniques can be used withion-implanted GaAs layers, the latter increasing yield and device reli-ability since the gate metal does not have to go over a mesa step. Withreference to Figure 4.40 typical processing steps for an ion-implantedplanar FET are as follows:

1. The wafer is coated with a layer of silicon nitride which remainson the substrate during subsequent processing. The nitride is

if Sputtered Si3N4

N S.I. GaAs 1

(a)

Ge-Au-Ni-Au

^~—<"?M J 1N SIGaAs

(b)

SbN*

Aluminium

N SIGaAs

(c)

Figure 4.40 Example of GaAs FET Processing using Ion-ImplantedGaAs (after Rode et al)


removed from the channel region using a plasma etching technique(Rode et al, 1979).

2. A Si+ ion implantation creates the active channel. The Si3N4 actsas an implantation mask, thus ensuring that only the channel isimplanted.

3. Activation of the ions is accomplished by annealing using a Si3N4cap.

4. The cap is removed only in the source and drain regions which aredefined using photoresist. This same photoresist is used to lift offthe ohmic metal (in this case, Ge-Au-Ni-Au). The source and drainohmic contacts are alloyed to produce low specific contact resistance.

5. The gate metallization (in this case for a dual-gate FET) is putdown by using a photolithographic technique to open up areas in theremaining Si3N4 followed by a resist stage and a float-off process todefine the gate stripes resulting in the structure shown in Figure4.40(c).

4.4 Conclusions

This chapter has attempted to give a review of material preparation

techniques and FET fabrication processes related specifically to GaAs.The reader is referred to the bibliography that follows for further studyWith the advent of ion implantation and more complicated devicestructures 'wet' etching techniques are giving way to 'dry' methods suchas ion beam milling to define gate metallization (Bollinger et al, 1980)and plasma etching for dielectric definition (Tolliver, 1980). The latteris applied to the fabrication of scratch protection layers on GaAs FETs.Also, considerable effort has been applied to improving the reliability ofboth low-noise and power FETs by careful choice of metallizations anddevice design.

4.5 Bibliography

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Bass, S. J. Device quality epitaxial gallium arsenide grown by the metalalkyl-hydride technique. Journal of Crystal Growth Vol. 31, pp.172-178,1975.

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Bolger, D.E., Franks, J , Gordon, J. and Whitaker, J. Gallium Arsenideand Related Compounds, Institute of Physics Conference, 1966, p. 16.

Bollinger, D. and Fink, R. A new production technique: Ion milling. SolidState Technology, November 1980, pp.79-84.

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Butlin, R.S., Hughes, A.J., Bennett, R.H., Parker, D. and Turner, J.A. Jband performance of 300 nm gate length GaAs FETs. Int. ElectronDevices Meeting, Washington DC, Dec. 1978, pp. 136-139.

Cairns, B. and Fairman, R.D., Journal of the Electrochemical Society, Vol.115, p.327C, 1968.

Cairns, B. and Fairman, R., Journal of the Electrochemical Society, Vol.117, p.l97C, 1968.

Caruso, R., Di Dominico, M., Verleur, H.W. and Von Neida, A.R. JournalPhys. Chem. Solids, Vol. 33, p.689,1972.

Cho, A.Y., Di Lorenzo, J.V., Hewitt, B.S. et al, Journal of Applied Physics,Vol.48,p.346,1977.

Cho, A.Y., and Ch'en, D.R. GaAs MESFET prepared by molecular beamepitaxy. Applied Phys. Lett, Vol. 28, pp.30-31,1976.

Cho, A.Y., Di Lorenzo, J.V, Hewitt, B.S., Nichaus, W.C., Schlosser, W.O.and Radice, C. Low noise and high power GaAs microwave field effecttransistors prepared by molecular beam epitaxy. J. Applied Physics, Vol.48, pp.346-349,1977.

Chu, W.K. et al, Proc. 3rd Int. Conf. on Ion Implantation, Plenum Press,New York, 1973.


Cox, H.M. and Di Lorenzo, J.V. Gallium Arsenide and Related Com-pounds (St. Louis) 1976, Institute of Physics Conference Series No. 33b,pp.11-12.

Cox, H.M., Di Lorenzo, J.V. and D'Asaro, L.A. 1st GaAs Integrated CircuitSymposium Abstracts, Lake Tahoe, USA 1979.

Cox, H.M. and Di Lorenzo, J.V. Characteristics of an AsCI3/Ga/H2 twobubbler GaAs CVD system for MESFET applications. Institute ofPhysics Conference Series No. 33B, pp. 11-22,1976.

Di Lorenzo, J.V. Progress in the Development of low noise and high powerGaAs FETS. Proceedings of the 6th Biennial Cornell Electrical Engi-neering Conference 1977, Cornell University, Ithaca, New York, pp. 1-28.

Drukier, I., Camisa, R.L., Jolly, S.T., Huang, H.C. and Narayan, S.Y.Electronics Letters, Vol. 2, p. 104,1975.

Eddolls, D.V., Phys. Status Solidi, Vol. 17, p.67,1966.

Evans, C.A., Deline, V.R., Sigmon, T.W. and Lidow, A., Applied PhysicsConference Series No. 45, p. 114,1979.

Fairman, R.D., Morin, F. J. and Oliver, J.R. Institute of Physics Confer-ence Series No. 45m p. 134,1979.

Fainnam, R.D., Morin, F.J., Oliver, J.R. and Dreon, J.K. High resistivitychromium doped GaAs buffer layers grown by halide transport methods.Proceedings of the Seventh Biennial Cornell Electrical EngineeringConference, Ithaca, New York, 1979, pp.177-187.

For, W.M.-private communication.

Foyt, A.G., Donnelly, J.P. and Lindley, W.T. Efficient doping of GaAs bySe+ ion implantation. Appl. Phys. Lett. Vol. 14, p.372,1969.

Hallais, J., Andrew, J.P, Baudet, P. and Beccon-Gibod, D. New MESFETdevices based on GaAs-(Ga,Al)As heterostructures grown by organomet-allic VPE. 7th Int. Symp. on GaAs and related compounds, Institute ofPhysics Conference Series 1978.

Harris, J.S., Eisen, F.H., Welch, B.K., Haskell, J.D. et al. Influence ofimplantation temperature and surface protection on tellurium implan-tation in GaAs. Appl. Physics Lett., Vol. 21, p.601,1972.

Henry, R.L. and Swiggard, E.M., Institute of Physics Conference SeriesNo. 33b, p.28,1977.


Hewitt, B.S., Cox, H.M., Fukui, H., Di Lorenzo, J.V., Schlosser, W.O. andIngelsias, D.E. Low noise GaAs MESFETS: fabrication and performance.Institute of Physics Conference Series No. 33a, pp.246-254,1976.

Huber, A.M., Morillot, G., Merenda, P. and Linh, N.Y. 2nd InternationalConference on Secondary Ion Mass Spectroscopy, Palo Alto, USA, 1979.

Ito, S., Shinohara, T. and Seki, Y. Journal of the Electrochemical Society,Vol. 120, p.1419,1973.

Jacob, C, Duseaux, M., Farges, J.P., Van den Book, M.M.B. Journal ofCrystal Growth, Vol. 61, p.417,1983.

Kato, Y, Mori, Y and Morizane, K. Journal of Crystal Growth, Vol. 47,p.12,1979.

Kim, C.K., Malbon, R.M., Omoni, M. and Park, YS. Institute of PhysicsConference Series No. 45, p.305,1979.

Knight, JR., Effer, D. and Evans, PR. The preparation of high puritygallium arsenide by vapor phase epitaxial growth. Solid State Electron-ics, Vol. 8, pp.178-180,1965.

Komeno, J., Nogami, M., Shibatomi, A. and Ohkawa, S. Ultra highuniform GaAs layers by vapor phase epitaxy.

Lui, S.G., Douglas, H.C., Wu, C.P. et al. Ion Implantation of sulphur andsilicon in GaAs. RCA Review, Vol. 41, June 1980, pp.227-263.

Luscher, P.E. Crystal growth by molecular beam epitaxy. Solid StateTechnology, Vol. 20, No. 12, pp.43-52, Dec. 1977.

Manasevit, H.M. and Simpson, W.I. Journal of Electrochemical Society,Vol. 116, p.1725,1969.

Matsumoto, K., Hashizume, N , Tanoue, H. and Kanayama, K. Japan.Journ. of Applied Physics, Vol. 21, pp. L393-395,1982.

Metz, E.P.A., Miller, R.C. and Mazelsky, R. Journal of Applied Physics,Vol.33,p.2016,1962.

Mizuno, O., Kikuchi, S. and Seki, Y Japanese Journal of Applied Physics,Vol. 10,p.208,1971.

Moest, R.R. and Shupp, B.R. Journal of the Electrochemical Society, Vol.109, p.1061,1962.

Morkoc, H., Andrews, J. and Aeki, V. GaAs MESFET prepared by or-ganometallic chemical vapor deposition. Eletronics Letters, 15 Feb.1979, Vol. 15, No. 4, pp. 105-106.


Morkoc, H. and Eastman, L.F. Journal of Crystal Growth, Vol. 47,1.12,1979.

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Murai, F., Kurono, H. and Kodera, H. Intentional side etching to achievelow-noise GaAs FET. Electronics Letters, 26 May 1977, Vol. 13, No. 11,pp.316-318.

Nakamura, H., Sano, Y, Nonako, T., Ishida, T., and Kaminishi, K. Aself-aligned GaAs MESFET with W-Al gate. IEEE Technical Digest of1983 GaAs IC Symposium, pp. 134-137, October 1983.

Nanishi, Y., Takahei, K. and Kuroiwa, K. Journal of Crystal Growth, Vol.45, p.272,1978.

Nozaki, T, Ogawa, M., Terao, H. and Watanabe, H. GaAs and RelatedCompounds Institute of Physics Conf. Series, No. 24,1974, p.46-54.

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The Design of Transistor Amplifiers

5.1 Introduction

As has been seen in the previous chapters modern GaAs FET devicesare capable of producing noise figures of less than 2 dB at 18 GHz withalmost 10 dB associated gain whilst at the lower frequencies noisefigures of less than 0.5 dB are possible. Power FETs are now capable ofproducing 15 watts up to X-band in Class A operation with promise ofconsiderably more power in the pulsed mode of operation.

The GaAs FET offers in its simplest form a device having somewhatmore convenient impedances for matching than the bipolar device andit is also capable of exhibiting much superior performance above ap-proximately 4 GHz than the bipolar transistor. This chapter deals withthe theory and design of amplifiers using GaAs FETs.

5.2 Low Noise Small Signal Amplifiers

The measurements which are usually made on a three terminal deviceare those where one of the terminals is effectively earthed. In the caseof a microwave GaAs FET it is usual to measure the device in commonsource configuration, i.e. where the source electrodes are bonded to r.f.ground. This arrangement usually provides the design engineer withthe most stable arrangement and low feedback capacitance betweendrain and gate. Alternative configurations such as common gate andcommon drain are dealt with later.

The gain parameters of a microwave transistor can be completelyspecified by a set of 2 port parameters, the so-called 'scattering orS-parameters\ Other descriptions of the transistor such as H or Yparameters require open-and short-circuited measurements that aredifficult to establish accurately at microwave frequencies.

Because S-parameters are measured using travelling waves it is essen-tial to specify the plane of reference of the measurements with respectto the device. Usually FET data sheets specify the reference planes at


the end of wire bond lengths furthest from the device in the case of barechip transistors and at the package lead to substrate interface in thecase of packaged devices.

The S-parameters of a GaAs FET whether chip or package have to bemeasured accurately over a large range of frequencies.

Since errors can occur in measurement due to equipment and also thetest jigs used to hold the devices, all measurements made on FETsshould be obtained using an automatic network analyzer with postmeasurement processing to extract errors due to the equipment andothers due to causes such as microstrip transmission line losses, coaxialto microstrip transition errors and dispersion with frequency.

Commercial FET data sheets are the result of a relatively large numberof S-parameter measurements on a particular FET type allowing 'typi-cal' S-parameters to be generated. Since the maximum available gainof the device and the minimum noise figure are produced at differentd.c. bias conditions at least two sets of S-parameters are needed. Alsothe S-parameter data for the device biased for maximum output poweris often required. (This occurs at approximately 50% of the saturateddrain current for a GaAs FET).

Table 5.1 shows typical S-parameters for a FET chip device (PlesseyGAT6) over 2 to 18 GHz whilst Table 5.2 also shows the same data over4 to 16 GHz for a packaged GAT6. It may be seen that the packageproduces a considerable rotation in the phase of the S-parameters.

Bare chip devices should be used where the ultimate in noise figure orgain-bandwidth product is used. Packaged devices have the advantageof being pretested by manufacturers, being usually supplied in hermeti-cally sealed enclosures and being more easily handled. Offset againstthese advantages are the disadvantages of narrower band and slightlyinferior r.f. performance.

Chips or packaged devices should always be used with the groundingand mounting methods used by the manufacturer when measuring theS-parameters.

5.2.1 Stability of a 2 Port

One important parameter in the design of microwave amplifiers is thatof stability. An amplifier can be either unconditionally or conditionallystable. A circuit is unconditionally stable if its input and output resis-

The Design of Transistor Amplifiers 179

Table 5.1 Typical S-Parameters for GAT6 Chip at IDSS, VDS = 5

Freq.

GHz

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

Mag

.95

.92

.89

.85

.825

.8

.775

.75

.73

.71

.695

.68

.665

.665

.64

.63

.62

S11

Phase

-38

- 4 8

- 6 0

- 7 2

-84

-96

-107

-118

-128

-136

-145

-153

-161

-168

-175

-180

174

Mag

2.95

2.77

2.6

2.41

2.25

2.09

1.96

1.84

1.73

1.64

1.55

1.47

1.4

1.33

1.26

1.2

1.14

S21

Phase

150

140

130

120

110

100

90

81

73

64

56

47

40

33

27

22

16

Mag

.02

.02

.02

.02

.025

.03

.035

.04

.045

.053

.06

.065

.073

.08

.09

.1

.11

S12

Phase

75

74

78

83

90

97

104

110

114

115

115

113

110

106

100

93

86

Mag

.725

.725

.725

.725

.725

.73

.735

.74

.75

.755

.765

.77

.78

.79

.8

.805

.815

S22

Phase

-15

- 1 7

-21

-26

-31

- 3 6

- 4 2

- 4 7

- 5 2

- 5 8

- 6 2

-68

- 7 2

- 7 7

-81

-86

- 9 0

tances are positive for passive terminations. If the amplifier is condi-tionally stable then either the input or output resistances are negative.

The measured S-parameters of a transistor enable the maximum avail-able gain (MAG) of the device to be determined.

The transducer power gain, GT, of a transistor can be calculated as:

G r = -\(i-snrs)(i-s22rL)-s12s21rsrL\

5.1


Table 5.2 Typical S-Parameters for a P103 Packaged GAT6 at IDSS,

VDS = 5 volts

Freq.GHz

4

5

6

7

8

9

10

11

12

13

14

15

16

Mag

0.865

0.84

0.81

0.78

0.76

0.74

0.724

0.71

0.695

0.685

0.672

0.664

0.66

S11

Phase

-78

-94

-112

-113

-150

-164

-178

166

150

134

121

110

100

Mag

2.37

2.24

2.14

2.04

1.94

1.85

1.77

1.68

1.6

1.53

1.47

1.4

1.34

S21

Phase

112

99

85

70

55

44

30

20

6

- 4

-15

-25

-34

Mag

.04

.04

.05

.05

.05

.06

.06

.07

.07

.08

.09

.11

.125

S12

Phase

43

37

37

34

37

47

46

49

44

43

37

38

34

Mag

0.74

0.72

0.71

0.692

0.68

0.666

0.654

0.644

0.634

0.626

0.618

0.615

0.61

S22

Phase

- 3 5

- 4 4

- 5 3

- 6 2

- 7 0

-76

- 8 4

-95

-100

-114

-125

-136

-149

When the generator and load, Fs and FL are conjugately matched to thetwo FET ports the gain can be maximized. Assuming S12 = 0 then wehave:

5.2

where Fs = Sn*, FL = S22*, S11* and S22* being the complex conjugatereflection coefficients, and the device is assumed unilateral. The S-pa-rameters also determine Rollett's stability factor, K (Rollett, 1962).

74.1c c _ e

2\S2\S12S21\5.3


If K is larger than unity, i.e. when the FET is unconditionally stable, anoptimum combination of Is and FL can simultaneously match the 2 FETports to maximize the gain (Bodway, 1967). If K is smaller than unity,the FET is only conditionally stable and Fs and FL must be carefullychosen to operate the device in a stable region (Bodway, 1967; Gledhillet al, 1974). Since the FET's stability factor, K, will change with fre-quency it is possible to plot the regions of stability onto a Smith Chartat each frequency (Smith, 1995).

The input and output reflection coefficients with arbitrary source andload terminations are given by:-

5.4iiNz>11+1~'^22l L

and

r _ o • S21S12^S - -1 OUT ~^22^ 7 c j , O.O

If we set | FIN | equal to unity, a boundary is established beyond whichthe device is unstable and then

n\=]

This equation can be changed in form to give the solution as a circlewhose radius is given by

e ,2

22I

and whose center CL is given by

^ (S22-AS77*)*

where

A = 57 752 2 —S 12s 21

and the origin of the Smith Chart is at FL = 0

jr rj


The area either inside or outside the circle represents a stable operatingcondition. If |Sn|<l and |riN|<l then the shaded region in Figures5.1(a), 5.1(b) will enable stable gain to be realized. In Figure 5.1(b) thestability circle encloses the origin of the Smith Chart and hence itsinterior represents the stable region, in Figure 5.1(a) the origin isoutside the circle and the exterior of the circle represents the stableregion.

If | Sn | >1, the orign (i.e. at TL = 0) represents an unstable point. Figure5.1(c) is the case where the stability circle encircles the origin and itsexterior is the stable region. For the case where the circle does notencircle the origin, its interior represents the stable region as in Figure

For unconditional stability we must ensure that the magnitude of thevector CL (the distance from the center of the Smith Chart to the centerof the stability circle (Figure 5.1(a)) minus the radius of the stabilitycircle rL, is greater than one. Table 5.3 lists the stability results for apackaged Plessey GAT6 from 4 to 16 GHz. The device is conditionallystable at all these frequencies where the stability circles are given interms of their location in magnitude and angle on the Smith Chart andthe radius of the circle with an indication of the area of stability.

For the case where K<1 the maximum stable gain or MSG of the devicecan be calculated as

Figure 5.1 The Four Different Regions of Stability in the V Plane

Tab

le 5

.3 S

tabi

lity

Cir

cles

for

a P

acka

ged

GA

T6

havi

ng th

e S—

para

met

ers

of T

able

5.2

CD CD

Freq

.G

Hz

4 5 6 7 8 9 10 11 12 13

INP

UT

PLA

NE

Loca

tion

MA

G.

1.21

1.22

1.23

1.31

1.24

1.23

1.26

1.26

1.30

1.32

AN

G.

88 103

122

122

156

168

-17

9

-16

6

-15

0

-13

7

Rad

ius

0.29

0.26

0.31

0.31

0.26

0.29

0.29

0.30

0.30

0.33

Sta

ble

Reg

ion

Out

side

Out

side

Out

side

Out

side

Out

side

Out

side

Out

side

Out

side

Out

side

Out

side

OU

TP

UT

PL

AN

E

Loca

tion

MA

G.

1.61

1.51

1.42

1.51

1.35

1.32

1.34

1.35

1.38

1.41

AN

G.

59 63 70 77 79 82 88 95 100

110

Rad

ius

0.76

0.59

0.54

0.52

0.38

0.39

0.37

0.39

0.38

0.42

Sta

ble

Reg

ion

Out

side

Out

side

Out

side

Out

side

Out

side

Out

side

Out

side

Out

side

Out

side

Out

side

K

.67

.79

.68

.97

.87

.76

.9 .84

1 .97

MS

Gd

B

17.7

17.5

16.3

16.1

15.9

14.9

14.7

13.8

13.6

12.8

CD 3 00 CO


MSG ='12

5.8

In general,

MAG =

Thus MAG equals MSG when K is 1 and the MSG is the gain that canbe obtained from the GaAs FET when the input and output reflectioncoefficients fall on the boundaries of the instability regions.

5.2.2 Transducer Power Gain

In the design of small signal amplifiers, a transducer power gain asdefined, for example, in the Hewlett Packard Application Note 154(1972), can be calculated for the device terminated in arbitrary load andgenerator impedances, ZL and Zs.

The transistor power gain is given by Gr = | S211 2

We can write

5.9

5.10

When S12 is sufficiently small to be neglected (see Table 5.1 at the lowerfrequencies), the device is defined to have a unilateral transducer powergain

5.11

Gv -

The first term is related to the transistor used and remains invariantthroughout the amplifier design. The other two terms, however, are notonly related to the S-parameters Sn and S22 but also to the load and


source reflection coefficients. These latter two quantities are used tocontrol the design of the amplifier in terms of gain slope compensationetc.

The unilateral transducer gain can be divided into three independentgain blocks.

where

5.12a

G0=\S2if 5.12b

and

G UL 5.12cL = ] UL-

\(i-s22rL)\

5.2.3 Circles of Constant Unilateral Gain

Considering equation 5.12a we have that for Ts = Sn*, Gs = Gsmax andfor Ts = 1, Gs = 0

Thus for any arbitrary value of Gs there is a value of Ts which lies on acircle. The output gain term in Equation 5.12c is of a similar form andthus a similar set of circles can be generated. Such circles are calledConstant Gain Circles and can be generated from the FET S-parameterssince

d,~ /f i1 5.13al-\Suf(l-gi)

Ri= j—5 5.13b

where


where Gi is the constant gain represented by the circle, di is the distancefrom the center of the Smith Chart to the center of the constant gaincircle along the vector Sn* and Ri is the radius of a particular circle(Hewlett Packard Application Note 154 (1972)).

Thus gain circles enable the design engineer to choose a matchingtopology which, for example, will allow matching over a range of frequen-cies to produce constant gain or indeed gain of a specified slope withfrequency. Figure 5.2 is an example of the constant gain circles for aPlessey P103 packaged GAT5 at 10 GHz.

5.2.4 Unilateral Figure of Merit

Although the assumption that | S12 | = 0 is often made in initial ampli-fier design it is desirable to quantify the error involved in doing this.

The transducer power gain GT, from Equations 5.1 and 5.12 can bewritten as

GT =Jj-* l '

S,, = 0.55 < 141 • ^ ^ - ^ _ J _ _ - - - - ^ ' ' ^ Sa = 0.64 < -67°

Figure 5.2 Constant Gain Circles for a Packaged GaAs FET at 10GHz


where

Y --(i-rssn)(i-rLs22)

5-14

The ratio of the true gain to the unilateral gain is bounded by

1 ,GT. 1

W 5 1 5

For complex conjugate matching | Sn | <1 and | S22 | <1

1 G 1<-7r<——7 5.16(1 + X'f Gu (1-X'

where

A typical value for X' at 10 GHz for the GAT5 in Figure 5.1 is 0.1 giving

(7 + X')

1

A2 equivalent to - 0 . 8 dB;

equivalent to +0.9 dB

Thus the error in gain by assuming that the device is unilateral in anydesign will be approximately ± 0.8 dB.

5.2.5 Variation Of Gain With Drain Current And Temperature

The variation of maximum available gain of a GaAs FET with drainsource current IDS can be plotted a t different frequencies. This enablesthe design engineer to calculate the gain tha t can be expected undercertain bias conditions. Figure 5.3 shows the gain v drain current ratioIDS/IDSS for a typical high frequency FET at 8 GHz. It may be seen tha tbelow a certain IDS/IDSS ratio there is a sharp decrease in gain due to arapid decrease in transconductance gm and consequently of ft as might


16

12

co

Gain

,

00

4

n

/

i

°0 20

MAG, —-_-——

• —

40

-

IS2,lf

— - - ^

60

los/loss{%)

-

80

- — - —

^ — *

100

Figure 5.3 Gain v IDS/IDDS for a GaAs FET Chip at 8 GHz

also be seen by inspecting the drain current versus drain to sourcevoltage characteristic of the device for gate voltages close to pinch off.

Figure 5.4 shows the associated gain change with temperature for apackaged FET device over the temperature range -40 to +80°C wherethe transistor is biased and matched for minimum noise figure asexplained in Chapter 2.

Figure 5.4 Typical Associated Gain and Noise Figure VersusTemperature for a GaAs FET

The Design of Transistor Amplifiers 1 8 9

5.2.6 Optimum Load Conditions For Output Power

In certain cases the FET is designed to operate in a linear (Class A) modewhere the objectives are either lowest intermodulation distortion, larg-est added r.f. power or largest linear output power. In the last case, forexample, the d.c. bias is graphically determined from the static drain-current versus drain-voltage characteristic (Figure 5.5). The bias andload conductance line are chosen to maximize the product of the linearvoltage and current swing. The limitations are determined by themaximum d.c. power dissipation, the drain-to-gate breakdown voltageand the positive gate bias (VGS = 0.5V) above which appreciable gatecurrent flows. The optimum load conductance is typically much largerthan the GaAs FETs output conductance. Consequently the GaAs FETis not matched to the load and does not provide maximum gain. Theoutput load conductance and susceptance determine the optimum re-flection coefficient of the load, rLp The generator reflection coefficientthat provides a complex conjugate match to the input of the device isthen

,= s>//• 5.17

Gate-source voltage, VG!

0V

Drain to source voltage, VD!

— 0 . 5

— 1

—1.5

—2

—2.5—3

Figure 5.5 D.C. Characteristics of a Grounded Source GaAs FET


5.2.7 Equivalent Circuit Of The GaAs FET

It is convenient to use equivalent circuits of the GaAs FET for forminga clear view of microwave characteristics and noise characteristics of thedevice. The equivalent circuit can be used as the first step in amplifierdesign. Figure 5.6a shows an equivalent circuit of the GaAs FET.

This equivalent circuit is shown for the device operated in the saturatedcurrent region in common-source configuration. In the intrinsic FETmodel, the elements (CDG + CGS) represent the total gate-to-channelcapacitance, Ri and RDS show the effects of the channel resistance andIDS defines the voltage controlled current source. The transconductancegm relates IDS to the voltage across CGS. The extrinsic (parasitic) ele-ments are: Rs, the source resistance, RD the drain resistance, Rg the gatemetal resistance, and CDS the substrate capacitance. Typical elementvalues for a 0.5/nn gate length and 30Qam gate width FET are shown inTable 5.4.

Intrinsic FETGate U

Source

= C p 3 = C p 4

Figure 5.6 (a). Equivalent Circuit of GaAs FET Chip (b).Equivalent Circuit of Packaged GaAs FET


Table 5.4 Typical Equivalent Circuit Element Values for a 0.5jumGate Length GaAs FET

Intrinsic FET

Ri=6.95Q

RDS = 400Q

Cgs = 0.43 pF

Cdg = 0.01 pF

gm = 30 mS

Parasitic Components

Rg = 0.8Q

RD = 3 Q

Rs = 3Q

CDS = 0.16pF

LG = 0.2 nH

Ls = 0.05 nH

Very often the input circuit of an FET can be modelled as a series Reand the output circuit as a parallel Re for the case of a bare chip device.The equivalent circuit of a packaged transistor can also be found wherethe addition of package wire bond inductances, LG, LD and Ls and shuntparasitic capacitances Cpi, CP2, Cp3 and Cp4 on input and output togetherwith increased feedback capacitances, CFBI and CFB2 are usually suffi-cient to model accurately the device reflection coefficients as shown inFigure 5.6b. This is covered further in Chapter 8. By adding the currentsource as an element giving gain to the transistor we have built up asimple equivalent circuit for the FET.

5.3 Example of Narrow Band Amplifier Design

This example deals with the design of a simple narrow band amplifierto operate between a source and load of characteristic impedance of 50ohms, which provides a gain of at least 18 dB with input and outputreflection coefficients of less than 0.1 at 2 GHz. The scattering parame-ters of the transistor used are given in Table 5.1. The equivalent circuitof the transistor (Liechti et al, 1974) derived from the Sn and S22parameters is given in Table 5.4. The transistor is assumed unilateral(i.e. S12 = 0) for the initial design.

In order to resonate the reactance of the input circuit and transform theimpedance a series inductor is required to resonate with the 0.43 pFseries capacitor and a transformer to transform 10.75Q (Ri + Rg + Rs) to50Q. The latter can be achieved using a simple single section quarterwavelength transformer if the amplifier is to be realized using transmis-


sion lines or a combination of series inductance and shunt capacitanceif lumped element matching is to be used.

The scattering parameters of the transistor are

Sn=0.95<-38°

S21= 2.95 < 150°

S12=02<75°

S22=725<-15°

The stability factor K is calculated using equation 3.1 to be 0.33 i.e. thetransistor is only conditionally stable. The device can be stabilized bythe use of a 100 ohm shunt resistor at its output. The use of a resistivestabilization technique will decrease the maximum available gain andalso increase the noise figure, the degradation being minimized by usingthe resistor on the output of the FET. Common lead feedback is a bettermethod to effect an increase in the stability factor without degradingthe noise figure of the FET.

5.3.1 Input Matching Circuit

The source impedance for maximum gain is 10.75 + j 145.

First transform the 50Q generator to 10.75Q with a quarter wave lineof impedance Z, where

Z = J50(1075) ohms = 23 ohms

Then add a shunt open circuit quarter wavelength line of low charac-teristic impedance. This essentially adds shunt capacitance to thematching structure lowering the imaginary Dart of the matching admit-tance. A high impedance series transmission line or inductance com-pletes the input matching network. Figure 5.7a shows the steps in theinput matching sequence for the elements shown.

Starting at the center of the Smith Chart, i.e. at 50Q. The low imped-ance, A/4 transformer is used to transfer to a lower real impedance. Fromthis point an open circuit stub adds capacitive reactance enabling theseries inductance to transform the impedance to Sn*.

The resulting component values are optimized using CAD to give theoptimum input VSWR and the values shown in Figure 5.7a.


5.3.2 Output Matching Network

The output matching is considerably simplified because of the use of thestabilizing resistor which lowers the magnitude of the output reflectioncoefficient from 0.725 to 0.28. A 0.5 nH inductance (wire bond) is usedbetween the FET and the resistor to give enough space for the resistorwhen the circuit is made. The output matching circuit consists simplyof a series wire bond (which can be treated as a lumped 1.1 nH

Contour in theadmittance plane S,,* = 0.95<38'

11.6n

G a t e Drain

Source

S22* * 0.725 < 15°0.5n 1.1 6090° 50R

1 0 0 ^ Stabilizing resistor

: By pass capacitor

/7777

—90* (b) Output matching network for narrow bandsmall signal amplifier.

Figure 5.7 (a). Input Matching Network for Narrow Band SmallSignal Amplifier (b). Output Matching Network for Narrow BandSmall Signal Amplifier


inductance) followed by a single section transformer nominally 60 ohmsimpedance, A/4 long.

Referring to Figure 5.7b, the output source impedance needed is 0.725< 15°. Initially 50 ohms is transformed with a quarter wave length lineof impedance 60 ohms to a higher real impedance point on the SmithChart. A series inductor of value 1.1 nH is then used followed by theshunt stabilizing resistor. Figure 5.7b shows the sequence of matchingof the output of the device.

By using Equations (5.4), (5.5) and (5.11) the resulting circuit designgives an input reflection coefficient of 0.01 and an output reflectioncoefficient of 0.1 at 2 GHz with a gain of 18.9 dB and a stability factorof 1.2. The latter indicates that whatever passive loading is put on theinput or output of the amplifier it is not possible to make the circuitoscillate.

5.4 Example of a Broadband Amplifier Design

This example deals with the design of a broadband amplifier to operateover the frequency band 8 to 12 GHz. The amplifier design objective isto give maximum gain consistent with a bandpass characteristic havinga gain ripple of less than 0.5 dB over the band of interest. The scatteringparameters of the transistor are again given in Table 5.1. These parame-ters can be interpolated from the table in 500 MHz intervals.

The input and output matching networks are designed to give the bestinput and output VSWRs over the band. However, because of its band-width the VSWRs will only be optimum at certain frequencies and themain design objective is to obtain flat gain. To achieve this the devicecan be mismatched at the low frequency end of the band to reduce thecontribution of Gs and GL of Equation 5.12 to the overall amplifier gain.The gain can also be reduced by using absorptive resistive loadingpreferably on the drain side of the FET.

5.4.1 Lumped Element Designs-Design Where Stability Is NotConsidered

The equivalent circuit of the FET has been given in Table 5.4 andcalculation of the stability factor at 10 GHz gives a value of 0.8. Againlet us assume that the device is unilateral. A lumped element matchingtechnique will be discussed. Lumped element matching gives inher-ently broader bandwidth capability since the designer is not dependent


on components whose electrical length changes with frequency. Figure5.8 shows the input constant gain circles at 8 and 12 GHz and also showsthe sequence of input matching used at 8 GHz.

The input impedance of the FET will in practice be determined by theoutput matching conditions when the device is conditionally stable asgiven by Equation 5.4. A schematic of the lumped circuit is shown inFigure 5.9(a) together with its performance shown in Figure 5.9(b).

As may be appreciated from Figure 5.8 it is essential in the design ofbroadband matching networks to ensure that the network is capable ofsynthesizing the necessary changes in impedance such that a wantedgain slope compensation and gain ripple can be met. It is often necessaryto optimize the initial design values on a computer to minimize gainripples etc. Such an optimization will also account for the non-unilateralbehaviour of the transistor.

5.4.2 Design Where Stability Is Considered

A shunt resistor at the output of the FET can be used to increase thestability factor. A 500 ohm resistor can be used in this particular caseto produce a stable gain condition with a K = 1.7 at 10 GHz. This lowersthe amplifier gain by approximately 3 dB over the maximum available

180°|

T

The shunt LC combination is needed in order tobroadband the design.

-90*

Figure 5.8 Input Constant Gain Circles at 8 and 12 GHz and theMatching Sequence of the Network shown at 8 GHz


0.9n

GAT 6

1.5n 0.6n

1PT 0.3n 1.2n0.33n;

0.27nl1.3p 13

(a) Conditionally stable 8-12GHz GaAs FETamplifier.

(b) Response of 8-12GHZ amplifier having 8 9 10 11 12conditional stability. Frequency, GHz

Figure 5.9 (a). Conditionally Stable 8-12 GHz GaAs FET Amplifier(b). Response of 8-12 GHz Amplifier having Conditional Stability

Impedance or AdmittanceCoordinates

- 9 0 °

Figure 5.10 Output Matching Sequence for Stable Amplifier


gain with no resistor. Figure 5.10 shows the output matching sequenceagain using lumped elements where in this example the gain slopecompensation needed (approximately 3.8 dB per octave) is produced byreactively mismatching the FET at low frequencies but matching at thetop end of the band. Figures 5.11a, b show the complete matchingnetworks together with the amplifier response. It is noticed, becausethe input network has been chosen to give 0 dB gain slope, that the inputVSWR is much more constant than the output VSWR which is low atthe high end of the band becoming progressively larger towards the lowend, thus mismatching the output of the FET and lowering its gain.

Stabilization can also be produced by using common lead inductivefeedback, which is a popular method when noise figure is of importance.It is also possible to stabilize the previous example by using a balancedamplifier approach or using input and output isolators where the re-flected energy, due to | Sn | and | S221 not being zero, is dumped into aload other than the source load.

5.4.3 Distributed Designs

Since many amplifier designs are based on synthesis techniques requir-ing lumped elements it is often desirable to convert lumped elementdesigns to a close distributed element equivalent by using the following

GAT6

0.8n

0.38n

0.6n 0.8n 0.5p

1.46n >500 2.5n

(a)

8 9 10 11 12(b) Frequency, GHz

Figure 5.11 (a). Lumped Element 8-12 GHz GaAs FET Amplifier(b). Response of Lumped Element 8-12 GHz GaAs FET Amplifier


equations which are based on the use of n equivalent circuits fortransmission lines

= Z0sinO for0<9O° 5.18

5.19

where L is the inductance, C is the capacitance, Zo is the characteristicimpedance of the distributed elements and 6 their phase length. It isalso possible to design matching networks directly from transmissionline theory as was done in the narrow-band amplifier design previously.

Considering the conversion of the circuit of Figure 5.11 it is worth notingthat a good approximation is that inductors can be replaced by 120Qcharacteristic impedance short circuit stubs or unit elements and ca-pacitors can be considered as 25Q characteristic impedance open circuitstubs. This approximation is particularly useful when implementingthe resultant network in microstrip on alumina of 0.635 mm thicknesssince the two impedance levels correspond to the generally acceptedextremes of line widths which are conveniently reproduced. Figure 5.12shows the result of converting inductors and capacitors to transmissionlines. Note in Figure 5.12 that a small amount of inductance has been

(a)

10

E 9.5

Output

(b)9 10 11 12Frequency, GHz

Figure 5.12 (a). Distributed Element 8-12 GHz GaAs FET Amplifier(b). Response of Distributed 8-12 GHz GaAs FET Amplifier


left at the FET ports allowing wire-bonding to take place in the realiza-tion. Figure 5.12 also shows the resultant response of the circuit.

5.5 Designing an Amplifier For Optimum Noise Figure

In many applications such as for receiver preamplifiers the amplifierdesign objective is minimum noise figure rather than maximum gain.The main task is to synthesize the optimum source admittance forminimum transistor noise figure at the FET input plane.

The noise performance of GaAs FETs is superior to that of bipolartransistors above approximately 4 GHz. For example the Plessey GAT6device exhibits chip gains of 10 dB with a noise figure of 2 dB at 12 GHz.A theoretical treatment of GaAs FET noise performance has been givenby Hewitt et al (1976) and the bias dependence of the FET device noisefigure is predicted by the noise theory of Pucel et al. This theory predictsthat the minimum noise figure is obtained at low drain currents ofapproximately 15% of the saturated drain current. This is more fullycovered in Chapter 2.

5.5.1 Constant Noise Figure Circles

In many amplifier designs the overall noise figure of the amplifier isimportant since this defines the signal to noise ratio at the output of theamplifier.

If we consider an infinite cascade of transistors all operated at theirminimum noise figure d.c. bias conditions, then the lowest cascadednoise figure (often referred to as the noise measure, M) is given by

5 - 2 0

where each stage has a noise figure F and associated gain, G.

In general, for an arbitrary source reflection coefficient Fs, the noisefigure is determined by the equation

F = Fmin+4RN l 1 * " 1 ^ 5.21(7-|r5|2)|/+ro|2

where Fo is the optimum reflection coefficient of the source whichproduces the minimum noise figure Fmin and RN is the equivalent noise


resistance of the device. Equation 5.21 has the form of a circle. Todetermine a family of noise figure circles the noise figure parameter Niis defined where

where Fi is the value of the desired noise figure circle and Fo, Fmin andRN are as previously defined. The radius of the circle is given by

5 - 2 3

and the center by

5.24

From these equations we see that Ni = 0 when Fi = Fmin and the centerof the Fmin circle with zero radius is located at Fo on the Smith Chart.The equivalent impedance to Fo is often referred to as ZOPT, the optimumsource impedance for minimum noise figure.

The value of RN can be found by measuring the noise figure when thesource impedance is 50 ohms so that Fs = 0 and

~~ Fmin) . °a 5.25

Figure 5.13 shows the noise circles at 8,10 and 12 GHz for a GAT6 FETchip device. All these plots show ZOPT at a point where the gate wirebond is attached to the 50 ohm transmission line. Figure 5.14 shows aplot of RN against frequency for the same device.

5.5.2 Noise Modelling

It is useful to have the concept of a noise model when designingamplifiers which need to have optimum noise tracking over their fre-quency band. A device model can be derived that has an input imped-ance equivalent to the complex conjugate (ZOPT*) of the optimum noiseimpedance, ZOPT.


Figure 5.13 Constant Noise Circles

For an FET connected to a network at its input that presents ZOPT to theFET, the input impedance at the driving source terminal (50Q) is notpower matched, i.e. not 50Q. However, if the device is replaced by anequivalent noise model which represents ZOPT* over a frequency range,the input impedance is now 50Q. This technique enables networks to

30

w 20

Occ

10

0

-

8

\

\

10 12 14

Frequency, GHz

16 18

Figure 5.14 Frequency Sensitivity ofRn for a Plessy GAT5 Chip FET


be derived that provide optimum noise tracking. From the plots of ZOPTthat have been measured or extracted from a data sheet, ZOPT* can befound and an equivalent RLC model derived that fits this ZOPT* data.This RLC model can be computer optimized. This RLC model is used toprovide the impedance necessary to derive a minimum noise matchingnetwork which can be combined with the S21, S12 and S22 of the FET.

Podell et al (1979) have shown that the noise performance of GaAs FETscan be adequately described by two effectively uncorrelated noisesources-one at the input of the FET due to thermal noise generated inthe various resistances in the gate-source loop, the other in the outputof the FET due to the Gunn domain between the gate and the drain ofthe device.

The input conductance gi of the FET can be approximated by:-

(27tf)2CGS2(RI + RG + Rs) 5.26

Podell et al have found that RN in a GaAs FET can be approximated bythe expressioni-

where I = IDS /IDSS and Ko, K2 are empirical constants.

Ko is approximately 1 for 0.5 micron FETs and 0.5 for 1 micron FETswhilst K2 has a value of 2.5. Both these constants are independent offrequency.

The optimum source admittance can be calculated with the followingequations:-

5.28

5-29

where * denotes the complex conjugate and Qi equals 1/2TC fCGS (Ri + RG+ R) and A = giR. In addition

( 2f 5.30


From the above equations, once the equivalent circuit of one FET andits noise figure at one frequency are known, the optimum noise sourceimpedance and noise figure at any frequency can be calculated.

The equation for FMIN above relates the noise factor to the parameter A.It is desirable to minimize both the noise and the input Q of the FET,particularly at low microwave frequencies where the input Q is ex-tremely high, and losses in the input matching network can be asimportant as losses in the input of the FET itself. This is particularlytrue in MMICs where the Q of the matching networks is low (usuallyaround 50).

The reader is referred to the original paper for more details and exam-ples.

5.6 Broadband Amplifier Designed For Minimum Noise Figure

It is desired to design a low noise broadband 8-12 GHz amplifier foroptimum noise performance over the band together with a flat gainresponse using the device whose S-parameters are given in Table 5.5and whose noise data is given in Figure 5.13.

5.6.1 Input Matching

The equivalent noise input impedance can be approximated with acapacitance dm in series with a resistance Rim in series with an inductorLim with good accuracy over the desired frequency range. The valuesdm = 0.23 pF, Rim = 12Q and Lim = 0.41 nH are found by fitting themeasured input impedances to those predicted. It is desired to producea Tchebyshev impedance matching network to match the generatorimpedance Zo to the noise input impedance ZOPT. Tchebyschev proto-types (Matthaei et al, 1964) can be selected to maximize the bandwidthand provide a good match at the band edges.

In order to establish the number of resonators required to synthesizeZOPT* with a specified accuracy between the lower and upper band edgesa maximum noise figure increase from the optimum values has to bespecified. Let us assume that 0.6 dB excess noise figure can be tolerated.For example, at 10 GHz by inspecting the constant noise figure circlesit can be seen that a worst case VSWR of approximately 2:1 can betolerated with respect to ZOPT*. In synthesizing ZOPT* with a Tcheby-schev impedance matching network the bandwidth can be computed


Table 5.5 Typical S -Parameters for a GAT6 Chip at IDS = 10 mA,VDS = 5 volts (Minimum Noise Figure Conditions)

Freq.GHz

4

5

6

7

8

9

10

11

12

13

14

15

16

Mag

0.93

0.9

0.88

0.85

0.83

0.81

0.79

0.77

0.75

0.74

0.72

0.7

0.68

S11

Ang

-43

-54

-64

-75

-85

-93

-101

-110

-116

-123

-130

-137

-144

Mag

1.66

1.59

1.52

1.46

1.4

1.34

1.29

1.24

1.19

1.14

1.1

1.06

1.03

S21

Ang

134

125

115

106

97

90

80

72

64

55

47

38

31

Mag

.039

.042

.045

.048

.05

.052

.055

.057

.059

.061

.063

.066

.068

S12

Ang

64

62

61

60

60

61

63

65

67

69

71

72

71

Mag

0.79

0.79

0.78

0.78

0.77

0.77

0.77

0.77

0.77

0.77

0.77

0.77

0.77

S22

Ang

-24

-29

-34

-39

-44

-49

-54

-60

-65

-70

-75

-81

-85

using the VSWR versus load decrement curves plotted in (Matthaei etal, 1964, Figure 4.09-3).

The network shown in Figure 5.15 will provide wide-band input imped-ance matching. Details on the use of inverters in network synthesis,shown in Figure 5.15, can be found in Matthaei et al.

The FET's equivalent noise input impedance is resonated with the seriesinductance Li and coupled to a network consisting of 2 quarter wave-length resonators. In this technique the resistance Rim = 12Q can beconsidered the load resistance and (Li + Lim)-Cim the last resonator ofa 3 stage bandpass filter coupling Rim to the source resistance Zo.

By choosing the resonator line impedances to be equal to Zo the inverterconstants of Figure 5.15 are given by (Matthaei et al, 1964)


Impedanceinverter

—134 —134

Zo T Zo

Input, Zo M X *

Inverter KM

constants:

A/4Resonator

Zo

Admittanceinverter

- l 2 3 - l 2 3

Zo Zo

A/4Resonator

1 r-Zo

Impedanceinverter

-1,2 - U L,

Zo T

Mjx,2

jK« 1

Rmi

FET Input

Figure 5.15 Wideband Impedance Matching Network for MinimumNoise Figure

v -- H 5.31

710) ( 15.32

and

K -z( *" 5.33

where w is the relative bandwidth

(0 = •

fo5.34

where f0 is the center frequency =


and where fu and ft, are the upper and lower amplifier band limts. d isthe decrement of the load impedance at f0 given by

dj2nfoRimCim) 5 3 5

CO

gi, g2, g3 and g4 are the normalized element values of the Tchebyschevimpedance matching prototype for the decrement d (Matthaei et al,1964).

Series Inductance

L Z Lim 5.36C

Impedance Inverters

5.37

to

-iK=j^tan-'\-^\ 5.38

and

T ~ K12

Admittance Inverter

J

5.39

B23=—^-T 5.40

£23=—tan '{2B23ZO) 5.41

where X is the wavelength of the transmission line at f0.

The synthesis of the X-band amplifier with

f=8tol2GHzRim = 12


dm 0.23 pFLim = 0.41 nH (including 0.12 nH of wire bond)

is as follows

(12-8) ^Aa) = = 0.4

10(2101012

6=-0.4

6=0.433

For a decrement 6, Figure 4.09-3 of (Matthaei et al, 1964) indicates thatan insertion loss maximum of 0.85 dB will be achieved with n = 2 witha corresponding Tchebyschev ripple of 0.4 dB. However, this will not fallwithin the criterion of 0.6 dB increase in noise figure. Thus with n = 3we have an insertion loss maximum of 0.6 dB and a corresponding rippleof0.2dB.

For the decrement 6 = 0.43 and n = 3 the normalized element values ofthe Tchebyschev impedance-matching prototype can be found fromFigure 4.09-7 of (Matthaei et al, 1964).

gi = 2.3, g2 = 0.68, g3 = 1.5 and g4 = 0.53.

Series Inductance

109

L (0.41 - 0.14) nH(27flO10) •0.23*10~12

= 0.81 nH

Impedance Inverters

12 = -———

7 -

where

7fO.4*1212 \4 • 2.3•0.68Zo* 0.43

TO Or

••• .. nH, i.e.0.3nH2x*1010


the equivalent shunt inductor being

and

Thus the first inductor is (0.8-0.27) nH = 0.53 nH

X = K*

1-

where

the

and

K - \K34 ^ 4

.'.X34=52

equivalent

5227flO10

(OAJI)

•1.5*0.53

shunt inductor being

0.83 nH

which is equivalent to a phase length of 26.3°

Admittance Inverters

where


23 4ZO {o.68*1.5

therefore B23 = 13.1 xlO~3 the equivalent series capacitor being

13.1 *10~3

l23 = -A- tan-1 (2 •B23*ZO) = 0.073X471

and I12 + I23 = (0.05 + 0.073)A = 0.123A

Thus the resonator length is (0.25-0.123)A = 0.127A

and I23 +134 = (0.073 + 0.09)A = 0.163A, with the corresponding resonatorlength of: (0.25-0.163)A = 0.087A.

5.6.2 Output Matching Network

In this example the transistor has been matched for minimum noisefigure over the band so that the device will exhibit a gain slope ofapproximately - 3 dB/octave, a figure found by measurement for theparticular FET. An ideal output network then has to couple all availablepower to the load at the upper band edge, fu and provide a frequencydependent attenuation that compensates the FET's gain slope for f < fu.

A network suitable for this is shown in Figure 5.16.

The output impedance of the transistor Rom (in this particular case equalto 250 ohms), in parallel with COm (in this case 0.17 pF) is resonated withthe series inductance Lo at the upper frequency, fu. The transformermatches the resulting resistance to the load Zo.

At fu, no power is dissipated in the resistor Ri since it is connected inseries with a short-circuited stub being A/4 at fu. Below fu the powertransferred to the load decreases since the impedance of the resonatedFET output changes rapidly and the shunt branch with the resistorbecomes increasingly lossy. The resistance RM and the transmission lineimpedance ZM are chosen to give the best approximations to a 3 dB/oc-tave slope.

The complete circuit is shown in Figure 5.17.


Output coupling network load

Figure 5.16 Wideband GaAs FET Output Matching Network

The value of the resonating inductor Lo is found at the upper band edgefrequency of 12 GHz to be:

(27fl2*109) •0.

= lnH

The Q of the FET output is given by

/ 37fi \V.089A/

R.F. input J a 8 3 n

J(10n)0.3n(0.42n)

(0.97n)1n 35^,76°

R.F. Output

195ft 76°1(1170,77°)

Figure 5.17 Single Stage Low Noise XBand GaAs FET AmplifierWith Absorptive Output Matching


Q = 2nfuRomCom

= 2n*12*109*250*0.17*10~n

= 3.2

Leichti et al (1974) have shown that for such a Q value

-^- = 0.21, i.e.R1 = 52.5Q

^ = 0.38, i.e. Zj =z,

Rom

and the transformer ratio

m = 0.707

i.e. a quarter wavelength resonator of impedance 35Q of length 0.2 Xk atthe center frequency of 10 GHz.

The accuracy of the design using the unilateral model has been checkedusing computer analysis and optimization with the FET represented byits S-parameters and optimum noise reflection coefficients etc., usingthe COMPACT program. The resulting element values are shown inFigure 5.17 in brackets. It may be appreciated that the initial elementvalues are close to those finally adopted after optimization and thiscircuit gives a theoretical noise figure which is 0.6 dB higher than theoptimum noise figure at 8 GHz. Worst case input and output VSWR'swere 3.5:1 and the gain was 8.8 dB ± 0.25 dB.

It should be stressed that the above example is only one method thatcan be used to synthesize networks suitable for low noise amplifierrealization. The choice of a particular means of matching into a deviceis often dictated by the available technology and the device selected. Forpackaged devices, for example, it is desirable to add a short length ofline to the packaged FET S-parameters to act as a soldering area. Suchaction moves the matching load impedance of the device and this shouldbe assumed at the beginning of the design.


5.7 Computer-Aided Design Practice

Computer-aided analysis and optimization of microwave circuits is nowprevalent. Although the computer should not be a replacement for goodmicrowave engineering practice it is a highly useful and desirableaddition to the microwave engineer's aids to design. Since the firstedition of this book was written in 1981 there has been a revolution inthe power and sophistication of desktop and microcomputers which hasled rapidly to the acceptance of microwave CAD in the general labora-tory.

For details of the methods by which microwave circuit analysis wasperformed up to 1974 the reader is referred to Monaco and Tiberio(1974). That review included network representation in terms of S-pa-rameters, admittances and impedances, with interconnections definedby topological matrices. Mixed formulations and the ABCD matrixtechnique were used frequently. Sparse matrix techniques were intro-duced to speed up algorithms and the use of syntax oriented topologydescriptions to avoid large network matrices were employed in someadvanced work. However, in the majority of these programs the ele-ments were highly idealized and the consideration of parasitics, forexample, in analysis was rare. There were, however, computer-aidedmicrowave integrated circuit (MIC) layout facilities available as part ofa number of 'in-house' design packages. None of these were commer-cially available.

In 1992, Version 4.0 of the program =SUPERSTAR= PROFESSIONALwas released (Eagleware, 1992) which employed graph theory tech-niques to avoid building a matrix, thus eliminating "nodes" in thenetwork formulation. Typical microwave networks can be formulatedwith only an input node, an output node and the datum (ground) node.This node elimination algorithm is invoked once during a translationphase and generates "inline" instructions for rapid analysis, tuning andoptimization, resulting in execution speeds typically a full order ofmagnitude faster than sparse matrix techniques.

Some time ago optimization had achieved a high level of sophistication(Bandler, 1969 and 1971; Charalambous, 1974), including sensitivity andtolerance analysis of circuits. Since that time progress has beenachieved mainly in the areas of application flexibility, speed, man-ma-chine interfacing, employment of 'smaller' computers and accuracy.Monolithic microwave integrated circuits have increased further theneed for improved CAD tools and have started a new phase of develop-


ment mainly directed at being able to interactively analyze microwavecircuit performance using the geometry of the circuit rather than elec-trical equivalent circuits of the components.

In the field of non-linear microwave CAD numerous results have beenpublished and unified approaches to computer-aided non-linear MICdesign have emerged (Chua et al, 1981; Rizzoli et al, 1982; Sobhy, 1984).Modifications of the harmonic balance method (Lipparini, 1982) havethe best chance to become general purpose algorithms. A particularlyelegant approach by Lipparini eliminates the need for repeated completeanalyses of the circuit by using a special optimization strategy.

5.7.1 Typical Linear Microwave CAD Program Format

There are a number of commercially successful linear microwave circuitanalysis and optimization programs in use today including =SUPER-STAR= PROFESSIONAL, TOUCHSTONE, and SUPER COMPACT, aswell as lesser known and 'in-house' packages. Additional informationon the evolution through the mid 1980s of CAD for microwave circuitsis found in Jansen (1983) or Hoffman (1984).

All microwave CAD programs tend to have a number of items incommon. Many of these features as they relate specifically to =SUPER-STAR= PROFESSIONAL (Eagleware, 1995) are now described.

Circuit Elements. Circuit elements, both passive and active, are inputinto the program as building blocks in either a text file "net-list" or as agraphic schematic using the editor =SCHEMAX= (Eagleware, 1995).Passive elements may be either lumped or distributed and can be easilyvaried manually (tuning) or automatically (optimization). While manyprograms use a full or sparse matrix reduction algorithm, =SUPER-STAR= PROFESSIONAL uses a faster node-elimination algorithmbriefly described previously. Either provides complete interconnectionflexibility. Accurate and up-to-date formulations, equations or look-uptables are used for element models derived from the geometry of theparticular component structure under consideration. For example, amicrostrip transmission line whose parameters are input as line width,physical length, effective dielectric constant and loss factor at a definedfrequency are transformed within the program to characteristic imped-ance and electrical length considering dispersion and loss. S-parameterand optimum noise figure data are read from standard device librariestypically provided by the active device manufacturer.


Analysis Specifications. Analysis specifications are entered andstored with the net-list or in a text portion of the schematic. Suchspecifications include the frequency sweep range and number of fre-quencies, the output data to be displayed and scales for graphing, andresponse goals for optimization or yield analysis.

S-Parameter and Noise Figure Data. S-parameters are specified inlibrary data files. Each row in the data file begins with a frequencyfollowed by the magnitude and angle of the S-parameter data for thatfrequency. The S-parameters data is automatically interpolated (andextrapolated) for the frequencies specified for the analysis. Noise datafor transistors is specified in terms of the minimum noise figure, theoptimum reflection coefficient, ZOPT, and the equivalent noise resistance,RN. The format of these files has become standard. Such device data isavailable from many device manufacturers and thousands of data filesare supplied with =SUPERSTAR= PROFESSIONAL. One, two andmulti-port data is supported.

Variable Parameters. Components which are to be varied for tuning,optimization or statistical analysis simply have a "?" prefix added to thecomponent value. For example, C = ?10pF.

Embedded Equations. The user may substitute a variable name forone or many element values within the network. An EQUATE block inthe net-list or schematic is then used to define and compute the elementvalues. For example, C=Ctotal could be followed with an EQUATE blockcontaining three lines; Cl=?10, C2=O.5*C1+1 and Ctotal=Cl+C2.

Negative Components. Many element models allow negative valuesso that the the user may 'subtract' elements from a circuit, thus allowingthe engineer to 'strip-off' certain parts of a circuit, for example, to revealthe S-parameters of an 'embedded' device. This is useful, for example,in obtaining the chip parameters of FETs, referenced to their bondingpads. It is also useful for removing phase rotation to observe peak-to-peak phase ripple on flat instead of sloped phase responses.

Optimization. A number of optimization algorithms have been devel-oped. Direct search algorithms can be made resistant to "hang" whilegradient algorithms offer rapid initial progress. =SUPERSTAR= PRO-FESSIONAL includes an automatic mode which dynamically selects theappropriate algorithm to use during different phases of the optimizationprocess. Optimization adjusts element values with a "?" prefix in anattempt to minimize an error function. The total error function is a sumof even p-th powers of individual errors from response targets for gain,phase, return loss, group delay, etc.


Statistical, Sensitivity and Yield Analysis. Statistical analysisprovides the user with insight into the effects of component tolerance.One method is Monte Carlo analysis where components are altered ina random fashion within specified limits thus simulating, for example,production tolerances on transistor noise figures and associated gains.Sensitivity analysis is used to ascertain which elements contribute mostsignificantly to specific response degradations. Yield analysis is used todetermine statistically the number of units in a sample which meetspecified response targets.

Noise Analysis. Early microwave CAE programs supported noiseanalysis only for restricted topologies and the user was required to writea special noise block. =SUPERSTAR= PROFESSIONAL uses the noisecorrelation matrix (Hillbrand et al, 1976 and Rizzoli et al, 1985) tocompute global circuit noise with no topological restrictions and withoutthe need for a special noise block.

Automatic Layout. Early programs which provided circuit layoutsincluded AUTOART for use with SUPERCOMPACT and MICAD for usewith TOUCHSTONE. Today most PWB manufacturing facilities useGERBER files for photographic generation of film. A layout module for=SCHEMAX= is available which generates laser printer, Postscript,DXF, HPGL and GERBER output.

5.7.2 CAD Program Techniques

A few rules worth bearing in mind when using microwave CAD, andspecifically optimization, are:

1. Use conventional matching theory with a Smith chart or synthesistechniques to obtain a starting circuit for analysis and optimization.

2. Avoid large numbers of frequencies or variables. This results inexcessive computer time. It is often possible to select the mostsensitive elements by inspection of the individual component errorfunction evaluations after a few trial analyses.

3. Devices should be stabilized before optimizing amplifier circuits.Shunt resistors at the device input and output, resistive feedback orsource-to-ground inductance often improve stability.

4. Complicated circuits, such as multistage amplifiers, should not beoptimized before individual, single-stages are analyzed.


5.7.3 Non-Linear Analysis Programs

Advances in non-linear analysis of microwave circuits, particularlyemploying FETs, have become significant during the last few years. Thepower of workstations and personal computers has aided the growth inthis area tremendously. The first unified approaches to computer-aidednon-linear MIC design are now emerging (Sobhy et al, 1985; Chua et al,1981: Rizzoli et al, 1982 and Lipparini et al, 1982, for example). Non-linear analysis of circuits requires bias dependent electrical models ofactive devices such as FETs and diodes. These general CAD packagesemploy either frequency or time-domain analysis techniques. Time-do-main analysis requires all circuit parameters to be input in the timedimension e.g. transmission line lengths are usually given in picosec-onds of transit time. Results are given in the time dimension as voltagesand currents at any node within the circuit. Fast Fourier transformationis employed to display results in the frequency dimension. This tech-nique can be very powerful since, for example, transient voltages andcurrents can be inspected at points both 'inside' and 'around' activedevices giving information on whether the maximum ratings of thedevice are being exceeded. Time-domain analysis, on the other hand,tends to be slow requiring many CPUs particularly if low frequencies(with corresponding large periods) are involved. A good example oftime-domain non-linear analysis is the ANAMIC program by Sobhy etal (1985) which employs state-space variable techniques.

Analysis and optimization in the frequency domain is most effectivelyproduced using harmonic balance techniques. Problems involving evenstrong non-linearities have been treated and the application to Class-Camplifiers, oscillators and frequency dividers has been demonstrated. Aparticularly elegant approach by Lipparini et al (1982) eliminates theneed for repeated complete analysis of the circuit by a special optimiza-tion strategy.

Whether the non-linear analysis program employs time or frequencydomain techniques non-linear models of active devices are requiredwhich reflect accurately the bias dependent d.c. and r.f. behavior of thedevice simultaneously.

5.7.3.1 General non-linear MESFET model

A circuit model that can be used for the MESFET tinder large-signalconditions is shown in Figure 5.18. There are five non-linear elements


I—!>HGo—A/W—rw^-

f VW 1I Rf Cf

-V\A^-nnrL-OD

' C DS

-OS

Figure 5.18 Non-Linear Equivalent Circuit ofMESFET

Cos, CGD, DGS, DGD and IDS and a non-linear parametric resistor, Ricontrolled by VGS, the voltage across CGS.

Both the capacitances CGS and CGD can be described by the relation:

C(V) = -i 5.42

where Co is the value of the capacitance at V = 0 and VBI is the built-inbarrier voltage of either the gate-source or the gate-drain Schottkybarrier diodes, DGS and DGD.

The currents through DGS and DGD are given by:-

l(V)=Ioexp\— -7 5.43

where Io is the saturation current at V » V T where VT is the thresholdvoltage. The non-linear controlled source IDS is a function of the delayedvoltage VG = VGs(t-r) and the voltage, VDS.


IDS is given by:

D{VG))

•Gunn(VG,VDS) 5.44

where

5.45

5.46

5.47

Gunn (VG, VDS) is present to simulate the Gunn effect on the staticcharacteristics.

The parametric resistor, Ri, is a function of the voltage, VGS:

5.48

VBI can be calculated from:

Vm= 0.706 + 0.06 loge(ND*106)volt 5.49

where ND is the channel doping density in cm"3.

Io is calculated from 3.395 • 10'2LGmWG microamps 5.50

where LG and WG are the gate length and width in microns respectively.

where n is the ideality factor of the Schottky diode.

In order to use the non-linear MESFET model in a non-linear analysisprogram such as ANAMIC (Sobhy et al, 1985) or harmonic balance CAD(Lipparini et al, 1982) it is necessary to evaluate the constants, VT, A, B,L, E, R, F and G, so that the measured static I-V characteristics agreewith the calculated ones.


Table 5.6 Complete non-linear model parameters for 1 micron, 300micron FET

RG = 0.3 ohm

RD = 2 ohm

Rs = 2 ohm

LG = 0.06 nH

LD = 0.03 nH

Ls = 0.07nH

CDS = 0.06 pF

CGSO = 0.25 pF

CDGO = 0.03 pF

VBi = 0.79 volt

Rio = 5 ohm

VR = 0.9 volt

IDGSO = IDGSO= 10// A

VT = nkT/q = 0.04 volt

V T = 1.4 volt

A=1 V"1

B = 28 mA/V2

L = 0.07 V"1

E = 1.9

R = 0.35

F = - 0 . 5 7 volt

G = 0.018 V"2

D = 1 + VG/VT

For example, for a 1 micron, 300 micron wide FET, having an IDSS of 40mA and a VT of 1.4 volts

B = 28mA/V2

L = 0.07V'1

E = 1.9

R = 0.35

F =-0.57V

G = 0.02V~2

Now the small signal S-parameters of the FET will also be known withits corresponding equivalent circuits at different drain to source biaslevels.

A complete set of data is thus available for the design of non linearcircuits such as multipliers and oscillators. An example of such data isgiven in Table 5.6.

5.7.4 Network Synthesis

The use of the Smith Chart is effective and straightforward for narrow-band applications. Simultaneous solutions for multiple frequencies isconsiderably more difficult and time consuming. Passive network syn-


thesis, has been used in the design of filters and can be effectivelyapplied to the design of interstage input and output matching networkseven when the networks operate between unequal impedance termina-tions and parasitic elements are included.

Synthesis routines (Skwirzynski, 1971; Saal et al, 1958) have been inuse for many years and more recently have been extended to include thesynthesis of networks of prescribed gain, bandwidth, ripple, slope andimpedance transformation. Mellor et al (1975) has produced a synthesisroutine on which is based a commercial synthesis computer program,AMPSYN.

The linear circuit simulator =SUPERSTAR= PROFESSIONAL inter-faces directly with a number of circuit synthesis programs also devel-oped by Eagleware Corporation. These programs include =FILTER=which synthesize lumped element filters, =EQUALIZE= which synthe-sizes group-delay equalizers, =A/FILTER= which synthesizes active R-Cfilters, =OSCILLATOR= which synthesizes lumped, distributed, SAWand quartz-crystal oscillators, =M/FILTER= which synthesizes distrib-uted microwave filters and =MATCH= which synthesizes lumped anddistributed matching networks.

5.8 CAD Example

Next, the complete design of a small-signal lumped-element 2-stageX-band wideband (8 to 12 GHz) GaAs FET amplifier is illustrated usingthe synthesis program =MATCH= and the simulation program =SU-PERSTAR= PROFESSIONAL. We will use an Avantek 0.3 micron gatelength GaAs FET model ATF-13336 in a micro-X package biased at 2volts and 20 mA. The design will be based on measured S-parameterdata provided by the manufacturer.

5.8.1 Step 1 - Stabilize

The first step is to examine the stability of the active device. A commondesign mistake is to examine stability of only the finished amplifier. Anamplifier which would be stable at the external terminals may stilloscillate due to improper internal termination of the active devices.Therefore the stability of the ATF-13336 is examined without anyamplifier circuitry. Fig. 5.19a is a =SUPERSTAR= PROFESSIONALscreen plot of the S-parameters for the ATF-13336.


S12 S11 S22

12000i 10.852i2U5%

S12 —8000 120008.88744 8.4S79S

..-2SJ.Q2A rZLJlSL.

160004.64494

S11 —2000 8000-0.755691 -6.6618

S22-—12000-4.93966 -5.5175

--JQJ3Q75-

12000 8000 12000 16000 2000 S U S i M 1 2 0 0 0 16000fSTABLE STABLE STABLE STABLE STABLE STABLE STABLE STABLEIOUTSJPJ..pJJTSIDE.OyjjSIDE.OUTSIDE. OUTSIDE ,.j,NS(DE.,...J.NSIDE....,..IJ!JSiD.E...

/

^2000 8000 12000 16000 2000 8000 12000 16000?STABLE STABLE STABLE STABLE STABLE STABLE STABLE STABLELQUTSiQJLQUT^lDEag^

(a)

(b)

(c)

Figure 5.19 (a) S-parameters plotted for an ATF-13336 FET, (b)stability circles and (c) stability circles with 0.12 nH source inductance.


Plotted in Fig. 5.19b are the input plane (left) and output plane (right)stability circles computed from the device S-parameters. The circles areplotted for the frequencies listed in the top row of the numeric data atthe bottom of the computer screen. The first four frequencies are plottedas circles labeled 1 through 4, respectively. Circles labeled 5 through 8represent the same frequency range on the output plane. In Fig. 5.19bwe see that the input plane has regions of potential instability insidecircles 1 and 2 at frequencies of 2000 and 8000 MHz, respectively. Byinference we may assume that circles at intermediate frequencies lieinside the Smith chart. Therefore the ATF-13336 should not be termi-nated at the input in an impedance with a low resistive component,particularly at frequencies below the desired 8 to 12 GHz passband.

Notice at the output plane some of the stability circles represent regionswhich are stable inside the circle and others are stable outside the circle.The stability is even more precarious at the output than at the input.Circle 5 at 2000 MHz has a large region of instability. By 8000 MHz theunstable region is much smaller. As with the input, stability would beenhanced by output terminations at low frequencies with a high resis-tive component and a capacitive reactance. This is satisfied by usingmatching network structures with a series capacitor adjacent to theATF-13336.

Stability at both the input and output is improved slightly by adding asmall amount of inductance in series with the device path to ground atthe source. Stability circles with 0.12 nH of inductance at the source areplotted in Fig. 5.19c. The resulting S-parameters are plotted as dashedtraces in Fig. 5.19a. Additional inductance reduces available gain fromthe device. Additional stability could be achieved by adding shuntresistance at the device input and output. However, that would alsofurther reduce the available gain. In this design we will managestability by selecting matching networks with series capacitance adja-cent to the device.

One final note on stability. It is important to analyze stability over abroad frequency range and not just the frequency range of the desiredamplifier. In this case, had stability been analyzed over the 8 to 12 GHzrange the instability problem at lower frequencies would have beenmissed. Achieving stability over the desired range is of little help if thecircuit is oscillating at lower frequencies. Furthermore, we probablywould have missed the concept of using a series capacitor in the match-ing networks.


5.8.2 Step 2 - Synthesize for Maximum Gain

The next step in the design process is to find the input, interstage andoutput matching network topologies and element values which realizethe highest gain with a flat frequency response and minimum noisefigure. To do this, we will use the matching network synthesis program=MATCH=. Shown in Fig. 5.20 is the Intial Network Parameter screenof=MATCH= which supports up to 11 entities in a match problem. Eachof these entities may be a matching network type synthesized by=MATCH= or a call to a file containing S-parameter data for a device.A button (A through K) corresponding to one of these entities is pressedand then a network type and details are specified in lower portion of theIntial Network Parameter screen. In this case only five entities areneeded, the two devices and three matching networks.

| i Initial Network Parameters

'£;'' a.

rs-: CL-

CL-TTF

Custom Ji'fr

S Data File: atf13336.sta H

L-C Bandpass 1<

S-Data File: atM 3336.sta JL

|L-C Bandpass |

Data File

C Pi Network

C Tee Network

1L 1/4 Wave

C Allow Transformer

O N O Transformation

<§ No Transformer

0 TRL Sng/Dbl Stub C TRL Stepped Zo |

SjL-C Bandpass] Q Custom \

OL-CPseudoLowpass |

0 TRL Pseudo Lowpass \

Order: 3 S

Figure 5.20 =MATCH= Synthesis Program Screen for Selecting theMatching Network Type for Each Stage.


In Fig. 5.20, button E is active and an L-C bandpass structure is selected.The allowed complexity of this network is controlled by user specifica-tion of the network order, in this case 3. The interstage was alsoselected as an L-C bandpass structure. The input network was specifiedas a custom network. ropt for best noise figure suggests the inputmatching network should be a shunt capacitor followed by a capacitorin series to the ATF-13336 gate. Fortunately this is consistent withstability needs. Selection of custom allows the user to build a networkschematic using inductors, capacitors, transmission lines, resistors andtransformers. In this case, within =MATCH= the capacitive networkneeded for best noise match was built. The algorithms which findelement values are not as efficient for custom networks as for the built-instructures, however in this case it supports achieving specific require-ments.

Other screens within =MATCH= allow the user to specify the desiredfrequency range for matching (in this case 8 to 12 GHZ and not the fullrange of S-parameter data) and the terminations. In this example theinput and output terminations are simply 50 ohms resistance.

Once the match problem is defined, =MATCH= synthesizes the net-works to minimize the mismatch at each interface. In general thedevices are not unilateral. Therefore, as each network is synthesized anew impedance is presented to previously synthesized networks.=MATCH= handles this by repeatedly re-synthesizing the networks.This is more effective than optimizing all element values becausesynthesis is closed-form, rapid and more efficient than search algo-rithms.

5.8.3 Step 3 - Optimize for Desired Responses

Given in Fig. 5.21a is a schematic of the 2 stage amplifier with matchingnetworks and value as synthesized by =MATCH=. The element valueshave been rounded to two significant digits. =MATCH= synthesizes forminimum mismatch at each interface. This maximizes available gainbut typically results in gain down-slope with frequency.

The solid traces on the =SUPERSTAR= PROFESSIONAL simulatorscreen as shown in Fig. 5.21b are the cascade gain (S21) and noise figureon the left grid and input and output return loss (Sn and S22) plotted onthe Smith chart. Next, optimization in =SUPERSTAR= PROFES-SIONAL was used to flatten the gain response and improve the outputmatch. Without the use of an isolation device such as a circulator,


ATF-13336

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2 5 (b)

eoooS21 —800020.23542.45221

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9200-2.37367-10.9012

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S2210800-10.5572-24.348

CJC10

89 B.1B4231

12000-3.08281-21.1685CX7 CX5

12S0642 1.51!

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(c)

S11 S22

S21 —800020.37442.55331

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920020.76111 82101

a.i iX212 0.15

1080017.8066213192

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120001834682.4549

CXS LL3062 0.3

S11 —8000-2.69304-24 3201

L.L415

9200-2.79404-8.96369

C.C2 C.C31 1

S22—-10800-10.4617-14 5052

C.C10DIE

12000-3.17936-252047CJC7 CCS0 27 15

t 25 (1BR|. F3-Opl F4-Iuo. TB-HmA FfrEA F7 T«tr. 5* FS

Figure 5.21 (a) 2 Stage X-Band Wideband GaAs FET AmplifierSchematic, (b) Responses Before (Solid) and After (Dashed)Optimization and (c) Monte Carlo Analysis.


excellent input match and optimum noise figure are typically notachieved simultaneously. In this case, optimization was applied to thenoise figure and the resulting input match (the dashed response gener-ally in the upper half of the Smith chart well removed from the centerof the chart) was poor. The output return loss was successfully confinedmuch nearer the center of the chart. The noise figure is less than 2 dBacross the frequency range of interest. The optimized element valuesare given along the bottom of the computer screen.

In Fig. 5.21c the optimized element values were rounded off and a MonteCarlo analysis with a uniform distribution of 5% tolerance of elementvalues is plotted.

5.9 The Use Of Single Ended And Balanced Amplifiers

The examples of amplifier design which have been given indicate thatit is possible to design more than one stage of amplification to achievegain flatness over a specified bandwidth. However, for multistage am-plifiers where gains of 30 dB or greater are required the use of such"single-ended" realizations can lead to difficulty in producing the re-quired gain flatness etc. This is because of the mismatches occurringbetween gain stages causing gain and phase variations, in the single-ended case it is possible to significantly reduce such gain ripples by usinginterstage as well as input and output isolators. These devices canproduce significant loss which will increase the overall noise figure ofthe unit. For integrated amplifiers such isolators can also be compara-tively large unless they are integrated into the amplifier medium, e.g.the use of planar isolators with a microstrip amplifier.

An alternative approach which is often used in commercial amplifiersis the adoption of balanced amplifier techniques. Figure 5.22 illustratesthe concept. Two amplifier units of the same performance are arrangedbetween the output and input ports of quadrature 3 dB couplers. Thetheory of balanced amplifiers has been given by Kurokawa (1965) andit may be shown providing the two amplifiers are matched in theircharacteristics that the input VSWR and output VSWR are predomi-nantly dependent on that of the couplers.

If the individual amplifiers in the balanced pair are not perfectlymatched at certain frequencies then a signal in the 0° arm of the couplerwill be reflected from the corresponding amplifier and a signal in the7t/2 arm of the coupler will be similarly reflected from its amplifier. Ontraveling through the coupler after reflection the signals will again be


R F Input °°

V3dB quadrature coupler

Amplifier

Amplifier

n/2\ /y

0/ \

3dB Quadrature coupler

Isolatednport

_R.F.Output

Figure 5.22 Balanced Amplifier Arrangement

phased 0 or 7t/2 and the reflected power is 'dumped' into the isolated port(Figure 5.22).

In a microstrip realization for octave band-amplifiers one of the mostpopular 3 dB couplers is the so-called Lange coupler which achieves thecoupling factor required by using interdigitated A/4 fingers (Lange,1969). Another coupler which is used for more narrow band applicationsis the 'branch-line' coupler (Reed et al, 1956).

The overall noise figure of the amplifier is the same as the equivalentsingle-ended amplifier with the addition of the loss of the input coupler.However, the amplifier is able to handle an increase of 3 dB in input r.f.power for the same compression characteristic and the third orderintermodulation performance is increased by 9 dB assuming perfectphase matching between the 2 parallel and matched amplifier chains.

Figure 5.23 shows the microstrip realization of a balanced amplifierwhich is fabricated with chip FETs on an alumina substrate medium.

The balanced amplifier has the further advantage that if for some reasonone of the FETs fails in a unit then the amplifier will still operate albeitwith a reduced performance.

Balanced amplifiers enable the design engineer to produce a matched'gain block' which is able to be cascaded with other matched 'blocks' suchas other amplifiers, attenuators, detectors etc.


HHHBBHBHHHHI

weFigure 5.23 Example of Wideband Balanced Amplifier (5 to 10 GHz)

A major advantage of the balanced configuration is that of stability. Ashas already been demonstrated stable gain can be assured in a single-ended amplifier by using a stabilizing resistor (or reactance in the sourceto ground connection). However, such action reduces the available gainof the transistor and does not allow the minimum noise measure to beachieved in a multistage amplifier. The use of balanced units ensuresthat the input and output of each FET stage 'sees' an impedance closeto 50 ohms. Indeed the stability factor of such a balanced stage can bean order of magnitude higher than its single-ended equivalent, depend-ing on the VSWRs and isolation of the quadrature couplers used (Kurok-awa, 1965).

The disadvantage of using the balanced approach is that the unit usesdouble the number of active devices in a single-ended unit, is larger andconsumes more d.c. power. However the advantages to be gained fromthe balanced approach will usually outweigh the disadvantages.

5.10 Variations In Amplifier Performance

Transistor parameters which are given in manufacturers' data sheetsare only typical sets of data collected from a large number of measure-ments. In order to allow the use of any transistor of a particular type


and also to allow for circuit realization tolerances it is often necessaryto include some means of adjustment in the designed matching circuits.

For amplifiers realized in a planar transmission medium such as mi-crostrip or triplate the use of adjustable open and short circuited seriestransmission line elements can often compensate for variations in theFET gate-source and drain-source capacitance due to process variationsin channel doping density and variations in the input capacitance andgate resistance due to gate length variations.

Figure 5.24a and b show a typical spread of S-parameters and ZOPT datafor a transistor together with a corresponding circuit which was de-signed to compensate for such variations without affecting the perform-ance of the amplifier (Estabrook et al, 1978).

5.10.1 Variations in Amplifier Performance with Temperature

Figure 5.4 has shown the variation in the associated gain of a singlegallium arsenide FET over the temperature range -40 to +80°C.

Figure 5.4 also shows the effect of temperature on the noise figure of asingle transistor. For a multistage amplifier, therefore, substantial gainchanges can occur with temperature as well as variations in the overallamplifier noise figure. Because of small variations in the S-parameters

-90° f = 14GHz

Contour A is obtained by varying length of Element 2 (O/C stub)Contour B is obtained by varying length of Element 1 (O/C stub)

Intersections of these 2 contours defines the initial unalignedvalue. Impedance coverage about that point is delineated by thecontours emanating from that point. A similar method is used forS22.

Figure 5.24 Typical Method for Adjustment of AmplifierPerformance to Account for Transistor Variations


with temperature the gain ripple over the frequency band of interestmay also alter its character. Thus for certain applications, particularlymilitary, an amplifier must be constructed which has integrated com-pensation to maintain gain to within specified limits over a certain rangeof temperatures.

This can be achieved using three different techniques.

1. By varying the bias on single-gate FETs.

2. By using the AGC facility of a dual-gate FET by varying the biason the second-gate.

3. By using a PIN diode attenuator.

With all three methods a temperature sensing element is needed suchas a thermistor or diode, a circuit enabling the gain change law' of theamplifier to be realized and a drive circuit.

5.11 Designing an Amplifier for a Specified Linear Output Power

So far in this chapter we have described the design of maximum gainand low noise figure amplifiers. There are many cases where it is alsodesirable to be able to specify the r.f. power handling capabilities of theamplifier. This is usually achieved using the definition of 1 dB gaincompression point where large signal gain is 1 dB lower than the smallsignal linear gain of the device. For a GaAs FET the 1 dB gain compres-sion point for a small signal device is that measured at a specified drainto source voltage (e.g. VDS = 5V) and a gate to source voltage whichoptimizes the output power (usually such that IDS = 50% IDSS).

Small signal FETs usually have 1 dB gain compression points of+10 to+13 dBm but certain small signal FETs will give much higher outputpowers, e.g. a Plessey GAT4/021 will give r.f. output powers of+20 dBmat 8 GHz.

If two signals at frequencies fi and h are input to a FET device the thirdorder intermodulation products occur at frequencies 2fi-f2 and 2f2-fiwhere the products 2fi+f2 and 2f2+fi are assumed to be out-of-band.

By observing the 3rd order intermodulation products (IP) on a spectrumanalyzer, for example, it is possible to plot the graph of 3rd order productpower output versus input power, if this plot is compared with thefundamental output power plot a point of intersection occurs where the3rd order IP amplitude equals the fundamental signal amplitude. Thispoint is referred to as the 3rd order intercept point (Figure 5.25). The

The Design ofTransistor Amplifiers 231

3rd orderintermodulationproduct

3rd order-/intercept point

Gain = 25dB

Power output — + 20dBm(at 1dB gain compression)

Intercept point — + 30dBm

-65 -55 -45 -35 -25 -5 +5 +15 +25

Input power (dBm)

Figure 5.25 Intercept Point Response for a Typical Amplifier

3rd order intercept point allows the designer to predict the 3rd orderintermodulation product level at any r.f. input power.

An amplifier is designed for optimum output r.f. power handling usingthe same matching techniques already discussed. However, the S-pa-rameters that are used in the design should be those measured with thetransistor operating at V6IDSS. For amplifiers having output powers upto +13 dBm this technique of design is considered valid but for higherpower amplifiers the small signal S-parameters become invalid sincethe transistor impedance levels change when subjected to larger r.f.powers. This is more fully covered later in this chapter.

5.12 Feedback, Active Matching and Travelling Wave Circuits

The amplification of microwave signals in a single ultra-broadbandamplifier is attractive to a variety of systems designers involved inelectronic counter-measures. Wideband, high IFs are also being usedmore and more in receivers. One method of providing such widebandamplifier performance is to use shunt feedback between the gate anddrain of the MESFET. One major advantage of this technique overbroadband input, interstage and output matching is that the circuits areusually less complex and, therefore, easier to realize.


The performance of an amplifier is restricted by the parasitic elementsof the MESFETs employed. The gate-to-source and drain-to sourcecapacitances restrict the bandwidth of the circuit whilst the gate-to-drain capacitance restricts the upper cut-off frequency of the amplifier.By applying controlled amounts of external feedback to the MESFETwith frequency the gain of the device can be made almost constant withfrequency. In addition by correct choice of feedback resistance, feedbackinductance and drain inductance the terminal VSWRs and noise figureof the amplifier can be made acceptably low for a given MESFET (Niclas,1980 and 1982).

It can be shown, for a perfect match on the output of a feedback amplifiermaking the circuit cascadable with following stages, that the forwardtransmission coefficient of the amplifier will be:

5.55RDS

assuming a 50 ohm characteristic impedance system.

The input reflection coefficient of the amplifier is given by:

250<Lm+±

where

7 5-56

FB 50 5.57J —

where

gm is the MESFET transconductance,

RDS is the MESFET output resistance, and

RFB is the feedback resistance

Thus, for example, a feedback amplifier employing a 900 micron gatewidth MESFET with a gm of 80 mS and an Ro of 120 ohms will have an


| Sn | of 0.37 and a gain of 5.3 dB for a feedback resistor value of 378ohms.

Gain Bandwidth of Feedback Amplifiers

In order for the bandwidth of the feedback amplifier to be maximizedfor a given FET an inductance or high impedance transmission line, LD,in the drain line and a feedback inductance or high impedance trans-mission line, LFB, are required (Figure 5.26). LD compensates for thedrain-to-source capacitance of the FET at the upper band edge whilstLFB adjusts the S-parameters of the feedback amplifier so that maxi-mum feedback occurs at the bottom band edge and none at the upperband edge. Further amplifier terminal VSWR improvements can bemade by including simple input and output matching networks in eachstage which are only effective at the higher frequencies.

The best performance from such amplifiers has been found to occurwhere MESFETs whose Sn, and S22 phase angles never exceed -180°at the highest frequency of operation are used (Pengelly, 1981). In orderto ensure that this occurs it is necessary to employ MESFETs havingminimum CGS, CDS and CDG for a given gm. MESFET gate length,channel doping concentration and overall physical size affect thesecomponents. Figure 5.27, for example, shows the maximum availablegain of a 0.5 micron gate length, 900 micron gate width device as afunction of CDG. Figure 5.28 shows the measured MAG of two 900micron gate width FETs as a function of gate length and frequency.

Noise Figure

A feedback amplifier without any other passive matching elementsdepends for its noise figure on the MESFET and the value of thefeedback resistor. In the limit when the feedback resistor is not presentthe noise figure of the amplifier becomes that of the MESFET working

Figure 5.26 Basic Parallel Feedback Amplifier


9

8

CD

c5en

o

IsE

ui

3

2

x

X

\ Useful gain limit

1 1 1 J 10 0.02 0.04 0.06 0.08 0.1

Gate-to-drain capacitance, pF

Figure 5.27 Maximum Available Gain ofMESFET as a Function ofGate-to-Drain Capacitance (Wg = 900 micron, Lg = 0.5 micron)

18

16

U

CDT3 1 2

o2 j o

2 8

6

- \

N!K>I

Lg = 1pm

1

V MAG>v Wg=900um

\ Lg = 0.5p

Figure 5.28 Measured MAG for 900 Micron Gate Width MESFETsas a Function of Gate


into the system characteristic impedance which is usually 50 ohms. Asimple means of calculating the noise figure of a MESFET feedbackamplifier has been published (Honjo, 1983).

The feedback amplifier can be considered as two noise blocks-the noisefigure of the feedback resistor is given by:

\k+8"\Ros

UFB J

where RDS is the drain to source resistance of the MESFET

gm is the transconductance, and

RFB is the feedback resistor

If the MESFET has a noise figure of F2 with a 50 ohm source noise figureof F50, then it can be shown that:

F2-lT; 7 is approximately 1.5.t50~1

The 50 ohm noise figure is directly related to the noise resistance RN, ofthe FET From Fukui's theory (Fukui, 1979) it can be shown that:

where WG is the total gate width, LG is the gate length, a is the effectivechannel thickness and N is the carrier concentration in the channel.

The minimum noise figure of the MESFET is given by:

5.60,5.61


where f is the frequency of operation, RG and Rs are the gate metalliza-tion resistance and source resistance respectively, and CGS is the gate-to-source capacitance.

Thus by careful choice of the MESFET gatewidth and gatelength a lownoise figure with sufficient transconductance to enable drain-to-gatefeedback to be employed can be produced.

The total noise figure of the feedback amplifier i& given by:

FT = Fj + F2-l 5.62

Table 5.8 gives some examples of calculated noise figures of feedbackamplifiers at 3 GHz using four different types of MESFET, the parame-ters of which are given in Table 5.7. Some interesting features emerge.In order to design an amplifier having 12 GHz bandwidth with accept-able gain ripple, input and output VSWRs the 1 micron FET can onlyhave a gate width of 450 microns resulting in a low-noise biasedtransconductance of 40 mS. The gain and VSWR performance of a singlestage amplifier employing such a FET is shown in Figure 5.29. FromTable 5.8 the effect of such a gate width device on feedback amplifiernoise figure can be seen clearly. Figure 5.30 shows a comparison of thegains and noise figures of two feedback amplifiers employing MESFETsof different total gate widths and lengths.

Table 5.7 Normalized Equivalent Circuit Parameters for FourDifferent MESFETs

Parameter

Gate width, W

Gate Length, L

gm/W

CGS/W

CGD/W

CDS/W

FET1

900

0.7

80

1

0.05

0.4

FET2

900

1.0

89

1.17

0.13

0.2

FET3

900

0.5

80

0.58

0.1

0.2

FET4

900

1.2

60

0.95

0.08

0.28

Units

micron

micron

mS/mm

pF/mm

pF/mm

pF/mm


Table 5.8 Calculated Noise Figures at 3 GHz for FeedbackAmplifiers as a Function ofMESFET Type

MESFETType

1

2

2

3

3

FeedbackResistor

ohms

250

110 O

328

197 0300

NoiseResistanceRN, ohms

8

40.6

40.6

6.4

6.4

NoiseFigure dB

3.9/

8.8

5.8

4.5

3.9

Gate Widthmicron

900

450

450

900

900

GateLengthmicron

0.7

1.0

1.0

0.5

0.5

(V Feedback resistor chosen such that \S11\, \S12\ are minimized.

CD Gain

Input VSWR

Output VSWR

2 3 4 5 6 7 8 9 10 11Frequency, GHz

331 0.39n

-klOp0.26n

0 . 1 2 p = = 0 . 1 1 p

Figure 5.29 Performance and Circuit Diagram for 1-11 GHzFeedback Amplifier (Wg = 450 micron, Lg = 1 micron)


450/N.K-900/0.5 gain

5 6 7 8Frequency, GHz

10

Figure 5.30 Gain and Maximum Noise Figure of FeedbackAmplifiers

5.12.1 Travelling-wave Amplifiers

In traveling wave or distributed amplifiers the input and output capaci-tances of the active devices such as transistors (or earlier, thermionicvalves) are combined with inductors to form two lumped element artifi-cial transmission lines. These lines are coupled by the transconductanceof the active devices.

The principle of the traveling wave amplifier was first proposed byPercival (1936) in a British patent. However, first experimental resultsdid not occur for some years until Rudenberg and Kennedy (1949)described a 300 MHz traveling wave amplifier.

With the advent of MESFETs both monolithic (Ayasli, 1982) and hybridtraveling wave amplifiers (Niclas, 1983) have been reported exhibitingadequate gains and terminal VSWRs at bandwidths up to 30 GHz.Further their power-handling capabilities are now also being recognized(Ayasli, 1984).

This section describes three of the main characteristics of distributedamplifiers-their gain, noise figure and output power characteristics.


5.12.1.1 Gain

We will start with some elementary theory on the forward gain of atraveling wave amplifier utilizing the simple amplifier model of Figure5.31 and the simple MESFET equivalent circuit shown in Figure 5.32.The MESFET is firstly considered as being loss free consisting only ofa gate-to-source capacitance CGS and a drain current generator with itsassociated drain-to-source capacitance CDS. Later the gate and drainresistances will be added and their effect on the overall amplifier gainevaluated.

The artificial transmission lines which form the gate and drain lines canbe considered loss free in the first instance. Let the gate and drain linecharacteristic impedances be ZG and ZD with the idle gate and the idledrain ports terminated in RG = RD = Zo. The left-hand gate line port isterminated in a generator, Es, having impedance ZG. Note that thesecharacteristic impedances are frequency dependent since we are consid-ering an artificial transmission line.

A wave from the gate generator propagates down the gate line (with aphase constant /Jg per section) and is dissipated in the right-hand gateload. The voltage across each gate-to-source capacitor produces a cur-rent, gmVG, in the drain line and the current from each MESFET drainpropagates down the drain line in both directions (with a phase constant/Jd per section). Power will be dissipated in both the drain idle port loadand the amplifier output load. The forward gain (to the right-hand drainload) and the reverse gain (to the left-hand drain load) can be calculated.

1st stage 2nd stage mth stage nth stage

Figure 5.31Travelling Wave Amplifier with n Sections


Gate

CgsS' $ •

= C ds

-o Drain

-o Source

Figure 5.32 Simplified MESFET Equivalent Circuit

The total current ID (Figure 5.31) in the load Zd is given by

5.63

The voltage wave traveling down the gate line due to Es producesvoltages Vi, V2... Vn across each gate-to-source capacitor. If the voltageacross the input terminals of the amplifier is Vin, then

V- = V e~^e V -V e~2j^e V = V

Now

h = 8mVi> h = gmV2>~~ln = 8mVn so that

and

Therefore,

This reduces to

1-e


But Vin is equal to V6Es since the amplifier is matched to the generatorso that

The power dissipated in the load Zd is therefore given by2

16

Since the power available from the generator is Es2/4Zg the availableforward gain is given by

5.64

If it is arranged that the propagation constants /?d and fig are equal, thenequation 5.64 simplifies to

c_n2gm2ZgZd

Thus for the case where Zg = Zd = Zo

„ _ 8m2ZdZgu —

4

^(P'-P.)

2

G = -4

5.65

This equation is the result of simplifying the models for both the FETsand elements connecting the FETs. In practice the gain of the amplifierdoes not increase monotonically with n because of gate and drain linelosses. If these are Ag and Ad respectively a more accurate gain expres-sion for the traveling-wave amplifier with n sections can be found(Ayasli, 1982) as:


gm2z2 [exp(-Agn)-exp(-Adn)]G = — 1 : 72 5.66

4 ()

Given that the maximum frequency of operation of the amplifier isdetermined there exists an optimum number of sections, n, for theamplifier and, therefore, for the total gate periphery that can be em-ployed in a single-stage. The maximum gate periphery and, therefore,the maximum gain that can be expected are determined by the parame-ters of the discrete FET used in each section.

When the gate-and drain-line loading effects are included, the analyticaldescription of the traveling-wave amplifier is incomplete without theinclusion of:-

1. Capacitive drain-gate coupling;

2. Series feedback through the source resistance and inductance;

3. Mismatch at the end of the drain and gate lines; and

4. The effect of bias circuitry.

Analyses which take into account some of these effects have beenpublished (Niclas, 1983 and Beyer 1984).

Considering just the gate and drain line attenuations Ag and Ad it canbe shown that the number of devices which maximizes gain at a givenfrequency is given by:

5.6?

The expressions for gate-and drain-line attenuations can be derivedfrom the propagation function for a constant k-line (Beyer, 1984) and aregiven by

1-5.68

CO

0),


5.69

where co is the radian frequency, and cog = 1/RICGS, o)d = 1/RDSCDS and

2 2

where Ri is the intrinsic gate-source resistance in the FET and Lg andLa are the gate and drain inductances forming the artificial transmissionlines with the CGS and CDS capacitances.

The attenuation on gate and drain lines versus frequency with coJcDg andcod/coc as parameters are shown in Figure 5.33(a) and (b) respectively.For example, for 300//m gate width, l/*m gate length FETs operating ina 12 GHz bandwidth traveling-wave amplifier the following parameterscan be assumed.

CGS = 0.5 pF

CDS = 0.12 pF

L g = l n H

Ld = 1.25 nH

Ri = 8 ohm

RDS = 350 ohm

Thus cog = 2.5 X 1011 rads per sec, cod, = 2.4 x 1010 rads. per sec. and coc

= 8.9 x 1010 rads. per sec (14.2 GHz ).

Thus, for example, at mid-band (6 GHz)

=0.161

03-0.16


1

a

Ini_<ba<bc

b

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

Atte

0.5

0.4

0.3

0.2

0.1

-

-

-

I

Wc /Wg -0.5 /

- H — l ^ i . — i — - r — T i i

/

\

\

/

1

)

1 1

) 0.2 0.4 0.6 0.8 1.0

w/wcnuation on gate line versus normalised frequency

-

-

wd/wc«o

I 1 1 1 1 I I I

/

/

•VWC-O.O5

0 0.2 0.4 0.6 0.8 1.0

wc/wgAttenuation on drain line versus normalised frequency

Figure 5.33 Gate and Drain Line Attenuations

.*. The optimum number of stages is 4 or 5 in practice.

Let us now consider further the design of a traveling-wave amplifierfrom practical considerations. Considering again the 300/jm FET dis-cussed above we can calculate the maximum frequency of oscillation,fmax of each FET from the formula given by

5.70


For a ljum gate length FET gm = 25 mS at MJDSS SO fmax is 26.3 GHz. Wehave already calculated cog9 as 2.5 x 1011 rads (which is equivalent to fg= 39.8 GHz) and m 6 as 2.4 x 1010 rads (which is equivalent to f d = 3.82GHz). If we assume that the characteristic impedances of the gate anddrain lines are equal then because the cut-off frequencies of these linesare constrained to be equal, CGS = CDS + Cp where Cp, is an externalcapacitance added to the device output capacitance CDS.

We can therefore define a new characteristic frequency

U = ?3rR ,* + r , = 0.91 GHz 5.71

Assuming that n = 4 from equation 5.65 the d.c. gain is 7.95 dB.

The frequency response of a traveling wave amplifier (Figure 5.34 (a))using such FETS, predicted by using a CAD program where the fullS-parameters of the FETs is used, is shown in Figure 5.34(b). It can beseen from this example that the simple formula produces a predictedgain which is close to that achieved in practice and the calculatedamplifier bandwidth is also close to that predicted by the full CAD.

In order to be able to predict the element values of a travelling waveamplifier knowing the S-parameters of the FETs to be used is useful asa starting point in the optimization of the amplifier using CAD.

Up to now we have assumed the amplifier uses lumped inductors in thegate and drain lines such that together with the input and outputcapacitances of the FETs artificial transmission lines are formed. Whenreplacing the lumped elements by sections of transmission lines ofrelatively high characteristic impedance (say 100 ohms) the amplifier'sgain and VSWR performance experience only slight changes.

Consider the example shown in Figure 5.35 of a three section distributedamplifier required to cover 2 to 18 GHz. In order to obtain flat gain andlow input and output VSWRs it is possible in practice, to vary theparameters of the transmission lines between the transistors. Considerthe characteristic impedance of these transmission lines to be fixed at125 ohms.

In order to efficiently supply the amplifier module with its drain voltage,a drain inductor LD is connected into the drain line terminating port. Asimple input matching network can also be added to improve theamplifier's input reflection coefficient. Since the inductor LD and theinput matching network influence the amplifier's performance they are


0.28 0.98 0.98 0.98 42 1.1 K 20

Lg ^N=1.5x1017cm"3

a 2-12GHz travelling wave amplifierall inductors in nH, capacitors in pF

Output

1.0

0.8 g

0.6 8

2 3 4 5 6 7 8 9 10 11 12 13Frequency (GHz)

b Predicted response for 2-12GHz travelling wave amplifier

Figure 5.34 (a). 2-12 GHz Travelling Wave Amplifier (b). PredictedResponse for 2-12 GHz Travelling Wave Amplifier


Figure 5.35 Schematic of Three Section Amplifier EmployingTransmission Lines of Equal Impedance

also included into any CAD optimization routine. A full equivalentcircuit for the MESFET is also used including feedback capacitance asshown in Figure 5.36.

Niclas (1983) has shown that if the S-parameters of the FETs are knownthen the input and output reflection coefficients and the gain at lowfrequencies are respectively approximated by:

R g = lohmLg=0.085nHCgs=0.25pFRi = 5.2ohmRs=0.Aohm

gg m = 25mSCds=0.07pFRds=272ohmsLd = 0.35nH

Figure 5.36 FET Equivalent Circuit used in Figure 5.35


5.72GO

l-(GD+nGDS)Z0

and

i^ i ~2ngmZn

5 s ^ - ^ 5 74(i + KJQLQ )\l + VJJ^LQ + YILT^LQ )

where GG = I/RG, GD = 1/RD and GDS = 1/RDS, RG and RD being the gateand drain line terminations respectively.

Ideal matching at low frequencies ( | Sn | = | S22 | =0) results in RG =50 ohms and RD = 112 ohms from equations 5.72 and 5.73 respectively.For the 0.5 micron gate length FETs being considered gm is equal to 25mS and, therefore, from equation 5.74, | S211 2 = 5.5 dB. Increasing thedrain line load to 300 ohms results in a gain increase to 6.8 dB with anacceptable increase in input reflection coefficient to 0.16. The gate-linecut-off frequency is given by

By making the electrical length, 0, of the gate and drain lines equal (i.e.by supplying extra capacitance Cp in the drain line) and defining

75 - 7 5

where ZG,D are the impedances of the gate or drain lines respectively,we ensure that the amplifier will have a cut-off frequency, fc whenemploying transmission line sections.

Choosing ZGD = 125 ohms and fc = 20 GHz results in electrical lengthsof 27° in order to obtain an accurate value for the additional shuntcapacitance required in the drain line the influence of CGS, CDG, CDC andCDS have to be taken into account. Thus


-(CDS+CDC) =

This additional capacitance Cp can be formed with an open circuited stubof 50 ohm characteristics impedance where

6 =P «>cZpCp= 45°

Using the circuit schematic of Figure 5.35, the element values calculatedabove can be used as the starting point for a CAD optimization. Table5.9 compares the starting values of the elements before and afteroptimization.

Table 5.9 Element Values of Travelling Wave Amplifier Before andAfter Optimization

Element

LGI

LG3

LDI

LD2

LSI

LS2

RG

RD

LD

ZG, D = 125 ohm

Zs = 50 ohm

Units

Deg. at 20 GHz

Deg. at 20 GHz

Deg. at 20 GHz

Deg. at 20 GHz

Deg. at 20 GHz

Deg. at 20 GHz

ohm

ohm

nH

Before Optimization

27

13.5

27.0

13.5

45.0

45.0

50

300

10

After Optimization

22.5

14.9

34.5

34.9

25.5

0

36

300

9

All symbols refer to Figure 5.35.


5.12.1.2 Noise Figure

Since the traveling-wave FET amplifier has been demonstrated to haveultra-wide bandwidth capability with practical bandwidths in excess of30 GHz having been reported it is of particular significance to ascertainwhether such amplifiers are capable of noise figures which are signifi-cantly different from conventionally tuned circuits. Reported noiseanalyses on traveling-wave FET amplifiers are limited (Niclas, 1983).However a relatively simple analysis due to Aitchison (1985) is pre-sented here which is particularly applicable at low frequencies, anddisplays some of the main noise characteristics of traveling wave ampli-fiers. In order to calculate the noise figure the noise powers in the circuithave to be added. The intrinsic noise sources are:-

(1) noise from the gate source impedance, Zg(at temperature To)

(2) noise from the gate line load Zg(= Zo) (at temperature To)

(3) noise from the drain line load Zd (= Zo) (at temperature To)

(4) noise from each of the n FETs in the circuit.

The noise power available from the source impedance Zg (= Zo) is kT0B,where B is the noise bandwidth and k is Boltzmann's constant. Thenoise power dissipated in the load connected to the output of theamplifier is given by:

5.76

at low frequencies.

The noise power available from the left-hand gate line load is kT0B sothat the contribution dissipated in the load connected to the output ofthe amplifier is given by:

2rj 2

m sin (5 5.77

where the term in square parentheses is the reverse gain of the amplifier(Aitchison, 1985).

The noise power from the left-hand drain line load is KT0B assumingthat the drain line is loss free. FET noise behavior can be representedby a gate current generator Vi g

2 in parallel with the gate capacitance


and a drain current generator Vi g 2 in shunt with the gate drain

capacitance (Figure 5.37). A complex correlation coefficient, C, 'links' thetwo generators.

The mean square values of ig and id are given by

. C*

om

id2=4kToBgmP

5.78

5.79

where R and P sire fitting factors dependent on drain current and otherFET parameters (Brewitt-Taylor, 1980). The complex coefficient

It has been shown that Cr is close to zero and dm = 0.35. Noise fromthe mth FET of a series of n devices is transferred to the load connectedto the output by forward amplification in the (n-m)th stages and alsoby reverse amplification from preceding stages. The vector sum of thesetwo contributions is added to the drain contribution from the mth stagetaking into account the correlation coefficient, C, between the twogenerators. There are n FETs in the amplifier resulting in the summa-tion of uncorrelated noise powers from each device. The total noisepower dissipated in the output load due to the mth FET is given by:-

Figure 5.37 Simplified Equivalent Circuit ofMESFET ShowingGate and Drain Noise Generation


r=2

2(n-m+l)sin(m — l)fi cosmfi

sin 5.80

Summing the noise contributions from n FETs in the amplifier resultsin the expression

((wr*)1! (n-m+7)22 , (sin(m-l)P

sin i

2{n-m+1)sin(m—1)fi cosmP^ 8 5.81

Substituting equations 5.78 and 5.79 into 5.81 gives

Jn 2 J2, ^ - fsin(m-l)P\n m-ri) -rj

=1

4kToB )

2{n-m+l)sin(m — l)fi cosmfisin/}

5.82

The noise figure of a traveling wave amplifier containing n sections istherefore given by

/ . * \2 , _ ? — ? _ «

[nsinfi ) n2gm2Zo

2 n2g4P

5.83

where

/ x / x2 fsin(m—l)B^\ \f(m) = (n-m + iy+\ \ w \ +-

^ sinfi )

cosmfi

sinfi 5.84


Examining equation 5.83 shows that under normal design circum-stances the second term is negligible when n > 4. The third term is alsonegligible particularly when n and/or gm are large. Considering

fm (equation 5.83)

shows that the first term is the most significant summing ton/6 (n+l)(2n+l). Thus the gate generator contribution to equation 5.83is proportional to n.

Thus, for practical traveling wave amplifiers

There is an optimum value of the product nZ0 which minimizes equation5.85 to give a minimum noise figure, Fmin. The optimum product

corresponding to

F =2 +*• mm •*• ~

F• mm

For example, for the amplifier using \jurn gate length FETs discussedpreviously, (nZo)opr = 159, i.e. n = 3 and Fmin = 3.4 dB. This does notexactly correspond with the optimum number of stages for gain whengate and drain line losses are included. A more accurate expressionincluding gate and drain line losses is:

for small Ag and Ad.

.'. Fmin = 1 + 1.115 + 1.2 = 5.2 dB where Ag = 0.16 and Ad = 0.3.

Figure 5.38 shows noise figure variations with frequency predicted forlossless gate and drain lines for a 1 micron gate length FET. It will be


1.5

1 2 3 4 5 6 7 8 9 10 11 12 13Frequency (GHz)

Figure 5.38 Distributed Amplifier Noise Figure as a Function ofFrequency and Number ofFETs (ljum MESFETs)

noticed that in this case, at frequencies below the upper cut-off frequencyof the amplifier, the overall noise figure decreases with increasing n. Asbefore gate and drain line losses offset this effect such that there will bean optimum number of stages for minimum noise measure.

5.12.1.3 Power Output

So far we have only considered the small-signal behavior of traveling-wave amplifiers. For power amplification there are additional designparameters to be taken into account. Four separate power limitingfactors can be identified. These are:

(1) The RF voltage swing that can be allowed on the input gate line;


(2) The maximum total gate periphery that can be employed in asingle stage design within known bandwidth constraints;

(3) The gate to drain breakdown voltage of the FETs; and

(4) The output power that is transferred to the load because the ACload line is defined by the size of the FETs used for the requiredbandwidth.

We will now consider these four design parameters briefly.

(1) The RF swing on the gate line is limited on the positive cycle by theforward conduction of the gate Schottky diode whilst on the negativecycle the limit is set by the pinch-off voltage.

Thus, for a 50 ohm input impedance amplifier with a pinch-off voltageof - 4 volts where the FETs are biased at V&IDSS, the maximum powerthat the amplifier can handle is given by:

(4 + 0.5)2

PIN,MAX = Q SO = 0.051 watto

Thus the maximum output power from the amplifier cannot be largerthan the amplifier gain X PIN, MAX.

(2) As has already been shown the optimum gain per amplifier stage isrelated to the gate and drain line attenuation constants. Consideringgate line attenuation only Agn should be much less than 1 to ensure thatthe FETs are used efficiently in a single-stage design.

Ayasli (1984) has shown that

Rfi)2CGS2Zon<2 5.86

where Ri is the gate to source resistance and CGS is the gate to sourcecapacitance.

In equation 5.86 Ri varies inversely and CGS varies directly with MES-FET gate width. Hence, in terms of FET gate width, W, equation 5.86can be rewritten as:

nWa)2 < constant 5.87

Figure 5.39 shows the variation of maximum gate periphery of a trav-eling wave amplifier as a function of the highest frequency of operationfor 0.5,0.8 and 1.0 micron gate-length FETs. Thus, for example, for theamplifier discussed previously the maximum frequency of operation is


3000

2800

2 600

2400

22OO

2 000

1800

1600

U00

1200

1000

800

600

400

200

ZG«50ohm50ohm

Lg-0 .5

J—I—I—I—I I I I I I

0 2 4 6 8 10 12 14 16 18 20 22fH(GHz)

Figure 5.39 Maximum Total Gate Periphery per Gain Stage as aFunction of the Highest Frequency of Operation with Gate Length as aParameter

12 GHz for a four stage design with each FET having a 300 microngate-width.

(3) As with any class A power amplifier the maximum output voltageswing is limited by gate to drain breakdown. The drain terminals mustbe able to sustain the amplified RF voltage swing on the output trans-mission line. This voltage is given by:

Thus, for the case of a FET having a 24 volt breakdown, — 4 volt pinch-offand 1 volt knee, the maximum output power is 900 mW.

(4) Figure 5.40 shows the required optimum load-line for Class Aoperation of a MESFET. In a traveling wave amplifier each FET ispresented with a load-line that is predetermined by the drain-line


Id,

/ I °-5

Im V k n e e

7 i\Load line

1 \ / .^________—|vd |vb vdd

v« i~—-—J

Figure 5.40 Optimum AC Load Line for Class A Operation ofMESFET

characteristic impedance. The total gate periphery is also determinedby gate loading considerations. In the example above the total gatewidth is 1200 microns with each FET having a gate-width of 300microns. A typical load-line for such a device is 140 ohms representinga significant mismatch to a 50 ohm load impedance.

For the four section amplifier discussed above the maximum outputpower is 0.051 X 6.3 = 0.322 Watt. Accounting for the mismatch loss dueto the non optimum load line results in an output power of 250 milli-watts.

Of considerable interest is the relationship between individual FET gatewidth, bandwidth and power output for a distributed amplifier. Forexample, if each FET's gate width is increased to 600 microns, fromFigure 5.39, the maximum frequency of operation of the amplifierdecreases to 8 GHz. However, the gain increases to 14 dB and, therefore,the maximum output power increases to 1240 milliwatts. Reducing FETgate length allows the maximum frequency of operation of the amplifierto be increased for a given total amplifier gate periphery. Thus, forexample, decreasing the gate length to 0.5 microns allows maximumfrequency of operation to be increased to 14 GHz with a total gateperiphery of 2400 microns. With decreased gate length the transconduc-tance per FET also increases providing more gain per stage (neglecting


gate and drain line losses). In this case, therefore, drain-line breakdowneffects will limit output power.

5.12.2 Common-Gate and Source Follower Configurations

A GaAs FET is most commonly used in common-source operation sincethe device is designed to give its maximum gain and minimum noisefigure under this circuit condition.

However considerable advantage can be attained in terms of input andoutput reflection coefficients by using common-gate and common drain(source-follower) configurations respectively. Table 5.10 shows the S-pa-rameters for the common gate and source-follower connected GAT6 andmay be compared directly with Table 5.1. It may be seen that up to 6GHz the input and output reflection coefficients of the respective con-figurations are low indicating that these configurations would be suit-able as the input and output stages of an amplifier.

It should also be noted that | Sn | for the source follower configurationis very close to 1, whilst | S121 is large compared with a common sourceconnection. It may also be shown that in the common gate configurationthe optimum source admittance for low noise figure is close to 50Qparticularly at the low frequency end for a FET with a transconductanceof20mS.

In order to provide flat gain over a wide bandwidth the circuit of Figure5.41a is of a typical type where a common gate FET is connected to acommon source device. Figure 5.41b shows the performance of thecircuit of Figure 5.41a where the devices used were of the GAT6 type(i.e. 30Qam gate width and 0.5jum gate length). In order to flatten outthe gain it is necessary to include some simple matching between stagessuch as series inductance. Such circuits using impedance matching overbroad bandwidths by active devices are particularly suitable where verysmall components are needed such as in the case of integrated circuits(Suffolk et al, 1980).

Considerable advances are being made in the use of common gate andcommon drain (source follower) connected FETs in broadband amplifi-ers for frequencies up to 4 GHz or so where monolithic circuit techniquesare used. Decker et al (1980) have described promising initial results ofa common source, common gate, common drain cascade used as an IFamplifier covering the 500 to 1000 MHz band. The input impedance ofthe IF amplifier, shown in Figure 5.42a is high allowing it to be useddirectly after a FET mixer. The measured gain of the circuit is shown


Table 5.10 Common Gate and Common Drain Connected GAT6S-Parameters

Freq.CaHZ

2

3

4

5

6

7

8

9

10

11

12

MAG

.27

.26

.26

.27

.28

.29

.3

.36

.36

.36

.38

S11

ANG

-175

-176

-175

-173

-173

-171

-172

-173

-175

-178

178

MAG

1.26

1.25

1.25

1.25

1.25

1.27

1.29

1.32

1.35

1.41

1.49

S21

ANG

-9.9

-13.9

-18.2

-22.8

-27.9

-33.8

-40.2

-47.1

-54.4

-63.3

-73.8

S12

MAG

.116

.124

.139

.159

.178

.196

.218

.232

.244

.263

.251

ANG

23.6

27.8

32.1

35.6

36.3

36.5

36.8

36.4

36.1

36.3

37.5

MAG

.91

.92

.94

.96

.98

1.02

1.07

1.13

1.2

1.29

1.38

S22

ANG2

- 7

- 8

- 1 0

- 1 3

-16

- 2 0

-24

-28

- 3 3

- 3 9

- 4 2

Freq

GHz

2

3

4

5

6

7

8

9

10

11

12

S11

MAG

.98

.98

.97

.95

.94

.93

.92

.91

.9

.91

.88

ANG

-15

-20

-25

-31

-37

- 4 3

-49

-56

- 6 2

-68

-75

MAG

1.22

1.2

1.18

1.17

1.16

1.14

1.14

1.13

1.13

1.12

1.09

S21

ANG

-7.8

-10.9

-13.9

-17.1

-20.4

-23.9

-28.0

-31.8

-35.4

-40.5

-44.4

MAG

.202

.267

.343

.419

.492

.567

.635

.7

.757

.811

.882

S12

ANG

73.0

69.6

64.2

58.0

52.4

46.5

40.8

35.3

29.7

25.0

20.8

S22

MAG

.32

.3

.28

.26

.25

.23

.21

.2

.18

.17

.19

ANG

167

158

152

145

138

129

120

110

100

83

63


R.F. I/P

V3

4oon

200Q110°@10GHz

200Q110° @ 10GHz

R.F. O/P

20p

FETs have 3CXVim wide \

a.

Return loss dB

-10

5 6 iFrequency, GHz

10-11

Frequency, GHz

Figure 5.41 (a). Common Gate I Common Source I Source-FollowerAmplifier (b). Performance of Circuit in (a)

in Figure 5.42b and is compared with the predicted gain which takesinto account the additional parasitics and losses of the resistors andcapacitors in the circuit.

The performance of this circuit can be markedly improved by the use ofsimple inductive tuning between stages and more recently Suffolk et al(1980) have designed wideband bandpass amplifiers to cover the 2 to 4GHz frequency range which have 19 dB gain, 3 dB noise figures and verylow sensitivity to component value changes of the order of ± 20% fromtheir mean value. Figure 5.43a shows the chip realization 'if this circuitshowing the use of'spiral' inductors, thin film bias resistors, GaAs FETS,


Calculated

Measured

400 ®S$ 800 TfiS) 1200f(MHz)

(b)

Figure 5.42 (a). IF Amplifier Using Cascode Connected FETs andSource-follower Output (b). Gain of IF Amplifier

overlay capacitors etc. whilst Figure 5.43b shows the basic amplifiercircuit.

As the parasitic resistances and reactances of GaAs FETs are reducedby using monolithic fabrication techniques the use of common gate andsource follower configurations will become more common-place at higherfrequencies. This is also true of very wideband feedback amplifierscovered in another part of this chapter.

5.13 Power Amplifiers

High power, high efficiency amplification of microwave power usingGaAs FETs has been demonstrated over the past few years at frequen-cies in C, X and Ku band (Macksey et al, 1976; Tserng, 1979). Power FETdevices are commercially available which enable linear Class A powersof several watts to be achieved up to X band. A power FET is essentiallya multicell structure where the GaAs material and the fabricationtechniques used are optimized for higher breakdown voltage than asmall signal FET.

GaAs power FETs are very attractive solid state amplifiers. In compari-son with silicon bipolar devices, Schottky barrier power GaAs FETs havehigher maximum frequency of oscillation, low noise figures and largegains. Above 4 GHz they have higher efficiencies, do not exhibit secon-


12.5n

12V

1n 1OpHh-O/P110pHh-O/P2

O.5p 430

//////

Figure 5.43 (a). Low Noise Common Gate, Common Source, SourceFollower S-Band Active Splitter (b). Circuit Design for ActivelyMatched L.N. Preamp I Splitter


dary breakdown, are self-ballasting and have inherently higher inputimpedance. A typical power GaAs FET is shown in Figure 5. 44a.

5.13.1 D.C. Characteristics

The device shown in Figure 5.44a has a total gate width of 2400//m(compared to typically 30Qam for a small signal device) comprising 4unit cells each 600jum wide. Devices with well matched cell charac-teristics are required since such devices yield good power-added efficien-cies (over 30%) and good thermal characteristics.

The maximum output power obtainable from a GaAs FET in class Aoperation with full gate modulation is determined from the charac-teristic of Figure 5.44b. The maximum output voltage and currentswings give output power for a sinusoidal input of

iF(vB-vs)

where IF is the value of IDS corresponding to a forward gate bias of 0.7V(for an aluminum to GaAs Schottky barrier), VB is the source-drainvoltage at which breakdown occurs in the pinch-off region and Vs is thesaturation or Toiee' voltage of Figure 5.44b usually between 1.5 and 2volts. The optimum load resistance is

lF

From Equations 5.88 and 5.89, the requirements for high output powermay be seen. Large values of IF are obtained by placing in parallel anumber of FET 'cells' to give a large total gate width. The number ofgates put in parallel is limited by the minimum load resistance whichcan be presented to the device by equation 5.89.

The breakdown voltage VB is determined principally by the avalanchebreakdown of the gate to drain diode. These are related by the equation

V*=VA-V#, 5.90

where Vp is the pinch-off voltage.


5.13.2 R.F. Characteristics of Power GaAs FETs

The small signal scattering parameters of power FETs are usuallysupplied on manufacturers' data sheets. This enables the design engi-neer to obtain a device bandwidth capability and also indicates' theregions of instability of the device. The low frequency S parameters ofa power FET usually indicate, below 2 GHz, that the regions of instabil-ity are large particularly for the output of such a device so that it isnecessary to use bias networks, for example, that present an impedanceto the device close to 50 ohms. Table 5.11 shows the small signal

Figure 5.44 (a). 2 Watt Power GaAs FET (b). I-V Characteristics of


Table 5.11 Typical S-Parameters for a Plessy PGAT1000 Power FET(P105 Package)

Freq.

GHz

2

3

4

5

6

7

8

9

10

11

12

MAG

0.9

0.82

0.86

0.82

0.79

0.72

0.70

0.70

0.71

0.70

0.70

S11

ANG

-149

-171

168

145

126

107

88

68

50

25

12

MAG

3.15

2.57

2.11

1.71

1.38

1.17

1.07

0.88

0.784

0.65

0.60

S21

ANG

56.8

33.5

9.0

-13.1

-39.0

-64.0

-90.0

-114

-138

-158

-174

MAG

.035

.035

.036

.038

.039

.042

.052

.054

.060

.065

.074

S12

ANG

11.0

-4.0

-20.7

-30.1

-42.8

-53.0

-61.1

-75.0

-87.1

-102

-117

MAG

0.33

0.38

0.44

0.50

0.55

0.58

0.60

0.65

0.70

0.72

0.75

S22

ANG

-86.0

-104

-121

-142

-171

166

140

125

117

105

95

S-parameters for a 1 watt power FET from 2 to 12 GHz in 1000 MHzsteps. The Table shows the maximum available gain of the device aswell as the Rollett stability factor, K. It is apparent that the gain of apower FET is substantially lower than that of a small signal device, aresult of the device being optimized for its power handling performance.

5.13.2.1 Large Signal Parameters

The small signal S-parameters of a power FET, although useful designaids, are not so useful for accurate prediction of the large signal gain andpower output of a device either at a spot frequency or over a bandwidth.The measurement of high power S-parameters is difficult. The meas-urement of the source and load impedances for the device operating atits 1 dB gain compression point are more easily measured and togetherwith the small signal S-parameters give sufficiently accurate informa-tion for design. These impedances are measured by matching the deviceusing for example, stub tuners at the r.f. power levels of interest andthen separately measuring the tuner impedance using a conventionalsmall signal network analyzer. The required impedance is the conjugate


of the measured stub impedance. Figure 5.45a shows the result of doingthis for the large signal impedance at the output of a Plessey PGAT1000FET. The output power of power GaAs FETs largely depends on theoutput being matched at the large r.f. signal levels. Figure 5.45b showsthe effect of increasing the r.f. power level into a 250 mW power GaAsFET from 10 dBm to 26 dBm. The latter input power is larger thanwould be used in practice but the trends shown in Figure 5.45b may beused to modify the remaining small signal S-parameters. For example,<S2i is virtually unchanged. However both the magnitude and angle ofS22 change significantly.

For operation over medium bandwidths (i.e. 20% or so) it is desirable tocalculate the variation in output power with frequency. This can beachieved by plotting the large signal gain circles or constant outputpower circles at discrete frequencies over the band of interest andsuperimposing on these the matching circuit impedance chosen for theamplifier.

The large signal output impedance is usually used in the design of theoutput matching network together with an | S211 which reflects thedecrease in gain under large signal conditions. The small signal Sn andS12 can be used during design of the matching networks with final circuitadjustment being performed after the amplifier has been constructed.

Input level 10dBm

> Input level 26dBm

—90

(a) Large signal O/P reflection coefficientsfor PGAT1000

~ 9 0 ° (b) Changes in S • parameters with input r.f.level

Figure 5.45 Large Signal S-Parameters of GaAs FET Devices


5.13.3 Circuit Topologies For Matching Power FETs

To determine the suitable circuit topologies for microwave GaAs FETamplifiers in microstrip form, for example, consideration must be givento the bandwidth, output power and frequency of operation.

If high output power is required, a large gate width device will have tobe used. This will result in low input and output impedance and thecircuit designer will have to choose a circuit topology that can match tothese low impedances within the physically realizable limit of thetransmission line. One useful approach is the lumped element imped-ance matching techniques already discussed with reference to smallsignal amplifiers.

The impedance matching circuits that can be used for power GaAs FETamplifier design include the following:

5.13.3.1 Quarterwave Impedance Transformers

For moderate bandwidth applications (10 to 20%) a single section ofquarterwave impedance transformers may be used. A packaged deviceis most often used for power amplifiers (since to bond up a power FETis an intricate operation) and if the device impedance appears inductive,either a capacitive shunt stub or a series capacitor may be used forresonance prior to the necessary impedance transformation to thesource or load.

5.13.3.2 Matching Networks Based on Low Pass Filter Prototypes

For the broadband amplifier design, the lumped element equivalentcircuit model of the FETs may be used to compute the input/output Q'sof the device. These Q values are then used to determine the complexityof the network (the *n' value) and the prototype 'g* values (Matthaei etal, 1964).

Using the coupled-resonator matching technique Leichti (1974) hasdesigned a broadband amplifier. The broadband amplifiers with edge-coupled transmission line sections as described by Tserng (1979) can beconsidered a modified version of this broadbanding technique, since thesingle-section edge-coupled line can be represented as a series imped-ance transformer with two open-circuited shunt stubs connected to eachend of the transformer.


5.13.3.3 Lumped-Element Impedance Matching Networks

Lumped-element impedance matching techniques can also be used forpower FET amplifier design. For narrow to moderate bandwidths, asimple design procedure using a Smith Chart will be adequate. GaAspower FET amplifiers using lumped LC elements have been realized(Tserng et al, 1978). For wideband applications the initial elementvalues of the lumped element, low pass Tchebyschev impedance match-ing network can be obtained from the work of Matthaei (1964). Alow-pass to bandpass transformation can be made to obtain the correctelement values for the desired frequency of operation.

5.14 Narrow Band Power FET Amplifier Design

This example describes the design of a 9 to 10 GHz power amplifier. Theamplifier is to provide 20 dB gain at 32 dBm output power with threecascaded FET amplifier stages.

The optimum large-signal circuit impedances for three FET powerdevices with various gate widths are shown in Figure 5.46a, The FETshave gate widths of 30Qam, 1200jam and 2400jum to be used in the first,second and third stages respectively. The plot shows the effect of morecells lowering the impedance of the FET. The simple distributed match-ing networks shown in Figure 5.46b, are designed to give output powersof 120 mW, 500 mW and 1.5 watts with 9 dB, 7 dB and 5 dB of gainrespectively. The 1 dB bandwidth was 1 GHz with power-added efficien-cies of 23 to 30%. Based on the circuit topologies shown in Figure 5.46an integrated, 3 stage amplifier with 50 ohm interstage transmissionlines was designed. The performance of the overall amplifier is 20 dBgain with +12 dBm and an output power of 1.6W is obtained at 9.5 GHzwith a power added efficiency of 30%.

5.15 Broadband Power FET Amplifier Design

The use of distributed matching networks for broadband power ampli-fiers follows the same synthesis routines as for small signal amplifiers.Figure 5.47 shows for example the use of a particular circuit topologyfor broadband matching of a 60Qam gate width device over the frequencyband 6-12 GHz giving 100 mW output power. Performance is shown inFigure 5.47.

One of the most useful methods of broadband matching power FETs isto use 'internal' matching within a microwave package using wire bondsand chip capacitors. Such a circuit is shown in Figure 5.48 with a set of


performance curves in Figure 5.48. It is seen that output powers of theorder of 2 to 3 watts with 5 to 6 dB gain can be achieved with 1 dBbandwidths of approximately 2 GHz over the 7 to 10 GHz frequencyrange. Power-added efficiencies generally fall into the 20 to 30% range(Honjo et al, 1979; Mitsui et al, 1980).

o Input' Output

f = 9.5GHZ

21120.25A

18ft0.2k

30fym gate width device

0.17A0.5W device (1200Mm)

0.25A1W device (2400Mm)

Figure 5.46 (a). Input and Output Circuit Impedances for PowerGaAs FETs (b). Matching Circuits for 100 mWFET, 0.5WFET and1WFET


= 137ft

0.31A40ft.07A

Device S - parameters at 10GHzS,, =0.66 Z — 170° S* = 0.65 Z — 70°S,, = 1.07 Z 25° Si2 = 0.09 Z22°All electrical lengths are referenced to 10GHz

(a)

ZOE = 137ftZoo = 40ft

0.3A

N.O/P

(b)

7 8 9 10 11 12Frequency, GHz

Figure 5.47 (a). Broadband Power GaAs FET Amplifier for 6 to 12GHz Operation, (b). Gain-Frequency and VSWR Characteristic of6-12 GHz Power FET Amplifier

1n 1n1n 1n

0.6p; Circuitschematic

1.5pF 6

0.6pF

= 27dBm;u, = 33dBm;= 2 3 % ^

Performance

Package

— 8 9 -Frequency, GHz

4 Cell Power FET(4800Mm) width

Figure 5.48 Broadband Power FET with Internal Matching


5.16 Maximum Spurious Free Dynamic Range Amplifiers

The spurious free dynamic range of an amplifier is defined by theequation

2Spurious Free Dynamic Range, D = -(Pj- P0-10logB- F)dB

where Pi is the input intercept point (obtained by subtracting theamplifier gain from the output intercept point).

Po is the effective input noise power with no signal (-114 dBM/MHz)

B is the system noise bandwidth in MHz (controlled by the amplifierbandwidth).

F is the amplifier noise figure in dB.

Thus for example, if a FET amplifier has a gain of 10 dB with an outputintercept point of 25 dBm, a bandwidth of 1000 MHz and a noise figureof 6 dB the spurious free dynamic range is

D = j{(25-10)-(-114)-10loglOOO-6}dB= 62dB

i.e. the range over which the amplifier will not have any 3rd orderintermodulation products greater than the noise floor is 62 dB.

For any specified amplifier bandwidth the parameters available ena-bling an increase in the dynamic range of the amplifier are the overallnoise figure and the output intercept point.

Thus, the use of power FETs with their high 3rd order intercept pointand low-noise small signal preamplifier FETs will enable large dynamicranges to be achieved. In order to accurately predict the distortionproducts of a power FET amplifier considerable attention has been paidto the use of power FET models for predicting gain compression, har-monic and intermodulation distortion (Tucker et al, 1977; Willing et al,1978). Non linear circuit-type device models have been derived whichindicate that the third order intermodulation distortion of many GaAspower FETs does not follow a 3:1 slope. Indeed often the intermodula-tion products do not follow a monotonic relationship with the inputpower of the test tones (Fig, 5.49). This is covered further in Chapter 3.


f = 8GHzAf = 5MHz

= 10V

-20 -10Input power (dBm)

30

Figure 5.49 Measured Values of Output Power Level and IMDProducts for a Power GaAs FET

5.17 Power Combining Techniques

Often the design of power FET amplifiers is limited to the available r.f.power handling capability of the FETs available. Also, 1 dB gaincompression point output powers are at single frequencies whilst thewideband operation power outputs are significantly below these levels.Wide gate devices have low input and output impedances which aredifficult to match over wide bands. In addition gain is at a premium atthe higher frequencies.

In a search for a solution circuit designers have been employing varioustypes of hybrid power combiners to combine the output of several lowerpower amplifiers that incorporate more easily matched narrow gatewidth GaAs FETs. The main disadvantage with the use of hybrid powerdividers is that of gain and power losses due to their insertion losses andthat effect on overall power added efficiency.

Figure 5.50 is an example of a 4 way power combiner, where the gain ofthe driver stages is 6 dB with an efficiency of 20% and the output deviceshave a gain of 5 dB with the power added efficiencies defined as in Figure5.50. As may be seen if circuit losses and combiner losses are both equalto 0.5 dB and the output devices have power added efficiencies of 30%the overall efficiency of the circuit is only 15%.


Circuit CombinerDivider losses losses U losses U

tput

Inputl

!

Driver Output Device

ExamDle G2 - 6dB G a i n G 2 9 a i n G 1

Example ( * - « B E f f j c j e n c y EfficiencyT l 2 = 2 0 / o

HP.2 HP.1G1 = 5dB

"10 20 30 40

Output device efficiency, Power added %

Figure 5.50 Efficiency of 4 Combined Amplifiers

Two simple planar combining techniques that combine the outputpowers of four GaAs FETs are shown in Figure 5.51a,b.

The first technique makes the use of two-way combiners of the Wilkinsontype (Wilkinson, 1960) while the second approach employs two hybridssimilar to that described by Lange (1969) and a simple 2 way splitter.

Figure 5.51a shows the use of two-way combiners that have beenconnected to a branch like network by two cascaded transformingelements. In order to provide physical access to the single-ended ampli-fier submodules, additional line length can be inserted into the combinerand divider circuits. This is accomplished by means of the elements Z2and Z3 as well as Z5. In order to combine the output power of 2 balancedamplifier modules power combiners are used as shown in Figure 5.51b.In contrast to the four-way Wilkinson type combiner, the dual quadra-ture hybrid combiner has the advantage of the excellent matchingconditions that are typical of balanced amplifiers, As a result the overallamplifier exhibits very low return loss and a smooth gain response(Niclas, 1979).

5.18 Thermal Considerations In Power Amplifier Design

Unlike small signal FET devices attention must be paid to the heatsink-ing of power FET devices to avoid the channel temperatures of the


79S7V|46fi<78°//\ 74'

\ v J Z4

Inpurlcm^

(a)

5012tvH=^

^H=)

S1O4J2

^H IDZs

D^-^Ty104JK

—>-C=^ r85J190°//

InpulV

ZA

(b)

t Output

(

60fi

f A^ AAA / \ _ ,—LJ-X^—W—' M__>-J^;

l—AAA-/ \_T—l-T^3—^v— M-Z)—j p

1 °

Ou

tpu

t

A P7

z,

Figure 5.51 (a). Four-way Single-ended Amplifier (b). DualQuadrature Hybrid Balanced Amplifier

devices exceeding the manufacturer's specified maximum operatingpoint. For example, a 3W amplifier having 20 dB of gain using PlesseyPGAT1000 devices over a 1 GHz bandwidth centered at 8 GHz wouldhave an overall power added efficiency of approximately 15%, i.e. 6.7Wof d.c. power is input to the FETs plus dissipation in other componentssuch as regulators etc. 10W of heat could be generated in such anamplifier and this heat must be dissipated as efficiently as possible.Thus, it is necessary to heat sink the power FETs effectively. Power FETpackages are designed to allow this to be achieved conveniently, e.g. holesin the package base allowing the devices to be screwed into a baseplatemade of a high thermal conductivity material such as copper. PowerFET data sheets usually provide a derating curve if the amplifier is tobe operated at temperatures higher than 25°C.

5.19 Pulsed Operation Of Power FETs

With the advances in power FET performance anticipated in the lightof recently reported low noise FETs (Ohata, et al, 1980; Butlin et al,1978) above 20 GHz, power FETs operating in the 20 to 30 GHzfrequency range can be expected in the near future.


Although the limits of power FET device performance have not beenreached, present performance levels are already sufficiently high to havecreated applications in many systems. Schroeder and Gewartowski(1978) have reported a 2 watt 4 GHz amplifier for radio relay systemswhilst Tserng and Macksey (1980) have developed a 4 watt, 10 GHzamplifier module suitable for phased array radar applications providedthat cost reductions can be achieved. Power combining techniques arebeing developed that are resulting in the replacement of TWT's withtheir associated bulky power supplies.

Large periphery FET Power devices exhibit low input and outputimpedances which require the special matching techniques discussed inthis chapter. The incorporation of matching networks directly on thedevice carrier has improved power gain performance by minimizing theloss between the device and the circuit (Honjo et al, 1979).

The output power of large periphery devices is limited also by gate-drainbreakdown voltage and the channel operating temperature. Continueddevelopment in both device and material technology have significantlyincreased breakdown voltage. Many applications for power FETs, par-ticularly for radars, require pulsed operation of the devices. Significantimprovements in output power have been reported by pulsing the gateor drain of the FET whilst the FET is operated at elevated drainvoltages.

Pulsing the drain voltage appears to produce the most significantincreases in output power. Wade and Drukier (1980) have reportedincreases in output power from 2.3W to 3.5W with a pulse width of1.5jusec, a duty factor of 0.5%, for a 6 mm by 1.7jum GaAs FET operatingat a VDS of 9V. At a drain voltage of 14V, 5.9W was obtained with 5.2 dBgain. The overall increase in power output from CW to pulsed operationwas 4.1 dB. Figure 5.52a and b show the performance as a function ofdrain voltage, pulse width and channel temperature. Also a markedimprovement in bandwidth is observed probably due to device heatingunder mismatched conditions during CW operation. Bandwidth im-provements of over 3:1 in X band have been reported.

Temple et al (1980) have pulsed the gate of X band FETs to produce 2dB improvements in power gain when compared to CW operation.Figure 5.53 shows the output power improvement versus drain voltagefor a 2//sec pulse width at a duty factor of 20%.

It thus appears that the pulsed mode of power GaAs FET operation willgive significant improvements in performance such that low cost mono-lithic power amplifiers, for phased array radar transmitter applications,

276 Microwave Fteld-Effect Transistors

38

3 6

32

30

Pin = +32.5dBmi

•—• 30dBm*—•28dBm

— CW— Pulsed drain

6 8 10 12 14Drain voltage (Volts)

30dBm TT- - ' ^ 9 5

r8

N

35

Powerinput= + 31dBm

Powerinput=+28dBm

Power output at"I—Start *-* Peak channell r -end • - • temp. •-•

20 40 60 80 100 120'r

Pulse width fas)

36

35 «

34 8

33

(a) Performance at 8GHz of GaAs FET with (b) Pulse droop and peak channel1.7fim by 6mm gate, in pulsed-drain operation temperature versus pulse width, for a 1.7^m

by 6mm GaAs FET in pulsed-drain operation

Figure 5.52 Pulsed Performance of GaAs FET (Drain Pulsed)

will be able to operate at considerably reduced channel temperatures.This means that not only will less attention have to be paid to thermalimpedance between the chip and its carrier but that increased reliabilitywill result (Irie et al, 1976).

4.2

3.8

3.4

2.2

Frequency = 10GHzPower input = 1.6 Watts

Pulsed power2MS : 20% Duty factor

Improvement= 2.1dB

Comparison of pulsed and CW operationof a 4.8mm GaAs power FET

10 11Drain voltage (Volts)

12 13 14

Figure 5.53 Pulsed Performance of 4.8 mm GaAs FET (Gate Pulsed)


5.20 Reflection Amplifiers

The GaAs FET is the only three terminal device available in thefrequency range above X band. However the development of low noiseamplifiers above approximately 20 GHz is difficult due to the maximumavailable gain per stage. Because of the relatively low associated gainof the first few stages of a multistage amplifier the overall noise measureis poor.

Circuit losses, such as those encountered with microstrip at the higherfrequencies, can be substantially reduced by the use of waveguide.

The GaAs FET can be operated as a negative resistance two terminaldevice by inducing the correct impedance with feedbacks. Severalschemes to do this are available including operating the FET in commondrain and terminating the gate in the correct reactive load.

(Nicotra, 1979). The reflection coefficient measured from the source sideof the device Fs is then greater than one.

Ts=Sn(S12S21)

(1-S22TG)

where FG is the reflection coefficient at the gate of the FET.

As shown in Figure 5.54 source transforming networks can be designedsuch that the load matching network, having impedance RL + JXL,resonates the reactive component Xs' of the FET thus allowing themaximum output power of the FET to be delivered to the load. This isthe case when

PIN

A circulator is used to provide isolation between the input signal andthe output signal.

Tohyama (1979) has recently described the construction of a 23 GHzreflection type amplifier in waveguide which utilizes the resonant prop-erties of the sealing ring of a packaged NEC 388 GaAs FET. Figure 5.55a


—v

Gatevoltage

regulator

i Rs1 + jXs1

rrLT

Trans-formingnetwork

Frequency adjust

Figure 5.54 Negative Resistance Amplifier Using Common DrainFET

shows the structural details of the FET package whilst Figure 5.55bshows the waveguide mount.

In this amplifier the coaxial short circuits on the gate and drain of thedevice are adjusted such that the impedance looking into the drain-source port is negative over a considerable range of frequencies. Forexample Figure 5.56a shows the impedance at the drain-source portwhen the circuit has been adjusted for operation at 24 GHz. Figure5.56b shows the gain and noise figure of the amplifier over the 23.3 to24.2 GHz band. A gain of 8 ± 1 dB was achieved with a noise figurebetween 6 and 7 dB. In the usual transmission type amplifier circuitthe gain of such a packaged 0.5/mi gate length FET would be very lowparticularly since the package exhibits a resonance around 20 GHz.

Broadbanding of reflection amplifiers depends on the ability of thematching circuit to provide a reactance which is the conjugate of thereactive part of the FETs input impedance. Normally this is providedby, for example, resonating the gate-to-source capacitance, CGS, of theFET with an inductance, In order to broadband such a technique someof the network synthesis routines described in this chapter can beadopted.


GaAsFETSealing ring

Gate

-4mnri-

(a)

Waveguide Wall

(b)

-DC isolated bydielectric film.

-Coaxial short plunger.

Figure 5.55 (a). GaAs FETPackage Structure (b). WaveguideMount Structure

However, an attractive method of broadbanding is to use the activereactance compensation technique developed by Aitchison et al (1980).

Figure 5.56 (a). Measured Impedance at the Drain-Source Port (b).Gain and Noise Figure Characteristics of GaAs ME SFET ReflectionAmplifier in the 23 GHz band


Figure 5.57, for example, indicates that by connecting a similar negativeresistance FET device XIA away from the FET under consideration theinput admittance, YL of the FET can be exactly compensated.

If the input admittance,

then a perfect quarter-wavelength of characteristic admittance Yo,terminated in YL will have an input admittance

Y 2

8+jb

If YL is resonant at the center frequency then b = 0 and if g2 » b2

elsewhere in the band of interest

8

Connecting the two loads in parallel gives

Figure 5.57 Active Reactance Compensation ofGaAs FET ReflectionAmplifier


8

By choosing Yo = g

Ymr=2g

5.21 Conclusions

This chapter has dealt with the extensive subject of microwave amplifierdesign with particular reference to the use of gallium arsenide fieldeffect transistors. The descriptions given are by no means complete andthe reader is referred to the references as a means to farther study.

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Wilkinson, E.J. An N-way hybrid power divider. IRE Trans. MTT,Vol.MTT-8, January 1960, pp.116-118.

Willing, H.A., Rauscher, C. and de Santis, P. A technique for predictinglarge signal performance of a GaAs MESFET 1978 IEEE MTT-S Inter-national Microwave Symposium Digest, Ottawa, Canada, pp. 132-134(78CH1355-7).

Zurcher, J.F., Micros 3-A CAD/CAM program for fast realization ofmicrostrip masks. IEEE MTT-S International Microwave SymposiumDigest, pp.481-484, 1985.

6

FET Mixers

6.1 Introduction

The GaAs MESFET has gained a well deserved position amongstmicrowave solid state devices as a low noise amplifying device up to 30GHz or so. The performance of Schottky barrier FETs as mixers, par-ticularly utilizing low IF frequencies has been somewhat disappointingin respect of noise figure performance although there are undoubtedadvantages in terms of conversion gain and high compression point overSchottky diode mixers. Extensive studies have been carried out bylaboratories worldwide into the applications of both single and dual-gateMESFETs in up and down-conversion circuits. Recently, with the ad-vent of gallium arsenide integrated circuits, new device and circuittechniques have been adopted which are realizing low-noise figures withhigh conversion gains at frequencies up to X-band (Pengelly, 1980). Thereason for this latter success has been the realization of biasing andcircuit designs giving optimum performance in respect of signal andlocal oscillator injection as well as a fuller understanding of FETrequirements.

GaAs MESFETs utilize their nonlinearities to produce mixing (Pucel etal, 1975; Sitch et al, 1973)-namely, the IGS-VGS nonlinearity and theIDS—VGS nonlinearity. The first of these effects results from the Schottkybarrier between the gate and source and it shows characteristics analo-gous to Schottky barrier diodes. The second nonlinearity is caused bythe pinch-off effect described in Chapter 2.

6.2 The GaAs FET As A Mixing Element

Figure 6.1 shows the simplified equivalent circuit of a chip FET whereparasitic components such as wire bond inductances have been ne-glected. As has been described in Chapter 2, a low noise FET will havebeen designed to minimize the parasitic resistances RG, RS and RD,where RG and Rs are the principal contributors of extrinsic noise (Fukui,1979).


Gate R*

= 9MRO

Source

Drain—o

Figure 6.1 Small Signal Equivalent Circuit of the GaAs FET usedin Mixer Analysis

Mixing will occur in a FET if certain of the 'small-signal' elements canbe varied at a periodic rate by a large local oscillator (LO) signalconnected across two of the device terminals. The connections whichhave been investigated by various workers include putting the LO signalbetween gate and source and between drain and source. In a GaAsMESFET the strongest gate-bias dependent parameter is the transcon-ductance, gm. Mixing products due to the parametric 'pumping' of thesource-gate capacitance CGS and the intrinsic resistance Ri (which canbe considered as a charging resistance associated with CGS) are alsopresent but are neglected in the following analysis since frequencyconversion due to these is inefficient. Drain resistance is also a strongfunction of gate-bias and such dependence is analyzed later in thischapter. For the present analysis this parameter is time-averaged.

A plot of the measured transconductance of a typical 300jum gate width,]jum length FET is shown in Figure 6.2 as a function of applied voltagebetween gate and source where the drain-to-source voltage VDD is abovethe knee of the IDS—VDS characteristic.

Consider the case where a large LO signal is present across the gate-to-source of the FET in addition to a fixed bias voltage. Thus the transcon-ductance becomes a time varying function gm(t) with a frequency equalto that of the LO. If coo denotes the LO radian frequency then

FET Mixers 289

30

20

10

V* = 3vU = 70mAVp = -3 .3v

-3.0 -2.0 -1.0 0

Gate-source voltage Vgs (Volts)

Figure 6.2 Measured Transconductance as a Function of Gate Biasfor a GaAs MESFET

8mV) = 6.1

where

6.2

Neglecting the harmonic components of Ro(t) the time-varying voltageamplification factor ^(t) can be written as

~ t ) 6.3

Where Ro is the time-average drain resistance

With reference to Figure 6.1 a signal vc(t) whose amplitude is much lessthan the LO and of radian frequency coi is also present across thecapacitance, CGS. By the nonlinearity of the time-varying transconduc-tance a voltage (t)vc(t) will appear across the drain-to-source terminals.This signal will have 'sideband' components at |n<yo±on |, where n isan integer, since


JU (t) = Ro(go + 81 cosa)ot + g2 cos2o)0t+...)

•(Vo +Vj cosa)1t + V2 cos2ct)jt+...))1

For convenience this analysis will concentrate on the prime use of theMESFET, i.e. as a downconverter, such that the intermediate frequencywillbetO2= |o>o-ftn| (where C02 < coi). The other frequency componentof significance is the image frequency cos where (cos-coi) = 2a>2.

Figure 6.3 represents the FET mixer with the LO signal generatorimpedance represented by Zo and the input signal coi provided by avoltage source Ei with impedance Zi.

The other sideband components, namely the IF frequency, 02, and theimage frequency cos are terminated in complex impedances. The rectan-gles FK and FK' are ideal lossless filters having zero impedance at thefrequency of interest and infinite impedance at all other frequencies. Ofcourse, the distinct sets of input and output ports are not physicallyseparable in the real FET. Although in this analysis the LO is assumedto be injected between gate and source it can be inserted between sourceand ground. A port for the LO signal is necessary at the output since astrong LO component is present due to modulation of the drain currentat this frequency. The LO frequency is usually terminated in a shortcircuit at the FET.

Zo - Fo

Wo(LO)

z,' - F,

W,(RF)

F2

W2(l

z3 - F3

W3(image)

w

F;

F2'

Zo

o(LO) J

z/

,(RF) J

- Z5

W2(IF) ^

- z5

W3 (image)

Figure 6.3 Diagram of FET Gate Mixer Showing Signal, IF, LO andImage Circuits Used in Analysis

FET Mixers 291

The FET mixer operated in the above mode has been analyzed by Pucelet al (1976).

The linear circuit relationships between the various frequency compo-nents can be written as

6.4

and

6.5

where

E,*

0

0

0

0

0

6.6

where El* represents the lower sideband small signal at frequency <wi

V,*

V !

V46.7

6.8

Zm and Zt are the matrices representing the mixer and its terminations.Zm is given by


[zt] =

Zu

0

0

Z41

0

z *

z ;0

0

0

z220

0

z52z62

0

z2

0

z3

00

Z33

Z43

Z53

z63

•

z140

0

0

0

•

0

z250

0

Z55

0

•

00

z360

0

Z66

Neglecting harmonics of gm(t) we obtain

1

Z14 — Z25 = Z2(S =Z14 2(S

— ^ i V5

7 _ 81^0L62 - " ~^=

_ -gpRo~-—Zr^-

J°)3CGS

JC°3CGS

6.9

6.10

FET Mixers 293

For K = 1 to 3 and for K = 4 to 6 where C GS represents the time averagedvalue of the gate to source capacitance C GS.

The transducer conversion gain, Gm, between the RF input and the IFoutput is given by

_ |/6f ReZ6u">~ ( •„ .2 A 6.11

4ReZ

and therefore

Gm = 4RGRL

where

6.12

and

Z* =

where RL + J'XL is the load on the mixer FET at the IF frequency.

Gm is obviously a complicated function of the terminations on the inputand output ports. However, when the intermediate frequency is smallcompared to the input signal frequency (for example where the signaland IF frequencies are 8 GHz and 30 MHz respectively) some simplifi-cations can be made.

The terminations at the ports other than the signal input and IF outputare of secondary importance since Ro » RS,RD and goRS « 1, bothbeing true for well-designed low noise FETs, the solution of equations6.4, 6.5 and 6.12 gives the mixer transducer gain as

Rr

\(Ro +XL2

6.13


where RIN = RG + RI + RS is the input resistance. Considering the casewhere the source and load are conjugately matched to the FET, i.e. RG =RIN, ZG= (COIC GS)"1 and RL = Ro, XL = 0, we obtain the availableconversion gain, Gc given by

Ro

'GSj + Rs

6.14

This can be compared to the simplified expression for the amplifieravailable gain, Ga , given by

G —RG+R,

6.15

which can be determined from equations 2.21 and 2.35.

Equation 6.14 indicates that the conversion gain is a strong function ofthe gate bias and LO drive due to the conversion transconductance, gi.gi is most dependent on gate bias near pinch-off. This may be seen byplotting conversion transconductance versus gate to source bias for theFET used in the experiment of Figure 6.2. The result is shown in Figure6.4 where the instantaneous voltage across the FET's gate and sourceis given by

VGS(t) = VGS+Vocosa)ot

9m

10

-4 -3 -2 -1 0

Gate-source voltage, Vg, (volts)

(a)

-3.3 V« 0 0.5

1 Maximum forward| ; gate voltage

Figure 6.4 Calculated Conversion Transconductance at MaximumLO Drive as a Function of Gate-Source Voltage

FET Mixers 295

where VGS is the d.c. bias and Vo is the peak r.f. amplitude due to the LOdrive. Figure 6.4(a) and (S) show the relationship between gm and gi asthe LO amplitude changes from the positive peak value correspondingto the onset of forward conduction of the Schottky gate to the negativepeak value dependent on VGS. gi is found by calculating the Fouriercomponent of gm(t) from the experimental curve of Figure 6.2 usingequation 6.2.

It is noted from Figures 6.2 and 6.4 that the maximum value of gi isapproximately one-third that of the maximum value of gm. (The ratioobtained for the 'ideal' case when gm is a step function of the gate biasis \ITI). If the LO power is not at the maximum level then the gi valuewill be lower. This dependence is shown in Figure 6.5. The steeper thegm(t) curve is near to pinch-ofF, the steeper the gi curve is near zero LOdrive. An illustration of the way in which technology improvementshave increased the performance of FET mixers is shown in Figure 6.6where the IDS—VGS characteristics of two FETs is shown, one having abuffer layer, the other without. As has been explained in Chapter 4, thebuffer layer used with FETs fabricated on epitaxial layers results in theelectron mobility being maintained in the active channel up to theinterface. This means that combined with a well defined electronconcentration profile the value of gm(t) will be maintained at a highervalue close to pinch-off than a device without a buffer layer. Thus, the

1 2Local oscillator voltage

amplitude, Vo(volts)

Figure 6.5 Conversion Transconductance at Pinch Off Bias as aFunction ofLO Drive Level


Drain-sourcecurrent, lds

. Drain-source/ current, lds

Gate-source bias, Vos

Device without buffer layer

Gate-source bias, Vp

Device with buffer layer

Figure 6.6 Effect ofVPE Buffer Layer on IDS-VGS CharacteristicsofGaAsFETs.

gm(t) to VGS curve will be steeper close to pinch-off and consequently thevalue of gi will be higher.

Gate capacitance also varies with gate bias as shown in Figure 6.7. Thisfigure shows that CGS continues to decrease beyond the pinch-off voltageand can be approximated by a linear function. Thus the average capaci-tance C presented to the signal frequency will be equal to the staticcapacitance CGS at the gate bias point VGS.

6.2.1 LO Applied Between Drain And Source

Figure 6.8 is the equivalent circuit to that of Figure 6.3 where the LOsignal is applied between the drain and source. The parasitic resis-tances RG, RS and RD, the gate resistance Ri, gate-to-source capacitanceCGS and the gate-to-drain capacitance CGD which are partly voltagedependent as already explained are assumed to be constant. Both thedrain resistance Ro and transconductance gm are time varying functionsat the frequency of the LO, coo. The voltage amplification factor ^(t) =gm(t)Ro(t)//(t) is therefore time variant. As before, a conversion matrixcan be set up which relates the currents and voltages in the FET.

Assuming CGD = 0, we obtain

FET Mixers 297

3 1.0

o5

0.8

30.4

• Experimental

— Linear approximation

-4 -3 -2 -1

Gate-source voltage, Vo$ (volts)

Figure 6.7 Gate-Source Capacitance as a Function of Gate-SourceVoltage

Zo' 4 , - .Wo(LO)

z, Ill

(~) W,(signal)

7T7"

7

7 / - F,'

I W2(image)

T 7

z3' F3'

W3(IF)

o(LO) ^ ,

F,

W, (signal)

F2 zrW2(image) r;

F3

VAi /I

Figure 6.8 Diagram of FET Drain Mixer Showing Signal, IF, LOand Image Circuits Used in Analysis


zn0

0

z41Z51

Z6i

0

z22*0

Z42

Z52

z62*

00

Z33

Z43

z53z63

Z41

0

0

Z44

Z54

Z<>4

0 '0

Z36

z46z56Z66

h'hu//

6.16

The asterisks indicate complex conjugate values. The matrix elements

1

J°>KCGS

— ZK+RD + Roo

For K = 1 to 3 and for K = 4 to 6

V _ D _ t*O

L52/*o

Z43

L62

Z56

^42

r~ 1

j(i)3CGS

*

J«>3CGS*

Jo>iCGS

*

j(02CGS '~46

- 7 - 7 - p *

*

jco3CGS '"5i

= Z54 = Ro2

R01

f* 2

Jo>iCGS

FET Mixers 299

where Roo, Roi and R02 are the Fourier coefficients of Ro(t) and//o,^i,jU2, are the Fourier coefficients of ju(t).

From equation 6.16, the mixer gain is given by2

Gm=4RGRL 6.17

For the simple case, where Z3, Z4, and Z5 are large and conjugatematching is applied at the signal input and IF output ports, equation6.17 predicts the available conversion gain, Gc to be

G = b l ! 618C 4(O1

2CGS2(RG + R + R ) ( R + R + R )

The drain-to-source diode can be assumed to be driven by the instanta-neous voltage

VDS(t) = VDS+Vocosa)ot 6.19

where Vo is the peak local oscillator amplitude and VDS is the static drainbias voltage. Now,

where

and

K=-oo

where

and


Thus^(t) can be found by measuring the transconductance gm and drainresistance Ro of the FET as functions of gate and drain bias.

Figure 6.9 (Begemann, et al, 1979) shows, for example, the theoreticalconversion gain Gc as a function of the drain bias at the maximum LOdrive level for several different gate-to-source bias conditions. Figure6.10 shows the influence of the feedback capacitance CGD on the conver-sion gain of a drain mixer. It may be appreciated that the value of Gc

depends strongly on the value of CGD. CGD values are usually in therange of .01 to 0.02 pF for modern FET devices and with such valuesconversion gain decreases of 4 dB or so are apparent even at a relativelylow signal frequency of 4 GHz in the example quoted.

Indeed, Harrop (1979) has compared the conversion gains of FET mixerswith the LO injected into the gate and the drain with the signal at 7GHz and the IF at 1 GHz and shown that there is a 10 dB difference inconversion gain.

6.3 Experimental Results on Gate Mixers

Figure 6.11 shows a typical microstrip circuit used to exploit the singlegate FET as a mixer. One of the problems of the single gate mixer is therequirement to introduce both the LO and signal frequencies into thegate of the FET. This can be achieved using a coupler but will introduceloss and therefore degrade noise figure and conversion gain unless ahigh coupling ratio is used which will then necessarily mean the use ofhigh LO drive. The active signal adding technique described elsewherein this chapter is a convenient way of overcoming this problem.

Cripps et al (1977) have reported 6 dB conversion gains with DSB (seefootnote) noise figures of 8.5 dB including a 3 dB noise figure IF amplifierat a signal frequency of 10 GHz with an IF of 30 MHz. Pucel et al (1976)have reported a balanced mixer having a conversion gain of 3 dB and anoise figure of 7.4 dB DSB having a signal frequency of 8 GHz with a 30MHz IF. Harrop (1979) has reported a FET mixer using 1/ m gate lengthFETs with 10 dB conversion gain and a 8.3 dB noise figure with a 1 GHzIF.

The use of a balanced mixer arrangement with single gate FETs not onlyeases the LO and RF injection but also provides advantages in the formof LO noise suppression, increased dynamic range and good input match.Figure 6.12 shows a typical schematic for a balanced FET mixer ap-

FET Mixers 301

15

CD

H 10

§

s

—"—

A /// I I L.O. amplitude Vo

/ / / /

V

tofi =

o.= -0.2V

-0.8V

^ ^-1.4V

" - — ^

= 100MHz= 4.16GHZ

0.5 1.0

Drain-to-source bias voltaae (volts)

1.5

Figure 6.9 Conversion Gain ofGaAs FET Drain Mixer as a Funtionof Drain and Gate Bias Voltages

m•o

o

(3

f

sion

c

18

15

10

5

0

-

v-Vo

-

= 100MHz / ^ ""•"= 4.1GHz / X= -0.2V / ^ "

IlllIlll0.5 1.0

Drain-source bias voltage (volts)

Cgd«OpF

0.01pF

- ^O.O2pF

0.04pF

1.5

Figure 6.10 Conversion Gain ofGaAs FET Drain Mixer as aFunction of Feedback Capacitance, CGD and Drain to Source Voltage,VDS


LO. RF trap t j Low-pass! filter

Signal

Low pass bias filter

IF output

IIF matching

circuit

A Gate bias

Figure 6.11 Typical Circuit Configuration for a Microstrip GaAsFET Mixer

proach. The antiphase IF signals produced by the quadrature shiftedr.f. and LO signals have to be brought back into phase. In a diode mixerthis is conveniently achieved by reversing the diodes but this cannot bedone with FETs. Depending on IF frequency, these signals can either

R.F.l/p o

LO.ol/p

90°coupler

Matchingcircuit

Matchingcircuit

FETmixer

FETmixer

I.F.matching

circuit

IF.matching

circuit

+ 90°phaseshifter

-90°phaseshifter

/ 1*F./ OP

Figure 6.12 Diagram of Balanced FET Mixer Showing PhaseShifters in IF Circuit for LO Noise Cancellation

FET Mixers 303

be combined using a center-tapped tuned transformer with a bifilarwound primary or by the use of leading and lagging phase shifters asshown in Figure 6.12. These phase shifters can be constructed usinglumped elements or distributed transmission lines and can be incorpo-rated into the IF matching networks.

6.4 Noise Figure

The noise figure results in particular that have been quoted above aresomewhat disappointing when consideration is given to the fact that theequivalent noise figures for the same MESFETs operated as amplifiersare of the order of 3 dB at 12 GHz. Tie and Aitchison (1983) have derivedexpressions for the noise figure of the MESFET mixer using the linearcircuit analysis of Pucel et al (1976). The device analyzed was thePlessey GAT6 which is a 0.7 micron gated MESFET having a gate-widthof 300 microns. The two main non-linearities of the device are thetransconductance, gm, and the drain resistance, RD, as already discussed.In gate mixer operation the LO signal is injected into the gate terminalof the MESFET thus causing changes in the equivalent circuit compo-nent values. For simplicity only the gm, RD and CGS are assumed to beaffected by the LO.

The time-varying transconductance is given by:

where

Su=\— We (t)e~jk0)°tdt

and

where w0 is the LO radian frequency.

It is assumed for the purpose of the analysis that the main non linearityis the transconductance and, therefore, time-averaged values of _thegate^p-source capacitance and drain-to-source resistance are used (CDSand RDS).


The noise properties of the GaAs MESFET have been dealt with in somedetail in Chapter 2 and the equivalent circuit shown in Figure 6.13 iswidely used, (Statz et al, 1974). The current generator, io) representsthe MESFET drain current noise source whilst iG represents the inducedgate current noise source. Voltage generators eG, es and eD representthermal noise sources associated with the gate metal resistance andsource and drain contact resistances respectively.

The mean square values of the MESFET drain current noise source, iD2,that of its induced gate current noise source, iG2 and the correlationcoefficient, C, between the iD and iG can be expressed as:

T^^4kTB(a)CGS)2R

om

iD2=4kTBgmP

and

lG lD

where k is Boltzmann's constant, T is the absolute temperature, B is thebandwidth of operation, co is the radian frequency, and P and R are noiseparameters dependent on the biasing and structure of the MESFET.

Gate eg Rg

Source

R d ed Drain

Figure 6.13 The Common Noisy MESFET Equivalent CircuitRepresentation

FET Mixers 305

In order to ease the noise analysis of the mixer the usual noise sourcesiG and iD are transformed into noise current sources iNG and iND as shownin Figure 6.14. The relationships between the sources are given by:

im XGS[RSXDG(I + 8

XGS (XDG ~~ RS ) "" XGS (

and

lND __ ( XGS )J

DG )J

*D (Rs +ZD)[XGSXDG +ZSo(X \

where

Zso is the source impedance;

XGS is the reactance of the gate-to-source capacitance;

XDG is the reactance of the drain-to-gate capacitance;

XDS is the reactance of the drain-to-source capacitance;

ZD is the impedance of CDS in the parallel with RD.

The remaining thermal noise sources in the MESFET are given by:

Figure 6.14 The Mesfet Equivalent Circuit to be Used for NoiseAnalysis. Note that the ig and id of Figure 6.13 have now become ingand ind-


eG2 =4kTBRG

es2=4kTBRs

Let us assume in the mixer circuit that the IF is lower than the RF andthat the LO is higher than the signal frequency. The signal and IFcircuits will be considered on both the input and output of the MESFETusing the schematic shown in Figure 6.15 In this figure Vi, V2 and Ii, I2represent the complex voltages and currents of the RF and IF compo-nents at the FET input whilst V3, V4 and I3,14 are the correspondingvoltages and currents at the FET output. Generators Eo and Ei repre-sent the LO and RF signal sources respectively at the FET input withZo and Zi being the matching impedances into the FET gate. Z4 is theIF matching impedance at the FET drain whilst Zo, Z2 and Z3 arearbitrary terminating impedances. The reader will note that this sche-matic is very similar to that used in the gate mixer conversion analysisused in Figure 6.3. As in Figure 6.3 the rectangles Fo, Fi and F2 arelossless filters having zero impedance at the frequency of interest andinfinite impedance at all other frequencies.

Mixer MESFET

Kt)-gm(t).vc(t)

Figure 6.15 The Schematic of the MESFET Gate Mixer Includingthe LO, RF and IF Circuits for Signal Analysis

FET Mixers 307

The signal equations for describing the LINEAR circuit relationshipsbetween the different frequencies in the gate mixer can be expressed bythe matrix:

*

0

0

0

+z 12 z13

V

Z22+Z2

z32z42

zl4z24z34Z44 + Z4

hhhu

where the matrix elements ZNM (N = 1, 2, 3, 4 and M = 1, 2, 3, 4) arefunctions of the equivalent circuit parameters of the FET.

The equivalent schematic for the noise figure analysis is shown in Figure6.16 being derived from the circuits of Figures 6.14 and 6.15. Theassumption is made that the LO circuits of the mixer do not havesignificant effect upon the noise figure. This is an assumption which isonly strictly valid in a practical situation when the LO is numericallywell removed from the RF, i.e. when the LO frequency is high. Thecurrent generators iNGi and iNG2 represent the induced gate noise sourcein the RF and IF circuits at the MESFET input whilst iNDi and iND3 arethe corresponding drain noise sources. All the noise voltage sources inthe mixer circuit can be expressed using the same forms as already given

Mixer MESFET

IF(o.2) IF(o>2)

Figure 6.16 The MESFET Mixer Circuit Including the IF Input andRF Output Circuits for Noise Analysis


whilst the current sources are expressed as functions of the time-aver-aged values, P and R, of the FET noise parameters P and R.

All the noise current components arriving at the IF output port from thenoise sources within the mixer circuit can be summed using the formulaof Friis (1944) such that the noise figure, F, of the circuit of Figure 6.16is expressed as:

where INO, INO2 and INO3 are the noise components in the mixer's IFoutput circuit derived from the noise sources of the RF input, IF inputand RF output circuits respectively and iND2 and (4kTB/RD )% are thenoise current components generated within the IF drain circuit itself.INO is the noise current component in the mixer's IF output circuitcaused by the RF matching impedance at the FET gate.

INOI and the INOk terms can be derived from the voltage and currentexpressions above transformed to the IF output by transfer functionsderived from the signal matrix above. These transfer functions will notbe derived here.

Let Yi, Y2 and Y3 be the transfer admittances from the mixer's RF input,IF input and RF output ports to its IF output port, respectively and Gi,G2 and G3 the corresponding current gains from the three frequencyports to the output port.

Then it can be shown that:

JNO = Ylei*

JNO1 = Yl {el + eG +eS*) + G11NG1*

INO3 ~ Y3e3 3ND1

Substituting these values of INO and INOk into the Friis formula (1944)results in the following expression for noise figure:

FET Mixers 309

+ RS)R]+\Y2\2/\Y]\

+N7M

lND2

+2\

\2 IUr\2NG1

ND1

4kTBR

4kTBR7

2 Lr\2 4kTBR}

NG2 lNDl 4kTBRj

+2[iNG2\D2\2) MkTBR,

where Re denotes the real part of Ci and C2, the time-averaged valuesof the correlation coefficients between iNGi* and iNDi*, and iNG2 and IND2.Brewitt-Taylor et al (1980) have evaluated the noise parameters P, Rand the imaginary part of the correlation coefficient, C for a microwaveMESFET as a function of the device normalized drain current andsaturation index. Time-averaged values can be calculated approxi-mately from this paper.

Conversion gain calculations for the mixer employ the techniques dis-cussed in Section 2 of this chapter.

Consider the mixer circuit of Figure 6.17 where the IF is presented witha short-circuit on the FET input and the RF is presented with ashort-circuit at the output. The device used in the mixer is a PlesseyGAT6 having a gate length of 0.7 micron and a gate-width of 300 micron.Pinch-off voltage is approximately - 3 volt. The LO frequency, RF andIF were chosen to be 8.03 GHz, 8 GHz and 30 MHz respectively.


RF inputmatching

circuit

I IIF matching circuit

Figure 6.17 Schematic of the Mixer (the IF Input and RF OutputLoads are Short Circuits)

A comparison between the measured and calculated conversion gainsand noise figures versus LO power is given in Figure 6.18 for the mixerof Figure 6.17. It can be seen from the figure that the measuredconversion gain of the mixer can be predicted accurately by the foregoingtheory. The results of the noise figure calculations appear to be not soaccurate in terms of their trend with LO power levels although there isvery good agreement on the noise figure values themselves. The dis-crepancy may be due to the time-averaged values used for P, R and Cwhich have been derived from the curves of Brewitt-Taylor and do notnecessarily apply to the GAT6 FET used exactly.

Some interesting points do emerge from title expression for the noisefigure of the gate mixer. Tie has shown that the minimum noise figureof the gate mixer appears to be relatively insensitive to the values of theIF input and RF output loads (at least for frequencies whereby theinternal feedback in the FET can be neglected) although the conversiongain can vary by around 6 dB. This suggests that the mixer noise figureis dominated by the current gains acting on the noise current compo-nents at RF, IF and LO. The noise current contributions from the IF areupconverted via the mixing and hence 1/f noise will have a marked effectat very low IFs.

6.5 Signal Handling of FET Mixers

Even though the noise performance of FET mixers is somewhat disap-pointing at the present time their other outstanding advantages of high

FET Mixers

mT3

0>m

ix

o

ure

g>

oc

CQ

and

55

c

"icot/l

$c

16

14

12

10

8

6

4

2

0

-

-

-

-

-

-

_

-10

vGS--uv

<\ \No ise figure i

\ N, S* /

**"^—"^ . ^ ^ ^ ^ ^ ^ ^^^ ^ W

^r Conversion \ V// 9a l n \ ^

/ ^ --o— Measured/ / Calculated

/ /p /

i i i i i i i i i i

- 8 - 6 - 4 -2 0 2 4 6 8 10LO power (dBm)

311

Figure 6.18 The Measured and Calculated Noise Figure andConversion Gain of Mixer of Figure 6.17 (the IF Input and RF OutputLoads are Short Circuits)

output compression point and conversion gain over diode mixers oftenmake them the obvious choice for certain applications. Also the adventof the double-gate FET followed by a single gate mixer has meant thathigh conversion gain with noise figures only slightly inferior to that ofan equivalent 2 stage FET amplifier can be produced.

The conversion gain of a typical FET mixer versus LO power is shownin Figure 6.19. The LO power required for maximum conversion gain isdependent on the pinch-off voltage and substantial reductions can bemade in LO power by the choice of carrier profile and channel depth todecrease Vp.

The single gate FET has excellent signal handling properties as evi-denced by the results shown in Figure 6.20. Here is shown the mixerconversion gain as a function of r.f. input power for two different levelsof LO power. 1 dB output compression points of the order of 5 dBm areachieved with LO powers of 5 mW or so. The balanced mixer configura-tion will give a corresponding 3 dB higher output compression point(assuming ideal phase and amplitude matching). The figures for third


10

COT3

5 -

-5

Gate width

Gate length

7

= 500Mm

^ —• •

f = 8GHz

f,F = 30MHz

10 15 20

Local oscillator Dower, mW

25

Figure 6.19 Typical Conversion Gain as a Function of LocalOscillator Power for a Single Gate FET Mixer

order output intercept point performance are equally impressive withvalues of+20 dBm being readily obtainable with LO powers of the orderoflOmW.

6.6 Further Mixer Configurations Using Single Gate FETs

The recent advent of monolithic microwave circuits has allowed rela-tively simple single gate FET mixer circuits to be fabricated and evalu-ated where, perhaps, more than one FET is required, Figure 6.21 showsthree such circuits which have been investigated (Greenhalgh, privatecommunication) and show considerable promise. As with the single gateFET mixer short circuits at r.f. and LO are required at the outputs andi.f. short circuits at the inputs. Figure 6.2l(a) utilizes a common gateinput FET TR1 having two separate source electrodes with a commondrain. By optimizing the gate width of the device it is possible to biasthe device such that average gm is close to 20 mS.

Thus, at frequencies up to 4 GHz or so, the FET's input impedance willbe close to 50 ohms since the device is connected in common gate, TheLO to signal isolation provided by this connection is approximately 20dB at 4 GHz. Since the channel regions corresponding to the two sourcesare made separate no mixing occurs in the FET. The two signals aretherefore added and continue to the single gate mixer TR2. The common

FET Mixers 313

CD

•aI 4§

I8

PL0 = 15mW

PL0 = 5.2mW

1dB

1dB

f = 8GHz

fiF = 30MHz

-40 -30 -20 -10

R.F. input level, dBm

0 +10

Figure 6.20 Typical Conversion Gain of a GaAs FET Mixer as aFunction of RF Input Signal Level

LO.R.F.

TR1

TMatching

circuit

I.F.matching - I.F. output

(a) Common gate active combiner/singlegate mixer R.F.

R.F.match n:TR1 TR2

L.O.LO.

match

Matchingcircuit

I.F.matching

I.F.output

Matchingcircuit

TR2

LO.<TR3 Matching

circuit

I.F.I matching

(b) Common source active combiner/singlegate mixer

output

(c) Common gate LO. and R.F7switchingFET mixer

Figure 6.21 Various FET Mixer Configurations


Low-pass filter

LO. input o —

R.F. input c

LO.matching

Signalmatching

G2 D

s

7

noHigh-pass filter

11

I.F.matching I.F. output

Figure 6.22 Dual-Gate FET Mixer

gate FET TR1 will provide a small amount of gain at r.f. and LO whilstthe mixer TR2 provides considerable conversion gain.

In Figure 6.21(b) a similar technique is used but here the transistor TR1provides matched gain to the LO and r.f. frequencies up to a much higherfrequency. Again LO to r.f. isolation is of the order of 20 dB up to 8 GHzor so and mixing products in the signal adder are small being primarilydetermined by the fact that the device is biased as an amplifier ratherthan as a mixer and that the LO power can be kept low since the FETitself will give LO gains of 10 dB or so up to 10 GHz. Again the signaland LO frequencies are mixed in the single gate FET TR2 having passedthrough the interstage matching network.

Figure 6.2l(c) shows another common gate connection where the LO isinjected into the gate of FET TR2 which acts as a switch. This circuitconfiguration works well up to 4 GHz or so.

LO drives for all these circuit techniques is optimum around a fewmilliwatts for 300/jm gate width FETS (Greenhalgh, private communi-cation) providing noise figures of the order of 6 dB at 4 GHz for thecircuits shown in Figure 6.21(a) and (c).

The circuit of Figure 6.21(b) has demonstrated noise figures as low as 3dB with conversion gains of 15 dB at signal frequencies of 4 GHz withan IF frequency of 200 MHz.

FET Mixers 315

6.7 The Dual Gate Mixer

The dual gate FET has been shown to be a simple but effective micro-wave mixer (Cripps et al, 1979). The local oscillator signal is applied tothe second gate via a suitable matching network and modulates thetransconductance measured at gate 1 at the local oscillator frequency.Mixing action is therefore obtained, analogous to that of the single gatemixer, already analyzed with the signal applied to gate 1 and the IFextracted via suitable filtering from the drain, as shown in Figure 6.22.The way in which the second gate voltage varies the transconductancecan be seen from Figure 6.23 which shows the IDS-VGIS curves as afunction of VG2S, the second gate to source voltage. It may also beappreciated from Figure 6.23 that a considerable change in gm occursfor relatively small changes in VG2S especially when VG2S is between zeroand the maximum forward diode voltage (approximately 0.5V). Thisreflects itself in the ability of the dual gate FET mixer to give highconversion gains even when the local oscillator power is very low.

Figure 6.24 shows the conversion gain of a 30Qam gate width dual-gateFET mixer as a function of LO drive in a single ended configurationindicating that LO power as low as 100/* W gives 10 dB conversion gain.

Figure 6.25 shows a typical gain and noise figure variation with LOpower for a simple dual gate mixer where VG2S = OV. For this case the,optimum LO power drive was approximately 10 dBm in order to obtainthe best DSB noise figure of 6.5 dB (Cripps et al, 1977).

The best result achieved to date has been an 8.0 dB noise figure with 14dB conversion gain at 8 GHz with a 0.5/zm gate length dual gate FET(Cripps et al, private communication). The IF amplifier noise figure forthis mixer was 3 dB. The mixer circuit used a balanced arrangementwith a 150 MHz IF.

Assuming the r.f. input signal to be input at gate 1 of the FET then thedevice may be described as an amplifying common source MESFETconnected in series with a common source (modulating) MESFET. Thetransconductance of the whole FET is modulated by the local oscillatorvoltage applied to gate 2. Figure 6.26 shows the mixing mechanismwhere in Figure 6.26(b) the conversion transconductance gi is calculatedby the Fourier analysis of gm(t) from Figure 6.26(a). For the particularFET concerned in these calculations (Stahlmann et al, 1979) the opti-mum conversion gain occurs at a VG2S of — 1.5V with peak LO voltage of2.35V (the FET having a l//m gate 1 length, 2/um gate 2 length and 200jumgate width).


-3

Gate 2—source voltage+ 0 . 5 /

-2 -1 C

Gate 1 —source voltage (volts)

70

60

50

40

30

20

10

0)

1

Dra

in c

urre

nt

Figure 6.23 Transconductance Control of Dual Gate GaAs FET bySecond Gate Bias

CD

•a

30

20

10

o -10O

-20

-30-20 -16 -12 -8 -4

LO. power level, dBm

VDS = 5VVgis = -0 .5V

Figure 6.24 Conversion Gain of a Dual-gate FET Mixer as aFunction ofLO Power and Second Gate Bias

FET Mixers 317

mig

ure

ois

efer

sion

gai

n a

nd n

i

15

10

5

0

ti\\\\

/

0 5

VG,s =

Vc,?s =

I.F. =

= -3V

= ov30MHz

Signal = 10GHz

.^ *""""

10 15 20Local oscillator power (mW)

^-Gain

^-N.F.

i

25

Figure 6.25 Conversion Gain and Noise Figure of Dual-Gate FETMixer

6.8 Image Rejection Mixers

A mixer which provides rejection of signals on the image channel hasimportant applications in microwave systems, especially where lowintermediate frequencies are used. With the increasing use of GaAsFET preamplifiers to realize low noise front-ends image rejection notonly rejects interfering signals but amplifier noise at the image fre-quency as well.

The development of the single ended mixer into an image rejectionconfiguration is shown in Figure 6.27.

The principle of the image rejection mixer circuit is well established(Weaver, 1956) where a balanced arrangement is used in which the twosignal gates (the gate Ts of the dual gate FETs) are fed from a broadband90° hybrid coupler and the two local oscillator gates (the gate 2's) areexcited in phase by the signals from a power divider. It can readily beshown that the IF output at the drain of one of the FETs either leads orlags that of the other FET output by 90° depending on whether the signalis in the wanted band or in the image channel. The signal and imagechannels appear on separate output ports of a 90° IF hybrid circuit, thusadding a further 90° phase shift between the two IF signals from the


WL0(t)

= 9™ + 2 ^ 9MKejkwLOt-co

= 1.14V

, Vo = 0.28V

1 0 - 1 - 2 - 3

VC2S.Volts

Figure 6.26 Dual-Gate FET Mixing Mechanism

Signal

3dB90°Hybrid

In-phasepowersplitter

Low-passfilter

High-passfilter

Low-passfilter

High-passfilter

90° I.F.Hybrid

Uppersideband

Figure 6.27 Image Rejection Mixer Using Two Dual-Gate FETs

FET Mixers 319

mixer FETS. In addition to providing image rejection, the circuit ofFigure 6.27 also has a low input VSWR due to the balanced arrangementprovided that symmetry is maintained at the two FETS. The balancedarrangement also increases the power handling capability of the mixerby 3 dB. Cripps (1979) has reported the results of an X-band imagerejection mixer built in microstrip on an alumina substrate, where theinput 90° quadrature coupler was of the Lange type (Lange, 1979) andthe local oscillator inputs were fed from an in-phase Wilkinson powerdivider (Wilkinson, 1960). Bias and IF output networks were low-passfilter structures incorporating resistive elements to aid stability. Figure6.28(a) shows the conversion gain for the upper and lower sidebandswith no attempt to r.f. match the dual-gate FETS.

The 30 MHz IF circuit on the drain of each FET consisted of a tappedparallel tuned circuit feeding the inputs of a commercial TO-5 packaged90° IF hybrid. In the tuned state, conversion gains of 10 dB have beenreported with image rejection of 20 dB (Figure 6.28(b)). Input VSWR wasalways better than 2:1 over the 8-12 GHz band being determinedprimarily by the Lange coupler. Noise figures of 8.5 dB have beenmeasured with an IF of 30 MHz and 7.5 dB with an IF of 150 MHz.

9.7 9fl 9SFrequency (GHz)

10.2I/P Frequency (GHz)

10.3

Figure 6.28 (a). Conversion Gain of Dual-Gate IR Mixer without RFtuning (b). Conversion Gain of Dual-Gate IR Mixer with RF tuning.


6.9 Frequency Up-Conversion Using Dual-gate FETs

The dual gate FET can be conveniently used as an up-converter wherethe IF signal is applied to gate 2 and the LO to the signal gate 1.

Figure 6.29 (Tsai et al, 1979) shows the bandwidth and conversion gainattainable in a single-ended up-converter designed to operate in the 7to 8 GHz communication band. LO and lower sideband suppression canbe produced by the frequency selectivity of the output matching network.The typical saturated output level in the 7 to 8 GHz band is 8 dBm usinga dual gate FET having a gate length of 1/jm and width of 50Qam. Sincethe dual-gate up-converter has gain it can eliminate up to two stages ofamplification in a normal heterodyne transmitter chain at these fre-quencies.

6.10 Frequency Multiplication

Both single and dual-gated FETs are finding increasing applications inthe area of frequency multipliers where the major advantage greater

7.0 7.1 7.2 7.3 7.4 7.5

Output frequency, GHz

7.6 7.7

Figure 6.29 Gain Response of 1.7/7.5 GHz Up-Converter usingDual-Gate GaAs FET (Tsai et al, 1979)

FET Mixers 321

than 100% efficiency-results in the replacement of complicated varactordiode chains with their resultant pre-and post-amplification needs.

Although the dual-gate FET has been used extensively as a frequencymultiplier, the single gate device has also received considerable atten-tion and is a rather simpler device to understand in this mode ofoperation. Although the single gated FET has been used as a tripler,quadrupler and quintupler the device has been used most extensivelyas an efficient doubler. Both Gopinath (1982) and Rauscher (1983) havepublished papers dealing with theoretical derivations of conversion gainas a function of FET operating bias, fundamental signal level and circuitconfiguration. Optimum conversion gain and compression point notonly depend on the input fundamental matching circuit, the outputharmonic matching circuit but also on the fundamental frequencytermination at the output and the effect of internal feedback in the FETitself. The latter is particularly important as the frequency of thewanted harmonic approaches the fr of the FET. In contrast to theoperation of power amplifiers and oscillators frequency multiplicationdepends on nonlinear device behavior as its basis. Device-circuit inter-action not only at the fundamental frequency but also at its harmonicsis very important. Due to the number of variables involved it is imprac-tical to attempt to provide experimentally general design principles for,even, doublers. Large-signal simulations are therefore normally em-ployed to aid the analysis of such circuits.

Efficient doubling can be produced by using the FET as a half-waverectifier. Such rectification is produced if the FET is biased either nearpinch-off or close to saturation (i.e. forward conduction). Measurementsby a number of different workers using different FETs have shown thateither of these two bias conditions is capable of giving superior conver-sion gain. Close to pinch-off is often used because it also tends to producebest conversion efficiency since the FET power dissipation is minimized.Rauscher (1983) has considered only the voltage controlled currentgenerator and the output conductance as requiring full non-lineartreatment (Figure 6.30) (Willing, 1978). The non-linearities associatedwith the gate-to-source capacitance and resistance and the gate-to-drainfeedback capacitance are represented by large-signal time-averagedvalues for their respective voltage-dependent values. The gate-to-sourceand gate-to drain diodes in Figure 6.30 are accounted for by limitingtheir positive voltage swings to 0.7 volt. In order to produce non-linearmodels for the FET to be used in the multiplier it is necessary to measureS-parameters at several bias levels give.


Figure 6.30 GaAs MESFETEquivalent Circuit

The output non-linear elements can be considered to consist of a con-trolled current source whose current iGOM(t) can be expressed as a timeinvariant function of the voltage Vi(t) across the gate-to-source capaci-tance and V2(t) across the output resistance as well as the time-delay rbetween gate and drain.

The function iGOM(t) can be approximated by the expression:

where VTL, O is the intrinsic drain-to-source bias voltage. Rauscher hassubstituted empirical relationships for the terms iA(Vi) and gA(Vi).These are:

and

The expression for iA(Vi) accounts for the major part of the Vi depend-ence of iGom where Io is the value of IDSS at the nominal drain-source

FET Mixers 323

voltage and the coefficients Ii, and h are obtained by curve fitting toexperimental data. The expression for gA(Vi) approximates the vari-ations in output conductance with bias, Go being the small-signal valueof the conductance under nominal bias conditions. Vp is the pinch-offvoltage defined in the normal way and G0Sub is the substrate leakageconductance.

The most usual form of FET doubler is the common source circuit shownin Figure 6.31. A modified harmonic balance technique can be used toanalyze such a configuration whereby the overall circuit can be dividedinto linear and non-linear sections. This allows most of the circuit to betreated in the frequency domain whilst time-domain analysis is used forthe non-linear portion. From the above the nonlinear portion onlyinvolves the controlled current generator-the solution to the problembeing found by forcing coincidence between the current i2(t) of the linearsection and the current iGOM(t) Of the non-linear section (Figure 6.31).Coincidence is found by allowing the Fourier components of V2(t) to bevaried during the analysis.

The three most important parameters affecting doubler performance inthe circuit of Figure 6.31 are:

(a) the fundamental frequency drive level;

(b) the FET output terminating impedance at the fundamentalfrequency, Zi/fo); and

(c) the FET input terminating impedance at the second harmonic,Zi(2f0).

(optional f0 and 2f0

external feedback)

Inputcouplingnetwork

Generatorfor fft

I I

Outputcouplingnetwork

Loadfor 2fo

Figure 6.31 GaAs MESFET Frequency Doubler


This is, of course, in addition to optimally matching the input and outputof the FET to the fundamental and second harmonic respectively.

For FETs operating at second harmonics which are close to the fradditional external gate-to-drain feedback can counteract the deviceparasitic feedback.

Figure 6.32, for Sxample, shows the conversion gain of a 0.5 micron longgated FET (with a gate width of 250 microns) as a function of fundamen-tal frequency reactive load impedance, Ziifo) and second harmonicoutput power at an input frequency of 15 GHz. Reactance is expressedas a function j50.tan^ ohms where 0 can be visualized as the electricallength of a short-circuited stub at the FET output. The FET's input isassumed to have a short-circuit at the second harmonic.

As can be observed from Figure 6.32 the conversion gain is highlydependent on the fundamental load reactance. This dependence is infact linear in nature and is linked to parasitic feedback within thetransistor. Parasitic feedback at the second harmonic becomes promi-nent as the harmonic frequency exceeds the normal operating frequency

CD

cou

y ZTL «O) - J 50n-tan (6). / ZT,(2fo) = 0

-10 0 102nd harmonic output power, dBm

Figure 6.32 Simulated Large-Signal Conversion Gain as a Functionof Fundamental Frequency Load Reactance ZTL(fo) and Second

FET Mixers

CD

n g

ain

'sio

ver

con

]DU

2

1

-1

-2

-3

~4.2*-5V)<b

cn

Lar

-6

-7

fo=18GHz\ ZTL(fo) = j50n-tan(138.

/ X.

j " -j * \

- \- \- J_ _

i% Dissipation in load

Loss due to negativefeedback

_i i i i i i i i i

-OO-120-50-20 0 20 50 120 ooReactance Xi|(2f0), OHMS

2°)

0.7

CL6U.D0.5

OA

0.3

0.2

0.10

325

coo

ssip

uco

a"D

CM

>

Bcc

Figure 6.33 Simulated Maximum Achievable Large-SignalConversion Gain and Corresponding Components of Second HarmonicPower Dissipation as Functions of Second Harmonic InputTerminating Reactance XTl(2f0)

of the transistor. Figure 6.33 shows conversion gain plotted as a functionof input reactance) Xi(2f0). An input frequency of 18 GHz has beenchosen to accentuate the rapid change in conversion gain as the reac-tance is altered. The effect of the second harmonic input reactance onconversion gain is lessened as the frequency is lowered. This is shownin Figure 6.34 where the maximum achievable conversion gain is plottedas a function of second-harmonic input reactance for signals at 13, 15and 18 GHz. Even at 13 GHz the feedback effect is quite noticeable. Byincorporating feedback of the proper amplitude and phase it is possibleto increase conversion gain by canceling out destructive intrinsic feed-back effects.

Rauscher has used such theories to design a 15 to 30 GHz doubler in awaveguide configuration using a 0.5 micron FET resulting in the circuitof Figure 6.35(a) and the experimental results of Figure 6.35(b). The


5

4

co 3

c 2

a 1§ 0

1 - 11 - 2- - 3o

I'5

P-6a-1 -7

-8

-

\ : = = — =} fo=13GHz, 6 = 147.4°VI ,} fo = 15GHz, 0-143.5°

= : = : = : } fo«18GHz, 0= 138.2°

ZTL(fo) = j5OO-tan(0)

i i i i I i i i i-oc-120-50-20 0 20 50 120 oo

Reactance XTi (2 fJ , OHMS

Figure 6.34 Simulated Maximum Achievable Large-SignalConversion Gain as a Function of Second Harmonic InputTerminating Reactance XTl(2f0) for Incident Signals at 13 GHz, 15GHz, and 18 GHz. (The three bottom curves represent doublerperformance without additional external feedback, whereas the threestraight lines indicate achievable performance with appropriateexternal feedback applied to elininate second harmonic parasiticfeedback losses.)

circuit contains a quarter wave (at 30 GHz) open-circuited stub, L.6 atthe FET input.

At lower frequencies, 5 to 10 GHz doublers with conversion gains of 5dB have been produced using 1 micron gate-length FETs (Swift, 1984).The conversion gain versus gate-to-source bias of this multiplier isshown in Figure 6.36.

6.11 Conclusions

This chapter has dealt with the subject of single and dual gate FETsused in frequency conversion applications. It has been shown (Loriouet al, 1976) that both types of MESFET suffer from 1/f noise contribu-tions for IFs much below a few hundred megahertz. The general device

FET Mixers 327

Microstrip lines

o—CZZHIInput(500)

//////

Gatebias

77777

Draind bias

Waveguideoutput

77777"

7777T

Cg

Measured

fo=15GHz

4 6 8 10Input power. dBm

12

Figure 6.35 (a). Achematic Circuit Diagram of 5 to 30 GHzFrequency Doubler (b). Measured and Predicted Performance of 15 to30 GHz MESFET Frequency Doubler

requirements for FETs to be used in mixer and other conversion circuitsare very similar to those requirements for low noise amplifiers. Re-cently, considerable theoretical work has been achieved to explain ob-served FET mixer noise figure performances with the frequency of the


6

5

4

3

CD

c-2

o

1

0

-1

-2

-

' J

r

-1.00

-

-

-1.25

\m^ ^ v i

\ \\\\\\\\\

1 1 1

-1.50 -1.75 -2.00Vg(V)

s.

'-2.2

\\\\

\

V PIN

\^3dBm

\5dBm

\

. \2dBm

5 \'"1dBm

OdBm

Figure 6.36 Conversion Gain of Doubter as a Function of Gate BiasVoltage and Input Fundamental Signal Level

IF and the signal LO and IF loads. Recent studies into the signal, LO,IF, image and sum frequency terminations have given an insight intothe optimum conditions for conversion gain especially with single gateFET mixers. Since the matching of the second gate of a dual gate FETcan be difficult over relatively broad bandwidths, as it is in the amplifiercase discussed in Chapter 2, the use of dual-gate FETs in mixers,although producing simple injection of LO and signal frequencies, hasled to other FET based circuits being realized particularly at the lowerfrequencies (Van Tuyl, 1980; Suffolk et al, 1980; Ablassmeier, et al, 1980).

FET Mixers 329

Dual-gate FETs are now receiving considerable attention as efficientup-converters and multipliers as well as in self-oscillating mixer circuits(Stahlmann et al, 1979).

6.12 Bibliography

Ablassmeier, U., Kellner, W. and Kniepkamp, H. GaAs FET up-converterfor TV tuner. IEEE Transactions on Electron Devices, Vol. ED-27, No.6, June 1980,pp.ll56-1159.

Begemann, G. and Hecht, A. The conversion gain and stability of MES-FET gate mixers. Conference Proceedings of the 9th European Micro-wave Conference, Brighton, 1979, pp.316-320.

Begemann, G, and Jacob, A. Conversion gain of MESFET drain mixers.Electronics Letters, 30th August 1979, Vol. 15, No. 18, pp.567-568.

Brewitt-Taylor, C.R., Robson, P.N. and Sitch, J.E. Noise figure of MES-FETS. IEE Proceedings Part I, Solid State and Electron Devices, Vol.127, pp. 1-8, February 1980.

Cripps, S.C., Nielsen, O., Parker, D. and Turner, J.A, An experimentalevaluation of X-band GaAs FET mixers using single and dual-gatedevices. 1977 IEEE MTT-S, International Microwave Symposium Di-gest, San Diego, June 1977, pp.285-287.

Cripps, S.C, et al. An experimental evaluation of X-band mixers usingdual gate GaAs MESFETs. Proceedings of the 7th European MicrowaveConference, Copenhagen, 1977, p.101.

Cripps, S.C, Nielsen, 0. and Cockrill, J. An X-band dual-gate MESFETimage rejection mixer. 1978 IEEE MTT-S, International MicrowaveSymposium Digest, Ottawa, Canada, June 1979, pp.300-302.

Cripps, S.C. The All FET front end-a step closer to reality. Microwaves,October 1978, Vol. 17, No. 10, pp.52-58.

Cripps, S.C. and Vudali, T.-private communications, 1979.

Friis, H.T. Noise figure of radio receivers, Proc. I.R.E. pp.419-422 July1944.

Fukui, H. Design of microwave MESFETs for broadband low-noiseamplifiers. IEEE Trans. Microwave Theory and Techniques, Vol. MTT-27, No. 7, July 1979, pp.643-650.


Gopinath, A. and Rankin, J.B. Single-gate MESFET frequency doublers.IEEE Trans. Microwave Theory and Techniques, Vol. MTT-30,pp.869875, June 1982.

Greenhalgh, S.G.-private communication. 1980.

Harrop, P, and Claasen, T.A.C.M. Modelling of a FET mixer. ElectronicsLetters, 8th June 1978, Vol. 14, No. 12, pp.369-370.

Harrop, P. FET mixers and their use in low noise front ends. ColloquiumDigest on low noise microwave front ends-systems needs and componentcapabilities, IEE Savoy Place, London, March 1979.

Lange, J, Integrated stripline quadrature hybrids, IEEE Trans. MTT,Vol. 17, Dec. 1979, pp.1150-1151.

Loriou, B. and Leost, J.C. GaAs FET mixer operation with high interme-diate frequencies. Electronics Letters, 22nd July 1976, Vol. 12, No. 15,pp.373-375.

Pan, J.J, Wideband MESFET microwave frequency multiplier. 1978IEEE MTT-S International Microwave Symposium Digest, Ottawa, Can-ada, June 1978, pp.306-308.

Pengelly, R.S, GaAs monolithic microwave circuits for phased-arrayapplications, IEE Proc. Vol. 127, Part F, No. 4, August 1980, pp.301-311.

Pucel, R.A., Bera, R, and Masse, D. An evaluation of GaAs FET oscilla-tors and mixers for integrated front-end applications. IEEE ISSCCDigest of Technical Papers, p.62, February 1975.

Pucel, R.A., Masse, D. and Bera, R. Performance of GaAs MESFETmixers at X-band. IEEE Transactions on Microwave Theory and Tech-niques, Vol. MTT-24, No. 6, June 1976, pp.351-360.

Rauscher, C. High-frequency doubler operation of GaAs field-effect tran-sistors. IEEE Trans, on Microwave Theory and Techniques, Vol. MTT-31, No. 6, pp.462-472, June 1983.

Sitch, J.E, and Robson, P.N. The performance of field-effect transistorsas microwave mixers. Proceedings of the IEEE, Vol. 61, p.399,1973.

Stahlmann, R., Tsironis, C, Pouse, F. and Beneking, H. Dual-gate MES-FET self-oscillating X-band mixers. Electronics Letters, 16th August1979, Vol. 13, No. 17, pp.524-526.

Statz, H., Haus, H. and Pucel, R. Noise characteristics of galliumarsenide field effect transistors. IEEE Trans. Electron Devices, Vol.ED-21, pp.549-562, September 1974.

FET Mixers 331

Suffolk, J.R., Cockrill, J.R., Pengelly, R.S. and Turner, J.A. An S-bandimage rejection receiver using monolithic GaAs circuits. Paper 27, Ab-stracts of the 1980 GaAs IC Symposium, November 1980, Las Vegas,U.S.A.

Swift, J.S, private communication, 1984.

Tie, G.K. and Aitchison, C.S.-private communications 1980.

Tie, G.K. and Aitchison, C.S. Noise figure and associated conversion gainof a microwave MESFET gate mixer. Proceedings of the 13th EuropeanMicrowave Conference, pp.579-584,1983.

Tsai, W.C., Paik, S.F. and Hewitt, B.S. Switching and frequency conver-sion using dual-gate FETs. Proceedings of the 9th European MicrowaveConference, 1979, Brighton, pp.311-315.

Van Tuyl, R. A monolithic GaAs FET signal generation chip. Digest ofTechnical Papers, ISSCC, San Francisco, Feb. 1980, pp. 118-119.

Weaver, D.K. A third method of generation and detection of SSB signals.Proc. IRE, pp.1703-1705, December 1956.

Wilkinson, E.J. An N-way hybrid Power divider. I.R.E, Trans. MTT,V6LMTT-8, Jan. 1960, pp.116-118.

Willing, H.A., Rauscher, C. and De Santis, P. A technique for predictinglarge signal performance of a GaAs MESFET. IEEE Trans, on Micro-wave Theory and Techniques, Vol. MTT-26, pp.1017-1023, December1978.

GaAs FET Oscillators

7.1 Introduction

The 1960's saw the development of first practical microwave solid statesources such as transferred-electron device and IMPATT diode oscilla-tors and the extension of bipolar transistor oscillators to microwavefrequencies. The development of GaAs MESFET devices in the early70's has significantly influenced the choice a system designer has tomake on the selection of a microwave power source.

The transferred electron or the Gunn oscillator, which has been themainstay for low power solid-state oscillator applications, suffers fromtwo main drawbacks. One is the low d.c. to r.f. conversion efficiency andthe other is the threshold current requirement, both of these resultingin higher d.c. input power consumption. Low operating efficiency alsomeans that the Gunn device works at high temperatures, unless the heatcan be removed effectively. The GaAs FET oscillator provides a higherd.c. to r.f. conversion efficiency (>10%) and does not have any thresholdcurrent requirements. Being a three terminal structure the GaAs FETis an extremely versatile active oscillator circuit element and by makinguse of this feature it is possible to control the behavior of the oscillatorto provide modulation, compensation and stabilization etc.

The GaAs FET oscillator activity has received much attention in therecent years. High efficiency fixed frequency oscillators have beenreported in the literature for frequencies up to 25 GHz and beyond.Electronic tuning of FET oscillators by YIG resonators and varactordiodes has been extensively researched. As most GaAs FET oscillatorsare realized in low Q microstrip circuits, efforts have also been directedtowards improving their close to carrier noise and temperature stabilityby employing stabilization techniques. Other applications like mono-lithic oscillators and pulsed RF oscillators etc. have also been reported.

In this chapter GaAs FET microwave oscillator design philosophy isreviewed, steps leading to the design of a free running oscillator areindicated and their reported performance reviewed. Techniques forfrequency stabilization of these oscillators using dielectric resonators


are reviewed. Design criteria for electronically tunable oscillators arepresented and performance capabilities outlined. Finally some novelGaAs FET oscillator circuits are described.

7.2 Induced Negative Resistance

For solid state devices like the tunnel, Gunn and IMPATT diode, theapplication of appropriate d.c. bias is generally sufficient to producenegative resistance at the device terminals. This negative resistancecondition exists up to microwave frequencies and by suitably couplingan external circuit to the device it is possible to deliver useful r.f. powerto the load. These devices are thus inherent negative resistance devices.Broadly speaking, the effort of the circuit designer is mainly directedtowards coupling the required power level to the load over the desiredfrequency range.

Application of d.c. bias to the bipolar or the field-effect transistor, on theother hand, does not generally result in the negative resistance condi-tion. This condition has, therefore, to be induced in these devices so thatuseful power at microwave frequencies can be obtained. The frequencyrange over which the inherent negative resistance or conductance de-vices exhibit the condition is determined by the physical mechanisms inthe device. For induced negative resistance devices it is influenced bythe chosen circuit topology.

For an active two port device like the GaAs FET, negative resistancecondition can be induced at one or both the device ports by suitablycoupling the input and output ports of the device. There are two basicfeedback arrangements as shown in Figure 7.1 for a general threeterminal device. The device may be in common source, gate or drainarrangement. In the series feedback arrangement the feedback elementis the common current carrying element between the device input andoutput ports. For the parallel feedback arrangement it is the voltagetransforming element between the two ports. A combination of seriesand shunt feedback elements and higher order feedback elements canalso be envisaged (Figure 7.2).

These feedback elements, which are usually reactive, can take the formof lumped or distributed components. In practice, however, an inductiveparallel feedback element requires a d.c. block which would introduceproblems due to its associated parasitic components at higher frequen-cies. Also because of d.c. biasing or grounding requirements it is usuallydifficult to have a capacitive series feedback arrangement.

GaAs FET Oscillators 335

Series

Parallel

„ Active- •1 device

Feedbackelement

Feedback element

Active- • 1 device 2«

Figure 7.1 Basic Feedback Arrangements

Figure 7.2 Higher Order Feedback Arrangement


7.3 S-Parameter Mapping

The influence of feedback on the behavior of the transistor can best beevaluated by mapping techniques. Bodway's (1968) general analysis isrelevant here, Consider a transistor as a general three port network withits three terminals and a common ground plane forming the three ports.

If two device ports are terminated in the characteristic impedance Zoand the third port in an arbitrary feedback impedance Zf, the configura-tion is equivalent to the series feedback case of Figure 7.3. The two portS-parameters can be obtained in terms of the three port parameters andthe feedback impedance Zf. In the special case when the common loadimpedance Zf is zero one obtains the conventional S-parameters.

A further transformation from these S-parameters (referred to a com-mon terminal) would result in a 3 port S-parameter matrix in which theports are referred to each other. In the special case when two terminalsare referred to each other in an impedance Zf', the configuration isequivalent to a shunt feedback case (Figure 7.4). Again, the two portS-parameters can be obtained in terms of the three port S-parametersand the impedance Zf'. The conventional two port S-parameters areobtained when the impedance Zf' is infinite.

The two port S-parameters with feedback are of the same general formas for terminated two port networks (see Chap. 5).

• *1 3 _ •

//// ////

Zo

IFigure 7.3 Series Feedback as a Special Case of a Three PortNetwork Representation


Figure 7.4 Parallel Feedback Case Obtained from Transformation ofFigure 7.3

1c

r

7.1

where a, b and c are related to the three port S-parameters and arecomplex in nature. The parameter r is the reflection coefficient corre-sponding to the feedback impedance referred to the characteristic im-pedance.

Equation 7.1 is a standard equation in complex variable theory and therelationship between r and s can be written in a bilinear form

a + r(b—ac)l^Vc 7.2

This form of equation is similar to Equation 5.12 for amplifiers whichwas used to plot constant gain circles as functions of load or sourceimpedance. Similar techniques here would result in constant gaincircles as a function of feedback impedance. However, the alternativetechnique of handling Equation 7.2 is much more meaningful here. Inthis the r-plane is mapped onto the s-plane. From the bilinear propertyof Equation 7.2, circles on the r-plane map onto circles on the s-plane.This means that the Smith Chart for the r-plane can be mapped ontothe s-plane giving both the magnitude and phase of s for each value ofr (Smith, 1995).


For a general passive feedback impedance the resistive part may varyfrom 0 to oo and the reactive part from ± jO to ± joo. These values arebounded by the Smith Chart which merely represents magnitude andphase of the reflection coefficient. Thus the transistor S-parameterswith feedback form the outline of a distorted Smith Chart due to thebilinear property.

This impedance mapping can be done by converting the transistor twoport S-parameters to Y or Z parameters and incorporating the feedbackimmitance. It can also be done by using the mapping function routinein COMPACT (Users Manual). Figures 7.5 and 7.6 show the commongate series and common source parallel feedback impedance mappedonto the S-parameter plane at 10 GHz for a Plessey GAT4 transistorwith 1 X 300jum gate geometry.

It can be seen that for series inductive feedback the magnitudes of bothSn and S22 are greater than unity and can thus induce negativeresistance conditions at both the input and output ports. The capacitive

/

\ i\ /

1\\\\

/jo.5/ ^-j-

w

.

/1 \

X

yf TA1»0.!

^ ^

I\I

/ \iqSi,max|= 1.7 \

\ /^ \ /

%-5i/j/o.5j

t/

/

S D

I

J/jR + jX

If = 10GHz

Figure 7.5 Grounded Gate with Series Feedback


11

0.5JT

/

11

\\

/// |S22max|=

\f

-i5yJ5V

V

i

^ \

S,,

0.5

2.16

—-—^I\\A/ ris\-5f

--—

*f5i

CO

\

\

R = jX

1o

f = 10GHz

—o2

L)

s

Figure 7.6 Grounded Source with Parallel Feedback

parallel feedback condition gives rise to negative resistance conditionsat the output port only because only | S221 is greater than unity.

7.4 Oscillator Design

The GaAs FET can be used in common source, common gate or commondrain configuration for oscillator applications. It is first necessary toinduced negative resistance condition by introducing feedback elements.Impedance mapping techniques can be adopted to study the effect offeedback on the input and output reflection coefficients of the circuit.The particular configuration chosen should be capable of providingnegative resistance (i.e. | Su | or | S221 > 1) conditions at one or both thedevice ports over the desired frequency range. If the input port is nowterminated in an impedance so as to maximize the magnitude of thereflection coefficient at the output port, the circuit can be reduced to aone port network with negative resistance -RD(CO) and its associatedreactance +jXd(co) which are, in general, frequency and amplitude de-pendent.

If the output port is now terminated in an impedance ZL((D) = RL(G>) +JXL(<W), which includes the matching network and the load, then foroscillations to occur the following, conditions must be satisfied.


The total resistance

R((o) = -RD(a)) + RL(co)<0 7.3

and the total reactance,

X(a))=XD(co)+XL(a)) = 0 7.4

In general, Equation 7.3 can be satisfied for a number of frequencies butsustained steady-state oscillations are possible if and only if the stabilitycriteria (Edson, 1953; Kurokawa, 1973) are also satisfied, which statesthat

d R{co) d X(co)— — > 0 and —>0 75

d(O d(O

Equation 7.3 establishes the potential for oscillations. Initially foroscillations to start from noise there should be a net negative resistancein the circuit. As the oscillation amplitude builds up the negativeresistance — RD diminishes and under steady state conditions becomesequal to the load resistance RL. The oscillation frequency is determinedby the zero reactance condition of Equation 7.4. Equations 7.3 to 7.5thus comprise the necessary and sufficient conditions for steady stateoscillations.

The conditions expressed by Equations 7.3 to 7.5 apply to both smalland large signal operations. However, in order to apply these conditionsto large signal operation, it would be necessary to ascertain the depend-ence of - R D + JXD on the oscillation amplitude. This information is noteasily obtainable due to nonlinear effects under large signal conditionsand therefore experimental measurements are necessary.

Calculations on the basis of small signal S-parameters usually providegood agreement between the theoretical and experimental oscillatorfrequencies. These are, however, unable to predict the output powerlevel and the conversion efficiency of the oscillator.

The alternative approach in which the input port of the transistor isconsidered, with the output port terminated in the load and matchingnetwork, has also been analyzed. This technique is mainly applied tothe design of tunable oscillators in which the tuning elements like theYIG resonator, varactor diode etc. are coupled to the input port. Krowne(1977) has presented an analysis based on the incident and reflectedpower at the input port. For a unit incident power on port 1, | Sn' | 2 isreflected back (where prime denotes the modified S-parameters where


feedback has been taken into account). If | Sn' | is greater than unitythen the reflected power is higher than the incident power. If a losslesscircuit element or cavity with reflection coefficient magnitude | Fr | isconnected to the input port (Figure 7.7) then each round trip sees| Fr |

21 Sn' | 2 power returning to the active device port. For oscillationsto build up from noise this quantity must exceed unity or

|rr||-v|>7 7.6

Also the first round trip reflected power | l+rrSn' | 2 is maximized when

n = 0,l,2,3... 7.7

where 0r and 0n' are the phase angles associated with Tr and Sn'.

In general, | Fr | which corresponds to a resonator or a reactive termi-nation with negligibly small losses will be nearly equal to unity andEquation 7.6 can be reduced to

\Su'\>l 7.8

The small signal S-parameters of the device may be used to establishthis condition but once oscillations build up, due to large signal operationthe steady state condition becomes

\SII'\LS=1 7 9

For broadband tunable oscillators, the feedback arrangement is selectedsuch that Equation 7.8 is satisfied over the desired frequency range. Forfixed frequency oscillator applications the topology is selected to maxi-

Termination

rr

H ejer

Active2 port withfeedback

[s]

Matchingnetwork Load

Figure 7.7 Oscillator Schematic


mize | Sn' | at the desired frequency. This technique is also applicablewhen the output port is terminated in impedances other than thecharacteristic impedance. This merely modifies Sn' in accordance withthe standard equation.

7.10

where rm represents the reflection coefficient corresponding to theoutput matching network.

It has been seen that having incorporated the necessary feedbackelements to the basic transistor, the input or the output port has to beterminated to reduce it to an equivalent two-terminal negative resis-tance device. The input port is generally terminated for fixed frequencyoscillator applications and the output port termination is generally usedfor tunable oscillators. The aim in both cases is to ensure that | Sn' | or| S22' I is greater than unity. Golio and Krowne (1978) analyzed thecondition when the output port of the transistor with feedback isterminated and the terminating reflection coefficient values whichensure | Sn' | > 1 were investigated.

A general analysis applicable to either the input or the output port withthe other terminated can be enunciated. The terminated reflectioncoefficient at one port with the other port terminated in reflectioncoefficient TR can be written as

s r v ^ ji»u* - * u ^ j ^ f 7 . 1 1

TK JJ

where i = 1, j = 2 and K = corresponds to the input port with the outputport terminated in Ti and i = 2, j = 1 and K = s corresponds to the outputport with the input port terminated in Fs. Equation 7.11 can be handledby computer analysis techniques but it would be useful to get somephysical insight. Rewriting

SiiT = Sii'+AjK 7.12

The magnitude of SuT is determined by the magnitude and phase of Su'and AjK-Su' depends upon the two port network, characteristics whileAJK is dependent upon the terminating reflection coefficient FK which isthe controllable parameter. Thus for a given magnitude of AJK, the


magnitude of SiiT is greatest when the phase angles of AJK and Su' areequal. This is the condition of phase addition. Also from Equation 7.11AJK-*00 when FKSJJ' = 1 resulting in the largest possible value of | SiiT |Additionally, | AJK | = 0 when | FK | = 0 which corresponds to the condi-tion when the jj port is terminated in the characteristic impedance.These two points thus represent the end points of the phase additioncurve and the point

is called the limiting match for a given frequency.

For most practical applications the reflection coefficient FK correspondsto passive impedance elements only. If | Sii' | is less than unity, thenthere is a minimum value of | AJK | corresponding to some FK beyondwhich | SuT | is greater than unity. This satisfies the relationship| AJK | min = 1 - | Sii' |. On the other hand if | Sii'l > 1 this value is zerocorresponding to F^ = 0 and the device feedback itself is sufficient toproduce a negative resistance condition.

Now considering the terminated port jj, if | Sjj' | > 1 then the limitingcondition in which AJK-* °° corresponds to a FK value realizable by passiveelements. If, on the other hand, | Sjj' | < 1 then the | FK | is greater thanunity for the limiting condition of | AJK | - °° Under this condition thepoint at which | FK | = 1 on the inphase addition curve gives the upperlimit of | AJK | realizable by passive elements.

Equation 7.11 can also be used to determine FK contours for constantSiiT magnitude and phase (Golio and Kroxme, 1978). This informationprovides the designer with the overall picture of the effect of theterminating impedance.

The form of Equation 7.11 is similar to Equation 7.1. Thus it is alsopossible to use mapping techniques to study the effect of terminatingreflection coefficient FK on the value of SuT in manners similar to thoseconsidered in Section 3.

7.4.1 Small Signal And Large Signal Analysis

Large signal device characteristics should be used for the analysis anddesign of GaAs FET oscillators. The approach taken by some workershas been to measure small signal S-parameters of the device over thedesired frequency range and to extend the applicability of the measured


values to large signal operation (Maeda et al, 1975a; Maeda et al, 1975b;Finlay et al, 1978; Joslii et al, 1979). This procedure is capable of areasonable prediction of the frequency of operation as the change inS-parameters is largely resistive under large signal conditions. Becauseof this the oscillation frequency is not affected since it is determined bythe reactive part of the circuit impedance. This technique would how-ever, not be able to predict performance characteristics like the outputpower efficiency.

Large signal S-parameter measurements can be used to characterizethe GaAs FET at a particular frequency and bias arrangement (Mitsuiet al, 1977a; Mitsui et al, 1977b). This procedure provides enoughinformation to predict oscillator performance but involves extensivemeasurements and therefore has limited application.

Johnson (1979) did extensive small-signal S-parameter measurementsfor the FET covering a range of bias conditions and frequencies togetherwith a limited number of large signal S-parameters at several powerlevels for the desired frequency. An equivalent circuit model for the FETwhich includes non-linear circuit elements for large signal behaviourwas developed from this data. The nonlinearity was assigned to up to 7elements of the equivalent circuit and was expressed in terms of thenonlinearity of the transconductance. This provided a reasonably com-plete large signal FET model and gave good agreement between thetheoretical and experimental results for an FET oscillator.

Rauscher and Willing (1978,1979) characterized the performance of theFET under small signal conditions using extensive small-signal S-pa-rameter measurements over a wide range of bias conditions and fre-quencies. This data was used to develop an equivalent circuit modelcapable of large signal description. With this information the form ofnonlinearity of the equivalent circuit elements was derived to predictthe large signal behavior. This was achieved through the relationshipsbetween the "small signal incremental values" of nonlinear circuitelements (predicted from small-signal S-parameter measurements) andthe "instantaneous values" (applicable to large signal oscillations in biasconditions) in the form of sets of differential equations. This method hasthe advantage that only small signal S-parameters are required butneeds many computationally intensive steps to fit the equivalent circuitmodel to the measured S-parameters.

Rauscher used this to establish design techniques for fixed frequencyand varactor tuned GaAs FET oscillators for optimum large signalperformance. The technique requires the synthesis of a lossless three


port coupling network which simultaneously provides the optimumterminating impedances for the transistor ports and the optimum feed-back between the drain and gate terminals to maximize the r.f. powerdelivered to the load. The coupling network must yield only one stablestate of oscillation, thus suppressing spurious oscillations. In his designexample the external load to which the power is to be coupled wasconsidered an integral part of the coupling network. Maximum netoutput power from the oscillator was obtained by maximizing thedifference between the power available at the drain port and the powernecessary to be fed back into the gate port to sustain oscillations.

7.5 Free-running Oscillators-Performance Review

The first detailed work on microwave GaAs FET oscillators in which apackaged device with inductive impedance at the gate and capacitiveimpedance at the source was utilized was reported by Maeda et al,(1975a, 1975b). These impedances were optimized to yield the maxi-mum negative resistance at the drain-source output port of the FET.The output was coupled to a 50 ohm load through a matching network.The imaginary part of the device impedance was resonated with theimaginary part of the load impedance at 10 GHz (the desired oscillationfrequency) (Equation 7.4). The circuit was realized on a 0.6 mm thickalumina substrate using thin film technology. The oscillator provided apeak power of 40 mW and a maximum efficiency of 17% (Figure 7.8).The oscillation frequency was in the 10 to 10.6 GHz range for a numberof oscillator circuits. The output power and frequency variation withtemperature from —20 to +60°C was also measured (Figure 7.9). Thefrequency variation was dependent upon the gate bias value. Thefrequency variation with temperature was reduced as the gate wasbiased. The best value obtained was -0.45 MHzAC at -3.0V gate biasbut was -0.9 MHz/°C at the maximum output power gate bias level of-2.0V.

The output power variation with temperature was found to be minimalat the gate bias level corresponding to the maximum output power, Forthe minimum dF/dT condition of —0.45 MHz/°C the output powervariation was -0.02 dB/°C.

The AM and FM noise spectra of the GaAs FET oscillator were alsomeasured and compared with Gunn and Impatt oscillators. The AMnoise could be reduced by reducing the drain bias level while the FMnoise was insensitive to this variation. The measured AM and FM noiseresults are shown in Figures 7.10 and 7.11. The AM noise of these free


(a) Oscillation characteristics as a function (b) Oscillation characteristics as a functionof drain bias voltage at a fixed gate bias of gate bias voltage,voltage that yields maximum output power.

8 10

Drain voltage V,,(v)(a)

0 - 1 - 2 - 3 -4 - 5

Gate voltage (V0(v)(b)

Figure 7.8 Bias Dependence of a GaAs FET Oscillator

(a) Oscillation frequency as a function of (b) Output power as a function oftemperature temperature. The OdB corresponds to an

output power of 23mW

T

treq

.io

n

iS

8

10.3

10.2

10.1

. I,,, = 56mA Vd = 8v

. . . iV 35v

3.0

2.5

"—-—^-2.0" ^ — - - 1 . 5

—20 0 20 40 60 80

Temperature (°C)(a)

- 2 0 0 20 40 60 80

Temperature (°C)(b)

Figure 7.9 Temperature Stability of a GaAs FET Oscillator


e -120

gra

t

oz -130CO

8

-140

IN 100Hz band

^^^^

• ^ ^ > ^ _ GaAs FET

^ ^ ^ ^ • ^ ^ ^ ^ ^ GaAs Impatt

Gunn

10 100 1000

Frequency off carrier (kHz)

Figure 7.10 AM Noise of GaAs FET, Gunn and Impatt Oscillatorsas a Function of Frequency off the Carrier

100

> fre

q. d

evia

tion

(Hz)

o

CO

1

x v ^ IN100Hzband

^ • ^ ^ s . ^ ^ ^ ^GaAs Impatt (Qe, = 250)

^ ^ ^ ^ . GaAs FET

Gunn(a« = 800)

10 100 1000

Frequency off carrier (kHz)

Figure 7.11 FM Noise of GaAs FET, Gunn and Impatt Oscillatorsas a Function of Frequency off the Carrier


running GaAs FET oscillators was seen to be higher than that of theGunn oscillators but comparable to that of the GaAs Impatt oscillator,The FM noise of the GaAs FET oscillator was found to be worse thanthat of the Gunn oscillator but better than the GaAs Impatt diodeoscillator.

A figure of merit for comparison of GaAs FET oscillator output powerwas introduced by Joshi and Turner (1979). A term called the PeripheralPower Density (PPD) was introduced which normalizes the outputpower of the oscillator to the gate width of the FET used. The maximumvalue reported so far is 0.33 mW/ micron gate width and was realizedwith an oscillator circuit using series and shunt feedback. The gatewidth of the FET was 30Qam and the oscillator efficiency was 24% (Joshiet al, 1979).

Low power oscillators using smaller gate width FETs (e.g. 30Qam) havebeen realized with both series and parallel feedback elements. Thedesign is generally based on small-signal S-parameters and provides'ball-park' results on oscillator frequency. The maximum reported con-version efficiency from FET oscillators is 45% and was obtained byTserng and Macksey (1977) for a 0.5 x 300jum device at 10 GHz.

Kim et al (1985) have described the highest frequency FET oscillatorsrealized at the time of writing. These oscillators were produced using0.2 micron gate length, 75 micron gate width devices fabricated onmolecular beam epitaxial layers. Output powers in the 70 to 80 GHzrange were a few milliwatts whilst at 110 GHz 100 microwatts has beenobtained. The same device produced 30 mW output power at 35 GHzcorresponding to a d.c. to r.f. conversion efficiency of 16%.

High power free running oscillators using large gate width multi celldevices are usually designed using large signal S-parameters, Rectorand Vendelin (1978) used large signal Sn and S22 data with small signalS21 and S12 data. The large signal S11 and S22 were derived by conju-gately matching the transistor at the desired signal level and frequencyand measuring the tuner impedances. Rector and Vendelin (1978) usedthese parameters to design a common gate oscillator which gave 1.2 wattoutput power at 8 GHz. The device geometry was 1 x 300/^m and anefficiency of 27.2% was achieved.

Abe et al (1976) used a similar technique to measure large signal Snand S22 parameters of a 'subnetwork' on a chip carrier which includedthe 1.5 x 250Qam FET with parallel feedback elements. Such a tech-nique for oscillator design was first demonstrated by Gonda (1972). Onthe basis of this information the gate port was terminated in an open


circuited line and the output was coupled to the load. The oscillatorprovided 250 mW output power with 22% efficiency at 6 GHz.

Mitsui et al conducted large signal S-parameter measurements forpower levels varying from -10 to +20 dBm. A standing wave methodwas employed for Sn and S22. The magnitudes of S12 and S21 weremeasured by direct observation of the transmitted power and phaseangles by using a magic T method. The amplitude dependence is shownin Figure 7.12 as a function of incident power level at 10 GHz. The phaseangles of the S-parameters remained virtually unchanged. The markedchange in the magnitude of S22 and S12 with increased power level wasattributed to the increase in drain conductance and feedback capaci-tance between drain and gate terminals. These large signal S-parame-ters were expressed as functions of drain and gate current amplitudesand were used to design a composite series and parallel feedbackoscillator network. The oscillator provided a maximum power of 45 mWat 10 GHz with 19% efficiency.

The grounded gate configuration does not provide adequate heatsinkingwhen used for power FET oscillators. A grounded source configuration

0.1 1.0 10.0 100.0Incident power (mW)

Figure 7.12 Dependence of the Amplitude of the S-parameters on theIncident Power Level


can be utilized but the parallel feedback element coupling the gate anddrain terminals has to be small enough to minimize parasitic elementsat the desired frequency. The source terminal is either flip-chip mountedor via hole techniques are used to obtain low thermal resistance (seeChapter 3). Common drain configurations possess a natural tendency(due to | Sn | « 1) for oscillations. The drain terminal, however, doesnot have low thermal resistance. Wade and Camisa (1978a, 1978b) andSechi (1979a, 1979b) have used the so called "reverse-channel" or com-mon-drain oscillator in which the roles of source and drain terminalsare interchanged. The new drain terminal (formerly source) is flip chipmounted for good electrical and thermal grounding. This voltage rever-sal is possible for some FETs in which the gate is symmetrically placedin the channel and thus exploits the symmetry of the self-aligned gateprocessing, oscillator applications with a single power supply are possi-ble with this topology.

These reverse channel oscillators have given output powers up to 1 wattwith 24% maximum efficiency at 7 GHz (Wade). Camisa and Sechiobtained 370 mW output power at 8.5 GHz with 24% efficiency. Amaximum efficiency of 26% was obtained.

7.5.1 Output Power

When small signal S-parameters are used for the oscillator design goodagreement between measured and predicted oscillation frequencies canbe obtained. It is, however, not possible to predict the output power level.The large-signal characterization work undertaken by Mitsui et al(1977) was able to give good agreement between the measured andcalculated power level and frequency of the oscillator.

Pucel et al (1975) and Johnson (1979) have used the power gain satura-tion characteristics of a FET amplifier to predict the oscillator outputpower and to derive an expression for the maximum oscillator powerobtainable from a particular device. Typical characteristics are shownin Figure 7.13.

The output power asymptotically reaches a value Psat, the saturatedpower which is device and bias point dependent. The difference betweenthe output power, POUT, and the input power PIN, which would indicatethe oscillator power is also known. This in principle represents thepower available from the device as an oscillator.


of

1O

utpu

!

C

6P00, = 1 . , .

1 r

)Input power Rn

Figure 7.13 Power-Gain Saturation Characteristics

Pucel et al (1975) indicated that this characteristic can be approximatedas where Go is the small signal gain. From Equation 7.13 the maximumoscillator power is given by

P =*-1 out — 7 + -

7.13

where GO is the small signal gain. From Equation 7.13 the maximumoscillator power is given by

p =ss p / =1 osc max ~ L sat\ J 7.14

This value is lower than the saturated power output of the correspondingamplifier and reaches it when the small signal gain is very large.

Johnson's approximation for this is given by Equation 7.15 and wasderived from experimental observations,


7.15

and the point of maximum oscillator power was computed to be

inGo= P

osc{max) rsat

7 l

7.16

and the maximum efficient to gain GME defined as the power gain whichmaximizes the two port added power, is given by

-17.17

Using these equations an estimate of the output power obtainable froma particular device can be obtained.

7.5.2 Noise

Although GaAs FET oscillators have the attraction of high efficiency andconvenient biasing requirements their noise performance is poorer thantransferred-electron devices. This has made them less attractive forapplications where noise performance is critical. Although the noise

CD"O

O

1

-20

-40

-60

-80

-100

-120-

-140

-160

100

(Abeetal)

\ t(Maeda et. a!)

(Finlayetal) ^ (Abeet.al)

• • • • i • i i • » • • ' ! i • • i • m i i i i 1 1 1 n l — i i i M i n i

1KHz 10KHz 100KHz 1MHz 10MHz

Frequency off carrier

Figure 7.14 GaAs FET Oscillator FM Noise Results


behavior of GaAs FETs used as small-signal amplifiers has been quiteextensively investigated and theories adequately describing their per-formance presented there has been no similar investigation of the noisein a GaAs FET when it is used in oscillator applications.

Experimental results on the close to carrier AM and FM noise of FEToscillators have been presented by several authors for free-runningoscillators (Omori et al, 1975; Mitsui et al, 1977b; Abe et al, 1976 : Finlayet al, 1978). FM noise for a number of oscillators reported in theliterature and their Q values are shown in Figure 7.14.

It has been Generally observed that FM noise is very device dependent.Ruttan (1977) reported FM noise data at X-band for a number of FETsin the same circuit and observed a variation of up to 20 dBs.

Recently Debney and Joshi (1983) have reported the development of ananalytical theory for the noise in GaAs FET oscillators with particularemphasis on FM noise.

Noise in oscillator circuits is described in terms of modulation phenom-ena where the noise in the output RF power spectrum is characterizedin terms of amplitude modulation (AM) and frequency modulation (FM)components. These arise from amplitude and phase fluctuations, AA(t)and A0(t), in the output current, which may be assumed to take the form:

7.18

In general the output of the oscillator contains a combination of bothAM and FM noise contributions. When the output of an oscillatorfollowing AM limiting is displayed on a spectrum analyzer the FM noisespectrum appears in the form of sidebands on each side of the carrierfrequency, f0. The FM noise spectrum is defined as the noise power in a1 Hz bandwidth of a single sideband at a frequency f removed from thecarrier, divided by the power in the carrier.

Many GaAs FET oscillators have FM noise spectra which exhibit a 1/f3

frequency dependence over the frequency range from 1 kHz to at least1 MHz. Theories which are based on white noise sources within the FETsuggest a 1/f2 dependence which is clearly incorrect. The model adoptedby Debney et al is based on that proposed by Graffeuil et al (1982). GaAsFETs exhibit low-frequency noise with a spectrum of the form f~x, wherex is close to unity. For the particular devices described by Debney therelationship holds for frequencies up to 50 MHz or so beyond which thenoise is white. The FET operates in a non-linear mode since it is thisfeature which stabilizes the amplitude of the oscillations. Low fre-


|X

eg(t)

IIY

a Lumped equivalent circuit of a seriesfeedback FET oscillator

IX

IYb One-port representation adopted in

analysis of AM and FM noise

Figure 7.15 (a). Lumped Equivalent Circuit of a Series FeedbackFET Oscillator (b). One-Port Representation Adopted in Analysis ofAM and FM Noise

quency device noise is mixed with the carrier signal via the non-linearityof the FET to produce upconverted noise at microwave frequencies.

In order to produce a full analytical theory for FM noise from deviceparameters certain model simplifications have to be made. Figure7.15(a) shows a lumped equivalent circuit model for a series feedbackoscillator in which the feedback component is a common current carry-ing element between the two FET ports. Consider the intrinsic low-fre-quency noise generator eg(t) located at the gate terminal of the FET. Alarge signal model of the FET is used to derive the equivalent noisevoltage generator ea(t) at the output port of the oscillator. The generatorea contains the internal mixing of device noise within the FET. Afterthis derivation the oscillator is treated as a one port network in whichthe FET and feedback circuit are represented by a negative resistancegenerator. This is illustrated in Figure 7.15(b) where the device and thecircuit to the left of X-Y are described by the impedance ZD(A,f). Thecurrent amplitude and phase fluctuations as described in Equation 7.18can be analyzed by the method of Kurokawa (1969) and from the noisespectral density functions for the amplitude and phase fluctuations theAM and FM sideband noise to carrier ratios can be obtained. The noisespectra of phase and amplitude fluctuations are given by:


7Z IT 9

2RLP0{u2+t2)(f)2

(su + rtf7.19

and

;f0 + f) + S(ed;f0-f)](u2+t2)7.20

The noise spectral density function S(X;f) for a function X(t) is obtainedvia the definition:

cos27ifcX(t)X(t+r)dr 7.21

where X(t)X(t + r) is the autocorrelation function for X(t). The parame-ters r, s, t and u are dimensionless quantities which characterize thefrequency and signal amplitude behaviour of ZD and ZL and are givenby:

r_AodXT

RL d A

t-fo**T

._AodRT

RL « A

Rr B f

7.22

where

RT = RL and XT = 7.23


The four parameters defined in Equation 7.22 have to be determined inorder to characterize any particular oscillator. One of the terms whicharises in Equation 7.20 and 7.21 can be equated to the Q of the outputof the oscillator by the expression:

Q= 2 7.24

The single sideband noise to carrier ratio for FM noise L(f) is obtainedfrom S(A0;f) by dividing by a factor 2. Since the range of frequenciesremoved from the carrier is such that f«f0, the expression for the FMnoise spectrum can be simplified to:

i ,16RLP0Q\ff

The single-sideband noise to carrier ratio for AM noise can be obtainedfrom S(AA;f) by multiplying by the factor RL/4P0.

The dependence of FET oscillator noise on the noise spectral densityfunction for ea indicates two important points:

(1) The noise frequency components of ed which give rise to FM noisesuggest that the Kurokawa noise theory is a linear theory. Micro-wave frequency noise in the oscillator output arises from microwavefrequency noise components of ed. Noise from the generator ed isessentially linearly translated in frequency into the oscillator out-put. In the theory of Debney a nonlinear description for the oscilla-tor is implied through the parameters r and s. In Kurokawa's theorynonlinearity is used only to provide stabilization of the oscillationsand it is not involved in the noise mechanisms. The mixing effect oflow-frequency noise upconverted to become sidebands of the carrierfrequency is therefore not inherent in the latter theory and must beincluded in the evaluation of ed(t).

(2) If the noise spectrum of ed is white then L(f) has a characteristic1/r frequency dependence which is not the case experimentally.

The intrinsic low-frequency noise of the MESFET can be representedthrough a noise voltage generator at the gate terminal. Justification forthis is given by the work of Das and Ghosh (1981) who concluded that1/f noise in GaAs FETs is dependent strongly on gate leakage and is alsorelated to the process of electrons tunnelling into deep levels in the


depletion region beneath the gate with subsequent thermal emissioninto the conduction band. The gate noise generator is characterized bya noise spectral density function which has a low-frequency semi-em-pirical relationship given by:

7.26

where &NEE and F are two parameters needed to characterize a particu-lar FET (Monham et al, 1982). &NEE is the frequency at which the noisechanges from 1/f to a white spectrum and was about 50 MHz for thedevices described by Debney. F is a dimensionless quantity charac-terizing the amplitude of the noise and is close to unity. The interestedreader is referred to the original paper for a full description of thedetermination of the output port equivalent noise voltage generator.

Suffice it to say that the FM noise of a GaAs FET oscillator requires alarge number of parameters to be determined. These are given belowfor the complete expression for L(f):

L(f) = — 2

8f3RLPoQ2GMGD

2\Yof

where

and

1

M2

A =

c d°MGS

av

(su + rtf(st-ruf

n'd

GD

VGS

GD

vDS

GM and GD are the DC transconductance and output conductance of theFET respectively. The modulus of cp describes the ratio of the amplitudeof the RF signal voltage developed across the gate-source terminals ofthe FET to that across the drain-source terminals. The argument of <pgives that phase difference between the two RF signal voltages, cp canbe found by analyzing the oscillator circuit using a nonlinear analysisCAD program although the small signal S-parameters can be used to


Table 7.1 Parameter Values used in the Calculations of the FM SSBNoise-to~Carrier Ratio

Parameter

fKNEE (MHZ)

r

fo (GHz)

E2 (volt)

IM2 + Mi l 2 (sV 2 )

1+A

RL (ohm)

Po(mW)

Q

GM (mS)

GD (mS)

IYol2(s2)

GAT4

40

1.0

8.84

2.0

1.0 X 10"10

1.2

50

9.4

30

30

20

3.5 x 10"5

GAT6

40

1.0

14.05

2.0

1.0 X 10~10

3.0

25

20.0

20

30

20

1.3 x 10"5

provide a useful starting point. The frequency of oscillation, f0, theoscillator output power) Po, and the Q can be measured directly, t andu can be found from small signal analysis circuit. The parameter r is anegative quantity whilst s is positive and for a well-designed close to itsmaximum output power has a value of 2. A is of the order of unitydepending predominantly on the values oft and u. Table 7.1 shows thevalues of the parameters for two oscillators, the first a series feedbackoscillator using a Plessey GAT4 FET and the second a parallel feedbackcircuit utilizing a Plessey GAT6 FET.

A comparison between the measured and calculated FM noise perform-ance of the two oscillators is shown in Figure 7.16. The spectral depend-ence of the FM sidebands was found to be described well by a 1/f3

behaviour in both cases. Bearing in mind the number of quantities tobe measured and calculated the degree of agreement is very good. Thenoise performance of the GAT4 oscillator proved to be significantlybetter than that of the oscillator based on the GAT6 FET although thedecreased | Yo |

2 of the parallel feedback arrangement is the main causerather than the FET. From Equation 7.27 some general guidelines for


-10-20

S-30^-40

d -50o-60^-70m-80to __t o - 9 0

-

I -

- MeasuredTheory

i

0.1 1Offset frequency

^ X

1

10from carrier,

5^GAT6

NGAT4i

100kHz

Figure 7.16 Comparison of Theory and Measurements for FM NoisePerformance of Two GaAs FET Oscillators (after Debney)

the selection of FETs and circuits for a low-noise oscillator can be made.Since output power, Po, transconductance, GM and output conductance,GD are proportional to gate width, L(f) decreases as the FET gateperiphery is increased. GaAs FETs with intrinsically low 1/f noiseshould be chosen. The choice of circuit topology and the optimization ofthe circuit to maximize the Q are also important factors.

7.6 Stabilized Oscillators

Microwave radio relay and communication systems require a highlystable source with extremely low noise performance. A conventionalmethod of obtaining such high stability is to employ a quartz crystaloscillator followed by frequency multiplier chain. With this the fre-quency change with temperature is increased by the order of multipli-cation n while the close to carrier FM noise power is increased by a factorof n2. The conversion efficiency also worsens as n increases.

It is attractive to use fundamental frequency solid state sources for theseapplications but it puts severe restraint on their frequency-temperaturestability and FM noise performance. Such solid-state sources wouldtherefore require frequency stabilization before they could be used forsuch applications. This can be achieved by several techniques likefrequency or phase locking to a stable reference signal, discriminatorstabilization or high-Q cavity stabilization.


7.6.1 Stabilization Techniques

Stabilization by frequency or phase locking is a fairly standard tech-nique adopted at low microwave frequencies. Post multipliers are usedif higher frequency is desired. In discriminator stabilized oscillators asmall fraction of the oscillator output signal is coupled to a discriminatorand its output signal which is proportional to the difference between thediscriminator center frequency and the oscillator frequency is amplifiedand fed back to a frequency control element in the microwave oscillator.Glance and Snell (1976) reported this technique with a microstrip Gunnoscillator with a varactor diode as the control element. Cantle et al(1978) used this technique with coaxial GaAs FET oscillators and MICdiscriminator. The gate terminal was used as a frequency controlelement. The performance of such an oscillator depends upon thediscriminator characteristics and the frequency-temperature variationis controlled by the characteristics of the discriminator itself.

7.6.1.1 Cavity Stabilization

In the cavity stabilization method, the oscillator is coupled to a high-Qresonator and a trade-off between the oscillator power and stability canbe established. The advantages of this technique are low cost, simplicityand small size, With the use of high Q ceramic resonators the techniqueis now compatible with MIC circuits also.

Absorption stabilised < ,

Reflection stabilised

Transmission stabilised< \

Figure 7.17 Basic Oscillator Stabilization Techniques


Figure 7.17 shows the basic cavity stabilization techniques. In theabsorption (or reaction) mode a high Q cavity is coupled to the transmis-sion line between the oscillator and the load. The cavity acts as a bandreject filter and at the resonant frequency a small amount of r.f. poweris reflected by the cavity which is fed back and injected into the oscillatorand improves stability. The reflected power is dependent upon themismatch introduced by the cavity.

This technique can also be termed "passive injection locking" as all theband reject filter spectral characteristics are transferred to the freerunning oscillator, in the reflection stabilization mode the cavity iscoupled to one oscillator port while the other port is coupled to the load.In the transmission cavity stabilization method, the resonator is treatedas a two port network acting as a band pass filter connected betweenthe oscillator and the load. This arrangement has its drawbacks in thatcoupling losses at two ports have to be accounted for.

When the physical size of the cavity is small, as in the case of compactceramic resonators, it is possible to use it as a feedback element couplingthe input and output port of the active device. This is essentially aspecial case of the transmission stabilization method.

A cavity stabilized oscillator is basically composed of two resonantcircuits: the oscillator resonant circuit and the stabilizing cavity. Anoscillator may show many possible modes which manifest themselves inmode jumping, frequency hysteresis etc.

James et al (1975) used Invar and titanium silicate band pass filtercavities to stabilize GaAs FET oscillators. The cavity size used was largeand was not compatible with the MIC techniques used for the oscillatoritself. With the use of recently developed dielectric material it is possibleto obtain thermally stable low noise oscillators. Improved performanceis possible because the ceramic resonators provide high Q in extremelysmall outline and the ease of coupling to the MIC circuits render themvery attractive for use with GaAs FET oscillators.

7.7 Dielectric Resonators

Material scientists have been engaged in the pursuit of a suitableceramic material for cavity resonator applications for about a decade orso (Day, 1970; Masse, 1971; Plourde et al, 1977). The requirements forsuch a material are low loss (or high Q), relatively large dielectricconstant and low frequency-temperature coefficient. A large dielectricconstant is required in order to realize compact resonators at the


required operating frequency and also to ensure that most of the elec-tromagnetic field be confined in them.

Rutile or titanium oxide (TiCte) has a high dielectric constant (er = 100)and a high-Q (10,000 at 4 GHz). The material would thus seem ideal formicrowave applications as the high dielectric constant ensures that thefields are contained within a compact resonator. The frequency-tem-perature coefficient of rutile is, however, poor («100ppm/°C) thus ren-dering the material unusable where high temperature stability isrequired.

Rutile has, however, been used as a constituent Dart of a new family ofceramics for this application. BaO-TiO2 system ceramics and a seriesof zirconate based compositions have been investigated. For BaO-TiC>2system ceramics, as the relative percentage of TiC>2 is varied two stablephase conditions corresponding to BaTi4C>9 and Ba2Ti9O20 are possible.The barium nanotitanate provides the best combination of dielectricproperties with er = 39, Q = 8000 and n = 1 to 3 ppm/ °C (Masse,1971;Plourde et al, 1977; O'Bryan et al. 1974).

The resonant frequency temperature coefficient l/fr. Afr/AT of a BaO-TiO2 system ceramic can be approximated as

1 1 Asr 1 Al2 er AT £ AT 7*28

In the room temperature range the, thermal expansion coefficient

1 A££AT

is approximately 9 ppmAC and the dielectric constant temperaturecoefficient is nearly -24 ppm/°C, giving the frequency temperaturecoefficient of 3 ppm/°C. Thus the temperature effects on expansion anddielectric constant offset each other to provide extremely small fre-quency change with temperature.

It is useful to characterize the material properties at microwave frequen-cies because measurements at lower frequencies may provide differentresults due to the dielectric relaxation phenomena. Different types oftest cavities or dielectrometers can be used to evaluate the dielectricconstant and frequency-temperature coefficient of the material (Hakkiet al, 1960; Courtney, 1970). Extreme care is required for the measure-ment of loss tangent (and hence Q) as its value is very small for a goodresonator material.


7.7.1 Resonant Frequencies Of Dielectric Resonators

Electromagnetic theory analyses of dielectric resonators have beenconducted by a number of authors (Cohn, 1968; Okaya et al, 1962; Yee,1965; Chow, 1966; Itoh et al, 1977; Konishi et al, 1968; Guillon et al, 1977;Pospieszalski, 1977; Pospieszalski, 1979). The analyses usually consid-ered the circular cylindrical resonator in free space and calculated theresonant frequencies for various TE, TM and HE modes. Pospieszalski'sanalyses of cylindrical resonators have direct practical application formicrostrip, stripline and TEM circuit configurations. The first analysisconsidered the case of a cylindrical sample of a low-loss high dielectricconstant material placed between two parallel conducting planes. Sucha configuration, known as the dielectric post resonator has been usedfor the measurement of dielectric constant and loss tangent of insulatingmaterials (Courtney 1970). The analysis derived resonance frequencyexpressions for the HEnie, TMome and TEome, modes as functions ofdielectric constant and the dimensions of the resonator. The propertiesof the TEon mode were discussed in detail and applied to the measure-ment of complex permittivity of microwave dielectrics.

Pospieszalski's second work considered a microwave cavity formed by acylindrical dielectric material of low-loss and high eT when placed a finitedistance away between two parallel conducting planes perpendicular to

Conducting planes

Dielectric

Substrate

(a) Symmetrical configuration

-Conducting planes

(b) Unsymmetrical configuration (shieldedresonator arrangement)

Figure 7.18 Dielectric Resonator Mounting Configurations


the sample axis. The resonant frequency expressions were derived forsymmetrical and unsymmetrical cases (Figure 7.18).

The unsymmetrical case represents a typical configuration used inmicrowave integrated circuits and is also known as the shielded resona-tor arrangement, The dominant TEoio mode indicating constant field inthe axial direction in this configuration is commonly designated as TEoidmode (Itoh et al, 1977). The calculation of the resonant frequency byPospieszalski's work involves finding the solutions of a Bessel andmodified Hankel function equation which also satisfies an expressionarrived at by imposing boundary conditions at the dielectric interface.These calculations are best undertaken by a numerical technique.

Table 7.2 shows resonance frequencies for TEmne, TMmne, and HEmne,modes for a cylindrical dielectric material contained between infiniteparallel plates as calculated from Pospieszalski's work.

Figure 7.19 shows the TEoia mode resonant frequency as a function ofthe air gap dimension for the same sample when placed on a 0.635 mmthick alumina substrate (dielectric constant = 9.8). The theoreticalvalues were obtained from Pospieszalski's analysis. The "tuning char-

Table 7.2 Calculated Resonance Frequencies (in GHz) for TEmn%TMmniand HEmni modes for a Cylindrical Dielectric ResonatorContained Between Two Infinite Conducting Parallel PlatesD = 7.2mm L = 2.3mm er = 39.1

I = 1

2

3

e = 1

2

3

e = 1

2

3

TEoie

12.464

14.014

15.786

TM01e

13.223

15.080

17.083

HEne

11.435

21.380

31.639

TEo2e

22.119

23.094

24.255

TM02e

22.387

23.532

24.863

HE21e

12.989

22.250

32.233

TE03e

32.198

32.908

33.764

TM03e

32.328

33.131

34.089


10.0

9.5

9.0

8.5

Resonant frequencyCalculatedMeasured o

0 1.0 2.0 3.0Ur, mm

4.0 5.0

Figure 7.19 Tuning Characteristics and Quality Factor of theResonator of Table 7.1 in a Shielded Arrangementacteristics" of the resonator indicate that for an air gap larger than acritical value (3 mm in this case) the resonant frequency remainsvirtually invariant. The available "tuning range" is a function of dielec-tric constant of the material and its dimensions. Unloaded Q of theseresonators is typically greater than 5000 at X band frequencies.

The microwave cavity formed by the dielectric resonator has multipleresonant frequencies corresponding to various TE, TM and HE modes.The circuit designer has to overcome this by suppressing or isolating theunwanted modes which might interfere with the proper circuit perform-ance. Figure 7.20 shows the transmission characteristics of a 50 ohmmicrostrip line when coupled to a shielded ceramic resonator. Thedesired TEoia mode is identified.

7.7.1.1 Dielectric Resonator as a Microwave Circuit Element

When a dielectric resonator is placed in the vicinity of a micro strip line,on an alumina substrate, magnetic coupling between the resonator andthe line is caused by the TEoi<5 mode in the resonator. For a match-ter-minated line of characteristics impedance Zo, an equivalent circuit ofFigure 7.21. can be established.

The impedance at reference plane A-A' can be expressed near theresonance frequency as


Figure 7.20 Resonance Frequencies for the Case of Figure 7.17 (Lair= 4.55 mm)

Figure 7.21 (a). Schematic Diagram of a Shielded DielectricResonator Coupled to a MIC Line of Characteristic Impedance Zo


K2R

1 +l + j2Qrdr

7.29

where Qr: unloaded Q factor of the resonator

fr: resonant frequency

= /?: coupling frequencyK2R

Abe et al obtained a family of impedance curves for the configurationshown in Figure 7.21 as a function of the distance between the resonatoredge and the microstrip edge. These are shown in Figure 7.22. By fittingthe impedance locus of Figure 7.22 to Equation 7.29,the values for /? andQr were found to be 2.2 and 4000, respectively for fy = 2.5 mm.

DL1,

= 10mm= 4mm= 3.5mm= 1.0mm« 5810 MHz

0.2/

/

n

0

0.2 10.5I ly = 3.

\^^1/=3

= ^5y^__[^-

1 n

)

\

^ % — A t = —1MHz

-AyT/r^bS = +IMHZ/0

Figure 7.22 Reflection Coefficients of the Resonator Coupled to aTerminated 50 ohm Microstripline


7.8 Dielectric Resonator Stabilized FET Oscillators

James et al stabilized GaAs FET oscillators with Invar and titaniumsilicate resonant cavities used as band pass filters. At lower frequenciesthe required cavity size becomes prohibitively large. Also the need forcoupling a resonant cavity directly to a FET oscillator fabricated usingMIC techniques presents difficult problems.

Abe et al used the dielectric resonator in the absorption or reaction modeto stabilize a free-running GaAs FET oscillator at 6 GHz. A GaAs FETchip for medium power applications with parallel feedback was firstfabricated on a chip carrier. A free running oscillator was obtained byconnecting an open circuited microstrip line at the gate terminal and anoutput matching network at the drain terminal (Abe et al, 1976). Thefree running oscillator gave 400 mW output power at 6 GHz with amaximum d,c, to r.f, conversion efficiency of 38%.

A triple-layered or shielded dielectric resonator configuration was em-ployed at the drain terminal to stabilize the oscillator. The dielectricresonator of dimensions D = 10 mm and L = 4 mm was characterized byreflection coefficient measurements indicated in the previous section.

The large signal reflection coefficient of the oscillator and hence theoscillator impedance appearing at the drain terminal was measured. Avariable tuner was connected at the output terminal for adjustment ofpower output and frequency. The reflection coefficients presented to theoscillator by the tuner were measured for constant power levels andfrequencies. The results (Abe et al, 1978) are shown on the so calledRieke diagram of Figure 7.23. The impedance contour of the stabilizingband rejection filter is also shown.

Theoretical analysis of oscillator stabilization was presented by consid-ering a parallel resonant circuit coupled to a transmission line termi-nated by a load with reflection coefficient |r |ei5 and applying thecondition that the oscillation frequency is determined by the zero suscep-tance condition together with dBT/df > 0.

Unstabilized oscillator oscillation frequency f0 and the external Q valueQo and the resonant circuit frequency fr and Q value were defined.Taking/? as the coupling constant between the resonant circuit and thetransmission line, expressions for stabilization range, temperature co-efficient p and pushing figure q were derived. The stabilization rangewhich includes hysteresis was given by


Resonator (D =9.0,1 = 3.6)

after Abe et al

Figure 7.23 Rieke Diagram

7.30

and the one which does not include hysteresis was given by

The temperature coefficient and pushing figure were given by

_1 I A/o

7.31

7 A / _ 7 A / r |

/AT frAT

and

(l + P)'Qo

Qr LAT 7.32

7.33


The output power delivered to the load is reduced by the insertion of theband reject filter by a factor given by

J YQ )i y+p)

K 7 - 3 4

where Po is the unstabilized oscillator output power level dependingupon the load conductance GL.

The performance of the oscillator with GaAs FET voltages, temperatureand as a function of resonator air gap was measured. Good agreementbetween the theoretical and the experimental values was obtained.Performance as bias voltages are varied is shown in Figure 7.24. Modejumping and hysteresis were observed. A stabilized output power of 100mW at 5810 MHz with 17% efficiency was obtained. Frequency andoutput power variations with ambient temperature are shown in Figure7.25. A frequency temperature coefficient of+2.3 ppm/ °C was obtainedwith output power variation of ± 0.4 dBm from 0 to 50°C temperaturechange. The mechanical tuning characteristics of the oscillator as theresonator air gap was varied is shown in Fig, 7.26. For Lair = 2.1 to 2.6mm the oscillator frequency followed the resonator frequency withoutany hysteresis or mode jumping. The FM noise improvement obtainedby stabilization was better than 30 dB.

Sone and Takayama (1978) have presented similar results on an absorp-tion stabilized FET oscillator. The design procedure adopted was similarto Abe et al (1978) but a grounded drain configuration as opposed togrounded source was utilized at 7 GHz.

A reflection type dielectric resonator stabilized FET oscillator has beenpublished by Podcameni and Bermudez (1981). The circuit topologywith feedback was selected to maximize the reflection coefficient mag-nitude at the gate-source port with the drain-source port terminated ina 50 ohm load. The reflection coefficient at the input port was measuredunder large signal conditions and a dielectric resonator was coupled tothe match-terminated input microstrip line to obtain stabilization.

Transmission-type stabilization, in which the dielectric resonator isused as a band-pass filter, has been presented by Alley and Wang (1979)at 1 GHz with bipolar transistor oscillators and by Shinokazi et al (1978)with FET oscillators at 12 GHz. In the latter the resonator is placedbetween two parallel microstrip lines and oscillation frequency between10 and 12 GHz is obtained by using different dielectric resonators.


6000_ 5900I 5800

If 570°- 5600

5500

i Vos = 7.0VTa = 25CC

^6100

| 6 0 0 0

^5900

- 5 8 0 0

-.300

—2.5 —3.0 —3.5 —4.0 —4.5Vos(V)

(a) Stabilized oscillator microwaveperformance as functions of gate-sourcebias voltage VGS.

_UI, - 2.5mm

300

100 CL

2 4 6 8VDS(y)

(b) Stabilized oscillator microwaveperformance as functions of drain-sourcebias voltage VDS (V)

Figure 7.24 Stabilized Oscillator Microwave Performance asFunctions of Gate-Source and Drain-Source Bias Voltages

+ 0.40

I •<-0.40

Resonator

VDsVGS

IDS

V\

. •

0

D = 10mm

-7.OV= -3.2V- 85mA

.—"

10

L = 4mm Substrate l2POUT = 20dBm(100mW)

fo = 5810MHz(Ta = 25° C)

*~AT ^^*

.

20 30 40

TaCO

= 0.635mm

^

50

+ 0.4

0

-0.4

r (dB

m)

.no

Q_

Figure 7.25 Deviations in Pout and fosc for Ambient TemperaturesBetween 0 and 50°C


^6200

§ 6100

§6000

"" 5900

*

1.0 1.5

"* —1

—

2.0

fosc•

P(XJT

• - "

VosVos

2.5

= -3 .5V= 7.5V

* ™ ^

3.0

300

200

100

o

!

0?

Figure 7.26 Mechanical Tuning Characteristics of StabilizedOscillator

Frequency tuning over a limited range was obtained by varying theassociated air gap.

Lesarte et al (1978) reported the first feedback stabilized FET oscillatorusing a dielectric resonator. The resonator (Ba2Tig02o) was mounted ona quartz spacer on an alumina circuit and was used as part of a feedbackcircuit coupling the drain and gate of the FET. The oscillator provideda maximum output power of 22 mW at 18% efficiency at 11 GHz. Theoutput power variation for an ambient temperature change of 0 to 60°Cwas less than 1 dB and the frequency variation was less than 1 ppm/°C.Saito et al (1979) reported a 6 GHz GaAs FET oscillator stabilized by adielectric resonator in an external feedback circuit.

Ishihara et al (1980) have described highly stabilized GaAs FET oscil-lators using dielectric resonator and stabilization resistors. Theirmainly experimental work shows that these oscillators have hysteresis-free operation, provide excellent stability against temperature, possesslow noise and a wide frequency range capability. By using five dielectricresonators of different dimensions the same basic circuit was tuned from9 to 14 GHz.

It was noted in Section 2 that for GaAs FETs the negative resistancecondition has to be induced by incorporating a feedback element. Mostfeedback elements are formed by using bond wires, microstrip lines etc.


Tuning plate

Ceramic substrate

Figure 7.27 (a). Feedback Circuit Using a Dielectric Resonator andStabilization Resistors (b). Cross Section of a Dielectric ResonatorFeedback Circuit

which can be in either lumped and distributed form. These componentshave low Q and can not be easily altered to produce a different powerlevel or frequency of oscillation. A dielectric resonator, however, due toits small size and compatibility with microstrip circuits, when used asa feedback element offers high Q, low frequency-temperature coefficientand ease of tuning.

Figure 7.27 shows a feedback circuit in which a dielectric resonator isused for coupling two microstrip lines terminated with resistors equalto the line characteristic impedance. The transmission characteristic is

m2,a

CL

1

Tran

sr

0

-10

-20

-100

f = 11.6GHZ

0

At (MHz)

+ 100

+ 90

0 |

-90

Figure 7.28 Transmission Characteristics of a Feedback Circuit


shown in Figure 7.28 in which the transmitted Dower and phase areindicated.

The resonator is in a shielded arrangement (Figure 7.18b) and theresonance frequency can be altered by varying the air gap. When thisfilter configuration is applied to the drain-to-gate feedback circuit of aFET amplifier, a highly stabilized GaAs FET oscillator can be obtained,provided the power gain of the amplifier is higher than the filtertransmission power loss. Because such an oscillator has a dielectricresonator feedback circuit it was termed the DRF GaAs FET oscillatorby Ishihara et al (1980). The transmission power and phase of the filtercan be varied by changing the distance between the dielectric resonatorand microstrip line, by varying the characteristic impedance of the linesand by varying the angle between the microstrip lines.

Schematic MIC patterns of these DRF oscillator types investigated byIshihara et al (1980) are shown in Figure 7.29. In these oscillatorsmicrowave power is incident on the gate terminal and the amplifiedoutput power from the drain terminal is fed back through the dielectricresonator to the gate. The output power was taken either from thesource terminal (Figure 7.29(a) and (c)) or from the drain terminal(Figure 7.29(b)). The former arrangement allows operation from a singlepower supply. Due to heat dissipation considerations the drain outputarrangement is preferable for high power oscillators. Comparison ofFigure 7.29(a) and (c) shows that the drain resistance RD can beeliminated by having an open circuited line of appropriate length (Ishi-hara 1980). The dielectric resonator made of SnO2-TiO2ZrO system witha dielectric constant of 37.5 was used. The oscillator configuration ofFigure 7.29(c) is preferable for low power oscillators due to its lowercomponent count and operation from a single power supply.

The mechanical tuning characteristic as a function of air gap for such aDRF stabilized GaAs FET oscillator is shown in Figure 7.30. Figure 7.31shows that an oscillator with the same MIC pattern and GaAs FET canbe tuned from 9 to 14 GHz by using dielectric resonators of differentthicknesses.

Oscillator performance with ambient temperature indicated that from—20 to +60°C change the output power variation was ±0.01 dB/°C andfrequency variation was ± 0.16ppm/°C(± 150 KHz total). The FM noiseof the oscillator was found to be comparable with Gunn oscillators.

Ishihara et al (1980) reported the results of incorporating a dielectricresonator as a band reject filter to the DRF GaAs oscillator. This dualstabilization scheme increased the external quality factor of the oscilla-


Figure 7.29 MIC Patterns of the DRF GaAs FET Oscillators (a).Source Output Type (b). Drain Output Type (c). Source Output Typewith only a Gate Resistor

tor. The frequency deviation with temperature was (±0 .1 ppm/°C) ±100 KHz from -20 to +60°C and the output power deviation was lessthan +0.022 dB/°C.

7.9 Electronic Tuning Of GaAs FET Oscillators

Many of today's electronic systems require the oscillating frequency ofthe microwave source to be variable. This frequency variation may bein discrete finite steps or may be a smooth transition between twofrequency states. This facility may be required from both transmittingsources which will usually be of high power and also from mainly lowpower receiving local oscillators. Tuning can be achieved by mechanical


13.0

_ 12.5

O

12.0

111.5

\

0 1.0

L = 1.8mmD = 5.5mm

f

' ^

2.0 3.0h(mm)

36

32

28

24

4.0

P(m

W)

Figure 7.30 Mechanical Tuning Characteristics as a Function ofAir-Gap Thickness (h)

P(m

60

40

20

nU

\

\

99.0

I1Vx V

A\\\

10.0

*\ A /\ J /\

X

11.0 12.0

Oscillation frequency f(GHz)

J

13.0

« LA4-o

= 3.8mm2.42.11.61.3

14.0

Figure 7.31 MechanicalTuning Characteristics with DifferentResonator Thickness (L) as a Parameter


means, but for ease of, and high speed operation most system needs canbe met by electronic tuning techniques.

The increasing use of electronically tunable oscillators in a variety ofmicrowave applications has brought into sharp focus both their steady-state and transient behaviour. The demands on broad tunability andhigh modulation capability are in direct conflict with high thermalstability and low noise requirements.

7.9.1 Electronically Tunable Oscillator Requirements

Consider an electronically tunable oscillator in a steady-state conditionoscillating at a frequency fi with a tuning input Vi applied at the controlterminals. At an instant t = 0 the tuning input is changed to V2. Theresponse of the oscillator and the input tuning signal are shown inFigure 7.32 in which the oscillator frequency reaches a steady statefrequency {2 after a finite time. The following terms describe the per-formance of the electronically tunable oscillator with reference to Figure7.32.

Slew rate: The rate at which the frequency of the oscillator can bechanged from one end of the tuning range to the other in responseto a step change from the tuning input is usually dependent on the

^ frequency

Figure 7.32 Characteristic Parameters of Electronically Tuned


external circuitry (for example, linearizing circuits, if employed). Itis given by the value Af/At and can be as high as 1 GHz/jusec.

Settling time: is defined as the maximum time taken by the oscilla-tor to settle within some small frequency band centered on thepredicted static frequency after a step tuning signal is applied.

Post tuning drift (PTD): Post tuning drift is defined as the largestvalue of frequency drift when measured over a time interval largecompared to the setting time but not including the settling timefrequency drift.

Tuning linearity: A useful measure of the tuning linearity is the .maximum frequency deviation of the experimental tuning curvefrom the best linear fit. This is an important requirement for someapplications.

These parameters along with low a.m. and f.m. noise and spurious andharmonic free response define the broadband electronic tuning oscillatorrequirements. Varactor diodes and YIG devices are the two main com-ponents used for electronic tuning applications and the performanceobtained from these two are complimentary rather than competitive innature.

The oscillation conditions for a negative resistance oscillator are givenby Equations 7.3 and 7.4. The stability criteria of Equation 7.5 must alsobe satisfied for sustained steady state oscillations. It is thus evidentthat, if the circuit reactance is varied by some means, the oscillatorfrequency will alter to satisfy the zero reactance condition. If theoscillator circuit incorporates a varactor diode or a YIG resonator thecircuit reactance can be changed by either varying the d.c. bias level onthe varactor diode or by varying the magnetic field strength applied tothe YIG resonator.

The gate tuning of free running GaAs FET oscillators can also beconsidered as electronic tuning. The variation of the gate bias alters thedepletion capacitance of the FET and consequently alters the oscillationfrequency.

7.10 Varactor Tuned FET Oscillators

Varactor diodes as tuning elements in conjunction with GaAs FEToscillators are quite attractive for high speed and moderate tuning rangeapplications. The circuit designer has to ensure that negative resistanceconditions are maintained over the desired frequency range of the


oscillator. There are mainly two topological arrangements in which avaractor diode can be incorporated in a FET oscillator circuit-as a partof the feedback element or as a terminating element to one of the deviceports.

Tserng and Macksey (1977) used small signal and power FETs ingrounded gate topology with series feedback to obtain varactor tuning.The varactor diode was either placed in series with the output matchingcircuit or with the gate feedback inductance. The small signal negativeresistance capability of such a configuration was measured. It indicatedthat for drain bias values greater than 5V negative resistance conditionsexist over the 7 to 12 GHz frequency range.

With the varactor diode in the drain circuit, frequency variation from 8to 11.5 GHz was achieved with a power FET device. Maximum outputpower was 210 mW with 17.5% efficiency. When the varactor diode isconnected in series with the gate feedback inductance frequency vari-ation of 8.2 to 13.2 GHz was obtained (Figure 7.33).

For X-band operation a varactor swing of 30 volts was sufficient. Itprovided less than 3 dB power variation over the tuning range with 50mW minimum power. A similar configuration was adopted for a smallsignal 0.5jum gate length FET Ku band oscillator. A tunable frequency

250

200

150

3

§" 100oLL

* 50

Gate width = 120fymVd = 8Vld = 141mA

/ •

+ 5 0 -10 -20 -30

Varactor voltage (V)

-40

14

13

12 -ft

11 o

10 £

9

8-50

Figure 7.33 Performance of an X-band GaAs MESFET VCO withVaractor Tuning in the Gate Circuit


range from 12.8 to 16.8 GHz was obtained with a nominal output powerof20mW.

When the varactor diode is used as a termination at the source port fora grounded gate arrangement with series feedback design techniquessimilar to those outlined in Section 4 can be utilized. The change invaractor bias gives rise to a variation in the phase angle 0r. With sucha circuit a tuning range of 1.7 GHz with less than ldB power variationand 16% minimum efficiency was achieved. The performance is indi-cated in Figure 7.34.

Camisa and Sechi (1979a and b) used a varactor diode in the gate circuitof a common-drain oscillator to realize a tuning range from 10.5 to 12.5GHz. The minimum output power and efficiency was 25 mW and 1.6percent respectively. Similar techniques were used by Wade.

Rauscher (1980) used the large signal design approach (Section 4.2) forvaractor tuned FET oscillators. Varactor tuning was provided in boththe gate and source leads of the device while the drain was connected tothe ground. A tunable range of 7.4 to 13.1 GHz was achieved and goodagreement between measured and predicted output power level wasobtained.

Scott et al (1981) used a circuit arrangement with varactor diodeslocated in series with the gate feedback inductor and across the sourceto ground port. A common power supply was used to bias the varactors.

2016

17

Vos = 5.0VVGS = 0.0VGAT5 FETVaractor CJ4 = 0.6pf

—10 —20

Varactor bias, volts

—30

11.5

11.0 o

10.5

10.0

Figure 7.34 Varactor Tuned FET Oscillator Performance


As the tuning voltage was varied from 0 to 16 volts the oscillator tunedfrom 7.3 to 15.6 GHz.

7.10.1 Monolithic Varactor Tuned Oscillators

Until the introduction of monolithic circuits the microwave broad-bandVCO designer had been restricted to the use of hybrid varactor diodeswhere the major design parameters can change with each batch re-ceived. Consistent resistance, zero voltage capacitance and capacitanceratio are necessary to maintain repeatable oscillator performance. Epi-taxial techniques used to grow the active layers required for hyper-abrupt diodes are rarely reproducible from wafer to wafer. Verticalstructured varactors for use at X-band and above, with zero voltagecapcitances of 2 pF or so, typically have 50 micron or less contactdiameters. Wire-bonding to such small areas becomes a problem inrespect to pull strength. Also the gate inductors in X-and J-Band VCOsare gold bondwires only 0.6 and lmm in length and it is the accuracy ofthese lengths which determine the starting frequencies. When thebond-wire is made too short during VCO assembly, the varactor must bereplaced since the pull strength of the diode bondpad is too low for thefirst wire to be removed and a second wire to be attached. With an MMICVCO all the critical components can be produced photolithographicallyto high accuracy which together with the employment of ion-implantedlayers for the FETs and diodes can lead to reproducible oscillatorparameters.

Common gate VCO configurations have become the most popular cir-cuits since they offer intrinsically wide tuning bandwidths. MESFETS-parameters measured in common-source configuration are convertedto equivalent circuits and then transformed to common gate devices. Forexample, FETs with gate lengths between 0.7 and 1 micron are suitablein common gate oscillators up to 18 GHz, the oscillation frequency beingdetermined by total gate width and gate regenerative feedback induc-tance. Stability circles can be generated for a number of gate inductancevalues. Thus, for example, where a 300 micron wide, 0.7 micron longFET is used source reflection coefficients of up to 4 can be induced up to18 GHz with a gate inductance of 0.3 nH. If this gate inductance ischanged from 0.3 to 0.9 nH the region of negative impedance changesfrom 18.5 GHz maximum to 8.7 GHz minimum. By choosing the correctseries inductive/capacitive combination this range of inductance can beeffectively generated by the use of a series variable capacitance. If thesource reflection coefficient phase angle is always positive then capaci-


tance in the source circuit can cancel the phase angle. By choosing thegate and source inductances and capacitances it is possible to tune thegate circuit and cancel the resulting phase of the source reflectioncoefficient with a tunable source tank circuit (Scott et al, 1982).

Figure 7.35 and Figure 7.36 show reflection coefficients at the predictedextremes for a 2 to 4 GHz VCO shown in simplified form in Figure 7.37.The predicted frequency tuning, from a small signal analysis CADprogram, with an 8:1 planar varactor diode capacitance ratio was from2.1 GHz to 4 * 35 GHz (determined by the frequencies at which thesource reflection coefficients have zero phase). The Q factor for thediodes was assumed to be 10 in the analysis. The design used a 1200micron gate width FET chosen to give the best compromise betweenrequired inductor and capacitor values. By using two varactors, one inthe source and one in the gate circuit, the range of frequencies of possibleoscillations is increased in comparison to a design where only onevaractor is used in the gate circuit.

511

Smithchart

Rho axis

-0.25 A

/ -r/

t/[f-0.5

\

-0.25

-3

0.5

\" ^\ "\

X

/ Nv[-0.333 [p

\ A

-0.5

-2 -1

/

4 -

A

V //

\

/

/ ^i

\

L-O-

I ,

0

0.667__ ,

iX! X

V|l-ii- -A^Kf J

-0.667i i i i i i I i i i i

1 2 3

Frequencyrange2-5 GHz

Marked freqin GHz

B = 3

D = 5

Figure 7.35 Reflection Coefficient at Source of Common Gate FETVCO at Maximum Tuning Frequency


511

Smithchart

Rh

0.2 /<

[

V

- 4 -3

0.4

I __

\\

y. \X/ \

\<^^ \

—*—_

-0.4. . i . . . i .

- 2 -1

t i i i

s

- v

"'"" fj**

^-1 > l~

. . I . .

0

R=-1

! ^ > x

1 >/1 ^ ^

. 1 . . . 1 . . . 1 . . . 1

1 2 3 4

Frequencyrange2-5 GHz

Marked freqin GHz

A = 2B = 3C = 4

Figure 7.36 Reflection Coefficient at Source of Common Gate FETVCO at Minimum Tuning Frequency

100PF

RFCRF output

Vgate

100pF

-^V^ Mono I it hiechip

Figure 7.37 Monolithic VCO Schematic


In order to obtain maximum tuning range from such a VCO in MMICform, planar varactor diodes with a large tuning range and low loss arerequired. If the Q of the varactors falls much below 2 in the 2 to 4 GHzdesign outlined above, for example, the analysis predicts that the circuitwill be prevented from maintaining oscillation. Normal varactor diodesuse n+ substrates with a thick n-epitaxial layer onto which the Schottkycontact is fabricated. For MMICs the reverse layer sequence is usedwhereby the n+ layer is grown onto an n-layer which is used for the FETchannel. Selective ion implantation can be used to implant regions of non n+ and n+ on n. Sobhy et al (1985) have reported MMIC VCOs whereinterdigitated Schottky barrier diodes were fabricated using essentiallythe same processing sequence as for the FET. Since the layer thick-nesses in the diodes were the same as in the FET the diode capacitanceratio can only be adjusted by independently recessing the anode allow-ing the depletion layer to punch-through to the buffer layer. It can becalculated (Brehm et al, 1981), for an n-layer donor concentration of 2x 1017/cc, 2 micron anode finger width, 100 micron finger length and 10fingers, that the zero voltage capacitance should be approximately 3.7pF including depletion layer sidewall capacitance.

The design route described briefly above is based on small-signal analy-sis. Such analysis does not take into account changes in the parametersof both the FETs and diodes under large signal, non-linear operation. Anumber of non-linear analysis programs are available and some of thesehave been described in Chapter 5. Such programs not only allow anaccurate prediction of tuning range but also allow the fundamental andharmonic power to be determined as well as any possible circuit prob-lems such as varactor overdrive leading to reduced reliability.

Two examples of MMIC oscillators are given in Figure 7.38(a) and (b).In Figure 7.38(a) is shown a 2 to 4 GHz VCO by Plessey which, in practicetunes from 2.9 to 4.5 GHz with a mean output power of 15 dBm and ad.c. to r.f. conversion efficiency of 27%. The MMIC chip, which is 1.8 x1.3 mm, contains decoupling capacitors as well as the FET, varactorsand other tuning elements. Figure 7.38(b) shows a similar circuit byTexas Instruments (Scott et al, 1984) which tunes from 7 to 12 GHz usinga 600 micron gate 600/*m FET. Output power was approximately 16dBm with a tuning range from 6.97 to 12.2 GHz. MMIC chip size was1.84 X 1.44 mm.

It can thus be seen that high power wideband varactor tuned microwaveoscillators can be obtained using GaAs FETS. The efficiency of theseoscillators is generally higher than Gunn or IMPATT diode tunablesources. The noise performance of GaAs FET tunable oscillators is also


Mr" _ -

1.84mm

7-12 GHz VCO

Figure 7.38 (a). 2-4 GHz MMIC Voltage Controlled Oscillator (b).7-12 GHz MMIC Voltage Controlled Oscillator


better than IMPATT oscillators. These tunable FET oscillators are nowbeginning to influence the design of microwave systems.

7.11 Yig Tuned GaAs FET Oscillators

Over the last several years, the YIG tuned Gunn oscillator has virtuallyreplaced the Backward Wave Oscillator (BWO) for X and Ku band signalsources such as in sweep generators, spectrum analyzers and militaryECM applications. However, with the emergence of the GaAs FET andits advantages over the Gunn-effect device it has become more attractiveto use it in similar applications. One factor which has made the choicemore attractive is that there is no physical limitation on the lowestpossible oscillation frequency of the FETs. Thus, with a judicious choiceof feedback network it is possible to obtain negative resistance conditionover a broad band of frequencies extending from 3 GHz or below to upto 18 GHz.

7.11.1 YIG Resonators

Single crystal Yttrium Iron Garnet (YIG) and gallium doped YIG arepart of a family of ferrites that gyromagnetically resonate at microwavefrequencies when immersed in a magnetic field. The rate of the ferriteinternal electron precession is 28 GHz/Tesla of the magnetic field withinthe ferrite and thus can be simply altered. The resonance frequency f0for an isotropic sphere in a magnetic field Ho is given by

fo=vHo 7.35

where v is the gyromagnetic ratio (28 GHz/Tesla).

Microwave energy can be coupled to the YIG sphere through a loop inthe plane of applied magnetic field Ho encirling the sphere. The equiva-lent circuit is shown in Figure 7.39 where Li is the self inductance of theloop and the parallel tuned circuit elements are related to the unloadedQ (Qu) of the YIG resonator (Carter 1961, Olliver 1972).

L = R°° Q 7-36


Coupling loop

YIG sphere

Figure 7.39 YIG Resonator and its Equivalent Circuit

where

jiio = permeability of free space

V = volume of the YIG sphere

k = Vdi = coupling factor

di = loop diameter

com = 2jrfm = 2;ri>(4#Ms)

4TTMS = saturation magnetization

The input impedance of the combination is given by:

Zin = ja)Lj+ ^—S 7.37

The unloaded Q, Qu of the resonator is related to the saturation mag-netization and is given by

„ 1

7.38AH

/ * J mo ~,

vAH


where AH is the resonance line width.

The premature decline phenomena or low level limiting (Olliver 1972)inside the YIG sphere limits its use as a high Q resonator to frequenciesabove fmin, where fmin is given by

7.39

From Equation 7.35 it can be seen that by linearly varying the magneticfield applied to the YIG sphere the oscillation frequency can be linearlyvaried. Thus linear variation of the coil current in the electromagnetwill give rise to linear frequency variation if no magnetic saturationtakes place in the electromagnet. Another important point to note fromEquation 7.38 is that the unloaded Q increases with frequency for theuseful operating range of the resonator.

7.11.2 Performance Review

A number of workers have used the grounded gate configuration withseries inductive feedback for the YIG tuned FET oscillator. The YIGresonator is coupled to the source terminal through a coupling loop andthe output is connected to the load through a matching network (Figure7.40). Negative resistance condition appearing at the sourcegate port isexpressed in terms of | SuT | > 1 and has been used to obtain tuningrange over the entire X-band.

For a circuit configuration in which the drain port is match terminatedthe gate feedback inductance which results in | Sn | > 1 can be evaluatedand the inherent trade-offs studied. In most cases the feedback induc-

Figure 7.40 YIG Tuned Oscillator Schematic


tance itself is not sufficient to provide | Sn | > 1 over an octave or largerbandwidth.

Trew (1980) used additional parallel feedback between the source anddrain terminals which caused an effective increase in the total band-width. With this compound feedback scheme and without any matchingat the output port it was possible to obtain oscillations from 5.9 to 13.25GHz. A minimum output power of 8 mW was obtained from 5.9 to 12.5GHz with a peak power of 22 mW at 6 GHz and a peak efficiency of 8%.

The alternative technique of presenting a negative resistance conditionis to mismatch the output or drain port in such a way so as to have thesame phase as the Sn' vector at all frequencies of interest and conse-quently to result in | SnT | being greater than for the desired frequencyrange. (Section 4.A). When the drain port is terminated in a reflectioncoefficient FL, SnT is given by

o T _ r, , , ^72^2777 - 77 + / 7.40

The objective is to choose a FL at all frequencies of interest so that | SnT |> 1 for a particular feedback inductance. The values of FL which satisfythis condition define a circle in the FL plane.

This FL circle can be constructed by solving for

p = 77 *n 7 4 1

^12 ^21 ™77 ^22 ^11 ^22

where SnT = lei0 and 6 = -180 to +180°.

Papp and Koyano (1980) plotted stability circles for |Sn T | = 1. Thecenter of the circle and its radius are given (Carson 1975) in Equations,7.42 and 7.43 respectively.

s22'*-V(V*s22'*-V*s2/*)C = : # — '2 7.42

\b22 I P77 ^22 ^12 d21 \

R=. |2 lSl2S21 5- 7.43

|°22 I P77 ^22 ^72 °27 |


The region inside or outside the circle represents the unstable region forwhich | SnT | > 1 and can be determined in a similar manner as foramplifiers.

Once the stability circles are plotted the load trajectory of TL withfrequency that would be necessary to produce oscillations in the requiredfrequency range can be determined. The design problem then reducesto the construction of a matching circuit which simulates the behaviourofrL.

Figure 7.41 indicates the stability circles for a 1 nH feedback inductancefor a grounded gate NEC 388 FET as reported by Papp and Koyana(1980). The arrows point to the desired unstable region and the trajec-tory for output reflection coefficient from 8 to 18 GHz is also indicated.Realization of a circuit which behaves in the desired manner is done bytrial and error-direct synthesis techniques have not been devised.

Trew (1980), Basawapatna and Stancliff (1979) and Papp and Koyano(1980) used empirical techniques to design the drain matching networkwhich provided the necessary performance. Basawapatna and Stancliff(1979) did load pulling measurements to verify the required trajectory.Their YIG tuned FET oscillator followed by a single stage amplifierprovided tuning from 5.5 to 14.1 GHz with 15 dBm minimum power from5.9 to 12.4 GHz. The design technique was applied to a bipolar oscillator

Figure 7.41 Stability Circles Together with Load TrajectoryAcross the 8-18 GHz Range


and provided tuning from 1.8 to 9.3 GHz, The circuit realized by Trewhad a tunability of 7.9 to 14.4 GHz with 10 mW minimum power from7.9 to 14 GHz and a conversion efficiency better than 6%. A postamplifier stage was not used in this case. Papp and Koyano (1980)achieved a tunable range of 7.9 to 18.5 GHz with the basic oscillator andwith the oscillator and a buffer amplifier, The results are indicated inFigure 7.42 and represent the highest power achieved so far with anunbuffered oscillator in this tuning range. Oyafuso (1979) presented theresults of the first YIG tuned FET oscillator which provided a tuningrange of 8-18 GHz. Buffer amplifiers were used to obtain a power levelof +10 dBm, Heyboer and Emery (1976) and Ruttan (1977) reportedinitial performance results on YIG tuned FET oscillators.

Careful circuit layout is necessary in order to prevent spurious oscilla-tions. These can occur when the oscillation conditions and the stabilitycriteria are satisfied even with no YIG bias. These oscillations aretermed spurious because they do not tune with the YIG resonator. Theactive circuit and the resonator need to be carefully designed to elimi-nate the possibility of spurious oscillations. The coupling loop induc-tance should be minimized so that the spurious oscillation frequencyoccurs out of the negative resistance condition. Parasitic source toground capacitance should also be minimized. Trew (1980) and Pappand Koyano (1980) have discussed the spurious oscillation problem insome detail.

20

18

E 16• o

i> 14

8. 12

1 10o

8

6

^ "^^^Oscillator with buffer amplifier

Oscillator onlyN.

\

3 10 12 14 16 18Frequency • GHz

Figure 7.42 Power Output Versus Frequency Across the 8-18 GHzBand for the Oscillator with and without Buffer Amplifier


A rather unique approach has been taken by Le Tron et al (1979) for thedesign of YIG tuned FET oscillators. They used a common YIG resonatorcoupled to both the source and gate port of the FET. In this configurationthe negative resistance condition is obtained only for a narrow range of50 MHz. However, as the magnetic bias is changed both the source andgate ports track together providing a tuning range of 3.5 to 14 GHz.

7.12 Pulsed RF Oscillators

During the last several years solid state microwave devices have madepossible many novel applications in radar techniques for measurementof range and velocity and have enabled utilization of these systems formany commercial non-military applications. The radar problem con-sists in the unambiguous determination of the range and/or velocity ofthe target remote from the sensor, The properties which may be used tocharacterize target behaviour are frequency, phase and time delay.These parameters are compared between the transmitted and receivedsignals to obtain range and velocity information about the target.

Doppler frequency shift provides an accurate technique for the meas-urement of radial target velocity for many applications. In CW Dopplerradar systems the Doppler shift is proportional to the radial componentof the velocity and is therefore related to the difference between thetransmit and receive frequency. Pulsed RF systems are capable ofproviding both the target velocity and range information. The transmit-ted and received signals when mixed generate the IF signal with theappropriate Doppler modulation impressed upon it. One transient effectwhich can cause problems in pulsed RF systems is the frequency changeduring the RF pulse due to changes within the microwave device. Thisphenomenon is commonly known as chirp, and has to be minimized if itis a significant fraction of or much larger than the receiver bandwidth.Elaborate and expensive techniques have to be employed to minimizethe chirp.

A novel approach for obtaining low power pulsed r.f. oscillators with verylow frequency variation within the pulse uses the dual gate GaAs fieldeffect transistor and indicates yet another application of this flexibledevice.

GaAs dual gate FETs have an inherent property which make themextremely suitable for low chirp pulsed r.f. oscillator applications. Thisproperty can be best illustrated by considering a simple physical modelof the dual gate FET. Figure 7.43 shows the equivalent of a dual gateFET. If the first FET containing gate I is used as an active element for


Figure 7.43 Dual Gate GaAs FET and its Equivalentobtaining steady state oscillations, the second FET containing gate 2 canbe operated as a high speed switch to obtain pulsed r.f. output. This canbe easily done by applying a negative pulse to the second gate.

Table 7.3 indicates the magnitude and phase of the gate 1-to-source andgate 1-to-drain scattering parameters Sn and S31 for different gate 2bias levels. It can be seen that as the second gate voltage is increasedfrom 0 to -0.9V the phase of the input reflection coefficient remainsvirtually unchanged while the forward gain of the device decreases byas much as 6 dB. This minimal phase change in Sn maintains theoperating frequency. However, the phase of Sn changes very rapidlybeyond this level as VG2 is biased towards pinch off. But this phasechange does not give rise to any change in oscillation frequency because

Table 7.3 Input Reflection Coefficient Sn and Forward Gain S31(between Drain and Gate 1) for the Dual Gate GaAs FET as aFunction ofVG2. VGI = -1.03V.

VG2, VoltS

0

-0.4

-0.9

-3.2

Mag

0.56

0.58

0.61

0.62

S11

Phase

-42.0

-42.6

-46.4

-95.3

Mag

1.15

0.93

0.57

0.03

S31

Phase

-58.5

104.8

116.7

171.0


the gain of the device has fallen to the extent that it is not able to sustainoscillations. Thus these two factors-minimal phase change in Sn andreduction of gain | S311 -act in unison to result in minimal frequencychange during the pulse.

On the basis of the above discussion low chirp GaAs dual gate FETpulsed r.f. oscillators can be realized by incorporating feedback andmatching elements between gate 1 and source. The drain/source port iscoupled to the load while modulation is applied to gate 2. An importantfactor to note here is that drain current is virtually zero when the deviceis off. This results in less heat dissipation in the device and thusimproves device reliability because of low operating junction tempera-ture (Joshi et al, 1980).

Figure 7.44 shows a schematic diagram of the dual gate GaAs FETpulsed oscillator. A series feedback element is introduced at the gate 1terminal while the source terminal is capacitively terminated by anappropriate 50 ohm short-circuited line length. The design procedurefor this oscillator was along the lines indicated in Section 4.

Figure 7.45 shows the spectra of the r.f. output for the X and J bandpulsed FET oscillators. From the side lobes of the output spectra ofFigure 7.45 it can be calculated that the frequency variation for theduration of the pulse is approximately 0.3 MHz. The output spectrumwas virtually symmetrical in both cases indicating linear frequencyvariation during the pulse duration (M. Brookbanks, 1980).

Matching O/P matching

Element7fh' Gil

Element

[[Feedbackelements

I

^Pulsed"R.F. output

'^J~LT>v G 2 S

Figure 7.44 Schematic Diagram of Dual Gate GaAs FET PulsedOscillator


IUHHH•HUH

; -AMI* W»7GHZ xt KHZ *tz

* * *t * *

• • • • •••

Figure 7.45 Spectra ofX and J Band Pulsed FET Oscillators

7.13 Conclusions

In this chapter the design and application of the GaAs FET as microwaveoscillators has been covered. It was seen that the introduction ofexternal elements is usually necessary to induce negative resistanceconditions. Apart from the relatively poor close to carrier noise perform-ance of free running GaAs FET oscillators, their other features appearquite attractive. The compatibility of FET oscillator circuits and ceramicresonators have resulted in improved performance of stabilized sources.Electronic tuning capabilities of GaAs FET oscillators using varactordiodes and YIG resonators are impressive and will form importantbuilding blocks for microwave systems.


7.14 Bibliography

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Abe, H, et al. A stabilized low noise GaAs FET integrated oscillator witha dielectric resonator at the C-band. 1977 IEEE-ISSCC Digest, pp. 168-169.

Abe, K. et al. A highly stabilized low noise GaAs FET integratedoscillator with a dielectric resonator in the C-band. IEEE Trans. MTTVol. MTT-26, No. 3, March 1978, pp. 156-162.

Alley, G. and Wang, H. An ultra low noise microwave synthesizer. IEEETrans. MTT, Vol. MTT-27, No. 12, December 1979.

Basanpatna, G.R. and Stancliff, R. A unified approach to the design ofwideband microwave solid state oscillators. IEEE Trans. MTT, Vol.MTT-27, No. 5. Play 1979, pp.379-385.

Bodway, G. Circuit design and characterization of transistors by meansof three port scattering parameters. Microwave Journal Vol, 11, No. 5.May 1968.

Brehm, G.E., Scott, B.N., Seymour, D. J., Frensley, W.R., Duncan, W.N. andDoerbeck, EH. High capacitance ratio monolithic varactor diode. 1981Cornell Conference Digest, pp.53-63.

Brookbanks, M.-private communication, 1980.

Camisa, R. and Sechi, F. ISSCC 1979a Digest, pp,160-161.

Camisa, R. and Sechi, F. Common drain flip chip GaAs FET oscillators.IEEE MTT-27, No. 5, May 1979b, pp.391-394.

Cantle, et al. A coaxial GaAs FET local oscillator and its stabilizationby a temperature-compensated MIIC discriminator, Proc. Eu MC, Paris1970, pp.259-263.

Carson, R, High frequency amplifiers* New York, Wiley 1975.

Carter, P.S. Magnetically tunable microwave filters using single crystalyttrium-iron-garnet resonators. IRE Trans. MIT, May 1961, pp.252-260.

Chow, K.K. On the solution and field pattern of the cylindrical dielectricresonator. IEEE Trans. MTT, Vol. MTT-14, p.439, September 1966.


Cohn, S.B. Microwave bandpass filters containing high Q dielectricresonators. IEEE Trans. MTT, Vol,MTT-16,pp.210-217, April 1968.

COMPACT User's Manual, Compact Engineering Inc., U.S.A.

Courtney, W, Analysis and evaluation of a method of measuring thecomplex permittivity and permeability of microwave insulators. IEEETrans. MTT Vol. MTT-18, pp.476-489, Aug. 1970.

Das, M.D. and Ghosh, P.K. Gate current dependence of low-frequencynoise in GaAs MESFETS. IEEE Electron Device Letters, Vol. EDL-2,no. 8, pp.210-213,1981.

Day, W.R. Dielectric resonators as microwave circuit elements. IEEETrans. MTT, Vol. MTT-18, pp.1175-1176, December 1970.

Debney, B.T. and Joshi, J.S. A theory of noise in GaAs FET Microwaveoscillators and its experimental verification. IEEE Trans, on ElectronDevices, Vol. ED-30, No. 7, July 1983, pp.769-776.

Edson, W. Vacuum pulse oscillators. New York, Wiley, 1953.

Finlay, H., Joshi, J, and Cripps, S. An X-band FET oscillator with low FMnoise,. Elec. Letts, Vol. 14, No. 6, March 1978.

Glance, B. and Snell, W. A discriminator stabilized microstrip oscillator.IEEE Trans. MTT, Vol. MTT-24, Oct. 1976, pp.648-650.

Golio, J.A. and Krowne, C.ll. Microwave Journal, October 1978, pp.59-61.

Gonda, J. Large signal transistor,oscillator design. IEEE MTT-S Digest,p.110-112, May 1972.

Graffeuil, J., Tantrarongroj, K., and Sautereau, J.F. Low frequency noisephysical analysis for the improvement of the spectral purity of GaAsFET oscillators. Solid State Electronics, Vol. 25, No. 5, pp.367-374,1982.

Guillon, P. and Garault Y. Accurate resonant frequencies of dielectricresonators. IEEE Trans. MITT, Vol. MTT-25, pp.916-922, November1977.

Hakki, B.W. and Coleman, P.D. A dielectric resonator method of meas-uring inductive capacities in the millimeter range. IRE Trans. MTT,Vol. MTT-8, pp.402-410, July 1960.

Heyboer, T. and Energy, F. YIG tuned GaAs FET oscillators. IEEE MTT-SInt. Microwave Symposium Dig., pp.48-50,1976.


Ishihara, 0. et al. A highly stabilized GaAs FET oscillator using adielectric resonator feedback circuit in 9-14 GHz. IEEE Trans. MTT,Vol. MTT-28, No, 8. April 1980,

Itoh, T. and Rudokas, R. New method for computing the resonantfrequencies of dielectric resonator. IEEE Trans. MTT, Vol. MTT-25,pp.52-, January 1977.

James, D. et al. Stabilized 12 GHz MIC oscillators using GaAs FETs.Proc. 5th Eu MC, pp.296-300, Sept. 1975.

Johnson, M.M. Large signal GaAs MESFET oscillator design. IEEETrans. MTT-27, No. 3, March 1979, pp.217-227.

Joshi, J.S. and Turner, J.A. High peripheral power density GaAs FEToscillator. El. Letters, Vol. 15, No. 5, March 1979, pp.163-164.

Joshi, J. and Pengelly, R. Ultra low chirp GaAs dual gate FET microwaveoscillator. 1980, MTT-S Symposium Digest.

Joshi, J.S.-unpublished.

Kim, B., Tserng, H.Q. and Shih, H.D. Millimeter-wave GaAs FETs withfmax of over 100 GHz. Abstract of Tenth Biennial IEEE Cornell Con-ference on Advanced Concepts in High Speed Semiconductor Devicesand Circuits, July 1985.

Konishi, Y. et al. Resonant frequency of TEO1 dielectric resonators.IEEE Trans. MTT, Vol. MTT-24, pp.112-114, February 1968.

Krowne, CM. Network analysis of microwave oscillators using micros-trip transmission lines. Elec, Letts, Vol. 13, No. 4, pp.115-117, Feb. 1977.

Kurokawa, K. Introduction to the Theory of Microwave Circuits. NewYork, Academic Press, Chapter 9,1969.

Kurokawa, K. Some basic characteristics of broadband negative resis-tance oscillator circuits. Bell Systems Technical Journal, pp. 1937-1955,July and August, 1969.

Kurokawa, K. Injection locking of microwave solid state oscillators. Proc.IEEE, Vol. 61, No. 10, October 1973, pp.1386-1410.

Lesartre, P. et al. Stable FET loscal oscillator at 11 GHz with electronicamplitude control. Eu MC Paris Digest, pp.264-268,1978.

Le Tron et al, Multioctave FET oscillators double tuned by a single YIG,ISSCC, February 1979, pp.162-163.


Maeda, M.,, Takahashi, S. and Kodera, H. CW oscillation characteristicsof GaAs Schottky barrier gate FETs, Proc, IEEE, February 1975a,pp.320-321.

Maeda, M., Kimura, K. and Kodera, H, Design and performance ofX-band oscillator with GaAs Schottky gate FETs. IEEE Trans. MTT-23,No, 8. pp.661-667, August 1975b.

Masse, D. A new low-loss high r temperature compensated dielectric formicrowave applications. Proc. IEEE Vol. 59, pp. 1628-1629, November,1971.

Mitsui, Y, Nakatani, It. and Mitsui, S, Design of GaAs MESFET oscilla-tor using large signal S-parameters. IEEE MTT-S, Symposium Digest,San Diego, 1977a, pp.270-272.

Mitsui, Y., Nakatani, II. and Mitsui, S. Design of GaAs MESFET oscil-lator using large signal S-parameters, IEEE Trans. MTT-25, No. 12,December 1977b, pp.981-984.

Monham, K.L., Burgess, J.W. and Mabbitt, A.W. PIN-FET receivers forlong wavelength fibre optic systems. Proceedings of Communications'82 Conference, Birmingham, England, pp.280-284,1982.

Mori, T, Ishihara, 0. et al. A highly stabilized GaAs FET oscillator usinga dielectric resonator feedback circuit in 9-14 GHz band. IEEE MTT-S.Symposium Digest, Washington DC, 1980.

O'Bryan, H., Thompson, J. and Plourde J. A new BaO-TiO2 compoundwith temperature stable high permittivity and low microwave loss. J.Am. Ceramic Society, 57(10), 1974, pp.450-452.

Okaya, A. and Barash, L.F. The dielectric microwave resonator. Proc.IRE Vol. 50, pp.208—209, October 1962.

Olliver,. P.M. Microwave YIG-tuned transistor oscillator amplifier de-sign: Application to C-band. IEEEJnl. Solid State Circuits, Vol. SC-7,No. 1, February 1972.

Omori, M. and Nishimoto, C. Common gate GaAs FET oscillator. Elec.Letts, Vol, 11, No. 16, pp.369-371, August 1975.

Oyafuso, R. An 8-18 GHz FET YIG tuned oscillator. IEEE MTT-S Sym.Digest, pp. 183-184,1979.

Papp, J. and Koyano, Y An 8-18 GHz YIG-tuned FET oscillator. IEEETrans. MTT, Vol. MTT-28, No. 7, July 1980, pp.8-14.


Plourde, J. et al. A dielectric resonator oscillator with 5 ppm long termfrequency stability at 4 GHz, 1977 IEEE MTT-S Symp. pp.273-276.

Plourde, J. et al. Ba2Ta9O2o as a microwave dielectric resonator, Jour-nal of American Ceramic Society, Vol. 58, No. 9-10, pp.418-420.

Podcameri, A. and Bermudez, L.A. Stabilised FET oscillator with inputdielectric resonator: large signal design. El. Letts. Vol. 17, No. 1,pp.44-45, January 1981.

Pospieszalski, M. On the theory and application of the dielectric postresonator. IEEE Trans. MTT, Vol. MTT-25, No. 3, pp.228-231, March1977.

Pospieszalski, M. Cylindrical dielectric resonators and their applicationsin TEM line microwave circuits. IEEE Trans. MTT, Vol. MTT-27,No.3,March 1979, pp.233-238.

Pucel, R., Bera, R. and Masse, D, Experiments on integrated GaAs FEToscillators at X-band. Elec. Letts. Vol.11, pp.219-220, May 1975.

Rauscher, C. and Willing, R.A. 1978 MTT, Vol. 26, p.1017.

Rauscher, C. and Willing, H.A, Simulation of nonlinear microwave FETperformance using a quasi-static model, IEEE Trans. MTT, Vol, MTT-270 pp.834-840,1979.

Rauscher, C. Optimum large signal design of fixed frequency and varac-tor tuned GaAs FET oscillators. Proc. 1980, IEEE MTT-S Int. Micro-wave Symp. pp.373-375.

Rauscher, C, Broadband varactor tuned GaAs FET oscillator. Electron-ics Letts. Vol. 16, No. 14, July 1980, pp.534-535.

Rector, R.M. and Vendelin, G.D. A LOW GaAs MESFET oscillator atX-band. IEEE MTT-S. Digest, 1978, Orlando, Florida.

Ruttan, T. X-band GaAs FET YIG tuned oscillator. IEEE MTT-S, Sym-posium Digest, 1977a, San Diego, pp.264-266.

Ruttan, T. GaAs FETs rival Gunns in YIG tuned oscillators. Microwaves,July 1977b.

Saito, T. et al. A 6 GHz highly stabilised GaAs FET oscillator using adielectric resonator. 1979, IEEE MTT-S Symposium Digest, pp. 197-199.

Scott, B. et al. Octave band varactor tuned GaAs FET oscillators. 1981ISSCC Symposium Digest, pp. 138-139.


Scott, B.N., Brehm, G.E. Monolithic voltage controlled oscillator forX-and Ku-Bands. IEEE Trans. Microwave Theory and Techniques, Vol.MTT-30, No. 12, pp.2172-2177, December 1982.

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Sone, J. and Takayama, Y. A 7 GHz common-drain GaAs FET oscillatorstabilised with a dielectric resonator. NEC R & D No. 49, pp. 1-8, April1978.

Trew, R.J. Octave band GaAs FET YIG tuned oscillators. Electron. Letts.Vol. 13,pp.625-630, October 1977.

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Tserng and Macksey. Wide band varactor tuned GaAs MESFET oscillators at X and Ku-bands. 1977, IEEE MTT-S, Digest, San Diego, pp.267-269.

Wade, P.C. X-band reverse channel GaAs FET power VCO. MicrowaveJournal, April 1978a, pp.92.

Wade, P,C. Novel FET power oscillators. El. Letts. Vol. 14, No. 20,pp.672-674, August 1978b.

Yee, H.Y. Natural resonant frequencies of microwave dielectric resona-tors. IEEE Trans. MTT, Vol. MTT-13, pp.256, March 1965.

8

FET and IC Packaging

8.1 Introduction

As has been seen in previous chapters the gallium arsenide field effecttransistor has revolutionized the design of low-noise and power micro-wave frequency amplifiers as well as providing an excellent device foroscillators, modulators and mixers. The GaAs FET is often used in itsunencapsulated or 'bare' chip form in microwave circuits but for manyapplications it is desirable to package the device or devices in wellcharacterized hermetic enclosures, For high frequency applicationsthese packages need to be as small as possible to minimize the effect ofreactances associated with the encapsulation. It is desirable to makethe electrical length between the packaged device and the circuit assmall as possible to avoid large phase angle changes in the input andoutput reflection coefficients as the frequency is changed. Such largephase angle differences lead to an inability to match the packaged FETover wide bandwidths. Small packages, however, tend to increase theeffect of feedback paths thus increasing the | S121 of the FET anddecreasing the frequency range over which the device is stable.

Microwave packaging techniques are only just catching up with therapid advances of the GaAs FET in its frequency performance and itsapplications and it is only recently that some fundamental problemsencountered with certain packaging techniques have been understoodand overcome at frequencies above 15 GHz.

"Pre-matching" the FETs, i.e. including matching circuits within thepackage so that the influence of the package on device performance isminimized, is one effective method particularly suitable for power FETswhere device impedances tend to be somewhat lower than 50 ohms.However, the pre-matching technique is to a certain extent a compromisesolution since it invariably limits bandwidth.

Figure 8.1 shows a photograph of a number of popular microwavepackages used for field effect transistors. Some of these packages, suchas the HPAC 100, are more readily available than others since they arehigh volume industry standard packages used for bipolar transistors.


HPAC 100P107

P103

P109

\

P110

HPAC 170

P108

Figure 8.1 Some GaAs FET Packages (courtesy ofPlessy Co. Ltd.)

Packages which have four leads such as the HPAC 100 result in deviceperformance compromises since such leads and their connections to theFET inside the package are electrically long at the higher frequencies.

8.2 Packages and Sealing

Package styles, materials, properties and manufacturing processes allinfluence their design. Such designs in turn influence device perform-ance whilst assembly and sealing techniques effect performance, yield,cost and reliability.

Packages can be divided into three main constructional types:-

1. Cofired ceramic

2. Hard fired ceramic

3. Glass-metal.

A cofired multilayer ceramic package involves the lamination and met-allization of two or more layers of ceramic in the unfired or 'green' stateand subsequent firing of the structure to form a simple, homogeneouspackage. Figure 8.2 shows an example of such a package, the P109,which enables GaAs FETs to operate with good performance up to 18GHz. The ceramic walls of the package are brazed to an oxygen-freecopper base enabling the FET source pads to be bonded to an effective

FET and IC Packaging 405

Figure 8.2 P109 GaAs FET Package (Courtesy ofPlessy Co. Ltd.)

microwave ground. The base to ceramic interface is important and carehas to be taken to avoid cracking the ceramic during brazing caused bythe different coefficients of thermal expansion between the aluminaceramic and the copper. Packages of the cofired type are usually sealedwith a gold-plated thin metal lid using a gold-tin solder preform.

Figure 8.3 shows an example of a glass-metal package which althoughpopular for such microwave components as PIN diode limiters, attenu-ators and switches has not found popularity as a FET device packagebecause of its relatively high cost in comparison to the cofired ceramicpackage. The glass-metal package is, however, finding increasing appli-cation for compact sub-system integration (Galli et al, 1980) as well asbeing a suitable packaging technique for GaAs integrated circuits (ICs)(covered in Chapter 10). Hard-fired ceramic packages usually consist ofseparate ceramic and metal parts which are held together by the use ofbrazes, epoxies or glasses.

Packages are sealed with either a ceramic or metal lid usually using agold-tin solder preform which has a melting point of 280°C. This tem-perature is ideal for the GaAs FET as it does not lead to degradation inthe device's performance. Temperatures in excess of approximately 350°C can affect the gallium arsenide due to arsenic outdiffusion and for thisreason sealing techniques are somewhat limited. Glass sealing using aceramic lid can be a very low-cost alternative to metal seals and the


Figure 8.3 Glass to Metal Seal Package

elimination of the metal sealing ring on the top of a ceramic package(Figure 8.1) can lead to reduced package capacitance.

The use of epoxies for lid sealing can be applied to certain high frequencymicrowave packages such as the dual gate FET package of Figure 8.4.where hermetic sealing can be achieved. However, there is no epoxyavailable to date which can provide an adequate moisture barrier andindeed many epoxies will not withstand temperature cycling over theusual military temperature range of -40°C to +80°C. Glass sealingusing a ceramic lid can be a very low cost alternative to metal seals. Thedevelopment of a low melting-point glass which does not absorb mois-ture and is hermetically inert (at least, to the types of reagents used inthe manufacture of FETs and packages) is mandatory to the success ofthis approach. Glasses approaching these desirable conditions are nowavailable including materials which melt at 385°C. By using heatedpackage holders and pulsed sealing techniques or using lasers it ispossible to seal effectively small packages without raising the FET chiptemperature higher than 300°C.

The design of a small, high frequency package is often constrained bythe need to allow ease of wire bonding of the chip. This results in severeconstraints on metal-to-metal sealed ceramic packages.

The metal sealing ring of many multilayer ceramic packages itself formsa resonant structure when coupled by the ceramic walls to the input and


Figure 8.4 P106 Epoxy Sealed GaAs FET Package (Courtesy ofPlessy Co. Ltd.)

output leads. This produces a low Q resonance in the package input tooutput isolation characteristic. This resonance is usually only modifiedby the presence of the metal sealing lid, careful package design and lidgrounding being required to move the resonance to a higher frequencywhere the FET is not to be operated or to remove it altogether. Eventhough the lid may be 'grounded' by package metallization the resonancemay only be moved in frequency.

8.3 Package Modeling

Microwave modeling of packages is most important especially beforecommitting considerable effort and money to tooling for a new design.An equivalent circuit for a package is shown in Figure 8.5(a) togetherwith the origins of the package parasitics in Figure 8.5(b). Wire bondsto the FET are modeled as the gate inductance LG, the source inductanceLs and the drain inductance LD. There is also an inductance LM createdby the source lead metallization of the package and the package mount-ing. In Figure 8.1 for example some of the packages have a larger valueof LM than others due to the length of metallization between the sourcepads and the 'through wall' metal to the outside leads. To aid indecreasing this inductance the two source pads are connected bothinternally and externally as shown in Figure 8.5(b).


Figure 8.5 (a). Typical Equivalent Circuit for a GaAs FET Package(b). Origins of Package Parasitics

There are a variety of capacitances which include input and outputshunt values CIN and COUT created by the package geometry andmounting, Feedback capacitances CPI and CF2 are extremely importantand need to be minimized. They are caused by the internal packagemetallization geometry and the external lead sizes respectively. Theway in which these capacitances affect performance is demonstrated bycalculating and measuring the gains and stability factors of FETs indifferent package styles (Barrera et al, 1979). Figure 8.6 shows forexample, the relative gains of two packaged 1/um. gate length, SOOjumgate width FETs one in a cofired ceramic package (HPAC 100) and theother a low parasitic hard-fired package, the P103 (Pengelly, 1979).Grounding the lid and reducing lead pad size and proximity can be usedto minimize CFI and CF2. The need for small, yet repeatable parasitics


14

12

10

Gain, dB8

6

4

2

0j

^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ P 1 0 3 ^ ^ ^

^ ^ \ ^ P 1 0 7 ^ ^ ^ -

VDS = 5v ^ ^ \ ^ ^VGS = 0v ^ " " ^ *

GAT 5

3 10 12 14 16 18

Frequency, (GHz)

Figure 8.6 Comparison of Gains as a Function of Frequency for 1/umGate Length FET in Low-Parasitic P103 Package and Co-fired P107(HPAC 100) Package

often forces the package designer to impose tight dimensional toleranceson the already difficult to manufacture package.

Finally there are transmission line segments TIN and TOUT. Suchpackages as the HPAC 100 have the gate and drain connections broughtinto the package sandwiched between two ceramic layers which arebounded by the metal lid and the backside metallization. Such aconfiguration sets a limit on the characteristic impedance of the linesleading to and from the chip.

Providing CFI and CF2 can be minimized, the one parameter in a commonsource bonded FET that needs to be minimized is the source leadinductance. This is made up of the wire bonds, package metallizationand package to ground path defined by the chip mounting. Figure 8.7shows the effect of common lead inductance on a packaged 0.5//m lengthsmall signal FET where it may be seen that well over 6 dB change ingain results from introducing only up to 0.2 nH inductance in the sourcelead at 8 GHz. More importantly, the device is potentially unstable withinductances greater than 0.05 nH.


m

•is

•*-' CO« >

Iif

Unconditionally stable Conditionally stable

GAT6/P109 VDS = 5 volt|os = 10mA

f = 8GHz

0.04 0.08 0.12 0.16

Source lead inductance, nH

0.2

Figure 8.7 Effects of Source Lead Inductance on Gain of PackagedGaAs FET

8.4 Prematched GaAs FETs

The microwave design engineer often requires a packaged FET whichwill enable him to produce broadband amplifiers-typically of octavebandwidths-at frequencies up to 20 GHz. The scattering parameters ofsuch packaged devices (particularly Sn) rotate in phase on a SmithChart much too quickly to allow optimum matching over the requiredfrequency range. This is particularly true of power FETs where thevalue of gate-to-source capacitance is much larger than in a small signaldevice.

Conventional microwave amplifiers are usually designed using a dis-tributed approach which necessitates using a relatively large area ofdielectric for the microstrip circuitry. The only lumped' componentsused are usually the wire-bonds connecting the device either to thepackage or, in the case of chip devices, to the circuit. The pre-matchedtechnique in which the matching circuit is incorporated in the devicepackage is a low cost approach tb avoiding the problems of packageparasitics or, indeed, incorporating them as part of the matching circuit.For many chip FETs, Sn* or optimum noise impedance are convenientlymatched over wide bandwidths using simple inductive and capacitive


10 12 14 16 18 20Frequency, GHz

Figure 8.8 (a). Lumped-Element Broadband Matching Circuit fprGAT6 in P105 Package (b). Measured Response of BroadbandPre-matched GAT6 (c). Typical Prematched Transistor in Package(J-band Medium Power Amplifier)


8

GaindB 7,

6

0

10Returnloss, dB 20

30

Pout,'dBm

Input/

12 13 14

Frequency, GHz

15

Frequency = 14GHzPout at idBgainCompression = 20.5 dBm

2 4 6 8 10 12 14 16 18Pin, dBm

Figure 8.9 Response of Pre-matched J-band Medium PowerTransistor

components. This takes the form of wire bond lengths and chip capaci-tors (using MOS or MIS structures). The FETs can be self-biased by theuse of bypass capacitors on the source together with chip resistor arrayswhose value is selected on test.

For example Figure 8.8(b) shows the response of a single stage GaAsFET which has been prematched over the 10 to 20 GHz frequency rangeusing bond wires as inductors and chip capacitors as matching compo-nents (Pengelly et al 1979), as may be seen in the circuit diagram ofFigure 8.8(a). Figure 8.8(c) shows the general form of such a circuit. Aresistor array is used for self-biasing the FET as well as a source bypasscapacitor. It may be seen from Figure 8.8(b) that greater than 5.5 dBgain is achieved with a gain flatness of ± 0.2 dB. A medium powerprematched FET result is shown in Figure 8.9 where small signal gainsof 6 to 7 dB over 12 to 15 GHz were achieved with a 1 dB gaincompression point of over 20 dBm at 14 GHz. The placement of wirebonds can be made accurately by the use of an automatic bonder leadingto reproducible performance.

An extension of this technique is the matching and combining of powerGaAs FETs within a package to produce powers, at present, up to 15 to20W (Takayama et al, 1979) with good power added efficiencies andreasonable bandwidths. Figure 8.10 shows an example of an internally


Figure 8.10 Compact Power FET Module Showing Wire BondInductances and Parallel Plate Capacitances

Figure 8.11 Equivalent Circuit of'Internally Matched'Power FETshown in Figure 8.10.


matched power FET amplifier where the inductors are formed usingwire bonds and shunt capacitors are formed by the parallel platecapacitance of the metallized areas on high dielectric constant substratematerial. Figure 8.11 shows an equivalent circuit of this arrangement.

8.5 Packaging and Thermal Resistance

One of the most important properties of a package relating to devicereliability and its derating of maximum power dissipation above ambi-ent temperature is the thermal resistance of the structure. The totalthermal resistance of a packaged device will depend on the chip thick-ness, the way the chip is secured to the package and the package itself.In the latter case, for example, the P108 package of Figure 8.1 has betterthermal properties than the HPAC 100 package since in the first casethe chip is mounted directly onto the grounded metal base of the packagewhilst in the second the chip is mounted on a thin metal strip on theceramic. This thin strip is connected to the heat sink outside the packageby the same leads that act as the source connection.

Figure 8.12 indicates the way in which the channel temperature of aFET is composed of

TCH = TA + PD^cMp +Q solder + # amount)

Channel temperature, TCH

9 Chipf

9 Solder

Solder or Epoxy

10 Mount— J ^ ^ \ \ Y > r - - ^

Heat sink (TA)

Figure 8.12 Origins of the Thermal Resistance of Mounted GaAsFET Chip


where TA is the ambient temperature PD is the dissipated power and#chip, solder and Amount are the various thermal resistances where we haveassumed the chip is secured to the package using a eutectic preform.There are two general cases for thermal resistance (Pritchard, 1967),depending on the mode of heat flow. If the thickness of the chip materialis small compared to the lateral dimensions of the device and chip, heatwill tend to flow in a vertical 'column'.

If the chip material is thick compared to the device size, and the devicedimensions are less than 20 percent of the chip side dimension a'spreading' heat flow can be assumed. Generally FET dimensions,particularly power devices, fall into a region somewhere between spread-ing and columnar flow. Unlike the calculations performed for silicontransistors, the calculations performed for GaAs FETs (Cooke, 1978)have taken into account the fact that the heat source is made up of long,thin lines-the channels. Thermal resistance for a FET can be approxi-mated by drawing an analogy between fringing capacitance for anelectrical conductor and thermal heat-flow spreading.

Since the capacitance per unit length of a transmission line is ( 120JZE)/ZOwhere Zo is the characteristic impedance, formulas for transmission linecharacteristic impedance may be used to calculate thermal resistance,Using a formula for stripline characteristic impedance (Cohn, 1954) andthe equivalent ideal line (Oliver, 1955), we can derive the followingequation for a FET consisting of a single gate.

2KTHK(k')

where k = seem —— .L 4F J 8.1

andk' = tanh\^-\\_4F J

Where

LG is the gate length

F is the chip thickness

WG is the gate width

KTH is the thermal conductivity (0.44 for GaAs)

K is the complete elliptical integral of the first kind


6.0

rl , oI

4.0

360.1

Chip thickness = 125Mms

\

, i . . . . i i TXi •0.5 1.0 2.0 4.0

Gate lenath (urn)

Figure 8.13 Thermal Resistance of Single Gate GaAs FET

Equation 8.1 will be modified for multigate FETs since there is thermalcoupling and heat transfer between gates (see Chapter 3).

Equation 8.1 has been evaluated for GaAs FETs on a lOQam thick chipfor gate lengths of 0.1 to 4jum. (Figure 8.13) and Table 8.1 compares thethermal resistance of FETs with various gate length and gate-widthcombinations.

From reliability data (Drukier, et al. 1979) it is generally concluded thata GaAs FET channel temperature should not exceed 125°C.

Consider, for example, the GaAs FET in Table 8.1 having a thermalresistance of 19.5°C/watt, To this must be added the solder thermal

Table 8.1 Thermal Resistance of Various Gate Length I Gate WidthFETs

Gate Length (win)

0.5

0.5

1.0

1.0

Gate Width (am)

150

300

500

2400

0 W G ( ° C W ~ 1

cm"1)

5.17

5.17

4.68

4.68

0(°CW~1)

345

172

93.6

19.5


resistance and package thermal resistance giving a typical total of40°C/W. Under CW conditions with a heat sink temperature of 25°C:

125 = PD(70)+25°C

and therefore, PD = 2.45 watts.

Thus the device must not dissipate more than 2.45 watts. A FET witha gate width of 2.4 mm will give an r.f. output power of approximately1.5 watts with a power-added efficiency of 35% and 10 dB power gain at4 GHz, for example. Dissipated power will, therefore, be 2.35 watts, i.e.within the figure calculated. However, for higher ambient temperaturesthe power output and/or gain of this power FET would have to bederated. It may thus be appreciated that, particularly for power FETs,the thermal resistance of a package plays an important role sincewithout due attention particularly to chip mounting channel tempera-ture limits can be easily exceeded. Thus many power and small signalFET packages are designed to exploit the good thermal and electricalproperties of a copper base at the bottom of the structure.

Figure 8.14 Photograph of Integral Glass-to-Metal 50 ohm


8.6 GaAs IC Packaging

Chapter 10 gives an extensive account of both analog microwave anddigital GaAs ICs design. However, this section summarizes some of thework associated with the design and fabrication of microwave packagessuitable for integrated circuits.

Unlike the packages for transistors already described where the imped-ance of the leads and metallization need not be 50 ohms (because theeffects can be taken into account in the design of the circuit for whichthe device is being used), microwave IC packages need to have eitherelectrically very short leads or leads that are matched to 50 ohms. Thereare a number of ways in which this can be achieved largely dependingon the frequency range of application and the required physical size ofthe package. Glass-to-metal seal 50 ohm feedthroughs can be used insmall metal packages. An example of such a feedthrough is shown inFigure 8.14. The inner lead is usually attached to a small piece ofmicrostrip either by conductive epoxy or a short preformed gold tape.The microstrip insert then interfaces to the microwave IC as shown inthe schematic diagram of Figure 8.15. The lid of the all-metal packageis either laser welded or soldered to the package walls. Most glass-to-metal seals are thermally expansion matched to Kovar which deter-mines the package material.

,Laser weld or solder

Package wall

Glass 50flfeedthrough /Alumina substrate

Metal base

Schematic of glass/metal package

Figure 8.15 Schematic of Glass I Metal Package


Ground planeattachment pad

Exploded view, top

Kovarcover

RF throughhole (typ A places)

Circuit

Groundingthrough hole(typ A places)

Ceramicsubstrate

Plated lead"attachment pad

lead

Brazedfillet

Kovarleadframe

Substrate

Bottom

Figure 8.16 Schematic ofTlanar Pak'from Avantek

Or

1/1*

3-2

3

-

f

0.01

-^ J-oss

7\7/ v

Kl Return lossi i

A 8Frequency

i

12GHz

i16

1°\-

CD

- 1 0 aT01o

-20 §

20 ^

Figure 8.17 Performance of Package shown in Figure 8.16


Microstrip \

Metal

Alumina

Feedthrough

Figure 8.18 (a). Photograph of Package using CofiredAlumina /Metal, Microstrip Feedthrough (b). Schematic of CofiredAlumina/Metal, Microstrip Feedthrough


Where the electrical length of the feedthrough can be kept short and anapproximate 50 ohm impedance produced it is possible to producepackages such as the one shown in Figure 8.16. This package is proprie-tary to Avantek (de Boo, 1984) and has been used to package a numberof monolithic and conventional hybrid circuits up to 18 GHz.

The lead-ins to the package are formed on the reverse side of a thin-filmalumina substrate with plated through holes used to connect the reverseto the top-face. The substrate also contains ground metallization whichis via'd through to the reverse side of the substrate carrier, thus allowingthe metallization to be grounded as effectively as possible. A 'top-hat'style metal lid is welded to the peripheral metallization on the top sideof the substrate following the die and wire bonding of the componentson the alumina. The intrinsic performance of the package is demon-strated in Figure 8.17 showing that quite respectable VSWRs aremaintained as far as X-band.

Fujitsu have successfully used the package shown in Figure 8.18(a) upto 18 GHz or so. This package is a good example of a design whichemploys both co-fired ceramic and brazing technology to produce pack-age leadthroughs having 50 ohm impedance. The leadthroughs areproduced by employing square cross-section coaxial aluminafeedthroughs, as can be seen from the diagram of Figure 8.18(b). Thesetiny feedthroughs are brazed into the copper wall frame of the package.The advantage of such an approach, apart from producing a 50 ohmimpedance, is that each feedthrough is electrically isolated from itsneighbors thus reducing crosstalk between leads. The base of thepackage is gold-plated copper which allows a low thermal impedance

Approximate s ^ e ^ ^ T v ^ v ^ Grounding6mm s q u a r e ^ ^ T j s N v belt

JEDEC leads

Figure 8.19 Two Layer Microwave headless Chip Carrier


Metal _ - .lid ~~~^

Solderseal N . Vic / 7

( • ' : ' . . • • • • • . • • : . • • . • ; • . • • ; • . • • • • [ | : • ; • . . •

r-..-|f-!:.^v::::v,:-:

;-:. k:i:.:ii^:\

GaAs ICBypas:apaci

1

5

tor

;yia;-'.-_

:-:V.: :'•.:/. Fnrth'

Signal line

!:• ••:.•• 1 Polyimide

Thermal columns

• • • S o l d e r bumpBottomground/output

Figure 8.20 Multiport Package for GaAs ICs

path between the IC and the subsystem heat-sink onto which thepackage is mounted. The packages are also capable of being cascadeddirectly.

It has been possible also to convert Si IC packages to operate successfullyup to 5 GHz or so. One example is the Microwave Leadless Chip Carrier(MLCC) (Cooper et al, 1984) which is an adaptation of a standardJEDEC outline leadless chip carrier. Figure 8.19 shows a diagram of anexample of such a package where the internal metallization of some ofthe leadthroughs has been altered but more noticeably a 'belt' of goldmetallization runs around the package base both inside and outsideoffering an effective r.f. ground and improved thermal dissipation.

Significant work has also been completed on the use of novel materialsto produce multiport packages. Rowe et al (1984) have described pack-ages produced using a multilayer polyimide approach. The basic designphilosophy can be seen in Figure 8.20. Three ground planes are used toisolate the two functionally distinct regions of the package, namely, thesignal plane which is basically stripline utilizing the top and interme-diate ground planes, and the power plane which is also stripline utilizingthe intermediate and bottom ground planes. The top ground planeserves to isolate the signal lines from the cavity formed by the metal lid,preventing undesirable coupling between signal lines and eliminatingcavity resonances. The three ground planes are periodically shortedtogether through the vias. The copper thermal columns form a continu-ous thermal path from the bottom of the chip to the underside of thepackage. Thermal resistances of 6 deg.C/watt have been measured.


The overall package is designed to JEDEC standard size. The total delaytime in the signal lines was 180 psec. The packages have been employedup to 12 GHz with return losses of greater than 10 dB on all signal linesterminated in 50 ohms.

8.6.1 Digital Packaging

A significant adaptation of the MLCC has been reported by Gheewala(1984) for digital GaAs ICs. For digital ICs the package must have shortdelays to maintain the highest performance at packaged system levelas well as to minimize ringing caused by package loading effects.Secondly, the package must minimize cross-talk and power supplyinduced transients caused by extremely fast signal rise and fall times.The package dielectrics and conductors must be capable of handlingmulti-gigahertz signals without significant losses.

These features will now be discussed with reference to leadless chipcarriers.

8.6.1.1 Size and Delay

Chip carriers require to be as small as possible within the constraintsof the required number of inputs and outputs and pitch dimensions. Inaddition the carrier is made of a low dielectric constant material tominimize propagation delays. A carrier made from silicon dioxide hav-ing dimensions of 1 X 1 cm has a delay of approximately 35 psecs.

8.6.1.2 Loading

Where a transmission line carrying high-speed signals encounters achip-carrier interface, the signal encounters effectively an open circuitstub. Three techniques are available to minimize the standing waveratio of the carrier interface. The effective stub length can be minimized;the stub can be made as high an impedance as physically possible or adamping resistance can be placed in series with the stub.

8.6.1.3 Cross-Talk

Shielding of individual signal lines within the carrier is needed since,for example, a pulse having 100 psec rise and fall times can cause across-talk signal of 100 mV per volt of signal per centimeter of un-


t

S

Lid/

I/O

™—-

/

Ceramic

As

• hSi

Chip capacitor

i_ ;GaAs:iC{]• • • . : • : • : * : • : • • • . :

^ | )•:

- s i r . : . : . . : •I - - : ' . • • • . • . • : / • • . : • . - . • :

: • • . • • . • • . • • • • / • . • . • • • . • : •

JJ

/ /

Ground plane Signal line

GaAs IC/

/ - • „.,,„-„-...

/ • • •

/

chip carrier

I/O

Ground

Figure 8.21 (a). Multilayer Ceramic Carrier (b). Silicon ChipCarrier for GaAs IC

shielded line. Shielding can be produced by alternating ground stripsbetween the signal lines or by introducing a ground plane close to thesignal lines.

8.6.1.4 Power Supply Induced Transients

A transient in the power supply voltage to the IC can be caused when alarge amount of current is either switched ON or OFF at high speed dueto the series impedance of the power supply. For example, a 20 mA signalwith a 100 psec rise or fall time can generate an approximate 1 volttransient in the power supply voltage in a package with 5 mm long wirebonds. This power supply transient can only be reduced effectively byincluding low inductance decoupling capacitors within the carrier, ashort wire bonding distance from the IC.

Gheewala has described two carriers designed to minimize the aboveproblems. A multilayer chip carrier is shown in Figure 8.21(a) whilst asilicon chip carrier is shown in Figure 8.21(b). The multilayer ceramicchip-carrier consists of four metallized layers. The first layer providespads for interconnection of the package to the motherboard and alsoprovides metallized holes through the ceramic to reduce thermal resis-


Table 8.2 Properties of Ceramic and Silicon Chip-Carriers

Feature

Overall Size (cm x cm)

I/O Propagation delay (pS)

Thermal resistancechip-to-case(deg.C/Watt)

Max. crosstalk from 1 voltsignal with rise andfall-times of 100pS(mV)

Integral bypasscapacitance (pF)

Series inductance ofbypass capacitance (nH)

Ceramic Package

1 x 1

50

10

60

100

2.5

Silicon Package

1 X 1

35

5

40

300

1.5

tance and also provide an effective ground return path. The second layerprovides a ground plane to shield the signal lines as well as to providea die attachment area. The third layer provides the signal interconnec-tion lines which are high impedance for the input signals and 50 ohmsfor the output signals. The final (top) layer is again a ground plane ontowhich low inductance chip capacitors are attached. Some properties ofthe multilayer ceramic carrier are detailed in Table 8.2.

-SiO2

^Coplanarstripline

Diffused-terminationresistor

Bypass"capacitordiode

Si0

n" Si substrate

Figure 8.22 Layout and Profile of Si Carrier


The silicon chip carrier is shown in Figure 8.2l(b) where the IC is.mounted on a Si chip which in turn is mounted onto a standard LCC. Aschematic of the silicon chip itself is shown in Figure 8.22. It consists ofinterdigitated, reverse biased p-n junctions which act as bypass capaci-tors, coplanar microstrip lines and diffused resistors. Si with a resistiv-ity of over 100 ohm.cm. is chosen. The properties of the Si chip carrierare detailed in Table 8.2. Measurements on such carriers have shownthat little ringing occurs in the pulse rise and fall responses with 100ohm.cm. Si and the sum of the cross-talk noise and power supplytransients can be kept to below 50 mV upon the simultaneous switchingof three adjacent drivers into 50 ohm loads.

8.7 Conclusions

Small signal GaAs FETs are, at present, available in hermetic packagesup to 20 GHz or so with power FET packages containing some internalmatching being available up to 18 GHz. Advances in packaging tech-niques are being seen in all areas perhaps most noticeably in the areaof low-cost sub-systems using analogue and digital ICs. Such packageddevices offer considerable advantages to the user. The components canbe pretested and screened to the quality levels demanded by commercial,military and space applications much more easily than bare-chip de-vices. The user is provided with a much easier to handle componentespecially if die handling and wire bonding facilities are not available.

8.8 Bibliography

Barrera, J.S. and Huang, C.L. Why use a packaged FET? MicrowaveSystem News, Aug. 1979, Vol. 9, No. 8, pp.144-152.

Cohn, S.B. IRE Transactions on Microwave Theory and Techniques, July1954, Vol. MTT-2, No. 2, pp.52-57.

Cooke, H.F. FETs and bipolars differ when the going gets hot. Micro-waves, Feb. 1978, Vol. 17, No. 2, pp.55-61.

Cooper, P.D., Jenkins, J.A., Parker, D. and Pengelly, R.S. Broadband GaAsmonolithic low-noise amplifiers and switches for L-Band. TechnicalDigest of IEEE GaAs IC Symposium, pp. 185-188, October 1984.

de Boo, R.J., Hinderks, S.B. and Osbrink, N.K. New surface-mountedpackage breaks from traditional MIC packaging. Microwave Journal,Vol. 27, No. 3, pp.126-134.


Drukier, I. and Silcox, J.F. A reliability study of power GaAs FETs.Proceedings of the 9th European Microwave Conference, Brighton, Sept.1979, pp.277-281.

Fukui, H. Thermal resistance of GaAs field effect transistors. TechnicalDigest of the International Electron Devices Meeting, Washington,USA,1980,pp.ll8-121.

Galli, J.G., Gilchrist, B.E. et al. Integration shrinks microwave frontends. Microwave Systems News, Sept. 1980, Vol. 10, No. 9, pp.119-130.

Gheewala, T.R. Packages for ultra-high speed GaAs ICs. TechnicalDigest of IEEE GaAs IC Symposium, pp.67-70, October 1984.

Oliver, A.A. IRE Transactions on Microwave Theory and Techniques,March 1955, Vol. MTT-3, pp. 134-143.

Pengelly, R.S., Arnold, J., Cockrill, J. and Stubbs, M.G. Prematched andmonolithic amplifiers covering 8 to 18 GHz. Conference Proceedings ofthe 9th European Microwave Conference, Brighton, Sept. 1979, pp.293-297.

Pengelly, R.S. Packaging of miniature, high frequency microwave ampli-fiers using GaAs FETs. Proceedings of the 1979 Internepcon Semicon-ductor Symposium 1979, October 1979, pp.274-277.

Pritchard, PL. Electrical characteristics of transistors. McGraw-Hill,Chapter 9.4, New York (1967).

Rowe, D.A., Lo, B.Y., Dietterle, R.E. and Moacanin, M.A. A low costmultiport microwave package for GaAs ICs. Technical Digest of IEEEGaAs IC Symposium, pp.63-65, October 1984.

Takayama, Y, Ogawa, T. and Aono, Y 11 GHz and 12 GHz multiwattinternal matching for power GaAs FETs. Electronic Letters, Vol.15No.ll, 24 May 1979, pp.326-328.

Novel FET Circuits

9.1 Introduction

This chapter is intended as an introduction to the use of GaAs FETs incircuit roles other than the usual ones of amplification, oscillation andfrequency conversion. Both single and dual gate FETS, whether theybe low noise or power devices have been used successfully in a varietyof microwave applications such as switches, attenuators, phase shiftersand modulators. The introduction of monolithic circuits, dealt with inmore detail in Chapter 10, has enabled many of these circuits to befabricated on single chips of GaAs. However, many of the circuits havealso been implemented using bare chip FETs and hybrid microstriptechniques (Pengelly et al, 1980).

9.2 Switches

For many years the PIN diode as a control element has dominatedmicrowave circuits such as switches and phase shifters (Garver, 1972).However, recently the use of both single and dual-gate FETs has receivedconsiderable attention in the design of fast switches.

Several configurations are possible to exploit the low-noise small signaland the power FET as switches (Figure 9.1). The series configuration(Figure 9.1(a)) makes use of the saturation and pinch-off conditions ofthe device and provides a broadband (untuned) response with zero d.c.bias power when using small signal devices.

The use of the series configuration to switch medium levels of r.f. power(i.e. a few watts) can be achieved using a power FET structure. However,such a configuration produces poor frequency response due to thecapacitance between the source and drain metallizations and ground.Figure 9.2(a) shows the simple equivalent circuit of a FET series switchin its ON and OFF states where in the OFF state the capacitance C3 willdominate, the channel resistance R being large. In the ON state,capacitances Ci and C2 limit the insertion loss but can be tuned out,using a low-pass filter synthesis technique, by inductors Li and L2.


Input s D Output Input D Output

'control

(a) Series mounted (b) Shunt mounted

Inputc

Tuningimpedance ?

YOnOff

oOutput

(c) Dual-Gate FET switch (d) Matched switch

Figure 9.1 Various FET Switch Configurations

Such a technique is demonstrated by the performance of a 1 watt seriesswitch shown in Figure 9.2(b) in the 'ON' state where the effect of tuningis shown on both the insertion loss and input VSWR obtainable over theoctave band 2 to 4 GHz.

However, in order to maximize the 'OFF' isolation it is also necessary toresonate the capacitance C3 with an inductor L3 as shown in Figure9.3(a). Such a simple resonant circuit results in the useful bandwidthin the 'OFF' condition being decreased.

Figure 9.3(b) demonstrates the result of a 1W switch which has beenoptimized in its ON and OFF state. McLevige et al (1980) have demon-strated such a circuit technique in X band whilst Gaspari and Yee (1978)have reported an 8 way switch utilizing tuned series connected FETsusing small signal devices.

The shunt mounted FET (Figure 9.1(b)) is somewhat easier to operateas a broadband switch. Figure 9.4(a), for example, shows the small andlarge signal operation of a 1 watt power FET (Pengelly et al, 1980)

Novel FET Circuits 431

(b)

m 1

to pi

i-(b)

(a)

c 4

Return loss ^

_ I5TReturn loss

* * {0

J.L J 1 0 |

2 0 |

3of

2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0Frequency (GHz)

C1 is source metallization parallel plate plus fringing capacitance.C2 is drain-gate capacitance plus parallel plate capacitance of drainmetallizationC3 is fringing capacitance between drain and source metallization

Figure 9.2 (a). Simple Equivalent Circuit of Power FET Switch(b). Frequency Response of Tuned and Untuned Series Power FETSwitch

Resonatinginductance

Source

R.F. Input =f

J H l D r a i n

—Control

:fR.F. Output f

(a) Circuit configuration

On

3 3.5 4.0

Frequency, GHz(b) Response

Figure 9.3 Resonated Series Power GaAs FET Switch Performance


0.2n 0.2n

200 ' 400 600 800 1000 1200 1400 1500R.F.I/P power (mW)

(a) Small and large signal operation of 1Wpower FET switch (b) Equivalent circuits

Figure 9.4 Power FET Shunt Switch

whilst Figure 9.4(b) shows simple equivalent circuits for such a devicein its ON and OFF states. Again tuning can be used to reduce theinsertion loss and broaden the bandwidth using low pass filter tech-niques similar to those adopted in PIN diode switch design.

Figures 9.5(a) and (b) show the way in which the insertion loss andattenuation of FET switches depends on the equivalent circuit parame-ters of the devices used without the addition of tuned circuits. The RCnetworks shown in Figures 9.5(a) and (b) are simple equivalent circuitsfor the FET switch where R is the channel resistance between Source'and 'drain' and C is the depletion capacitance.

The shunt mounted FET can be incorporated easily into a single pole,double throw switch (SPDT) as shown in Figure 9.6(a). When one FETis 'ON' and the other is 'OFF', where the 'OFF' FET is in its 'shortcircuit'state, the OFF FETs impedance is transformed through the quarterwavelength line to an open-circuit at the switch input port. Thus theinput impedance of the switch is dictated by the impedance of the 'ON'FET.

Such a circuit can be realized in either transmission line form or inlumped component form. In the distributed form (Figure 9.6(a)) the FET


100r

10

2,

10-1

<Off R = 4OOKS2C = 0.1pF (small

signal device)

\ R = 100Kfi\ C = 0.4pF

\C = 0.1pF

C = 0.4pF (medium power FETT*"Or?

0 2 4 6 8 10 12 14 16 18Frequency (GHz)

(a)

100

10

c 1o

10-1

10-3

R = 2fiC^= 0.4pF (mediurnpower_FE7)^

>Off> rOff "R = 8nC = 0.1 pF (small signal FET)

R = 100KflC = 0.4pF , ' '

2 4 6 8 10 12 14 16 18Frequency (GHz)

(b)

Figure 9.5 (a). Insertion Loss and Attenuation of Series SwitchInsertion Loss and Attenuation of Shunt Switch

(b).

can, in fact, be incorporated into the transmission lines themselves whenthe circuit is fabricated in monolithic form (Ayasli et al 1980) whilst inthe lumped form (Figure 9.6(b)) the FETs' capacitances again becomepart of the circuit when converting the quarter wavelength lines toequivalent inductances and capacitances (Pengelly et al, to be publish-ed). Figure 9.6(c) shows the response of a 1 watt SPDT switch designedin lumped form showing the excellent isolation and input VSWR thatcan be obtained.

The FET in shunt connection, is limited in its power handling capabilityby two factors. By monitoring the gate current under negative gate biasconditions, i.e. when the switch is in the low insertion loss state it ispossible to measure an input power level threshold at which significantgate current flows. This is due to avalanche breakdown on the negativepeaks of the r.f. cycle between the gate and drain. This breakdown is


A/4

R.F. Input

A/4

(a)

3n

^R.F."Output 1

_Controlvoltage

R.F.| Output 2H CrControl

Voltage+ 10

03"O

I +20

+ 30

-On-ARM

/VSWR

1.5

-Off-ARM

On2.5 3.0 3.5

Frequency, GHz

4.0

(c)

Figure 9.6 (a). SPDT Switch Using Shunt-Mounted GaAs FETs,(b). SPDT Switch Incorporating Lumped Components and GaAsFETs, (c). Performance of SPDT Switch

often accompanied by light emission from the channel region (Furut-saka, et al, 1978; Yamamoto et al, 1978).

To maximize power handling of the switches several improvements canbe made to the device. These include increasing the carrier level in thechannel region and decreasing channel depth to reduce pinch-off volt-ages. Optimum pinch-off appears to be around - 6 volts (McLevige,private communication). Also gate to drain spacing can be increased(although this will increase the drain to source resistance) as well aschanging the channel recess from an abrupt form to a graded form(Higashisaka et al, 1979).

Gate current is also observed when the FET switch is in the groundedgate state (i.e. the isolation condition) which is due to rectification of ther.f. power by the gate-source diode on negative half cycles of the r.f. drive.On positive half-cycles the gate goes negative with respect to the drain


tending to pinch-off the device thus reducing the isolation. By applyinga small positive bias to the gate in this state the isolation can be restoredto a value close to the small signal case.

The shunt mounted FET is a reflective structure in its 'OFF' state butmay be combined with a series mounted device in the n configuration ofFigure 9.1(d) to produce a broadband high isolation switch with lowVSWRs. The action of this switch or attenuator is similar to that of aPIN jt attenuator (White, 1974) and relies only on having known voltageto attenuation laws for the series and shunt mounted devices, n attenu-ators having close to 40 dB switching range with insertion losses of lessthan 1 dB in S band have been built giving VSWRs in all states of greaterthan 15 dB (Pengelly et al, 1980).

The major advantage of the FET over the PIN diode switch is that itrequires no control current and is inherently a very fast device (typically1 nsec or less rise times can be achieved with small signal devices).

The dual gate FET can also be used as a high isolation switch using acircuit as shown in Figure 9.1(c). Unlike the previous examples the dualgate FET is operated in the normal manner with drain to source voltage.The disadvantages of the dual-gate FET approach are:

1. The switch is non-reciprocal;

2. The switch takes d.c. power in its 'ON'-state, and

3. The device requires considerably more complicated matchingcircuits to operate over the same bandwidths as single-gateswitches.

However, the advantages of such a configuration are that gain is avail-able and the phase change between the 'ON' and 'OFF' states can bemaintained close to zero. Figure 9.7 shows the phase response for a300jum gate width dual-gate FET as the attenuation is increased fromthe 'ON' state to the 'OFF' state. It may be seen that for a 30 to 35 dBswitching range it is possible to maintain the phase change to within 1or 2 degrees.

Vorhaus (1979) has reported a multithrow dual-gate FET switch havingisolations in excess of 25 dB at X band using a novel four sided structurewith a common source connection to ground, The ground is supplied byintroducing a via through the GaAs substrate.

Figures 9.8(a), (b) and (c) illustrate the inherent bandwidth of thedual-gate FET as a switch as well as the on-off ratio attainable withsecond gate voltage (Tsai et al, 1979).


-Region of interest

ite 2 driven

-10 -20 -30Level change (dB)

-40

Figure 9.7 Phase Shift ofS2l with Attenuation for Dual-Gate FET

-40

2000

Vg2=0V

-1V

600 MHz/divn. 8000Frequency, MHz

(a) 0

-1

8 -2

5 -3-4

-5

Vg2 = 0V

2000 600 MHz/divn. 8000Frequency, MHz

(b)

Vg2 = 0V

Vg2 = -2.5V

2000 600 MHz/divn. 8000

Frequency, MHz

Figure 9.8 Magnitude of S-Parameter with FET Biased 'ON' and'OFF'


For example, the Raytheon dual gate FET (LND-841) having nominalgate dimensions of ljum by 50Qam has a gain of 6.5 dB over the frequencyrange 2 to 8 GHz without any matching networks. The RF attenuationwith the second gate pinched off is over 30 dB whilst input and outputreturn losses with the second gate biased 'ON' and 'OFF' are plotted inFigures 9.8(b) and (c). one significant characteristic of the device is therelative insensitivity of input/output VSWRs to the second gate bias.

The dual-gate FET has become a popular device for switching in PSKmodulators where the dual-gate FETs can supply high ON to OFFisolation over relatively wide bandwidths (Tsai et al, 1979) whilstmaintaining good input and output return losses in both the 'ON' and'OFF' states. Figure 9.9 shows the way in which two SPDT switchesusing dualgate FETs can be combined with unequal line lengths (overnarrow bandwidths) or Schiffman type meander line sections for broad-band applications (Schiffman, 1958; Schiek et al, 1977) to form a BPSK(bi-phase shift keyed) modulator.

Hwang et al (1984) have reported the novel employment of dual-gateFETs in a so-called segmented-dual-gate MESFET phase and gaincontroller in monolithic form. Conventionally, dual-gate MESFETs areused in analogue gain control by applying a negative voltage to thesecond gate. The control is non-linear and it is often difficult to providea control voltage with precision and repeatability. In the scheme ofFigure 9.10 each dual-gate FET is operated either fully 'on' or fully 'off.The gain of the circuit is proportional to the total gate width of theturned-on FETs. By selectively controlling the second gates, the gain ofthe device is programmed by the ratio of the gate widths. Provided thefrequency of operation of the circuit is low compared to the transition

Figure 9.9 Schematic Diagram of Biphase Modulator


Gatecontrol

Commongate

Gatecontrol

J kGatecontrol

, 3 i ,1 W1 6 Common

source

Common——odrain

Figure 9.10 Segmented Dual-Gate MESFET Device

a ON state

b OFF state

7777

-A/W—oD

1

G2 6 " :

7777

Figure 9.11 Simplified Equivalent Circuit Models of Dual-GateMESFET Operated in ON I OFF States


frequency of the FETs, the simplified models of the dual-gate MESFETshown in Figure 9.11 can be used to predict performance in the 'on' and'off' states. To verify the concept the circuit of Figure 9.12(a) has beenfabricated for the 1 to 1.5 GHz frequency range. A schematic layout ofthe GaAs IC is shown in Figure 9.12(b). The circuit is a binary weightedsealer in the ratio of 1-2-4-8 where the gate widths of the segments are50,100,200 and 400 microns respectively. The control voltages were fedthrough 2 kilohm resistors on the chip. The measured performance isshown in Figure 9.13. As can be seen the phase and amplitude trackingover the wide bandwidth is excellent.

9.3 Phase Shifters

Recently dual-gate GaAs FETs have been used to provide relatively wideband phase shifts which can be controlled with the voltages applied to

Gate controlsC B A RF out

RFin

50u.m

Source

Gateresistor

Drain

Figure 9.12 (a). Binary Weighted Dual-Gate FETs (b). Layout of1-2-4-8 Binary Sealer


2.0CD

T3

C

gi.oCM

^0 .5

1

-

-

.0

DCBA1000

0100

00100001

, , Qooo.1.5

GHz

8 72o

CM

1

1 ' • - J

-

-

0 1.5GHz

DCBA

^ 0 1 0 000100001

Figure 9.13 Magnitude and Phase Performance of the 1-2-4-8Binary Sealer

the gates of the device. The input signal can be applied to the first gate,the output taken from the drain whilst the second gate is terminated ina 50 ohm load. Matching is applied to all three ports to producemaximum gain. For example Pengelly et al (1981) have shown that, ifsome of this gain is sacrificed by adjusting the bias voltages on gates 1and 2, a multitude of voltage settings on the first and second gates areavailable for a specific gain. The transmission phase is found to varyhowever with the voltage settings as illustrated in Figure 9.14.

f§?2.

se s

hif

5QL

Rel

ati

+ 50

+ 40

+ 30

+ 20+ 10

0

- 1 0- 2 0- 3 0

- 4 0- 5 0

C) 0.5

. . ^ ^ - '

^>0^^^ Frequency = 3GHz

1.0 1.5 2.0 2.5

Voltage on gates (negative)

Figure 9.14 Transmission Phase Shift as a Function of Gate 1 andGate 2 Voltages for a Dual-Gate GaAs FET


For example, -30° phase shift at 0 dB gain was measured with VGI =-0.5V, VG2= -1.2V, and+10° phase shift, at OdB gain, with VGI = -1.7Vand VG2 = —2.2V. Obviously the phase shift will depend on frequency.

To determine whether the FET itself or the interaction between anycircuit and the FET is the major contribution to this phase shift, variouscircuit configurations have been tested with the results being summa-rized in Table 9.1.

There will be a transmission phase difference between gate 1 and drainand gate 2 and drain due to the different physical spacings of the gate1 and gate 2 electrodes to the drain. Two dual gate FETs were used, onehaving a gate 1 to gate 2 spacing of 1/nn, the other a spacing of 1.5/im.The results show that for both FET types the tuning conditions affectthe amount of phase shift achievable to a considerable extent. The mostcritical part of the circuit is the input matching network since high phaseshifts could be obtained with tuning on gate 1 only. The inherent devicephase shift, as appreciated from Table 9.1 is small. It is concluded that

Table 9.1 Variations in Phase Shift with Different Amplifier TuningConditions

DeviceType

1

1

1

1

2

2

2

2

Tuning Conditions

All 3 ports tuned formaximum gain at 3 GHz

Both gates tuned

Gate 2 tuned

No tuning

All 3 ports tuned formaximum gain at 3 GHz

Both gates tuned

Gate 1 tuned

No tunng

Gain

14 dB

12 dB

6dB

6dB

14dB

10 dB

10 dB

4dB

Set Gain

OdB

OdB- 2 d B

OdB- 8 d B

OdB- 8 d B

OdB

OdB- 4 d B

OdB- 4 d B

OdB-10dB

Max.Phase Shift

90°

80°85°

30°36°

13°15°

58°

53°61°

55°67°

10°23°


in such a dual-gate FET phase shifter, most of the phase shift whichoccurs at the gate voltages are varied is due to interactions betweenchanging device parameters and the input matching network.

Measurements made with a sliding short circuit as the termination ongate 2 result in phase shifts of up to 140° at 4 GHz.

As the Sn of the dual-gate FET changes with the first gate voltage,amplitude changes are incurred at the band-edges as shown in Figure9.15. However, by matching the device over a bandwidth typically 100%greater than is needed phase and amplitude ripples can be substantiallyreduced. For example (Figure 9.15) if a phase shifter element giving22.5 degrees needs to operate to an amplitude ripple of ± 0.1 dB overthe 2.7 to 3.2 GHz bandwidth then the matching circuits need to produceflat gain over the 2.2 to 3.7 GHz band in the reference phase shift state.

Tsironis et al (1980) have also used the dual gate FET as a phase shifterat X-band where the input signal is applied to the second gate and thefirst gate is made parallel resonant with an inductor. The dual-gate FETcan be modeled as the connections in Figure 9.16(a) where the parallelresonant circuit consists of L + LGI, CGSI, RGSI + Rsi and Lsi. The biasvoltage is varied on the first gate to change the value of CGSI resultingin a phase shift in S21 as shown in Figure 9.16(b). By optimizing thematching on gate 2 and drain it is possible to realize phase shifts ofaround 70° over 11.9 to 12.2 GHz, for example whilst maintaining a gainof3dB.

Amplifier bandwidth withis = VG2s = 0vwas12%

Amplitude ripple (10% BW)

Phase ripple (4% BW)

Amplitude ripple (4% BW)

Region of interest

10

2 "5

20 30 40 50 60 70

Figure 9.15 Amplitude and Phase Variations with Bandwidth for aDual-Gate FET Phase Shifter


Figure 9.16 (a). Equivalent Circuit (b). Transmission Phase andGain Behavior of Dual-Gate FET at 11.5 GHz.

Single gate FETs are used as switching elements in circuits such as theswitched line and high pass/low pass configurations (Pengelly, 1980).The switched line and its derivative the loaded line phase shifter, operateover relatively narrow bandwidths particularly as the phase shift re-quired increases. The high pass/low pass characteristic is producedusing lumped elements as shown in Figure 9.17(a).

Since the insertion loss and phase difference of the circuit depends notonly on the series resistance of the series FETs but also on the shuntcapacitance of the 'OFF' FETs the circuit of Figure 9.17(b) producesbroader band performance since the lead/lag networks are separatedfrom the switching elements. Such circuits can provide up to 180° phaseshift over 20% bandwidths. The flexibility of GaAs MESFETs as controldevices is exemplified in the vector modulator circuit (Brandwood, 1978)which provides both phase and amplitude control of a microwave signaland finds application in phased array radars and interference cancella-tion systems (Hicks et al, 1978).

Two circuit examples are shown in Figure 9.18(a) and Figure 9.19. InFigure 9.18(a) the input r.f. signal is equally divided with a singlegate/double drain FET to produce 14 dB gain over the 2.5 to 3.5 GHzband. This signal divider uses a common gate connected FET at theinput to provide a 50 ohm match by employing a 30Qam FET operating


Figure 9.17 (a). High I Low Pass Phase Shifter using FET Switches(b). High I Low Pass Phase Shifter using SPDT FET Switches

at a drain current such that its transconductance is 20 mS. The commonsource connected FET is matched passively on the drain to provide a lowoutput VSWR. The n attenuators use small signal FETs where thedevices are chosen for low on-resistance and small 'OFF' capacitance asexplained earlier. Phase lead/lag networks supplying +45° and -45°phasing follow the attenuators. The phase shifted vectors are thenrecombined in a lumped element combiner which provides low insertionloss and signal isolation between its input ports. Figure 9.18(b) showsa photograph of a hybrid microstrip realization of such a circuit whichprovides 0° to 90° phase shift between 2.5 to 3.5 GHz with an overall lossof -15 dB in the 'OFF' state. Figure 9.18(a) also shows the manner inwhich the other three quadrants of phase shift 90° to 180°, 180° to 270°and 270° to 360° can be produced using FET switched +90° and -90°phasing networks.

Figure 9.19 shows an alternative circuit configuration for a vectormodulator where the vector amplitudes are produced using dual-gateFET attenuators, followed by common source and source follower FETsfor the 180 and 0° vectors. Matched broadband switches are producedby modifying the it attenuators of Figure 9.18 such that the shunt FETclosest to the common source and source follower FETs, has a 50 ohmr.f. resistor in its source to ground lead. Together with the A/4 sectionsthe switch provides a match at all its ports in both is 'ON' and 'OFF'


Matched 9 0 ° l e a d / l a 9 1 8 0 ° lead/lagattenuators networks networks

CG/CS activesplitter

Similar to above

(a)

Figure 9.18 (a). Schematic Diagram of Vector ModulationPhotograph of Hybrid Vector Modulation

(b).

states. The insertion loss of the switches and phasing networks iscompensated by the active combiner at the output of the vector modu-lator. The active combiner consists of a FET in common gate configura-tion with two separate source electrodes and one common drainelectrode. If two independent channels in the common gate FET arepresent then the signals are added and no mixing takes place.


Dual gateFET attenuators

Match

LE. Wilkinson dividerand +45°,—45° phasenetworks

Total no. of FETs = 22

Figure 9.19 Vector Modulator

The circuit of Figure 9.19 provides full 0° to 360° phase shift in acontinuously variable manner whilst providing an overall gain of 14 dBwith input and output VSWRs of 1.5 to 1 or better operating over 2.5 to3.5 GHz (Pengelly et al, private communication).

9.4 Discriminators

Frequency discriminators or IFMs (instantaneous frequency measure-ment) usually use two diode mixers following unequal phase lengthcircuits from a power divider. Since the phase difference in the 2 circuitsprior to the mixers will increase with frequency, frequency can bemeasured as a phase change by monitoring the baseband voltage outputof the two diode mixers. This output will have a cosine relationship tothe phase difference. Over a large range of frequencies (depending onthe phase length differences used) the difference between cos 0 and 9(radians) is small. Thus frequency is approximately equal to the base-band output voltage.

The dual-gate FET has recently been shown to exhibit intrinsic phaseand therefore frequency discrimination properties when the r.f. signal isapplied to both the 1st and 2nd gates (Pengelly, 1979).

To be able to use successfully a dual-gate GaAs FET as a frequencydiscriminator several factors have to be considered in circuit design.


Firstly, the mixing action of the device must be considered. Thus, thedevice needs to operate in a bias region where the transconductance ofthe device can be varied periodically as strongly as possible by one orboth of the two applied gate voltages.

As may be seen from Figure 9.20 the actions on the drain currentcharacteristics of a dual-gate device by the first or second gate voltages,VGIS or VG2S, are similar when the gate voltages exceed a certain value.In a discriminator circuit the r.f. applied to gates 1 and 2 periodicallymodulate the gm of each FET. The relative phase difference between thefirst gate-to-drain and the second gate-to-drain transmission coeffi-cients will determine the action of the device as a microwave discrimi-nator.

Considering the simplified equivalent circuit of Figure 9.21 it may beappreciated that the conversion gains of FETs 1 and 2 of the dualgateconnection _depend on the time-averaged gate-to-source capacitancesCGSI and CGS2 as well as the time-averaged output resistances Roi andR02. An analogous equation to Equation 6.13 for the 'mixer' gains ofeach of the FETs in the dual-gate FET connection can be formed whichcan be reduced in a simpler form to, for example

vG2S = o v

Drain voltage, Vos, volts Drain voltage, VDS, volts

Figure 9.20 Dual-Gate FET d.c. Characteristics


Gate 2 -R.F.W, Ro

•AAA/V ° Drai n

ft*

>Ri2

Gatei-R.F.W, h-AM/V

Figure 9.21 Simplified Equivalent Circuit ofGaAs FETDiscriminator

Sl2 R02

4a)j CGS2

I RG2 + R12 + Ri2

-l -l

.-1

+ Rsi

A similar expression exists for gci, the conversion gain of the other FETin the long-tail connection of Figure 9.21.

Since CGSI and CGS2 are directly related to the Sn, S21 and S33, S23 Ofthe dual-gate FET S-parameters where port 1 is gate 1, port 2 is thedrain and port 3 is gate 2, it may be expected that the addition of thetwo IF ' outputs from the action of FET 1 on FET 2 and vice versa willbe related to the relative phases of Sn, S21 and S33, S23. The transmissioncoefficients' angle difference A0 (S23-S21) is found to be linear over alarge range of frequencies as shown in Figure 9.22. The linear portion


1

1

110

100

90

80

70

60

50

Ui =IDS =

y

^ 6 7

LQ2 = iMm,Woi = Wo2 = 300Mm20mA for VgK = 0V /

/ ^

^ ^ /

8 9 10 11 12 13 14Frequency, GHz

70

60

50

40

30

20

10

l*1

i

Figure 9.22 Measured Phase Difference Between Gate 1-Drain andGate 2-Drain Transmission Coefficient Angles

of the relationship is variable in slope and frequency by the appliedsecond gate voltage since <S23 is effected by second gate bias much morethan <S2i.

As the second gate voltage is increased until the device is near pinch-offthe linear portion of this phase difference increases in slope and fre-quency. The change in the frequency coverage of the linear portion ofthis phase difference is due to the rotation of the angles of S23 and S21with second gate bias. This phase shift can, therefore, be brought intoa particular frequency range by changing the matching on gates 1 and2. Frequency ranges of 2 to 6 GHz, 6 to 12 GHz and 12 to 18 GHz havebeen reported. In order to achieve reasonable conversion efficiency inthe discriminator (i.e. to maintain efficient mixing) and also to allowoperation in the linear region of the phase difference graph, the first andsecond gate bias voltages are adjusted such that the drain current isapproximately 10% of the saturated value IDSS.

By dividing the r.f. signal into two equal amplitude and phase compo-nents and applying these signals to the dual-gate FET's two gates it ispossible to produce a discriminator output voltage whose magnitude isproportional to cos A0, where A(f> is the phase difference between the gate1 to drain and gate 2 to drain transmission coefficient phase angles. In


Gain slopecompensation

circuit

GaAsFET , .Limiting amplifier l n prase

RF input

Attenuator

Biasnetwork

VDS = 5 volts

Load resistor

Videoplifier

yDiscriminatoroutput voltage

rfo Dual gate FET Offsefvoltage

Figure 9.23 Schematic of Dual-Gate FET Frequency Discriminator

order to maintain the linearity of the discriminator, broadband matchingcircuits are needed on the gate 1 and 2 ports to maintain flat gainbetween gate 1 and drain and gate 2 and drain over the band of interest.

Figure 9.23 shows a schematic diagram of the dual-gate GaAs FETdiscriminator. A signal limiter is needed before the discriminator toensure that a constant signal level is available whatever the input signallevel over a certain dynamic range.

The response time of the discriminator to pulsed r.f. inputs depends onthe cut-off frequency of the low-pass filter following the drain of the FET.

9.5 GaAs FET Osciplier

Chapter 6 has indicated that the dual gate FET can be used as afrequency multiplier because of its transfer nonlinearities controlled byeither the first or the second gate bias. Since the dual-gate FET has alsobeen used as a self oscillating mixer (Tsironis et al, 1979) it becomesclear that the device should be capable of acting as an oscillator andmultiplier simultaneously. Figure 9.24 shows a schematic diagram ofthe so-called osciplier.

The circuit within the dashed lines is a varactor tuned oscillator de-signed using the feedback element Li at the first gate and a GaAsvaractor at the source. Chu (1980) has reported oscillators capable of


operating from 6 to 11.5 GHz using 1/im long, 40Qam wide gate MES-FETs. A capacitance load C2 at the second gate improves the conversionefficiency of the multiplier. The optimum load impedances for maximumoscillation efficiency at frequency fi and for maximum multiplicationconversion efficiency at frequency nn (where n is the multiplicationfactor) will be different. Thus, frequency selective tuners can be used,as shown in Figure 9.24, to provide at least two distinct impedances atdifferent frequencies. Thus, once the oscillation builds up at the firstgate, the harmonic of this oscillating signal is generated by two kinds ofnonlinearities, namely, the second gate input nonlinearity and the drainoutput nonlinearity. The resultant harmonic is then amplified andextracted from the drain through a circulator by tuner 2 in the frequencyselective tuner.

Figure 9.25 shows, for example, the output power measured for twooscipliers at various doubling frequencies.

9.6 Pulsed Oscillators

During recent years solid state microwave devices have achieved con-siderable technical importance in radar applications in the measure-ment of range and velocity.

Tuner 1

VTo-

1 -it.

Vo,

Figure 9.24 Osciplier Using Dual-Gate FET


20

18

E 1 6

S 1 4

Osciplier 1 Osciplier 2

Pi = Output power at f0P2 = Output power at 2f0

2fo12 14 16 18 20 22 24

fo 6 8 9 10

Frequency, GHz

11 12

Figure 9.25 Power Performance of Two Dual-Gate MESFETOscipliers

Doppler frequency shift provides an accurate technique for the meas-urement of target velocity for many applications. In CW Doppler radarsystems the Doppler shift is proportional to the axial component of thevelocity and is therefore related to the difference between the transmit-ted and received frequencies. Pulsed RF systems are capable of provid-ing both the target velocity and range information. The transmitted andreceived signals when mixed generate the IF signal with the appropriateDoppler modulation impressed upon it. One transient effect which cancause problems in pulsed r.f. systems is the frequency change during theRF pulse due to changes within the microwave device. This phenomenonis commonly termed 'chirp' and has to be minimized if it is a significantfraction of the receiver band width. Extremely elaborate and expensivetechniques have been employed to minimize 'chirp' in Gunn diodeoscillators, for example.

The GaAs dual gate FET can be employed in an oscillator circuit suchas the common gate configuration of Figure 9.26 and a property of thedevice exploited producing a low chirp pulsed r.f. output. This propertyis best illustrated by considering the model of the dual gate FET as thecascode connection of a common source device used as the element forobtaining steady state oscillations followed by the common gate FET


Matching O/P matching

Element Element

^Pulsed"R.F. output

G1

o—nnnrv.

VG,sT

T

[[Feedbackelements

i i_n_rV G 2S

Figure 9.26 Schematic of Pulsed Dual-Gate FET Oscillator

operating as a high speed switch to obtain pulsed r.f. output. This iseasily done by applying a negative pulse to the second gate.

Table 9.2 shows the magnitude and phase of the gate 1-to-source andgate 1-to-drain scattering parameters, Sn and S21 of a chip ljum by30Qum GaAs FET for different gate 2 bias levels. It can be seen that asthe second gate voltage is increased from 0 to -0.9V the phase of theinput reflection coefficient remains virtually unchanged while the for-ward gain of the device decreases by as much as 6 dB. Minimal phase

Table 9.2 Input Reflection Coefficient Sn and Forward Gain S21 fora Dual-Gate GaAs FET as a Function ofVG2

VG2, volts

0

-0.4

-0.9

-3.2

MAG

.56

.58

.61

.62

S11

ANG

-42.0

-42.6

-46.4

-95.3

VG1 = -1.OV

VDS = 5 volts

MAG

1.15

0.93

0.57

0.03

S21

ANG

-58.5

104.8

116.7

171.0


change in Sn maintains the operating frequency. The phase changebeyond -0.9V is quite rapid as the device reaches pinch-off but the gainof the device has already dropped to such an extent that oscillations canno longer be sustained. An important factor in the dual-gate oscillatorsfavor is that drain current is virtually zero when the device is 'off \ Thisresults in less heat dissipation in the FET channel and thus improvesreliability.

Joshi et al (1980) have reported pulsed oscillators operating at X and Jband frequencies with pulse widths ranging from 20 nS to ljusec andduty cycles ranging from 1 to 25%. The frequency variation for theduration of the pulse was approximately 0.3 MHz with an output spectrawhich was virtually symmetrical indicating linear frequency variationduring pulse duration. Such a figure is considerably better than thatfor diode sources.

9.7 Transformer Coupled Circuits

Monolithic microwave integrated circuit (MMIC) technology with itsfine photolithographic resolution and ability to integrate FETs, capaci-tors, inductors and resistors allows the engineer flexibility in designingcircuits which otherwise, using conventional techniques, would be eithervery difficult or impossible to realize (see Chapter 10 for more detailson monolithic circuits). One excellent example of this is the class ofcircuits which use transformers to couple individual circuits or performcircuit functions themselves such as impedance transformation or phaseshifting. Transformers used to generate phase reversed signals areused, for example at low frequencies, for push-pull power amplifiers.Jamison et al (1982) and Ferguson et al (1984) have reported trans-former-coupled MMICs such as amplifiers, receivers and transmitters.

The MMIC transformers consist of two interwound spiral inductors. Byplacing the primary and secondary turns of the inductors very close toeach other-typically a few microns on a 500 micron thick GaAs substrate-it is possible to produce coupling factors of 0.8 or greater. In comparisonwith conventional wound transformers such MMIC transformers oper-ate up to 8 GHz or so with acceptable loss. This is because the structurescan be made very small such that the side of the square inductors areonly a few hundred microns long. Parasitic capacitance between theturns and to ground can be modeled accurately enabling the transform-ers to be used in such circuits as the one shown in Figure 9.27. In aMMIC the use of transformers allows greater packing density of thecircuit elements to be achieved since the transformer acts firstly as an


Figure 9.27 Transformer Coupled MESFET Amplifier

r.f. choke allowing d.c. voltages to be introduced to the FETs conven-iently; secondly no d.c. blocking capacitors are needed between stagesas the turns of the transformers are isolated from each other and thirdly,for example in the amplifier design of Figure 9.27, the inductance of thesecondary of the transformers is chosen to resonate with the inputcapacitance of the next stage FET producing a medium bandwidthmatch. On 500 micron thick GaAs the transformers were designed withthree micron line/ space layout rules and the coupling was close to 1:1.As can be seen from Figure 9.27 an AGC function was implemented withthe addition of a second FET, F3 that subtracts bias current from theamplifier in response to an AGC control voltage.

Figure 9.28 shows a MMIC chip containing a pair of transformer coupledamplifiers operating over 3 to 5 GHz as shown by the amplifier responseof Figure 9.29 (Jansen et al, 1985). Such circuits are driven by antiphasesignals derived with transformers which after amplification are com-bined in a push-pull arrangement in much the same way as at audiofrequencies. By optimizing the geometry of the transformers it ispossible to cover relative bandwidths in excess of 40%.

Ferguson et al (1984) have described an image rejection mixer and atransmitter using such transformer coupled circuits. The image rejec-


Figure 9.28 Microphotograph of Transformer Coupled MESFETAmplifier (Courtesy-Plessy Research)

15

* 1 0

"°. 5cB 0o <

-5—in

1U

-

-I

2 3i IU 5

Frequency, GHz

i

6

Figure 9.29 Gain Performance of Trans former Coupled MMICMESFET Amplifier


tion mixer consisted of a single stage of RF gain, two local oscillatorbuffer amplifiers, a fixed 90 degree phase shift and two double balancedmixers using Schottky diodes. The mixers were driven with in-phaseRF signals whilst the LO signals were in quadrature. At an LO fre-quency of 4 GHz image rejection of greater than 25 dB was achievedbetween 4.12 and 4.18 GHz with an overall conversion loss of 10 dB. Thecomplete receiver although being narrowband was contained on a chiponly 0.7 by 1 mm. The transmitter having an output power of 240 mWconsisted of an oscillator and three stages of gain on a chip measuring1 by 1.5 mm.

9.8 Integrated Optoelectronic Circuits

Integrated optoelectronic circuits (IOECs) are being developed to meetthe needs of future digital communication systems operating at multi-gigabit data rates. These systems require extremely broadband, lowdispersion, low-loss data buses for chip-to-chip, board-to-board andsystem-to-system interconnection. Long distance fiber optic communi-cations require gigabit/sec capabilities for the transmission of multi-plexed signals over one channel. Optical interconnects and fiber opticlinks consisting of an integrated optoelectronic transmitter, optical fiberand integrated optoelectronic receiver are probably the best solution tomeet these requirements. Besides IOECs offering predicted superiorspeed and noise performance there are also advantages to be gained interms of compactness, reliability and low fabrication cost. The subjectof IOECs is a vast subject in its own right. Two examples are presentedin this section on the employment of MESFETs in such circuits. Thefirst is an optical high impedance receiver for operation up to 1.2 Gbit/secwhilst the second is a gigabit transmitter operating at 160 MHz clockrates.

9.8.1 Preamplifiers for Optical Receivers

The most suitable circuit for an integrated preamplifier for opticalreceivers is a GaAs MESFET cascode with either a source-followeroutput or emitter-follower output to enable the preamplifier to beinterfaced with further amplification and processing circuits. Such acircuit produces a low effective input capacitance which is determinedby the gate-to-source capacitance and the gate-to-drain (Miller) capaci-tance of the common source connected input MESFET. It is also possibleto maximize the optimum signal-to-noise ratio of such a circuit by


0.8pm gatelength FETs

2V-2V I-J J-,

300k||RB

I

12V 99 *i

Vj»

i 05V

[[500

Figure 9.30 Circuit Diagram of Optical Receiver for 1.2 GBit/secdata

optimizing the gate length, pinch-off voltage, operating current andtransconductances of the MESFETs.

The dominant factor in the sensitivity of the FET receiver is given by:

(cs+cGSfp8m

where P is a function of the MESFET noise coefficients. This factor mustbe minimized to maximize the receiver sensitivity. Cs is the PIN diodeoptical detector capacitance, including any strays due to the diodemounting or diode bias resistor (Figure 9.30) whilst CGS is the FET inputcapacitance and gm is its transconductance at the bias condition foroptical overall signal-to-noise ratio. All the most critical componentswithin the equivalent circuit of the FET are dependent on drain current.These components include the gate-to-source capacitance, CGS. In theoptical receiver circuit of Figure 9.30 it can be shown that the totalspectral noise density is a strong function of the FET drain bias condi-tions as well as the various noise sources of the individual FETs(Monham et al, 1982).

These FET noise sources are the shot noise from gate leakage current,thermal noise generated by the gate and source resistances, inducedgate noise brought about by fluctuations in drain bias, noise generatedin the FET conducting channel and 1/f noise.


10-12

-N-U

nri8

: I 10a .~ o

I | 10"20

UJ u200

Bipolar highimpedance

MESFET highimpedance

1000 1800Bit rate (Gbit/sec)

2600

Figure 9.31 Noise Spectral Density Versus Data Rate for FET andBipolar Receivers

It can be shown that the cascode FET with a source follower output hasa lower equivalent noise current power than a bipolar junction transistorfront end amplifier particularly in the 565 Mbit/s region (Figure 9.31).This means that the bit error rate (BER) of a receiver as a function ofaverage received optical power will be lower for a MESFET receiver thanfor a totally bipolar receiver. Even at high data rates an increase insensitivity of 1 dB can decrease the BER by three orders of magnitude.Thus, for data rates as high as 2.4 or 4.8 GBit/s the small increase insensitivity is well worth while. Figure 9.32 shows the transfer gain forthe circuit of Figure 9.30 from 1 KHz to 10 GHz using the microwave

InQ.

E736§5

f'1

0

_

-

-

-l

10*

40dB/decade

I I I ! !

106 108

Frequency (Hz)

\

i

1010

Figure 9.32 Transfer Gain of High Impedance MESFET OpticalReceiver


Figure 9.33 Microphotograph ofMESFET Optical Receiver Chip(Courtesy-Plessy Research)

CAD package SUPERCOMPACT. The 3 dB bandwidth for such anamplifier is greater than 1800 MHz. An example of a simple opticalreceiver chip is shown in Figure 9.33. The chip measures 0.9 mm X 2mm. The PIN optical detector diode is flipchip mounted onto the GaAschip as shown. Such a circuit with FETs having 0.8 micron gate lengthshas achieved an optical sensitivity for a BER of 10"9 of - 36.5 dBm whichcompares very favorably with a conventional hybrid approach using chipFETs and wire bonded components on a thick film substrate.

9.8.2 Integrated Transmitters

Carney et al (1983) have described the integration of a semiconductorlaser diode with a 36 gate GaAs circuit. As shown in the schematicrepresentation in Figure 9.34 the basic components of the transmitterare a transverse junction stripe laser, a FET power driver and a 4:1multiplexer. The multiplexer and driver active layers were formed byselective ion implantation into the semi-insulating GaAs substratewhile the laser is fabricated in epitaxial layers grown by liquid phaseepitaxy in a well that was etched into the substrate.

A 4:1 multiplexer was chosen as the circuit to integrate with the laserbecause time division multiplexing (MUX) of multiple low data ratesignals for transmission over a single optical fiber was one of the primaryapplications of the IOECs. The MUX and driver circuits were fabricated


FET laser_driver

multiplexerBuffer

Counter

Clock

Processedlaser ^mirror

Integratedlaser

structure

Clear

Input 1Input 2Input 3Inputs

Buffer

Semi-insulatingGaAs substrate

Laser TG5LPE in well

Driver Power FETSelective ion implantation1 micron gates

MUX 36 gate GaAs ICSDFL(DFETs)Selective ion implantation1 micron gates

Figure 9.34 Schematic of Integrated OptoelectronicTransmitter IReceiver (Courtesy-Honeywell)

using D-MESFETs having 1 micron gate lengths with the 4:1 MUXconsisting of 36 NOR gates. The driver circuit for the laser consisted offour separate FETs connected in parallel. The complete transmitterchip was approximately 1.8 x 1.8 mm2. The packaged laser/MUX ICwas tested at a 160 MHz clock rate and operation to over 1 GHz waspredicted by the workers at Honeywell.

9.9 Conclusions

There is now no doubt that the GaAs MESFET has established itself asa very versatile three-terminal device much as various silicon FETshave at lower frequencies previously. This chapter has demonstratedthat both single and dual-gate FETs have a number of properties


making them attractive for a variety of applications. The single-gateFET has also found applications in tunable (Presser, 1979), transversalrecursive filters (Rauscher, 1985). With the increase in the use of andpopularity of monolithic circuits the future of the MESFET in such novelroles is assured and many of those described in this chapter will becomecommonplace.

9.10 Bibliography

Ayasli, Y, Pucel, R.A., Fabian, W. and Vorhaus, J.L. A monolithic X-bandsingle pole, double throw bidirectional GaAs FET switch, ResearchAbstracts of the 1980 GaAs IC Symposium, Las Vegas, USA, Paper 21.

Brandwood, D.H., Cross coupled cancellation system for improvingcross-polarization discrimination. Antennas and Propagation-IEE Con-ference Publication, No. 169, Part 1, November 1978, pp.41-45.

Carney, J.K., Helix, M.J. and Kolbas, R.M. Gigabit optoelectronic trans-mitters. Technical Digest of IEEE GaAs IC Symposium, pp.48-51,1983.

Chu, A.S. and Chen, P.T, An osciplier up to K-band using dual gate GaAsMESFET. IEEE MTT-S International Microwave Symposium Digest,May 1980, pp.383-386.

Fabian, W., Vorhaus, J.L., Curtis, J.E. and Ng, P. Dual gate FET switches.GaAs IC Symposium, Research Abstracts, Lake Tahoe, Sept. 1979, Paper28.

Ferguson, D. et al. Transformer coupled high-density circuit techniquesfor MMICs. Digest of Papers of IEEE Microwave and Millimeter WaveMonolithic Circuits Symposium, pp.34-36, May 1984.

Furutsaka, T, Tsuji, T. and Hasegawa, F. IEEE Trans, on ElectronDevices, Vol. ED-25,1978, p.563.

Garver, R.V Broadband PIN diode phase shifters. IEEE Trans. 1972,MTT-20, pp.314-323.

Gaspari, R.A. and Yee, H.H. Microwave GaAs FET switching. IEEEMTT-S International Microwave Symposium Digest, Ottawa, Canada,1978, pp.58-60.

Hicks, D. and Raymond, G. Adaptive arrays and sidelobe cancellers forcommunications and radar applications. Proceedings of the 1978 Mili-tary Microwaves Conference, London, Oct. 1978, pp.366-378.


Higashisaka, A., Furutsuka, T. et al. Power GaAs MESFETs with agraded recess structure. Proceedings of the 11th Conference on SolidState Devices, Tokyo, 1979, Japanese Journal of Applied Physics, Vol. 19,pp.339-343.

Hwang, Y.C., Chen, Y.K., Naster, R.J. and Temme, D. A microwave phaseand gain controller with segmented-dual-gate MESFETs in GaAsMMICs. Digest of papers of IEEE Microwave and Millimeter WaveMonolithic Circuits Symposium, pp. 1-5, May 1984.

Jamison, S.A. et al. Inductively coupled push-pull amplifiers for low-costmonolithic microwave ICs. Abstracts of IEEE GaAs IC Symposium,Phoenix, USA, 1982.

Jansen, R.H., Wiemer, L., Robertson, I.R., and Swift, J.B. Computersimulation and experimental investigation of square spiral transform-ers for MMIC applications. IEE Colloquium on CAD of MicrowaveCircuits, Savoy Place, London, Digest of Papers, November 1985.

Joshi, U.S. and Pengelly, R.S. Ultra low chirp GaAs dual-gate FETmicrowave oscillators. IEEE MTT-S International Microwave Sympo-sium Digest, May 1980, pp.379-382.

McLevige, W.V. and Sokolov, V. A monolithic microwave switch usingparallel-resonated GaAs FETs. Research Abstracts of the 1980 GaAs ICSymposium, Las Vegas, USA Paper 20.

McLevige, W.G.-private communication.

Monham, K.L., Burgess, J.W. and Mabbitt, A.W. PIN-FET receivers forlong wavelength fibre optic systems. Proceedings of the Communica-tions '82 Conference, Birmingham, England, pp.280-284,1982.

Pengelly, R.S. and Suckling, C.W. The application of gallium arsenideFETs in microwave signal control circuits. IEE Colloquium, London,December 1980, Digest No. 1980/81.

Pengelly, R.S. and Suckling, C.W., to be published.

Pengelly, R.S., Suckling, C.W. and Turner, J.A. Performance of DualgateGaAs MESFETs as phase shifters. 1981 IEEE International Solid StateCircuits Conference, New York, Feb. 1981, Session XI on MicrowaveCircuits.

Pengelly, R.S. GaAs monolithic microwave circuits for phased arrayapplications. IEE Proc. Vol. 127, Pt.F, No. 4, August 1980, p.301-311.

Pengelly, R.S. and Suckling, C.W.-private communication.


Pengelly, R.S. Broad and narrow-band frequency discriminators usingdual-gate GaAs field effect transistors. Proceedings of the 9th EuropeanMicrowave Conference, Brighton, England. Sept. 1979, pp.326-330.

Presser, A. High speed, varactor^tunable microwave filter element.IEEE International Microwave Conference MTT-S Digest, May 1979,pp.416-418.

Rauscher, C. Distributed microwave active filters with GaAs FETs.IEEE MTT-S International Microwave Symposium Digest, St. Louis,USA, pp.273-276, June 1985.

Schiek, B. and Kohler, J. A method of broadband matching of microstripdifferential phase shifters. IEEE MTT Trans, p.666-671, Aug. 1977.

Schiffman, B.M. A new class of broadband microwave 90-degree phaseshifters. IRE MTT Trans, pp.232-237, April 1958.

Tsai, W.C., Paik, S.F. and Hewitt, B.S. Switching and frequency conver-sion using dual gate FETs. Conference Proceedings of the 9th ,EuropeanMicrowave Conference, Brighton, Sept. 1979, pp.311-315.

Tsai, W.C., Tsai, T.L. and Paik, S.F. PSKmodulator using dual-gate FETs.1979 IEEE International Solid State Circuits Conference Digest,pp.164-165.

Tsironis, C. and Harrop, P. Dual gate GaAs MESFET phase shifter withgain at 12 GHz. Electronics Letters, 3rd July 1980, Vol. 16, No. 14,pp.553-554.

Tsironis, C, Stahlmann, R. and Pouse, F. A self oscillating dual gateMESFET X-band mixer with 12 dB conversion gain. Proceedings of the9th European Microwave Conference, Brighton, 1979, pp.321-325.

White, J.F. Diode phase shifters for array antennas. IEEE Trans. MTT-22,1974, pp.658-674.

Yamamoto, R., Higashisaka, A. and Hasegawa, F. IEEE Trans, on Elec-tron Devices, Vol. ED-25,1978, p.567.

10

Gallium Arsenide Integrated Circuits

10.1 Introduction

The superior physical properties of gallium arsenide over those of siliconhave led researchers worldwide to use the material as a semiconductingand semi-insulating substrate for both high frequency analog and high-speed digital integrated circuits. Much activity is now concentrating onthe ability to integrate large numbers of FETs into chip areas of lessthan 4 mm2 to perform sophisticated functions such as code generationand random access memories at speeds of up to 4 GBits/sec. AnalogueICs which contain complete receiver front-ends, phase and amplitudecoded transmitters, analogue to digital converters and synthesizers, forexample, are presently being developed following the encouraging re-sults produced during the last five years with single function circuitssuch as low-noise amplifiers and oscillators.

In parallel with the utilization of both silicon IC circuit techniques atthe lower frequencies (i.e. up to approximately 4 GHz) and the ingenioususe of FETs in circuits up to 35 GHz or so, sophisticated technologiesare emerging to cope with the demands of the circuit designers.

This chapter is divided into four main sections. The first section dealswith the philosophy behind and design approaches of analogue circuits.This is followed by an equivalent account for digital GaAs ICs. A reviewis presented of the various approaches and technologies that have beendeveloped including the use of ion implantation and 'planar' IC process-ing. A considerable number of circuit examples are included to indicateto the reader the range of activities being pursued in this exciting fieldof microwave solid state device development. An attempt has been madeto include up-to-date circuit examples which aim to demonstrate the wayin which gallium arsenide ICs-whether they be monolithic microwaveor digital-are rapidly increasing in complexity.


10.2 Monolithic Microwave Circuit Design

As may be appreciated from the rest of this book, GaAs is an excellentmaterial for field effect transistors and Schottky diodes. Because it canalso be a low loss dielectric in its semi-insulating form it has become thebasic material for microwave integrated circuits where both active andpassive elements are combined on the same chip. The passive elementstake the form of either distributed or lumped elements. The two mostpopular transmission lines used on GaAs are microstrip and coplanarwaveguide. Of these two, microstrip has become the most exploited sincethe advantage put forward for coplanar waveguide, that of accessibleground planes on the top surface of the chip is only useful for simplecircuits. With the advent of Via' technology microstrip is much moreflexible. Lumped elements produce more circuit design flexibility, too,provided that the equivalent circuits of these components (i.e. thecomponent parasitics and loss) can be accurately modeled. In manycases these models are most easily predicted by the use of transmissionline theory, either single or coupled. Lumped components are particu-larly useful at frequencies up to J-band. However, in certain cases (forexample, where the chip needs to be thin for thermal dissipation rea-sons) the loss factor of these lumped components can be low (i.e. 20 orso). Much of the early work on GaAs monolithic circuits used lumpedelements to gain their advantages in broad-band circuits.

10.2.1 Lumped Components

The lumped inductor may take one of three forms-a single loop, astraight ribbon or a multiturn 'spiral'. In MMICs single loop inductorsrarely exceed a few nanohenries whilst multiturn spiral inductors havebeen fabricated on GaAs up to 50 nH (Suffolk, 1980). Of these threetypes of inductor the first two are the easiest to construct in that theyrequire the use of only one metallization layer, which may be either firstor second level. The metal thickness usually is 3 microns or greater tominimize resistive and skin depth losses. The multiturn spiral requiresthe use of an underpass or airbridge to connect the center of the spiralto the external circuit. An example of a spiral inductor using anunderpass connection is shown in Figure 10.1(a).

Ribbon and single loop inductors tend to be used mainly at the higherfrequencies where the resonances associated with spiral inductors pre-clude their use.

Gallium Arsenide Integrated Circuits 467

Figure 10.1 (a). Example of Spiral Inductor with UnderpassedConnection (Courtesy Plessey) (b). The Equivalent Circuit of a SpiralInductor

Single loop inductor calculations use the formula of Grover (1946) whichis:-

10.1

where

L is the inductance in nH


a is the mean radius in cm

W is the strip width in cm

\x is the relative permeability of the strip

<5 is the skin depth.

For sufficiently thick metallization at microwave frequencies the judcontribution in Equation 10.1 can be neglected and hence:-

L = 12.571 log e j - 21 nH 10.2

As an example consider a single loop inductor needed to operate at 10GHz. At this frequency the wavelength on a typical MMIC will beapproximately 12 mm (assuming a microstrip effective dielectric con-stant of 6.9). To ensure that the self-resonant frequency of the inductoris far higher than 10 GHz, the overall diameter of the loop should be lessthan A/20, i.e. in Equation 10.1 'a' should be no greater than 0.3 mm.From loss considerations the track width may be considered not to beallowed to be less than 20 microns such that from Equation 10.2 thelargest inductance that can be formed from the single loop geometry is1.5 nH. The self-resonance of such inductors on 200 micron thick GaAswill be greater than 20 GHz. For the larger diameter inductors theproximity of the ground plane reduces the inductance by a factor (1 +A), where A is given by A = (5.2 ± 1.5)a.

The ribbon or straight inductor has a greater inductance than the singleloop inductor having the same physical length. The classical formula isgiven by:-

where 1 is the ribbon length in cm.

For a strip width where W » t h e metallization thickness and where 1 >50W this formula reduces to:-

L = 21\loge\ — \+0.5\ n H 10.4

For example, if 1 = 1 mm and W = 30 microns, Equation 10.4 gives L =0.94 nH whilst Equation 10.3 gives 0.87 nH. Equation 10.4 is also useful


in converting inductance to an 'equivalent' length of transmission lineprior to optimization with CAD.

Before using the above equations due consideration must be taken ofthe effect of the MMIC ground plane metallization. This can be achievedby considering the inductor strip as a transmission line of characteristicimpedance, Z, from which it can be shown that the effective inductance,LE, is given by:-

where 1 is in mm, LE is in nH and £EFF is the effective dielectric constant.

As an example, consider the ribbon inductor above on a 200 micron thickMMIC GaAs substrate. With a width of 30 microns the track has acharacteristic impedance of 93 ohms when treated as a microstrip linewith an effective dielectric constant of 6.9. From Equation 10.5, theeffective inductance can be calculated to be 0.8 nH as compared to theresult of Equation 10.3 which gives a value of 0.87 nH. Thus, for trackwidths less than 25 microns on 200 micron thick substrates Equation10.4 provides the accurate prime inductance value whilst for wider trackwidths (Z» 100 ohms) Equation. 10.3 gives the more accurate value.

Also, when the ribbon is 'folded' into a meander line, to reduce the areaof GaAs covered, the negative mutual inductance associated with thecoupling between adjacent tracks must be considered. The method ofGreenhouse (1974) can be applied in this case to estimate the magnitudeof the effect. As a general rule, mutual coupling effects are usually smallif the line-to-line spacing is greater than five track widths where thetrack width is much less than the substrate thickness.

Equations for spiral inductors range from the original expressions byTerman (1943) through the expressions of Grover (1946) to the morerecent expressions of Dill (1964) and Greenhouse (1974). The initialdesign equations that are used for rectangular spiral inductors arederived from static, or quasi-static (low-frequency) approximations.Although developed many years ago the formulae of Grover have beenfound to be entirely satisfactory for the determination of primary induc-tance values, provided that a correction for the finite gap between theturns is used.

The formula for square muliturn spirals, with an infinitely thin insulat-ing space between the turns, is given as:-


L = 0.0008N2S8s2 10.6

where

N is the number of turns,

S is the mean side of the spiral,

b = pN, where p is the pitch of the spiral (the sum of the track andgap widths).

Equation 10.6 only applies if the turns are not wound too tightly intothe center of the inductor. Very little additional inductance results fromsuch action particularly since the extra turns increase resistance andinter-turn capacitance.

A more accurate formula for the inductance of such an inductor, whichincludes the correction for finite separation of the turns is given by:-

= 0.0008N2S l0726l0J78b !

?228S2 NnH 10.7

where the correction factors Gi and Hi are given by:

Gj = loge(W+3)/p 10.8

and

(G04\Hj=H-\ — \{023 + 0.38N + loge N/2} 10.9

where W is the conductor track width and H is a variable dependent onthe number of turns of the inductor, typically 0.2 for 4 turns and 0.25 for8 turns.

In order to model accurately the spiral inductor it is necessary to includeparasitic elements which are associated with it. These comprise theinterturn capacitance and the shunt capacitance to the ground plane.In addition the ground plane also reduces the primary inductance byproviding a negative mutual inductance to the inductor. This lattereffect is most noticeable when the overall dimensions of the spiral exceedthe substrate thickness. The equivalent circuit that is most often used


is shown in Figure 10. l(b). The element values are related to the physicalstructure as follows:-

The inductance L and the resistance R are the primary elements; Ci andC2 are the input and output shunt capacitances. These capacitances arenot equal since the presence of the under-or overpass destroys thesymmetry of the inductor; and C3 is the interturn feedback capacitance.

A number of workers have derived equivalent circuits for spiral induc-tors (Pengelly et al, 1977; Cahana, 1983; Parisot et al, 1984 and Wiemer,L. et al, 1985).

Figure 10.2(a) shows the inductances derived from Equation 10.7 for aninductor having a 12 micron wide track and an equal gap with an innerdimension of 100 micron. Also shown are the primary inductancesdetermined from the equivalent circuits generated from r.f. measure-ments (Brookbanks, 1985). The usable frequency range for the inductoris dependent upon the self-resonant frequency which is shown as a

20

15

Xc

hoo

Indu

d

5

o

r

o Design (nox Meas

-

I i

) 1 2

ground

/

1 1

3 4No. of

plane)

A

i

5turns

f

12um/i2prnp /

/ x

/ // /

/

i |

6 718

Figure 10.2 (a). Inductance of Rectangular 'Spiral' Inductors


GH

zfr

eque

ncy

Res

onan

t

25

20

15

10

\A\-

i

I 4

\

i

6

\

i i i i i

8 10 12 14 16Inductance nH

18

Figure 10.2 (b). The Resonant Frequency as a Function ofInductance

function of inductance value for the above structures in Figure 10.2(b).The proximity of the ground plane leads to a reduction in the primaryinductance value. For example, for a spiral inductor having an outsidedimension of 375 microns on 200 micron GaAs the measured inductanceis approximately 10%.

The total shunt capacitance (Ci + C2), in pF, is given by:-

(9.6 ± 2.0)10~7d2 10.10

where d is the outer dimension in microns. The capacitance is dividedbetween the input and output in a ratio of approximately 3:2 for the caseof a spiral with an underpass connection between first and second levelmetallization.


Feedback capacitance is sensitive to the gap between the inductor tracks.For the case of equal track and gaps of 12 microns, for example, themeasured feedback capacitance, C3 (in pF), is given by the expression:-

M(4.6±0.4)10'5 -0.023 10.11

where M is the mean perimeter in microns, which is taken as four timesthe mean side. The feedback capacitance is related strongly to thegeometry of the spiral and can be scaled from the values found from theabove equation by using coupled line theory (Smith, 1978).

The resistance of the inductor is related to the total track length andwidth for a given metallization thickness. The measured values for a 12micron wide track of 3 micron thick sputtered gold is shown in Figure10.3(a) as a function of total spiral length. At frequencies above approxi-mately 4 GHz skin effect losses begin to contribute to the overallresistance. In practice it has been found that the effective resistancehas increased by 50% between 4 and 12 GHz for 3 micron thick metal.Figure 10.3(b) shows, for example, the way in which the measured Qvalue of a 1.0 nH single loop inductor varies at 10 GHz as the metalli-zation thickness is increased from 0.5 to 5 microns.

10.2.1.1 Capacitors

There are two types of capacitor that are used in MMICS-these are theinterdigitated capacitor (Figure 10.4(a)) and the parallel plate or overlaycapacitor (Figure 10.4(b)). For capacitances greater than a few pico-farads it is convenient to use overlay capacitors employing a thin filmof dielectric such as silicon nitride or polyimide. Film thicknesses areusually in the range of 1000 to 3000 Angstroms for silicon nitride and0.5 to 1 micron for polyimide. Since polyimide has a dielectric constantapproximately half that of silicon nitride, the effective capacitance perunit area of polyimide capacitors can be as low as one twentieth that ofnitride types.

The interdigital capacitor is formed as the result of the fringing fieldsbetween two sets of thin metal fingers as shown in Figure 10.4(a). Limand Moore (1986) have derived a closed form expression for the capaci-tance of such periodic structures. The theory neglects the effects of thecorners in the structure and assumes the fingers to have zero metalli-zation thickness. Alley (1970) has shown that an equivalent two portmatrix can be calculated for interdigital capacitors but his work coveredonly capacitors in shunt with a transmission line. More general and


7 -

12|im track

4 6Track length, mm

Outside diameterTrackwidthMeasured •

0.1 1 10Thickness (microns)

100

Figure 10.3 (a). The Resistance of Rectangular Inductors (b).Measured Variation in Q-Value with Metallization Thickness of 1.0nH Single Loop Inductor at 10 GHz


f//////////

(a)

Cp. ={=

Series

G.I-CP4 are parasiticLPI- Us are parasiticR represents loss

Shunt

(c)

Figure 10.4 (a). Interdigital Capacitor(c). Equivalent Circuits

(b). Overlay Capacitor

accurate methods have been introduced by Hobdell (1979) and Es-fandiari (1983). These last two theories allow the derivation of thevarious components in the equivalent circuits shown in Figure 10.4(c).Figure 10.5 shows the Q factor of a 0.25 pF capacitor versus finger widthto gap ratio at a test frequency of 10 GHz. As may be seen the Q valueis low until the aspect ratio of the capacitor becomes such that thecapacitor is wide compared to its length.

For example, for a 10 micron finger width and 5 micron gaps, thecapacitance of an interdigitated capacitor can be determined by:-

= 0.83(NF-l)L 10.12

where NF is the number of fingers and L is the length of the fingers incm.


o

100

80

60-

40

20

Metallisation thickness = !Frequency = 10 GHzCapacitor length = 0.6mm

Theory

Measurement

0.1 1Finger width to gap ratio

10 50

Figure 10.5 Q-Factor as a Function of Finger Width to Gap Rationfor Interdigital Capacitors

For applications in which larger values of capacitance are required, forexample, in the case of decoupling capacitors, the overlay capacitor ofFigure 10.4(b) is employed. RF measurements have shown that theprimary capacitance in Figure 10.4(c) agrees with the value obtained at1 MHz using autoprobe measurements. For silicon nitride capacitorsthe total shunt capacitance (C2 = C pi + CP2) is given by the capacitanceof a metal plate of the same area of the capacitor to the ground plane.For polyimide capacitors the change in the fringing fields around thetwo capacitor plates leads to a reduced shunt capacitance which can beadequately described by 0.4C 2n, where C211 is the shunt capacitance ofthe silicon nitride capacitor of the same area. The series resistance, R,in the equivalent circuit gives the losses of the capacitor and arises fromresistive loss on the capacitor plates and dielectric losses in the thin film.The latter losses dominate in a MMIC overlay capacitor. Typically theloss of an overlay capacitor can be described by series resistances of 0.5and 1 ohm for silicon nitride and polyimide respectively.

10.2.1.2 Resistors and Active Loads

Resistors for gallium arsenide ICs can be made by employing either theintrinsic resistivity of the n-type layer (which for a carrier concentrationof 1017 donors cm"3 is approximately 300 ohms per square) or the


resistivity of thin deposited films. The parameters, that determine thechoice of resistor type include:-

1. Current density handling;

2. Power handling:

3. Temperature coefficient of resistance;

4. Reproducibility;

5. Reliability.

Current handling is determined by the amount of current that can bepassed through the resistor structure per unit thickness and width.Typical values are in the mid 104 A cm"2 for composite thin filmmaterials such as tantalum nitride (Ta2N). Thin metal films may havehigher current handling properties but usually have considerably lowerresistivities. The temperature coefficient of resistance is important inthat it effects, for example, the bias point of transistors. Since GaAsFETs have a positive temperature coefficient of resistance, i.e. theirdrain current decreases with increasing temperature it is desirable touse resistors with a negative temperature coefficient. Such resistormaterials will be discussed later in this chapter.

In many applications bulk GaAs resistors can be used (even thoughthese have high positive TCR). As we have already seen in Chapter 2such resistors will have a saturation characteristic which will dependnot only on the carrier concentration but also on the geometry of theresistor. This saturation characteristic can be used to advantage in logiccircuits for example where a non-linear pull-up resistor is required toload inverter circuits (Mun, 1980). However, for linear circuits suchsaturation characteristics are undesirable. The use of active loads inthe drains of common source connected FETs (Figure 10.6 (a)) ratherthan resistor loads results in better large signal performance for a givensmall signal gain (shown in Figure 10.6(b)). This is because the r.f. signalresistance of the active load is substantially higher than the d.c. biasresistance. With the active load it is possible to choose a quiescent d.c.operating point near, say, half the value of the Idss of the common-sourceFET. This circuit can, therefore, source or sink nearly equal currentsinto capacitive loads-an improvement over the poor sourcing capabilityof the resistive load.


Active loadGate width = W/2

FET Gate width = W

IDS (mA)

(a)

Active load. Gate width = W/21

Resistor load

AmplifyingFET

(gate width= W)

Figure 10.6 (a). Resistor and Active Loads (b). Comparison ofResistor Load to FET Active Load

10.2.2 Distributed Components

Two different transmission line techniques have been considered forapplication to GaAs monolithic microwave circuits. These are the mi-crostrip approach and the coplanar approach. In the microstrip ap-proach the ground plane is on the backside of the insulating GaAssubstrate material. This presents grounding difficulties (for compo-nents on the top of the GaAs) which have been overcome by the use ofvia technology as explained later in this chapter. In the coplanartransmission line approach the ground plane is on the same side of theGaAs as the active devices. In certain cases this can be more convenientthan a microstrip approach but the ground planes occupy valuable GaAsarea and also result in topographical difficulties.


The insertion loss of transmission lines on GaAs have been measuredby various workers (Courtney, 1977, Ch'en et al, 1979 and Finlay et al,1984). In an MMIC there are usually at least two dielectrics present,the GaAs substrate itself and a passivation or separation dielectricdepending on whether the transmission line is fabricated from first orsecond level metallization. For example, for the case of microstripfabricated on top of a polyimide interlayer with silicon nitride passiva-tion as shown in the diagram of Figure 10.7, the loss as a function ofstrip width and frequency is shown in Figure 10.8, where the stripthickness is 3 microns. Figure 10.9 shows the results of measurementson the dispersion characteristics of microstrip on a GaAs MMIC withfrequency where the GaAs was 200 microns thick. A number of modernCAD routines are available to predict the losses and effective dielectricconstants of such microstrip and coplanar waveguide structures (Jansenet al, 1984).

Getsinger's formula (1973) with modified constants for the effectivedielectric constant is given by:-

£EFF —SS\£S £ EO)

10.13

Strip widthW

Silicon nitridepassivation layers

Polyimide interlayer dielectric

niuTTTTiTTTTiiiiiiiiuiiiMiii|iinniiiiiinimimniiTTHiiiiiiiiiiiiiiiijirTnTiTnnnTnTrrnTinnBackplane metallisation

UhU

Figure 10.7 Example of Cross-Section of Microstrip TransmissionLines on GaAs MMIC


0.09

0-08

E 0-07

f 0.06o

S0.05c°0.04C

^ 0-03

0.02

0.01

o

-

-

-

-

-

1 1

0 2i I 1 1 1 1

4 6 8Frequency (GHz)

Strip width,micronsy 20

1 1 1 110 12

40

60800020

200

Figure 10.8 Microstrip Line Loss as a Function of Frequency andStrip Width

where es is the substrate relative dielectric constant, SEO is the micros-trip effective dielectric constant at zero frequency and G is given by anempirical formula:-

= 0.5 + 0.01Zn 10.14

where Zo is the microstrip characteristic impedance at zero frequency,and fp is given by:-

fP= 2fioh 10.15

where /u0 is the permeability of free space and h is the GaAs thickness.


8.5

,58.0

-o

7.0

6.54 6 8

Frequency (GHz)10 12

Figure 10.9 Effective Dielectric Constants ofMicrostripTransmission Lines as a Function of Frequency and Strip Width

10.2.3 GaAs Planar Diodes

The rest of this book has given extensive details on MESFET theory anddesign. As the MESFET is a major component for both analogue anddigital GaAs ICs up to 35 GHz or so, the Schottky barrier diode is alsoan important component for the higher frequency millimeter wave GaAsICs. An idealized drawing of the type of diode a number of workers havebeen developing for use in the millimeter and submillimeter frequencyrange is shown in Figure 10.10.

The important feature is that both diode terminals are accessible fromthe same side of the GaAs wafer. In order to keep the parasitics of thediode small, the region of conducting GaAs must be limited to only thatnecessary to support proper device operation. Several different tech-niques have been adopted for making Schottky diodes including selec-tive epitaxy, molecular beam epitaxy and ion implantation. Figure10.11(a) shows the construction of selective epitaxy diodes. Texas In-


Ohmic contact Schottky barrier contact

Conducting GaAs High resistivity GaAs

Figure 10.10 Surface-Oriented Diode

struments were amongst the earliest to produce diodes using thistechnique (Mehal et al, 1968; Shaw, 1966) whilst Standard Telecommu-nication Laboratories (Antell, 1971; Allen et al, 1973) used selectiveepitaxy to produce 5 to 7 jum diameter mixer diodes giving conversionlosses of 7.5 dB at 70 GHz. Vapor phase epitaxy has also been used inJapan (Sato et al, 1975; Araki, 1978) to produce diodes having a cut-offfrequency of greater than 700 GHz.

Immorlica and Wood (1978) have developed a fabrication techniquewhich exploits carefully controlled shadow masking of a proton and anevaporated beam to produce a Schottky barrier junction at the edge ofthe conductive region in a self-aligned manner (Figure 10.11(b)).

Ion implantation can also be utilized to produce surface oriented diodesas shown in Figure 10.11(c). The devices are made with material inwhich two epitaxial layers of GaAs, an n+ layer followed by an n layer,are grown upon a semi-insulating substrate using the AsCl3-GaH2system. The n+ layer was approximately 3jum thick with a carrierconcentration of 3 X 1018 cm"3 and the n layer was 0.2/um thick with a1 to 2 x 1017 cm"3 carrier concentration. Se ion implantation was usedto decrease the resistance of the alloyed Au-Ge ohmic contact. Protonbombardment was used to isolate the devices from other parts of thecircuit (Murphy et al, 1978).


Selective epitaxial pocket

(a) Selective epitaxy diode

} ProtonconvertedGaAs

(b) Shadow-masked diode

Se* implantedA

} ProtonconvertedGaAs

Oxide

Ohmic contact

High resistivityGaAs

nGaAs

n*GaAs

Metal overlay

(c) Planar ion-implanted diode

Figure 10.11 Various Planar Diode Structures

10.2.4 Low Frequency Circuit Techniques

At frequencies below approximately 4 GHz the reactances associatedwith the parasitics of MESFETs are small enough to enable them to beused without the need for matching components. Figure 10.12(a) showsthe circuit of a 50 ohm input impedance amplifier which uses threeFETs, one in common-source the other two in source-follower mode toproduce a 50 ohm output impedance with stable operation (Wilcox,private communication). As may be seen from Figure 10.12(a) the 1 dBbandwidth of the amplifier is approximately 1.5 GHz. By introducingsome inductive peaking into the drain load of the input stage thebandwidth is extended to 3 GHz. Figure 10.12(b) shows the effect ofintroducing inductive peaking at the interstage between the commonsource and source follower FETs. A bandwidth of well over 5 GHz with5.5 dB gain results. Obviously, the presence of the shunt 50 ohm resistor


-L = 0-L = 10n- L = 20n

100 MHz

100 MHz

0.5nO-l BOttO ^

Input

50 \10C

>

I

S300>

nJ>2K <> <

0.5n

50p Output

>500

Ir

Frequency 1 0 G H z

(a)

1GHzFrequency

10GHz

(b)

Figure 10.12 (a). Common Source, Source Follower Amplifier andEffect of Inductive Peaking (b). Common Source I Source Followerand Effects of Interstage Inductive Peaking


at the input of the amplifier will increase the noise figure. However, formany IF applications the high input impedance of the amplifier (withoutthe 50 ohm resistor) is desirable enabling the circuit to work directlyfrom the output impedance of either diode or FET mixers. As may beappreciated from Figure 10.12 the amplifiers discussed are d.c. coupled.It is therefore, necessary that the peak output voltage from one stagedrives the subsequent stage correctly accurate bias voltages on the FETsare therefore essential. The use of ion implantation results in moreuniform FET characteristics thus minimizing this potential problem.

Figure 10.13(a) shows another approach to wideband amplifiers at lowfrequencies (Hornbuckle et al, 1981).

A common source FET is used as the basic amplifying element. Eachcommon source stage has a buffer stage following it consisting of asource-follower and level shifting diodes. For example, the level shiftingdiodes are arranged such that a +3 volt drain voltage at the commonsource FET will result in a - IV level at the output of the source followerwhich is suitable for direct coupling to the next amplifying stage. Thecircuit of Figure 10.13(a) has approximately 14 dB gain and a 2.7 GHzbandwidth when lightly loaded (Hornbuckle et al, 1981). Feedback canbe added to such an amplifying stage to produce the circuit of Figure10.13(b). Active feedback using a FET can be used with the advantagethat this type of feedback is superior to resistive feedback as will be seen.

•—£Input "~i

(a)

VDD

HL

2

2

J

o InputOutput

Vss

J—

i

|Voo

J

J

H:

r

f

f

Output

1-Vss(b)

Figure 10.13 (a). Open Loop Amplifier Utilizing Level Shift Diodes(b) Internal Feedback Amplifier


The gain of the two types of amplifier shown in Figure 10.13 can becalculated.

The voltage gain of the circuit of Figure 10.13(a) is given by

< - gmKWAD - j —r - — 1 0 1 6

where gm is the amplifying FET's transconductance, gd is the amplifyingFET's drain conductance and ^/2 is the active load drain conductance.The gain is independent of the gate width of the FET as long as theactive load FET has a gate width which is half the width of theamplifying FET.

dB 10.17

The gm per mm gate width of GaAs MESFETs with ljum gate lengths isapproximately 90 mS and gd per mm gate width is approximately 10 mS.

Thus from Equation 10.17

G1 = 15.6 dB

The gain of the buffer/level shift stage, G2, is given by:

Z~ 10.18

where

# 10.19

Thus

G2=-1.74 dB

Series diode resistance should also be taken into account. This is usuallyof the order of 0.2 dB per diode. Thus the calculated gain for theconfiguration of Figure 10.13(a) is 13.06 dB.

The gain of the circuit of Figure 10.13(b) can be determined by calculat-ing the effect of the feedback FET as an extra load on the amplifying


drain. The added conductance is gdf + G2gmf where gdf and gmf are thedrain conductance and transconductance of the feedback FET respec-tively.

If the feedback FET has a gate width which is 25% of the amplifyingFET then the latter's gain, G3, is given by:

175gd+0.2gn

G3=8.52dB

10.20

Subtracting the 2.54 dB loss due to the buffer and diodes results in acalculated gain of 5.98 dB per stage.

The gain, G4, for a four stage amplifier such as that shown in Figure10.14 will therefore be

G4 = 13.06 + 5.98 + 5.98 + 3.1 = 28.12dB

where the last term represents the gain of the common-source FET foroperation into a 50 ohm load, the FET having a gate width of 30Qam.

Voo

Bias

< —

J—-tInput *~!77

r-d rt)

[Yl 3

= Vlr

| _

[Yli r

? D.C. Sense

L — t Output

1400Mm wide FET

4(Vm wide FET's BO^m wide FET's

Figure 10.14 Multistage GaAs IC Feedback Amplifier


10.2.4.1 Mixers

There are a variety of ways in which the amplifying and switchingproperties of FETs can be combined to achieve mixing. These have beenmore fully covered in Chapter 6, including the use of dual-gate struc-tures. The disadvantage of the dual-gate FET mixer is that withbroadband IF operation a large local oscillator (LO) feedthrough canoccur which will overload the following IF amplifier. Since the IFamplifier is integrated with the mixer on the same chip, LO rejection isneeded. The three FET mixer shown in Figure 10.15(a) can be usedwhere the FET driven by the LO signal switches the path to ground fromthe amplifying FET's source. A constant current source is also incorpo-rated, which is connected to a negative supply, to bias the amplifyingFET's source to zero voltage resulting in no current flow when theswitching FET is 'on\ The LO feedthrough is therefore reduced but theconversion efficiency of this mixer is also lower than the dual gate FETmixer. However, greater conversion efficiency and further suppressionof RF and LO feedthrough can be achieved by the use of the configurationshown in Figure 10.15(b). In this balanced approach the outputs of twomixers are summed in an active load. The central node between the LOFETs is capacitively decoupled to ground.

Since the two LO and two RF signals are 180° out of phase the LO andRF signals are suppressed at the IF sum port.

?v D D

f ,rol.F.R.F. J R.F.o- -jr

0 H (-10dBm) •-

OVd.C.I 1 1 1 LA?'

- d 1 JL ( + 10dBm)O T7TT 1

(a)

TI j • I

^ IL

(b)

F.

-L R.F. 180°T (-10dBm)

1 n iftn°(+0dBm)

h.

Figure 10.15 (a) Three-FET Mixer (b). Active Double BalancedMixer


10.2.5 High Frequency Circuit Techniques

So far we have considered frequencies where the FET's parasitic ele-ments do not dominate the device and thus the FETs can be consideredas being transconductance devices with known drain conductances.

Provided the geometries of the FETs are sufficiently small monolithiccircuit techniques can be used to produce feedback amplifiers to muchhigher frequencies than hybrid circuits employing discrete FETs. Thus,FETs can be made as parts of monolithic circuits which have much lowervalues of gate-to-source and drain-to-source capacitance than discreteversions because of the lack of bonding pad areas and the much morecompact nature of their geometry

The design principles of feedback amplifiers can be extended to muchhigher frequencies and bandwidths by using low parasitic, high tran-sconductance FETs. For example, the high gm FET with the equivalentcircuit of Figure 10.16 has been used to produce a monolithic 4 to 18GHz amplifier. In Figure 10.16 the figures shown in parenthesis arethose associated with a normal discrete FET having the same gm. Asmay be seen there is a substantial reduction in the gate-source, CGS anddrain-to-source, CDS, capacitances over a discrete FET.

1.5Gate <

400 0.03pF

0.43(0.81)pF

86mS

Ro = 1VVW ° Drain

= 0.8(0.48)pF

133

,Rs = 0.9

» 0.15

Figure 10.16 High gm, Low Parasitic GaAs FET Equivalent Circuit


Figure 10.17(b) shows the performance of the circuit of Figure 10.17(a)which uses such a FET. Such low parasitic FETs mean that many of thecircuit techniques currently used up to 4 GHz are becoming availableup to 20 GHz.

Most analog monolithic microwave circuits of today, however, use con-ventional passive techniques to produce such circuits as amplifiers,mixers and oscillators. Such techniques are very similar to those usedin the generation of conventional hybrid circuits. However one of themain advantages to be gained from monolithic techniques is the repro-ducibility of fabricated circuits and their total lack of any need foradjustment. Such an advantage results partly from a judicious choice

198

0.4

CO•°. 6

o 4

0.3

0.91

4=O17p 5 1.75

0.53

(a) 6 7 8 9 10 11 12 13 14 15 16 17 18Frequency, GHz

CO 4C

•o «5

5 145 13

(b)6 7 8 9 10 11 12 13 14 15 16 17 18

Frequency, GHz

Figure 10.17 (a). Broadband 6-18 GHz Monolithic GaAs FET GainBlock (b). Performance of 2 Stage 'High gm, Low Parasitic' FETFeedback Amplifier


of the possible configurations available to implement a particular circuitfunction. The analysis and optimization of a circuit must be accompa-nied by a sensitivity analysis which will take into account the tolerancesassociated with both active and passive elements as well as predict theeffect of component values and parasitics only being known to a certainaccuracy.

The following example illustrates the technique (Pengelly, 1981).

10.2.5.1 Sensitivity Analysis

The design of monolithic low noise receiver front-ends has shown that,with careful consideration in the use of GaAs FETs and passive compo-nents, circuits can be designed which are much more tolerant of compo-nent variations from batch to batch and the absolute accuracy of thosecomponents in circuit realizations than in other circuits which producesimilar performance.

Two design examples are presented which offer two solutions to amonolithic broadband low noise amplifier circuit at S-band. The extentto which these circuits meet certain requirements is measured in termsof sensitivities of reflection coefficient, gain flatness and noise figure toon-chip passive component and GaAs FET S-parameter variations.Such sensitivities determine the variation that will be seen from batchto batch. Also the sensitivity of the circuits to prime component valuesand parasitic component values is assessed. The monolithic GaAs FETpreamplifier forms part of a complete S-band image reflection receiverfront end covering the frequency range 2.7 to 3.5 GHz to be realized ona GaAs chip approximately 6 mm square.

10.2.5.2 Monolithic Circuit Design Principles

The first solution consists of a passively matched preamplifier using asub micron gate length FET.

The circuit diagram is shown in Figure 10.18, the circuit producing again of 9 dB with a 3 dB noise figure, where the FET is stabilized usingresistive loading, rather than inductive loading in the source of the FET,the former technique leading to a circuit which is less sensitive tomatching component variations. The circuit consumes 50 mW powerand operates from a 5 volt supply. The IC measures 3.5 to 4.5 mm. TheGaAs IC uses a considerable number of passive matching componentsto produce flat gain over the operating frequency range. Hence the Q


5.9nH 0.95pF— n n n r > — . j| o output 1

15pF2.9nH 1.26nH 4.4nH I ^ T II o Output 2

Wire bond I I

RF Input =r0.62pF:T:0.87pFS7.6nH |]1200ft

Note: Bias components not shownIntrinsic circuit elements shown only

Figure 10.18 Circuit Diagram of Low Noise Passively MatchedSplitter Amplifier

values of the lumped elements used need to be as high as is feasible tominimize the effect of their loss on gain and noise figure. At S band mostinductors are produced using multiturn spirals which use 15//m wideconductors (assuming a 15Qum thick GaAs chip with a ground plane onits backside). Since the IC was designed initially to use VPE materiala number of 'select-on-test' bias resistors are required (to enable thedevice to be operated at approximately 15% IDSS for low noise operation)where the variation in IDSS and pinch-off voltage, Vp are of knowndistribution over a GaAs wafer.

The behavior of such a circuit is shown in Figure 10.19(a),(b) and (c).The input VSWR is not particularly low because the device is matchedfor noise figure in a common source configuration. Figures 10.20(a), (b)show the results of a Monte Carlo sensitivity analysis on the circuit ofFigure 10.18 where the components are varied by up to ± 10% in alltheir values in a normally distributed fashion. From these figures itmay be expected that the variation in gain of the chip design withrandom variations in component value will be of the order of + 1.3 dB(standard deviation about the mean value of 8.7 dB at 2.7 GHz). Inreality it is likely that major component variations will be systematic-forexample, resistors will be either all high or low in value due to theresistivity of the films being incorrect. For example (From Figure10.19(a)), if all the interdigital capacitors are calculated to be 20% toolow in value there will be a reduction of 1 dB in gain over that expected.More importantly if element values are calculated incorrectly (either


GO

•o

u _•

i2.4 2.6 j 2.8 ^3.0 3.2\ 3.4 ! 3.6 3.8 \ 4 . 0 f.GHz

(a)

\L + 5%

SC-2O%

Prime

\ C + 20%

/C + 20%

/Prime

2.4(b)

2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 f.GHz

C + 20%

L—50%

2.4(c)

2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 f.GHz

Figure 10.19 Performance of Passively Matched Low NoiseAmplifier (a). Variation of Gain (b). Variation of Input VSWR(c) Variation of Noise Figure


de

vic

es

"o

mb

erN

u

<n

•ice

mb

ero

D

z

50

40

30

20

10

50

40

30

20

10

No. of devices =f = 2.4 GHz

3 4 5 6s2

No. of devices =f = 3.0 GHz

•

•

2 3 4 5 6s?

100

I 1J 17 8 9 10 11

dB

100

*—i

j 17 8 9 10 11

,dB

f d

ev

ice

s

o

mbe

z

0)

"o

jmbe

r

z

50 •

40 •

30 •

20 '

10 •

50 "

40"

44I

No.

i2 4 6 8 10 12

n No

2 4 6 8 10 12

of devices = 100o A r* ui-»2.4 GHZ

14 16 18 20 22 24 26 28 30 32

VSWR

of devices = 1003GHz

14 16 18 20 22 24 26 28 30

VSWR

Figure 10.20 Monte Carlo Results for Passively Matched Low NoiseSplitter Amplifier

due to the use of incorrect formulae or component equivalent circuitmodels failing in accuracy) the circuit response will be affected. Forexample, if all inductors are calculated to be 50% lower in value thanlater measurements confirm, Figure 10.19(c) for example, predicts thatthe noise figure will increase to over 9 dB at 3.5 GHz as against thenominal value of 3 dB. Obviously such discrepancies are unlikely butaccuracies to within 10 to 15% are normal for spiral inductors, forexample, when using the formulae of Grover (1946) or Greenhouse(1974). Thus, such changes in performance are excellent indicators ofthe circuit sensitivity.

The second circuit design shown in Figure 10.21 uses a common gate,common source, source-follower cascade to produce a low noise pream-plifier. The common gate input stage provides an almost simultaneouspower gain and noise figure match for a FET having a 20 mS transcon-ductance. Although the noise figure and associated gain of a common


12V

9.38

R.F. Input

250

57.15

±100p =H

3K4

1n 10p

1n

4304=0.5 u

\L

Figure 10.21 Circuit Diagram of Low Noise Actively MatchedSplitter Amplifier

gate stage are higher and lower respectively than a common source stagea low I/P VS WR can be achieved over wide bandwidths without the needfor balanced stages.

The FETs used, employ submicron gate lengths. The GaAs chip meas-ures 2.2 mm by 3 mm. This circuit produces 19 dB gain over the 2 to 4GHz frequency range with a noise figure of <4 dB over the 2.7 to 3.5 GHzband.

Applying the same Monte Carlo sensitivity analysis as in the firstdesign, indicates that this preamplifier is three times less sensitive tocomponent value changes, even though there are more FETs, resistorsetc. Figure 10.22(a),(b),(c) show the gain, input VSWR and noise figurechange with ± 50% changes in inductors and ± 20% changes in capaci-tors. As may be seen the design is virtually insensitive to capacitancechanges of this order and indeed the | S211 and | Sn | are much 'more'well behaved' where in fact a 50% decrease in inductance only decreasesthe gain by 2 dB in the 2.7 to 3.5 GHz band. Noise figure is also relativelywell behaved for inductance values 50% lower than the optimizedvalues.

Thus the actively matched solution appears to offer a design which, withexpected ± 10% variations in component parameters, will produce amonolithic circuit with high reproducibility. The use of implanted ma-terial also means that IDSS and Vp variations will be considerably


S2,dB

Performance of actively matched low noise splitter amplifier

C + 20%

* " * ^ Prime

2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0f.GHz

f.GHz

Figure 10.22 (a). Variation ofS2l with Matching ComponentChange (b). Variation of Input VSWR with Matching ComponentChange (c). Variation of Noise Figure with Matching ComponentChange


smaller than for a smaller VPE wafer, thus lowering the cost of thecomplete IC.

For the case of likely variations in component values, based on measure-ments made using test structures, prime element values are known towithin 15%. Such variations in capacitor, resistor and inductor valuesshow that the circuit is well behaved with acceptable performancevariations.

So far the effect of variations in the parasitic elements associated withthe lumped components has been neglected. Extensive measurementson such components has shown that the parasitic elements can bepredicted to within 30%. Thus, the circuit of Figure 10.21 has beenassessed in its performance from the viewpoint of changing the parasi-tics from the values used for circuit design (which are actually thosefound by fitting the equivalent circuit models of the component to theirmeasured S-parameters) by ± 30%.

Figure 10.23(a) shows a mean gain value of 17.75 dB over the 2.7 to 3.5GHz frequency range which is a worst case value for probable componentvalue errors and loss. If all the parasitic capacitances are varied by ±30% a worst case variation in gain of ± 1 dB is observed.

Figure 10.23(b) and (c) show, respectively, the variation in noise figureand input VSWR for the case where the active and passive componentvalues are set for the expected worse case performance and the parasiticelements are varied by ± 30%.

The actively matched solution, uses approximately 480 mW of d.c. power,with a 12 volt supply rail (because of the utilization of resistive loadingof the FETs rather than r.f. chokes).

10.3 Digital Circuits

The principal requirements of any high speed digital integrated circuittechnology allowing the realization of large scale integration are:

1. A low chip area per logic gate;

2. A low gate power dissipation;

3. A low speed-power product;

4. A low gate propagation delay; and

5. A high yield.


S,,(dB)

(a)

2.

oz

(b)

N \Cp + 30%sCp-30%

f.GHz

limit

j1i

limit

I!C Q |

j

^ 4 -Cp + 30%

P

f.GHz

/Cp + 30%

Cp-30%

f.GHz

Figure 10.23 (a). Variation ofS21 with Parasitic Element Changes(b). Variation of Noise Figure with Parasitic Element Changes(c). Variation of Input VSWR with Parasitic Element Changes


The ultra-high-speed, low power performance requirements for the nextgeneration of electronic systems and computers depend on the exploita-tion of the tremendous strides that have been made recently in MESFETand HEMT technologies. Logic gates with tens of picosecond delay, tensof microwatts of dissipated power together with wide operating tempera-ture ranges and hardness to nuclear irradiation have been producedover the last few years. MSI and LSI levels of integration in GaAs havenow been demonstrated most notably in the USA and Japan. Theimplementation of these circuits has placed severe controls on materialand processing to allow high uniformity and yields to be achieved.

Mature Si bipolar and MOS technologies have demonstrated propaga-tion delays of 300 to 400 picosecond with several milliwatts dissipationper gate (commercial ECL) and 200 to 300 pS delay with less than 1 mWper gate for laboratory n-MOS circuits. By decreasing device dimensionsa 0.3 micron channel n-MOS circuit has achieved 30 pS gate delay at 1.7mW/gate (Lepselter 1980) whilst a self aligned bipolar process achieveda 5.5 GHz divider result (Sakai, 1983). Recently a 9 GHz dividerfabricated using a super self aligned bipolar technology (SST) with atransistor fr of 17 GHz was reported by Ichino of NTT, Japan (1984).Against this background GaAs MESFETs with 0.8 micron gate lengthshave achieved 25 pS delays at 3 mW/gate (Levy, 1982) and HEMTs havedemonstrated 16.7 pS gate delays at room temperature decreasing to12.8 pS at 77K (Abe, 1982). Recently a HEMT divider has been reportedby Bell Laboratories which operates up to 15 GHz (Asbeck, 1984). Rocchiet al have also reported MESFET dynamic dividers operating up to 10GHz (Rocchi, 1983). Preliminary results on the various GaAs technolo-gies' susceptibility to radiation suggest that GaAs is an order of magni-tude harder than radiation-hard bulk CMOS as far as total dose isconcerned (107 to 108 rads) and rather better than CMOS/SOS for doserate (1011 rads/sec). With the increase in GaAs digital circuit complexityit is clear that it is important to consider such items as power dissipation,crosstalk, packing density, fan-out sensitivity and yield. The followingsection of this chapter considers the factors involved in the selection ofthe technology and circuit techniques used in the realization of MSI/LSIcomplexity circuits.

The performance of a digital circuit is best described by the speed atwhich the logic gate changes state, gate delay rg and the power requiredduring this switching time, PD. The most commonly used figure-of-meritfor a logic gate is the dynamic switching energy or speed power product,TgPD.


Since this speed-power product is the minimum energy that a gate candissipate during a logic transition and, assuming two transitions pergate, the power dissipation for a chip with N gates with an average clockfrequency of fc can be approximated by:

P = 2Nfc(PDrg)

Table 10.1 demonstrates this equation in a form where the maximumallowable number of gates per chip or the maximum speed-powerproduct is calculated for a 2 watt maximum chip dissipation. It may beseen that for a clock frequency of 1 GHz and a complexity of 1000 gatesper chip a speed-power product of 1 pJoule per gate is required.

Eden et al (1979) have analyzed the dependence of the MESFET char-acteristics on the performance of the device as a high speed switch.Consider the circuit of Figure 10.24 where the I-V characteristics of theMESFET are shown in Figure 10. 25. The drain current of a MESFETof channel width, W is given by:

where Qc is the charge per unit gate area in the channel and Vd is thedrift velocity of the carriers in the channel. Qc and Vd are bias depend-ent. The charge Qc in the FET channel and the average control field Ecare both proportional to gate to source voltage above pinch-off (VGS~ Vp)(see Chapter 2), so we can write IDS as

where K=/aW/2aLG and a is the channel depth, ju is the electron mobilityin the channel and LG is the gate length.

The input switching FET has a maximum current of IDSM when thevoltage between its gate and source is Vp + VM. The active load FET hasa maximum current of Io with the load line as shown in Figure 10.25.The current I I which charges and discharges the following logic gates isthe difference between Io and IDS for the switching FET in either its 'on'or 'off states. When the switching FET is on, I I flows from the capacitor,CL (representing the input capacitance of the following gates) thoughthe FET discharging CL. Thus

_ J — J _ T —

'L — 'DSM lo


Table 10.1 Maximum Allowable Gate Speed-Power Product forVarious Average Gate Clocking Frequencies (assuming 2 watt per chipmaximum heat dissipation)

Gates/chip

ULSI

VLSI

LSI

MSI

SSI

DEVICE

100,000

10,000

1,000

100

10

1

0.1MHz

10

1,000

10,000

100,000

1 million

10 million

Clock Frequency

1MHz

10

100

1,000

10,000

100,000

1 million

10MHz

1

10

100

1,000

10,000

100,000

100MHz

0.1

1

10

100

1,000

100,000

1000MHz

0.1

1

10

100

1,000

10,000

10GHz

0.001

0.01

0.1

1

10

100

All energies are in picojoules

When the switch is 'off' (VGS = Vp) then the current through the load isIo and flows into CL to charge it. The charging time, T, is given by:

T =_CL[VP-VP+VM-VP]

h

Now I I = IDSM/2 and thus, T = 2CLVM/IDSM.

Figure 10.24 Logic Gate


Figure 10.25 Input FETI-V Characteristics with Load Line

The logic propagation delay for chains of inverters is related to this slewtime, T. For maximum FET currents of

K(VGS-VPf

the logic propagation delay is given by:

To = 2T^4CLVM

3 3IDSM

To a first order, therefore, the gate delay is proportional to the loadcapacitance and the logic swing and inversely proportional to the maxi-mum current of the device. The peak power dissipated by the logic gateis given by:

p — T/ / —rD ~VDD1O —1DSM

Thus the power delay product is given by:

p = 2CLVDDVM

3

The logic swing is always less than VDD. Let us assume a convenientvalue of VDD equal to 27VM/16. Thus:


Dtg 8

Now IDSM = KVM2 SO that the power delay product can be rewritten as:

K can be increased by going to a higher mobility material (e.g. GaAlAsinstead of GaAs) or by reducing the gate length Lg. CL is to a large extentdominated by the effect of interconnecting lines and other logic gatesconnected to the output of the inverter. This latter effect is known asfan-out which is defined as the number of identical gates being driven.The fan-in is defined as the number of input switching MESFETs in thegate. Thus for large fan-outs the speed of the gate will be degradedsignificantly. This is covered in more detail later. Before continuing todetail the different types of GaAs FET logic that have been implementedit is worth discussing the factors involved in the inevitable comparisonbetween GaAs and Si logic. Some of the most important factors aredetailed in Table 10.2.

The major advantage that GaAs digital ICs have over Si circuits is theirfaster speed. The speed or gain-bandwidth product of a FET is deter-mined by the velocity with which the electrons pass under the gate. As

Table 10.2 GaAs vs Si ICS

COST

MATURITY OF TECHNOLOGY

LEVEL OF INTEGRATION

yield

power dissipation/gate

gate size

SPEED FACTORS

carrier velocity

parasitic capacitance

parasitic resistance

current drive compatibility


has been explained in Chapter 2 when the field under the gate is highenough the electrons reach the saturated drift velocity which in GaAsis twice that in Si. As well as this effect GaAs ICs are fabricated onsemi-insulating substrates which produce lower parasitic capacitancesto ground than in Si ICs. The only comparable small-capacitance Sitechnology is CMOS/SOS. Because of its higher mobility, GaAs MES-FETs have a higher transconductance than equivalent Si FETs. Theelectric field necessary for the electrons to reach velocity saturation inGaAs is some ten times less than in Si. Thus at low-bias voltages thespeed ratio of similar GaAs and Si FET circuits is approximatelyproportional to their low-field mobilities. At higher bias levels the speedadvantage decreases because the carrier velocity in Si increases. Figure10.26 compares the experimental power delay product for 1 micron GaAsand CMOS/SOS inverters as a function of dissipated power.

Si ring oscillators with effective gate-lengths of 0.3 micron have achieved30 pS delays whereas 0.6 micron gate-length GaAs FETs have achieved

101

a,00UD

]$GL

>>O

--de

l

I1O-1o 10Q.

10"2

1(

_

* /CMOS/SOS / /

/GaAsFET

-

i i i i i i i l l i i i i i i M I i i i i

r1 io° io1

Power, mW102

Figure 10.26 Comparison of Si and GaAs 1 pirn Gate RingOscillators


the same performance. The speed advantage of GaAs over Si using thesame circuit technique is approximately two.

10.3.1 GaAs Digital Circuit Techniques

There are three basic types of FET technologies that have becomepopular in digital applications. These are the depletion-mode FET(DFET), the enhancement mode FET (EFET), and the enhancementmode junction FET (E-JFET). A brief description of each of these is nowgiven prior to a more detailed explanation of the parameters affectingthe speed and complexity of the circuits.

10.3.1.1 Depletion-Mode Logic

In depletion-mode logic the FET is considered to be normally 'on', i.e.negative gate-to-source voltage has to be applied to the FET channel toturn the FET 'off'. The DFET therefore has the largest current drivecapacity per unit gate-width which allows DFET logic to achieve thehighest speed of conventional GaAs FET logic. DFET circuits alsopossess low fanout sensitivity but display high power dissipation. Thepinch-off voltage, and thus the logic swing, can be made quite high (e.g.-2.5 volts) giving a high noise margin. DFETs are usually used in eitherbuffered FET logic (BFL) circuits or Schottky diode FET logic (SDFL)circuits. The BFL gate was developed by Hewlett-Packard (Van Tuyl,1974) and uses DFETs with level shifting diodes to make the input andoutput logic levels compatible. The negative voltage swings are pro-duced by level shifting the positive drain voltages at the gate output.Level shifting diodes are used in the source-follower output stage of thegate (Figure 10.27) This extra circuitry adds both delay to the switchingtime of the gate and power consumption. Because of this power con-sumption BFL is not suitable for LSI complexity circuits (that is, circuitswith greater than 1000 gates).

The SDFL gate was first developed by Rockwell (Eden, 1977) anddissipates approximately one-fifth the power of BFL but is also slowerby about two. Figure 10.27 shows a schematic of a SDFL gate wherevery small Schottky diodes perform the input OR function and alsoprovide level shifting. The invert operation is performed by the FETsin the second stage. Because the diodes are very small and lower powerdissipation is achieved, SDFL circuits are capable of dense packing(^1000 microns2/gate). SDFL is, however, sensitive to fanout such that


Figure 10.27 High Speed GaAs Logic Gates (a). Buffered FETLogic (BFL) NOR gate (b). Schottky-Diode FET logic (SDFL) NORgate (c). Direct-coupled FET logic (DCFL) NOR gate

for fanouts greater than 3 either buffer stages or wider FETs are neededin order to maintain speed.

10.3.1.2 Enhancement-Mode Logic

In enhancement-mode logic the FET is considered to be normally 'off',i.e. positive gate-to-source voltage has to be applied to the FET channelto turn the FET 'on'. Because the control voltage is positive only onepower supply is needed and the gates can be cascaded directly. This logicis, therefore, often known as DCFL (direct coupled FET logic). Thepermissible voltage swing is rather low because Schottky barrier gateson GaAs cannot be forward biased above approximately 0.8 volts withoutdrawing excessive gate current. A logic swing of 0.5 volt, therefore,although being a desirable goal, leads to the need for very tight controlin the fabrication of very thin active layers so that the FET is totallydepleted at zero gate bias but has a high transconductance per unit gatewidth when the device is 'on'. The very low power consumption andcircuit simplicity lead to high packing density (^200 microns2/gate) atonly slightly slower speeds than SDFL. The fastest circuits reported(Sadler, 1983) have been with heavily forward-biased DCFL (15 pS gatedelay) but under such conditions excessive gate current affects thereliability of the circuits. In normal operation DCFL using EFETs is


approximately two to four times slower than BFL. Table 10.3. comparesthe main features of BFL, SDFL and EFET DCFL.

The more difficult fabrication procedure of EFET logic compared withDFET logic can be partially overcome by the use of a p-n junction gateFET( JFET) since the larger built-in voltage of the p-n junction meansthat the JFET can be biased to approximately 1 volt without excessivegate current being taken (Zuleeg, 1978; Immorlica, 1977). E JFETs havethe lowest power consumption (approximately 50 microwatts/gate) atgate delays two to four times those of BFL for complex logic circuits.Table 10.4. compares the parameters of the FETs discussed.

Several variations to the main circuit techniques described above havecome to the fore over the last two years. The logic gate shown in Figure10.28(a) has been employed by Hewlett Packard in their word generator(Liechti, 1982) in order to reduce the power dissipation of the BFL gate.By removing the source follower, the output stage power dissipation isdecreased at the expense of fanout capability. The second gate is amodification of a BFL gate with the addition of a diode acting as aspeed-up capacitor, Figure 10.28(b) (Namordi, 1982) since at the highestfrequency of operation the reversed bias diode acts as a capacitor. Thediode needs to be a large area device to provide the correct capacitancevalue. Another variation to BFL is the LPFL gate of Figure 10.28(c)which is essentially a compromise between BFL and DCFL. The FETs

Table 10.3 Logic Gate Comparison

BFL

High Speed with fan-out

Large power dissipation,s 5 m/W gate

Good drive capability,Fo^3

Poor packaging density,= 1000 m /gate

Two power supplies

Poor fan-in

Limited to MSI-LSIcomplexity

SDFL

Medium speed with lowfan-out

Medium power dissipation,s 1 mW/gate

Poor drive capability,Fo^3

Medium packing density= 500/*m2

Two power supplies

Good fan-in

LSI complexity

DCFL

Medium speed with lowfan-out

Low power dissipation,<5QaW/gate

Poor drive capability,Fo<;3

Good packing density= 200//m2/gate

One power supply

Poor fan-in

VLSI complexity


Table 10.4 GaAs FET Comparison

Device Parameter

Pinchoff voltage, V

Gate turn-onvoltage, V

Current capacityMA/^m

Power dissipation

Process controls

GaAs FET

Depletion-ModeFET-(DFET)

Variable -0.7 to-2.5

High compared toVp

High 0.1

High

Medium

EnhancementMode (FET-(EFET)

Fixed 0.0

Low +0.5

Low 0.01

Low

Stringent

EnhancementMode JunctionFET -(E-JFET)

Fixed 0.0

Medium +0.7

Low 0.01

Low

Stringent

have a pinch-off voltage which is close to zero volts but do not requirethe tight control on pinch-off voltage that EFET DCFL needs (Nuzillat,1981).

Welbourn et al (1983) have produced a new logic gate called capacitorcoupled logic (CCL) which uses depletion mode FETs and inter-FET

Figure 10.28 Variations of GaAs Logic Gates (a). Higher switchingspeed-Lower power dissipation-Less fan-out capability (b). Higherswitching speed for low fan-out (c). Medium switching speed-Mediumpower dissipation-Less critical pinchoff control


capacitors thus removing the need for a negative power supply topinch-off the inverter FETs. The circuit is shown in Figure 10.29(a). Thegate does not operate down to d.c. but can be made to do so by incorpo-rating another diode as shown in Figure 10.29(b). The main advantageof such a scheme is that the logic is more tolerant of variations inpinch-off voltage than DCFL. CCL has a speed power product compa-rable to DCFL whilst the noise margin and fan-out capability areconsiderably greater. CCL can be considered for LSI level circuits.

Since the first edition of this book was published there has been atremendous growth in both analogue and digital circuits on GaAs. Inmany respects analogue circuits have used relatively mature technolo-gies in their fabrication. This has not been the case with digital coun-terparts where both the fabrication of the FETs and the manufacture ofthe GaAs together with its implantation have been aimed at producinghighly repeatable d.c. and dynamic parameters. The Japanese have, inparticular, developed such techniques as self aligned ion implantationfor n+-layer technology (SAINT) (Yamasaki, 1982 and Ino, 1982) toreduce parasitic series resistance in high performance LSI circuits. Alsothe recent introduction of dislocation free LEC GaAs has resulted indramatic reductions in threshold voltage standard deviations whencompared with conventional LEC material (by factors of four) (Ohmori,1984).

Figure 10.29 Capacitively-Coupled Logic Gate (CCL) (a).Capacitively-coupled NOR gate (b). Modified capacitively-coupledNOR gate


10.3.2 Circuit Models and Simulation

In order to design BFL gates the device widths, ratio of widths andnumber of level shifting diodes have to be determined. For simplicitywe shall assume the piece-wise model characteristics of the FET anddiode as shown in Figure 10.30(a). The ratio of the load FET, W L, to theswitch FET, Ws is determined by consideration of the logic gate opera-tion. When the input to the switch FET is at - VP such that the FET isturned 'off the load FET charges the gate capacitance of the followingsource follower and other parasitic capacitances, Cp. The voltage at thedrain of the switch FET is given by:

V =Q

(rGS

= f * hss(WL /Ws)dt/(CGS + CP)

where

'DSS

ino

VD5Q FET I-V characteristics

'DSS AAI II I

0.5 1

0.6 0.75

b Diode I-V characteristics

VDDVD5

c Load line analysis of input FET

Figure 10.30 Assumed Transfer Characteristics of Devices


When the input to the switch FET is zero volts, the switch FET is Wand its current is composed of that from the load FET and the dischargeof (CGS + Cp). The current is given approximately by

l — 'DSS 1DSS\"^r

The voltage at the drain of the switch FET is given by

V - Q

For TR and TF to be equal the ratio of Wi/Ws must be 0.5 (equal rise andfall times producing the fastest switching speed).

The ratio of source follower FET width to current sink FET is normallyunity since the current source has to be able to handle all the sourcefollower current.

The number of level-shifting diodes needed can also be calculated as afunction of the pinch-off voltage of the FETS. The drain voltage of theswitch FET will be equal to VDD when the input to the gate is low.However, when the input goes high the drain voltage will become equaltoWi/Ws,i.e.0.5.

The output voltage for each logic state is, therefore, given by:

Vin =-Vp> VO=VDD -VGS(low)-0.75n

Vin=O, Vo=0.5-VGS(high)-0.75n

where n is the number of diodes and VGS(IOW) and VGs(high) are thegate-source voltages of the source-follower when the input is low or highrespectively.

In order for the input and output logic levels to be equal

VDD-VGS(low)-0.75n = 0

0.5 - VGS (high) - 075n = -VP

The maximum current that can be supplied via the source-follower isIDSS. Thus n = (0.5 + VP)/0.75 and VDD = VGS(IOW) + 0.75n.


When the input goes low, the drain voltage will charge towards VDD andVGs(high) will be clamped at 0.75 volt because the source follower gatewill draw current. The load FET Vbs is greater than zero. Let VDS = 1volt so that the load FET is in the saturation region.

VDD=0.75 + l + 0.75n

= 1 + 0.75(1 + n)

For example if Vp = -2V then three diodes and a drain rail voltage of 4volts are needed. If Vp = - I V then the number of diodes reduces to 2and VDD to 3.25V.

The value of the source rail voltage, Vss, is controlled by the low outputlogic state since with the FET operating in the constant current modeV D s<lVand |Vss |>l+ |V P | .

We are now in a position to estimate the power dissipation in the lowand high logic states.

For the logic low state, PD(IOW) = (VDD + VSS)IDSS. For the logic high state,PD (high) = IDSS((1+WLWS)VDD+VSS). Thus, the average power dissipa-tion is given by:

DD

A similar analysis can be done for the SDFL gate. It is left as an exercisefor the reader. The average DC power dissipation is given by:

p —D ~ ws

The DCFL gate can employ either a resistive or depletion-mode activeload. The load lines for these two alternatives are shown in Figure 10.31.In order to achieve equal rise and fall times at the output drain the areabetween the static and dynamic load lines should be equal. This condi-tion determines the value of the load resistor, RL or the width of theactive load FET. Normally VDD = 1 volt for DCFL and, in practice, theload line of the active load is virtually resistive since the FET does notgo into saturation. For this reason most workers in the field use asaturating resistor rather than a depletion mode active load. Thecarriers saturate at a field of 3.2 X 103 V/cm in GaAs so that with aresistor ohmic contact spacing of 1.5 microns the current through theresistor saturates at 0.5 volt.


10.3.2.1 High Frequency Analysis

Greiling (1984) has reported the effects of circuit layout on the switchingspeed of a buffered FET logic gate. Consider the NOR gate shown inFigure 10.32 where the parasitic capacitances Ci, C2 and C3 can bevaried to simulate changes in layout. Figure 10.33 shows the transientbehaviour of the gate on varying RL whilst the delay time of the gate isplotted as a function of the values of the capacitances in Figure 10.34.Most effect is due to Ci which represents the parasitic load capacitanceat the high impedance drain node.

Van Tuyl (1974) showed that as the FET gate width is decreased thespeed of the gate remains constant until a width is reached whereby thedelay increases. Now, IDS is proportional to gate width and parasitic

Resistance-loadinverter

DFET-loadinverter

v G S =v H

_ Dynamicload line

V|_-« Logic swing-

VDSComparison of load lines

vGs-vL

Figure 10.31 Comparison of E-FETLogic Gate Loads


VDD

¥

Figure 10.32 NOR Gate with Loading Added

capacitance is a function of gate width and fringing capacitance, CF.Thus even when the device becomes very narrow the fringing capaci-tance, CF, becomes a large fraction of the total parasitic capacitancealthough the current drive decreases directly with device width. Figure10.35 shows the results of calculating gate delay and power delayproduct versus gate width for one micron gate length logic.

A comparison of the performance of the standard logic gates (DCFL withDFET load, DCFL with resistive load, SDFL and BFL) can be made.

Gate delay can be defined either as:

(1) The delay between the 50% levels at the input and output of thegate, TR and TF. with the rising and falling delays averaged; or

(2) The time constant of an exponential rise and fall TR and TF withthe two averaged. Greiling (1984) has simulated the four gates withthe fanout, Fo, set at 1,2 or 3. The results are shown in Figure 10.36.It can be seen that the BFL gate is the fastest as expected with theleast sensitivity to fanout. However, the gate power dissipation isalso most important and DCFL, with its accompanying speed com-promise produces a two order magnitude decrease in dissipation.Table 10.5 summarizes the effects of variations in process parame-ters on the performance of the various logic families.


3-0.5

'...Load resistor =250

_J I I0 50 100 150 200 250 300 350

Time, psec

Figure 10.33 Transient Response ofBFL NOR Gate as a Function ofRL

Figure 10.34 Delay Time vs Capacitance Loading


140 -

120

100

1 80

| 60

40

20

-

l

-

-

-

0

5iim

-«—r

I

20

rrr —_ ^ =

| |40 60

device width, im

F.O.«1Lg=1.0/imH = 200^im

= = = = =

i

80

-i3.5

_

-

-

-

3.0

2.5^;u

2 .o |Q.

1.5 g-at

1-0|

0.512

0100

Figure 10.35 BFL Inverter Performance vs Device Width

10.3.2.2 Performance versus Complexity

Greiling et al (1981) have estimated the performance tradeoffs as circuitcomplexity is increased for BFL, SDFL and DCFL. Irrespective of circuittype two fundamental factors will degrade circuit performance as chipcomplexity is increased. A higher percentage of chip area must beassigned to interconnect wiring and the increased parasitic capacitancewill degrade speed as outlined in the last section. Also, the chip thermaldissipation will limit the drive current that is available to each logicgate. The gate delay due to capacitive loading can be divided into threeparts:

(1) That due to the current drive of the logic gate;

(2) That due to the logic swing; and

(3) That due to the average interconnect capacitance per 'cell'.

The first two factors depend on the type of GaAs logic gate used whilstthe third depends on gate count.

The available drive current per unit gate width of the output FET of agate and its dissipated power can be calculated. Let us assume a 2.2volt internal logic swing for BFL, 1.8 volt for SDFL and 0.4 volt for DCFL.


Shaded bars indicate pulse delay T=(Tf+Tr)/2and unshaded bars indicate average timeconstant T=(ff +rr )/2 for various values offanout, F.O.

500r l T n n O f fscale

400

in

§300

100

FO-1

E-R E-D SDFL DFET

Figure 10.36 Comparison ofBFL Inverter Response Speed

Alexopoulos et al (1980) have calculated the interconnect capacitanceswhich include the parasitic capacitances to ground and the mutualcapacitances between the interconnecting lines. Table 10.6 shows theresults of these analyses. By combining these results with the averageinterconnect demands for the three different types of logic families it ispossible to produce an estimate of the added gate delay versus gate countas shown in Figure 10.37. Thus the total gate delays are the sum of theintrinsic gate delay and the added delays. In obtaining the results givenin Figure 10.37. a number of assumptions have been made. These are:

(1) The maximum limit on FET gate width is set at 200 microns;

(2) The maximum chip area is set at 1 cm ;

(3) The maximum chip power dissipation is set at 2 watts; and

(4) The average number of interconnects per logic 'cell' is set at three.

Some interesting and far-reaching conclusions can be drawn. Firstly,BFL logic becomes power limited very quickly when the number of gates


Table 10.5 Effects of Process Parameter on Circuit Performance

Process Parameter

Increasing doping density

Reduced layout area withdirect connection of gatemetal to ohmic contacts

Shorter gate length

Reduced pinch-off voltagein level shifter

Reduced pinch-off incomplete circuit

Effects on DeviceCharacteristics

Increased tranconductanceIncreased currentIncreased gate-sourcecapacitance

Decreased parasiticcapacitance

Lower gate-sourcecapacitance

Small increase in outputimpedance, large drop incurrent

Decrease in switchtransconductance,Decrease in current

Effect on CircuitSpeed and Power

Higher speedHigher power

Higher speed, especially insmaller lower powercircuits

Higher speedLittle effect on power

Large power decreaseMinor speed loss

Decrease in both speedand power

exceeds approximately 20. FET gate widths must decrease to satisfythe 2 watt chip power limit. SDFL is limited by the same cause at gatelevels of around 100. Thus, as we have seen in a previous section thespeed of BFL and SDFL will be degraded as the gate widths are reduced.If the logic swings and FET pinch-off voltages are reduced some increasein complexity can be produced but the uniformity of the FET parametersbecomes more important. DCFL becomes chip area limited above about3000 gates and as the gate width is decreased the added delay increasessuch that circuits with gate levels above 100,000 are impractical. Pre-sent state-of-the-art results confirm these predictions. BFL for examplehas reached MSI levels with for example the HP word generator shownin Figure 10.38 which is composed of approximately 100 gates andoperates up to 5 GBit/sec (Liechti, 1982). The circuit contains 400transistors and 230 diodes contained on a chip of 1.6 X 1.1 mm. Typicalflip-flop frequency divider output transition times are 80 psecs. Devel-opment efforts in SDFL have concentrated on achieving LSI levels. Forexample Lee et al (1980) have reported successful operation of an 8 by8 multiplier having 1008 gates with over 6000 active components. Thechip measures 2.25 by 2.7 mm and has a peak power dissipation of 2.08watts.


Table 10.6 Logic Gate Delay and Power Dissipation

Intrinsic Gate Delay, pS (Fo = Fi = 1)

Added delay per FOUT, pS

Added delay per FIN, pF

Added delay per mm of interconnectline, pS

Power dissipation per gate, mW (20//mnominal FET)

DFET

68

12.5

14.5

37

12

SDFL

150

50.5

40.5

90

2.2

EFET

170

106

23

121

0.06

DCFL has achieved even higher levels of integration with a notableachievement being the 16 X 16 multiplier from Fujitsu (Nakayama etal, 1983) which contains 3168 gates, has a multiply time of 10.5 nS witha power dissipation of 952 mW corresponding to a propagation delaytime of 160 pS per gate and a power dissipation per gate of 0.3 mW.Perhaps the major advancement in GaAs LSI has been made in the areaof static RAMs where, for example, Nippon Telegraph and TelephoneCorporation have produced 4Kb SRAMs with 26,600 devices per chipand access time of 2 nS with total power dissipation of 0.9 watts. The

600

£500

IUOOT3

!200

100

200/jm device width limit

10

ENFET

103

Gate count

200

150

100

50

010*

Figure 10.37 Added Gate Delay vs Gate Count


Figure 10.38 Photomicrograph of High Speed GaAs Word Generator(Courtesy of Hewlett Packard)


circuit uses 1 micron gate length self-aligned FETs and 2 occupies a chiparea of 15.5 mm2.

Significant improvements in the speed performance of digital GaAs ICscan be made by scaling both the device and the circuit dimensions. Ashas been explained earlier the switching speed of a logic gate is afunction of the drive current through the FET, the device and parasiticcapacitances, the fan-out of each gate and the interconnect loading. Themaximum reduction in logic gate delay will occur by shrinking thedesign rules for a given circuit. An estimate of logic gate delay versuschip complexity can be made as a function of the minimum designfeature size. As chip complexity increases for given design rules andgate dissipation a higher percentage of the chip area must be devotedto interconnect wiring and the drive current available to each logic gatemust be reduced to maintain total chip power dissipation. If the designrules are decreased then the intrinsic gate delay, gate areas and inter-connection lengths are reduced. Because many important logic 'buildingblocks' such as arithmetic logic units, multipliers, and multiplexers onlyrequire MSI and LSI complexity an analysis of design rule scaling onBFL is significant. Snyder et al (1981) have produced a three-dimen-sional capacitance analysis program that can be used to calculate the

W J

h«200j j .m " T

Interconnect line geometryand capacitance matrix

Figure 10.39 Geometry and Capacitance Matrix for InterconnectLines


oTO

OO

120

100

80

60

40

20

0

Gate

A LB L

" C L

-

-

delay vs fan-out for

g = 0.5jim, A—

• 2 ^ —

^^3

i i

1jim

• 2

i

BFL gate

C . — ^

B* ^

I i

3Fan-out

Figure 10.40 Gate Delay vs. Fan-out for BFL Gate

capacitance matrix of the electrodes of a typical logic gate as shown inFigure 10.39. FET parameters such as gate resistance, transconduc-tance and Schottky gate leakage current can be scaled with gate width.Figure 10.40 shows the delay of a BFL gate with unity fan-in as afunction of fan-out for three cases. Curve A shows the results for 1micron gate length FETs whilst Curve B shows the correspondingperformance if the dimensions are reduced to simulate a 0.5 micron FETgate. In Curve B all the dimensions in the logic gate have been reducedwhilst in Curve C only the gate length of the FETs has been reduced to0.5 microns. As can be seen in order to maximize the speed enhancementproduced by shorter gate lengths it is necessary to reduce all device andcircuit dimensions.

As complexity is increased the power dissipation per logic gate must bedecreased to maintain a constant and acceptable chip dissipation. This


120r

100 -

8 0 -

60

20

j* = 0.25pm

gm(1)=180m5/mmgm(2)=117mS/mm

2 4 6 8Power dissipation, mW/gate

10 12

Figure 10.41 Intrinsic Gate Delay vs Power Dissipation

is accomplished by reducing the FET gate width for a given technology.If we assume that a typical 'gate ceir consists of an area containing FETs.two Vow' and Tour column' interconnects then the area of this cell willbe virtually proportional to the design rules for a given chip complexity.Now the gate delay is composed of the intrinsic gate delay (with a fan-outof zero) and the added gate delay due to capacitive loading. The intrinsicgate delay has been calculated as a function of gate dissipation for twovalues of FET transconductance and three values of minimum designfeature size. The results are shown in Figure 10.41. Three conclusionscan be drawn:

(1) The intrinsic gate delay is inversely proportional to the FETtransconductance.

(2) The intrinsic gate delay is proportional to the design rule featuresize; and

(3) The intrinsic gate delay is only sensitive to power dissipation forvery small dissipations.


3.0

2.5

^ 2 . 0

lay

• D

£ 1.5oen

"D<b

TD

0.5

n

1\

\

-

i

0 2Power

i

4dissipation,

i

6mW/gate

•

i

8

I

10

Figure 10.42 Added Gate Delay vs Power Dissipation

The added gate delay as shown by Figure 10.42 is dependent on thepower dissipation because of its direct dependence on capacitive loading.Thus for given design rules it is necessary to estimate the effect of theinterconnect wiring on gate delay. The capacitance matrix for theinterconnections assumed earlier can be produced by solving Poisson'sequations with arbitrary geometries. The capacitance is not a strongfunction of the design rules since, in general, the line width-to-gap ratiowill be constant and the line widths involved are much less than onesubstrate thickness. The use of Rent's rule from Cook's paper (1979) canbe used to calculate the probability of an interconnect leaving anassembly of logic cells and the average length of that interconnect beforeit is terminated. By combining the cell area dependence on complexityand design rules with the results from Rent's rule it is possible toestimate that the capacitive loading of the interconnect wiring is pro-portional to the square root of the design rule when the complexity isrelatively low but becomes linearly dependent on the design rule for high


500

400

o.

j?300

£200en

1 HH

01

gm(2) = 117mS/mmF1 = F0=3Q=2W/chip

-

10 100Gates/chip

1 1

1000 10000

Figure 10.43 Total Gate Delay vs Chip Complexity

complexity. For example, the total gate delay for a fan-in and fan-out ofthree with a maximum chip power dissipation of 2 watts is plotted as afunction of chip complexity in Figure 10.43. For depletion mode logic, theFET widths have to be around 2 microns for chip complexities approach-ing 2000 gates. It can be seen clearly from Figure 10.43 that consider-able benefits in reduction of gate delay accrue from sub-micron FETsparticularly as the complexity is increased. For example, the addeddelay due to interconnects for a 1000 gate, 0.5 micron design rule circuitis approximately 20% greater than for a 500 gate, 1 micron design rulecircuit. However, it should also be pointed out that the added difficultyin producing 0.25 micron FET, high complexity circuits outweighs thebenefits to be gained as outlined here at the present state of lithography.


10.4 Technology of GaAs Integrated Circuits

In order to give the reader an understanding of the relative complexityof GaAs integrated circuit manufacture when compared to discrete FETdevices, the approaches being taken to define high yield processes arereviewed, Because many laboratories developing GaAs ICs have alreadyconsiderable experience in the fabrication of discrete FETs there tendsto be a marked resemblance between the two fabrication processesparticularly where epitaxial layers are used.

To realize low noise and high gain FETs, the devices are optimized withrespect to material parameters and device geometries as described inChapter 2. Apart from the use of low resistance ohmic contacts usuallyutilizing AuGe/Ni, the FETs have multiple parallel gates for analogueapplications to reduce gate resistance and as thick a gate metal as ispossible. Photolithographic techniques are usually employed to definegate lengths down to 0.5/tm. Below that value electron beam lithographyis used using such equipment as the Cambridge EBMF2 (Lawes, 1979).Electron beam lithography is used for gate lengths greater than 0.5/miwhen a fast turn-around time is required (since no high definition gatemask is required) by directly exposing a resist using the electron beam.The electron beam machine automatically aligns the gates to alignmentmarks usually defined close to source and drain contacts which havebeen previously defined. Gate lengths of 0.2jum can be successfullydefined.

In monolithic circuits device bonding pads generally do not occur asdirect connection to the circuit is made thus reducing the parasiticcapacitances (such as CDS). n+ contact layers are generally only usedwhere the lowest noise figures are needed and the FET devices employa channel recess to minimize this factor. A recessed gate structure canalso improve the power handling capabilities of the FETs as has alreadybeen discussed in Chapter 3.

When using ion implanted material the implants are arranged to givethe required FET or diode performance characteristics. Implantationmay range from simple Gaussian profiles involving one implant to morecomplicated implantations involving several energies and doses as wellas different species. For example, Hewlett Packard, in their BFL logicICs use a dual implant of Se and Si to produce the n, n+ regions requiredfor low forward resistance diodes and low channel resistance FETs.


10.4.1 Some IC Technologies-A Review

Figure 10.44 shows the silicon like planar ion-implanted process tech-nology developed by Rockwell in order to realize the advantages of ionimplantation in GaAs (Zucca et al, 1980). The figure shows the deviceprocess steps necessary to fabricate a planar GaAs integrated circuitincorporating a FET, a level shifting and a switching Schottky diode.Fabrication of the device wafer is started by the deposition of a SisN4(silicon nitride) layer onto a flat, qualified, semi-insulating GaAs sub-strate (qualification of substrates is described in Chapter 4). This layerof Si3N4 remains on the slice during all subsequent fabrication steps. Afirst photoresist stage defines the device and circuit areas which requirelow dose implants such as the channels of FETs. A shallow Se implant(Figure 10.44(a)) is then followed by a deeper n' implant (Figure10.44(b)) for device contact areas or Schottky barrier switching diodesafter exposure of a photoresist. The implantation steps are followed byencapsulation of the slice with Si3N4 and annealing at 850° C in an H2atmosphere. (Figure 10.44(c)). This high temperature anneal convertsthe shallow n-Se-implanted areas (approximately 1500A thick) into theFET active channel layers with pinch-off voltages dictated by the im-plant conditions. The n+ implanted areas using sulphur at a higherdosage provide a high conductivity region.

Device ohmic contacts are defined next with a standard photoresist andlift-off technique (see Chapter 4) (Figure 10.44(d)). After alloying theohmic contact areas at 450°C, a photoresist operation is again performedto define the Schottky barrier metallization for the FETs and diodes.Rockwell use Ti-Pt-Au for the Schottky barriers as well as for the firstlayer circuit interconnections (Figure 10.44(e)). A dielectric layer is thendeposited onto the entire wafer as insulation for the second layerinterconnection and dielectric for circuit capacitors. Via holes throughthe dielectric are used for interconnections between the first and secondlayers of metals. Figure 10.44(g) shows a cross-sectional view of thecompleted process where the interconnects can be clearly seen. Theapproach taken by LEP, France is to use a self-aligned process wherethe gates are automatically aligned to the n+ regions. A cross-sectionalview of the process is shown in Figure 10.45. The n-type active layer isgrown by the low temperature VPE technique discussed in Chapter 4.Isolation between active layers is obtained by implantation with boronusing a photoresist barrier over all the active areas. After the photore-sist is removed, a 5000A thick layer of aluminum is deposited. The gatemask is applied to define the transistor gate areas. The 3 micron gatesare undercut beneath the 2 micron-thick, photoresist barrier leaving a


Planar GaAs IC fabrication steps

Insulator deposition and masking for N- implant/ Insulator/ Photo resist

(a)

lol

N- Implant

Encapsulation and annealMulti-layer dielectric

Ohmic contact metallisationAuGe/Pt contact Insulator

Schottky barrier and interconnect metallisation_.,„ IA Schottky barrierJ./Pt/Augate v /interconnect

Cutaway view of a planar GaAs circuit fabrication with twolocalised implants.

Planar GaAs I.C._. i . First-second Second-level

Second-level interconnect via /interconnect

Substrateinsulator

\

\First levelinterconnect metal

Figure 10.44 Planar GaAs Circuit Fabrication Process Using IonImplantation Directly into Qualified Semi-Insulating SubstrateMaterial Adopted by Rockwell


PhotoresistIon implantation

l inn

(a) Semi-insulating substrate

ist Al 0.5 urn

mmmJ(b)

MilMIHIMJMIIMS-l

N.iMliml

; • : • • • ' * K ^ a #-:•• •• • . - 1 K V M

(c) S-lI H i i l l i l

•\:.-h-.l•• :\J& Irff-TV ^ / f

(6) S-ln i i i i i i i i n l i M M i

YY YFigure 10.45 LEP Self-Aligned Process


1 micron effective gate length as shown in Figure 10.45(b). A 5000A thicklayer of AuGe is deposited on the substrate. The 3 micron-wide photore-sist on top of the gate prevents the AuGe layer from contacting the Algates. The mushroom-like gate/photoresist structure provides themechanism for self-alignment of the gate to the source/drain regions.The AuGe metal layer provides the first level of interconnections.

An insulating layer is deposited following an alloy step to ensure goodohmic contacts. A metallization layer of molybdenum (Mo) is thensputtered onto the wafer (Figure 10.45(e)) to provide the interconnec-tions between the Al gates and the AuGe ohmic contacts. After the Mometal is patterned, another dielectric layer is deposited and contact viasetched. The second level of metal interconnections is then deposited andpatterned (Figure 10.45,(f)).

Figure 10.46 shows the processing sequence developed by Plessey inorder to fabricate ICs either on ion-implanted or VPE material. Figure10.46 relates specifically to the use of implanted material.

The active channel regions and ohmic contacts of FETs, for example, areformed by a dual dose and energy implantation schedule which willproduce devices with low source to drain resistance. This implantationmay be achieved through a thin Si3N4 mask to avoid ion channelingwhich leads to poor characteristics in the profile 'tail'. The wafer afterimplantation is then capped with reactively sputtered SisN4 and an-nealed at 850°C in an H2 atmosphere for 15 minutes. Figure 10.47 showsthe result of doing this using Se as the species. It can be seen that thelow energy implantation is successful in increasing the near surfaceelectron concentration to around 1018 cm""3 for the 5 x 1013 cm"2 roomtemperature implant. The active areas are defined by either a selectiveimplant or by a mesa process. Sourcedrain contacts are then definedusing a photoresist and lift-off technique and the contacts alloyed toproduce acceptably low specific contact resistances. At this point theISAT current is measured between the source and drain contacts ofmonitor FETs. The FET channels are etched to produce the requiredsaturated drain current the gates then being situated at or near the peakof the higher energy implant. Gates are produced using Ti-Al. FETsand diodes have now been produced.

First layer metallization is now defined using a photoresist and liftoffprocess-this metal may, for example, form the bottom electrodes ofoverlay capacitors. The silicon nitride for such capacitors is depositedusing a plasma enhanced deposition technique (Commizoli, 1976) andthe dielectric (of dielectric constant = 5.5) selectively removed using a


Si3N«

(a)

I Ivj./y/y/.'/. ///

n* implant

^ \ \ I I I

n implant

I I I I I I

(b)

(c)

(d)

-Si3N4Cap and anneal

_T

//////'//FET and diode formation

First level metallization

(e)

(9)

r V i a s inpolyimide [— 2nd level metallization

i—i-r *"

•\_J

Figure 10.46 GaAs IC Fabrication Sequence Adopted by Plessey


10 1 7

5x1013100KeV Se-/cmV4and

7.5 x 10'2 800 KeV Se* +/cm1/4

Room temperature implant

0.1 0.2

Depth,

0.3

Figure 10.47 Carrier Concentration of Dual Se Implant

plasma etching process (Tolliver, 1980). At this point a polyimide mate-rial is spun onto the wafer. This material has a lower dielectric constantthan Si3N4 (polyimide en = 3.5) and produces a uniform layer which canbe varied in thickness from a few thousand Angstroms to approximately10 microns by varying the spin speed, the dilution of the material or bymultiple coatings. This material is then cured to form an excellent lowloss dielectric which is used in several ways. Firstly it is used as thedielectric between metallization layers; secondly, it is used as a dielectricfor overlay capacitors; thirdly, it is used as a 'stress' relief barrierbetween the GaAs and certain other layers, such as resistive films andfinally it is used as an ion-milling barrier. In the latter case, since GaAsis removed rapidly by the ion-milling technique used to define certainmetallizations (particularly where the lift-off technique is inappropri-ate), the polyimide film (which is not milled) acts as a protective layer.

Following polyimide deposition, vias are opened up in the polyimide andthis is followed by the interconnect metallization which also forms thetop electrodes of overlay capacitors. Thin film resistors are put down onthe top of the polyimide film and interconnected to the metallizations.The polyimide film provides protection for the active and passive com-ponents on the IC.

In many cases it is necessary to provide low capacitance inter connec-tions between components such as FET sources or the centers of spiral


inductors to other circuit elements. These are produced by using an 'airbridge' technology which is the same as that explained in Chapter 3.These air-bridges are usually 2 to 4jum in thickness. ,here currenthandling is of importance and where circuit losses need to be reduced,the metal thickness has to be increased. This can be achieved in twoways-either by plating-up the evaporated metal or by depositing a thicklayer of metal with subsequent definition by ion milling.

Vias have been used successfully in discrete FETs to make connectionsbetween the source contacts of the FETs and the ground plane on theback of the GaAs wafers (D'Asaro et al, 1977). In GaAs integratedcircuits it is often desirable to ground various circuit components effec-tively without the need for top surface grounding areas which aresubsequently connected to the IC package ground. Such a method (stillused for simple single-function ICs) is a severe constraint to the GaAsIC circuit designer where more than a few active devices are present orwhere the frequency of operation is above 10 GHz or so.

Monolithic power FET amplifiers which rely upon microstrip transmis-sion lines for matching circuitry, for example, present a design trade-offbetween thermal considerations and low-loss circuitry (Driver et al,1981). The thickness of the GaAs is often chosen to be lOOjum. to giveacceptable losses in the circuit, while maintaining satisfactory heat-transfer for the power FETs. With discrete FETs the GaAs wafers areusually reduced in thickness to 25jum and then plated up to a greaterthickness following the etching of the vias. With ICs this substratethickness is not possible over the entire wafer for the reasons givenabove.

Two procedures have, therefore, been developed for producing vias inmonolithic circuits (Driver et al, 1981). In the first method, large areas(or 'tubs') (typically 300//m by 1500jum) are first etched in the back ofthe GaAs wafer using an acid-hydrogen peroxide based etch. Theseareas are aligned to the FET areas, for example, on the front of the waferusing infrared techniques. A second photoresist layer is used as anetching mask to produce lOOjum diameter holes to meet the source padsof the FETs. These holes, together with the back of the wafer aresubsequently metallized to form the via connections and ground planerespectively. Figure 10.48 shows the results of such a method.

In the second method, termed the sparse Via' approach only a few largearea (i.e. 250 by 250jum) vias are used. These may occur, for example, atthe ends and the middles of transistors for source grounding with thesource effectively connected together by air-bridges on the top surface.


Source

TOm;

1 J v.

Drain

u-lOO^m

Gate

uGaAs I

/ 11

Figure 10.48 Etched Tub and Vias

Shunt connected components can also be connected to ground using sucha technique. Elsewhere on the chin the GaAs is of the required thicknessfor distributed or lumped elements.

Raytheon (Vorhaus et al, 1981) have developed a method of producingplated gold integral beam leads which extend over the edge of the chiptypically by some 15Qams. Such beam leads simplify the mounting andbonding of the GaAs chips into test fixtures or packages. These beamleads are formed using the same process as is used to produce 'air-bridges'. Development of the integral beam lead approach is aided by'dicing' the wafers, following IC manufacture, from the backside usingchemical etching. This back side etching makes possible the use ofstructures on the front side, such as leads, which extend beyond theindividual chip boundaries through what would normally be the scribegrid. The chemical dicing also introduces much less stress than me-chanical techniques and also conveniently allows the fabrication ofnon-rectangular chips.

10.4.2 Resistor Technology

It is possible to make resistors from gallium arsenide by etching a mesain the highly n doped wafer surface and then making ohmic contacts tothis feature. Such resistors have a sheet resistivity of about 300 Q/Qfora typical GaAs FET layer. This resistivity is suitable for many resistorrequirements, but mesa resistors have two disadvantages which haveled to their replacement by other resistive films.

At certain current levels, the resistance of such resistors deviates fromohmic behaviour due to electron velocity saturation. This effect involvesthe limited velocity of conduction electrons within the material at a


given applied electric field, and cannot be avoided. The effect can, infact, be used to advantage in digital circuits but is undesirable in linearcircuits. Highly doped gallium arsenide resistor films also exhibit apositive temperature coefficient of resistance (TCR), which combineswith the positive TCR of certain active components to give unacceptableparameter changes with temperature. For these reasons it is desirableto utilize other resistor systems which will give truly ohmic behaviour,a negative TCR, and also will allow various resistivities to be achievedwithout wide variations in thickness. It is also essential that thedeposition and processing conditions are compatible with the compo-nents already on the wafer, and thus materials requiring high tempera-ture deposition or annealing are precluded. Two suitable resistorsystems that have been evaluated are tantalum nitride and chromium-silicon monoxide cermets.

Tantalum nitride is deposited by sputtering tantalum in an argonnitrogen mixture. As the partial pressure of nitrogen in the plasma isincreased the deposited film changes from pure tantalum to Ta2N andsubsequently to TaN. This change is accompanied by an increase inresistivity by a factor of about 10, and the TCR decreases from +1000ppm °C-1 to about -100 ppm °C-1.

It is a useful property of such reactively sputtered films that theresistivity and TCR vary with the nitrogen partial pressure over alimited range. If the nitrogen concentration is between 1% and 10% ofthe sputtering gas, both parameters vary only slightly even though thestructure and composition of the film changes (Gerstenberg et al, 1964).This variation is shown in Figure 10.49.

A serious drawback to the use of tantalum nitride resistors has been thetendency of sputtered films to craze, indicating that the films were incompression. Attempts were made to overcome this problem by sput-tering onto heated substrates and also by heat sinking the wafers to awater cooled pallet. Various annealing procedures were also investi-gated but no satisfactory solution to the problem has yet been found.

Tantalum nitride has a resistivity of 2.5 x 10~4 Q .cm which correspondsto a sheet resistivity of 25 Q/Q at a thickness of 0.1mm. This is felt tobe the minimum thickness compatible with stability and reproducibility,even at this thickness the sheet resistivity is rather low for many circuitrequirements. In addition it is necessary to consider the current densitylimitations of the resistive films in view of the need to pass currents ofthe order of tens of milliamps. Resistor films are in general limited tocurrent densities in the range 1-10 X 104 A.cm"2 and thus circuit


ai

esis

tivity

(x

13

2

1

10-6

V\ Resistivity

\ /y/ N. TCR

y \ . .

1 0 s 1O-*

Partial pressure of nitrogen (Torr)

+ 1600

+ 1200

+ 800

+ 400

0

-400

10-3

6

TCR

(pp

m

Figure 10.49 Resistivity and TCR as a Function of Nitrogen PartialPressure for TaN Resistors

requirements severely restrict the degree to which resistors can bereduced in thickness and width. Increasing the resistor length is aninefficient solution since it not only uses more wafer area, but alsoincreases the complexity of the circuit and the risk of parasitic effectsat high frequency operation.

Cermet resistors have an advantage over many other resistor systemsbecause their resistivity can be adjusted over a wide range by varyingthe material composition.

Chromium-silicon monoxide cermets have been used extensively asresistive films (Maissel, 1970) and have been deposited by co evapora-tion or RF sputtering.

The problems of evaporation have been well documented (Ostrander,1962; Braun, 1966 and Pitt, 1967), for GaAs IC's it was considered thatthe improved reproducibility gained by RF sputtering a composite targetwould be of great value.

Initial assessment of the cermet was carried out using a silicon monoxidetarget partially coated with chromium, leaving exposed areas of siliconmonoxide. This technique allowed the composition of the sputteredfilms to be varied by altering the relative areas of chromium and siliconmonoxide exposed to the plasma. The sputtered films were assessed


initially by Auger analysis (AES) and measurement of sheet resistivityby a four-point probe instrument.

In practice cermet resistors are sputtered from targets consisting of anintimate mix of chromium and silicon monoxide powders. A film resis-tivity of 1 x 10"2 Q.cm allows resistors of 300 Q/D to be fabricated at athickness of 0.33/nn, this corresponds to an atomic concentration ofabout 55% chromium in the film. The sputtering rate of chromium isless than that of silicon monoxide, and by applying a substrate biasduring sputtering it is possible to modify the chromium content of thefilm and thus make small adjustments to the resistivity from depositionto deposition. Auger analysis has indicated that bias sputtering, induceschemical changes in the film and this effect needs to be further investi-gated.

Films of 50-60% atomic chromium have been found to give TCR's ofbetween —400 and -250 ppm °C~1, which is acceptable for circuitstability. Limiting current densities of 3 x 104A.cm~2 are achieved. Thefilms are stabilized by annealing in air at 300° C immediately aftersputtering.

A summary of resistor materials is given in Table 10.7.

10.4.3 Capacitor Technology

Capacitors are required at various stages in RF circuits and in the caseof decoupling capacitors the values required can be several hundredpicofarads. Such values can only be achieved if large areas are employedor if very thin dielectric films are used. Capacitors of values less thanone picofarad can be made successfully by using an interdigital struc-ture.

The two dielectrics used in current Plessey designs, for example, arepolyimide and silicon nitride which have dielectric constants of 3.5 and7.2 respectively. Silicon nitride has the advantage that it can be appliedin thinner layers than polyimide and thus it is useful for the largervalues of capacitors.

10.4.3.1 Polyimide Dielectric Layers

A major advantage of the use of polyimide layers is the ease andcheapness of fabrication of such films. The starting material may be apolyimide precursor resin which on curing undergoes a condensation

Tab

le 1

0.7

Res

isto

r M

ater

ial S

umm

ary

or CO 00

Mat

eria

l

Ti NiC

r

Ta2N

Cr

CrS

iO(C

erm

ent)

Au

/SiO

2co

mpo

site

Bul

k G

aAs

CrG

e

TCR

ppm

/°C

+2,5

00

<200

-10

0Ty

pica

lly

+3,0

00

-30

0 to

+10

0de

pend

ing

on

com

posi

tion

and

anne

alin

g

-50

0 to

+50

0de

pend

ing

on

Q/Q

+3,2

00

Clo

se to

0

Q/Q

10 90Ty

pica

lly

90Ty

pica

lly

1.5

50 to

500

0.1

to 1

000

30 fo

r10

17/c

c m

ater

ial

100

Man

ufac

turin

g T

echn

ique

Fila

men

t or

EB

eva

pora

tion

Spu

tterin

g fr

om ta

rget

in in

ert g

as

Rea

ctiv

e sp

utte

ring

Eva

pora

tion

Spu

tterin

g fr

om a

com

posi

te ta

rget

r.f.

sput

tere

d fr

om c

ompo

site

targ

et

Epi

taxi

al o

r io

n im

plan

ted

Eva

pora

tion

Rem

arks

Exc

elle

nt a

dhes

ion

to G

aAs.

Goo

dst

abili

ty a

fter

ann

ealin

g

Q/Q

dep

ende

nt o

n a

nnea

ling

sche

dule

. G

ood

sta

bilit

y af

ter

anne

alin

g

Goo

d a

dhes

ion

ont

o p

olyi

mid

e

Low

Q/Q

/.

not v

ery

suita

ble

for

GaA

sIC

s. G

ood

adh

esio

n to

GaA

s

Q/Q

var

iabl

e ov

er g

ood

rang

e.A

nnea

ling

sch

edul

e fo

r w

ante

d T

CR

Diff

icul

t to

rep

rodu

ce Q

/Q a

ccur

atel

y

Cur

rent

sat

urat

ion

a d

isad

vant

age.

Lim

ited

Q/Q

with

out s

elec

tive

impl

ants

Diff

icul

t to

rep

rodu

ce Q

/Q s

tabi

lity

ques

tiona

ble

I CD S


reaction to form an imidised, cross-linked structure. Alternatively analready imidised material can be used, where curing is used to removea carrier solvent and to promote limited cross-linking.

Several resins of both types have been evaluated for application to GaAsIC's. The most suitable is a condensation polymer which forms anamide-imide structure on curing. Curing temperatures are limited tobelow 350°C (to avoid prolonged exposure of the active devices to hightemperatures), and adequate polymerization occurs at these tempera-tures.

Polyimide films are applied to the wafer by spinning in the same way asphotoresist layers and confer good step coverage of underlying struc-tures. For this reason polyimide layers are also used as interlayerinsulation in multilevel devices, the conformal nature of the spun filmgives a quasi-planar surface suitable for further processing steps. Poly-imide films allow sputter deposition and ion milling of conductor andresistor films without detriment to other device structures. In additionthese interlayers provide good stress barriers between thin film mate-rials which are not normally compatible.

Fabrication of polyimide layers by spinning a fluid is a satisfactoryprocess for producing films of a few microns thickness. For films ofthickness much less than a micron, pinholing of the spun film becomesa problem, and in order to reduce the physical size of high valuecapacitors, another dielectric is required with the capability of forminghigh quality layers approximately 0.1/mi thick.

10.4.3.2 Silicon Nitride Layers

Silicon nitride is a suitable dielectric material for microwave use, havinga dielectric constant higher than that of polyimide, and capable of beingdeposited in the requisite thin films. Of the various methods of deposi-tion available, the one chosen is plasma enhanced chemical vapordeposition (PECVD). This allows high quality films to be produced atsubstrate temperatures below 350 °C.

The deposition is carried out in a parallel plate reactor in which silane,ammonia and nitrogen flow across the wafers in a vacuum chambermaintained at a pressure of about one Torr. The wafers rest on a heatedpallet which forms the earthed lower electrode of the parallel platesystem. An RF discharge at 13.56 MHz sustains the reaction anddeposition rates of about 10 nm.min"1 are achieved at power levels of50 mW cm"2.


Films are assessed by measurement of refractive index by ellipsometryand measurement of etch rate in buffered hydrofluoric acid (BHF). It ispossible to vary the refractive index from 1.85 to 2.15 by adjustment ofthe flow ratio of silane to ammonia, and this ratio is usually set to givefilms having a refractive index of 2.00. The BHF etch rate of the filmsdecreases with increasing refractive index as the films become progres-sively enriched in silicon, as is shown in Figure 10.50(a).

An essential advantage of the PECVD method of deposition is that wafertemperatures are low enough not to damage the active areas of thedevices. In order to see how far the deposition temperature could bereduced, films were deposited under otherwise identical conditions onsubstrates at temperatures between 150° C and 300° C. Figure 10.50(b)shows that the BHF etch rates of the low temperature films were inexcess often times greater than those of films deposited at 300°C, eventhough the films had similar refractive indices. It is considered thathigh etch rates indicate poor quality films. Capacitor dielectric layersare therefore routinely deposited at the higher temperature of 300°C.

Reproducibility and uniformity are very important parameters for rou-tine production of high tolerance dielectric films, and the process hasbeen established with this in mind. The area available for deposition issufficient for four 3 inch diameter wafers. Uniformity under normaldeposition conditions is better than 6% over the whole deposition area,

Figure 10.50 (a). Etch Rate in BHF as a Function of RefractiveIndex for Silicon Nitride (b). Etch Rate in BHF as a Function ofSilicon Nitride Deposition Temperature


and better than 4% over individual wafers. Reproducibility from run torun is excellent, measured refractive indices varying by ±2%, which iswithin the measurement error of the ellipsometer. Deposition rates areconsistent to within ±7%, and equipment modifications are expected toreduce this significantly in the near future.

Of all the factors affecting the deposition process, it has been found thatpower density is one of the most relevant to uniformity. For this reasondepositions for capacitor dielectrics are carried out at power densitiesbelow 20 mW cm"2, Less critical depositions (such as passivation layers)can be carried out at higher powers in order to reduce deposition times(Figure 10.51).

Auger analysis of films has been used to measure the silicon to nitrogenratio, although this Measurement is complicated by the different re-moval rates of silicon and nitrogen by the Auger spectrometer. ThePECVD films are compared to a silicon nitride standard of composition

4. The results are shown in Figure 10.52.

It is recognized that the films will contain significant quantities ofhydrogen derived from the gases used in the deposition process. The useof an electron microprobe analyzer in conjunction with Auger spectros-

20 40 60Power (watts)

80 100

28

26

24

22 I20 |18 g16 S

<D

14 s12 g10 I8 «642

Figure 10.51 Variation Deposition Rate and Uniformity as aFunction of Applied RF Power for PECVD Silicon Nitride


icon

Ato

mic

% s

i

50

48

46

44

42

/

1.90

/

2.00Refractive index

x Experimental

2.10

Figure 10.52 Relationship Between Silicon Content and RefractiveIndex ofPECVD Silicon Nitride Films

copy has enabled an estimate to be made as follows of the atomiccomposition of a typical film: silicon 45%, nitrogen 35%, hydrogen 20%.

Since this instrument requires much thicker films than are normallygrown, microprobe analysis is not considered suitable for routine analy-sis of film composition.

A summary of capacitor materials is given in Table 10.8.

10.4.4 Plasma Etching

Both polyimide and silicon nitride are plasma etched (-see for example,Tolliver, 1980) to define dielectric structures. Polyimide is etched inoxygen at about 500 milliTorr in a system with,fixed parallel plateelectrodes. At a power density of 3.5 W.cm~2 polyimide films are etchedat a rate of about 50 nm min"1 which is similar to the removal rate ofphotoresist. Thus thicknesses of polyimide up to several microns maybe satisfactorily masked with photoresist layers.

Silicon nitride films are plasma etched in a parallel plate reactor usingcarbon tetrafluoride-oxygen mixture at 200 milliTorr and a power den-sity of 0.5 W cm"2 at an etch rate of 50 nm min-1. Positive photoresistlayers are used as masks without problems caused by rapid removal ofphotoresist by the oxygen component of the etchant gas mixture. Thisis because 0.1mm silicon nitride films can be adequately masks byphotoresist films thicker than 0.5/tm. The effect of electrode separation


Table 10.8 Capacitor Material Summary

Material

SiO2

Ai3N4

AI2O3

Polyimide

VaractorDiode

RelativeDielectricConstant

4-5

5.5

6-10

3-4.5dependingon material

-

C/AP F 2mm

400

485

795

31

1000

Q

Good

Good

Good

GoodtoV.Good

Good

TCCppmAC

50

25

100-500

- 5 0 0

-

ManufacturingTechnique

Sputtering with aSiO2 target

Reactive plasmasputtering

Anodization ofevaporated film

Spun and cured film

Evaporated Schottky

has been found to be very important in optimizing etch rate ratiosbetween the mask and the material to be etched.

10.4.5 Ion Milling

Ion milling (see for example, Bollinger and Fink, 1980) is carried outusing an uncollimated argon ion beam, which operates at a currentdensity of about 0.5 mA cm"2. This power enables conductor andinductor metallizations to be ion milled at a rate exceeding 25 nm min"1.The chief advantages of this technique are the elimination of undercut-ting of the metal being patterned and the ability to achieve precisedimensional control features of a few microns wide. Control of conductorprofiles is achieved by careful adjustment of the baking cycle applied tothe photoresist layers used as ion-milling masks (Brambley and Vanner,1979 and Vanner et al, 1981).

The removal rate of gallium arsenide by an argon ion beam at thecurrent density quoted, is much higher than the removal rates of theconductors. In order to avoid unwanted etchings, of the substrate,circuits are designed so that the gallium arsenide substrate is alwaysprotected by a polyimide layer during ion-milling. Polyimide has beenfound to be an excellent material for this purpose with a low ion-millingrate. After ion-milling, photoresist residues are removed by a brief


oxygen plasma etch followed by a solvent clean. This has been found tocause no adverse effects to the polyimide surface.

Wet etching of tantalum nitride or chromium-silicon monoxide cermetsposes additional problems. Tantalum etchants often attack galliumarsenide, and most cermets do not etch satisfactorily in chromium orsilicon monoxide etchants (Glang and Gregor, 1979). The use of ionmilling for patterning resistors made of these materials avoids all of theproblems involved in developing satisfactory wet etchants, and confersmore precise dimensional control.

10.4.6 Inductors

Single turn loop inductors for inductance values up to 1 nH are easilyformed using gold films. The requirements for low frequency circuitsare for larger value inductors necessitating the use of a spiral structure.The entire inductor can be covered by a polyimide film and the centercontact to the spiral made through a via. Alternatively, an airbridgetechnique can be used as shown in Figure 10.53 where, in order to avoidthe use of a long airbridae which may be mechanically unsound, theconnection from center to outside is made underneath the spiral. At

Air bridges

GaAs

Air bridge

Figure 10.53 Example of Airbridge Technique Applied to Spiral


frequencies below a few gigahertz the skin depth of the gold metalliza-tion becomes such that simple lift-off techniques cannot be used to definethe 3 to 5/*m thick inductors. Thus, the inductors are either plated-upor are defined using ion beam milling.

10.4.7 Interconnections

A reliable and reproducible interconnection technology is one of the keyfactors in successful monolithic circuit fabrication. FETs use Schottkycontacts formed from metals such as Ti-Al, or Al which although provid-ing good performance usually require an interconnect scheme to gold forreliability. Because there is no physical bond the oxide film that formson the top of aluminum, for example, prevents an ohmic contact betweenthe aluminum and the interconnect metal. Titanium, if sintered, willleach out the oxide to form conducting titanium oxide. A further barriermetal such as nickel is used to separate the titanium from the gold whichwould otherwise form intermetallic compounds. Figure 10.54 showsexamples of interconnections where in Figure 10.54(a) connection ismade between Ti-Al gates and a Au second level metallization and inFigure 10.54(b) between Au first level and second level metallizations.

10.5 Integrated Circuit Examples

This part of the chapter gives examples of analogue and digital GaAscircuits which have been chosen to give the reader an appreciation not

(a) Al-Ti-Ni-Au Interconnect

(b) Au-Ni-Au Interconnect

V//////////ML:Au

Polyimide

Figure 10.54 Interconnect Schemes


only of performances and techniques being used but also the growth inthe GaAs industry during the last decade. The first of the following mainsections deals with analogue microwave integrated circuits with empha-sis placed on small-signal amplifiers, power amplifiers, voltage-control-led oscillators, phase-shifters, switches, mixers and completesubsystems such as an image rejection receiver and a phased-arraytransmit/receive module. The latter not only contains GaAs MMICs butalso discrete FETs in hybrid circuits. The digital section again gives anumber of examples of circuits showing in particular the rapid growthin the level of integration achieved over the last five years. Theseexamples include a high speed word generator using BFL, a 4 kBitSRAM using DCFL and high-speed gate-arrays. Comparisons are madebetween the performance of reasonably complex existing state-of-the-art circuits in GaAs and Si.

10.5.1 Small Signal Amplifiers

There is no doubt that the area to have received most attention fromMMIC designers is the small-signal amplifier. Following the first re-ported monolithic GaAs IC to employ MESFETs by Pengelly et al (1976)which was a single-stage design covering 8 to 12 GHz there has been alarge activity in both narrow-band and ultra-broadband designs. All thebroadband IC amplifier designs achieved early on used reactively-matched networks synthesized by treating the input and output equiva-lent circuits of the MESFET as series and parallel resistor/capacitornetworks as explained in Chapter 5. An example of such a circuit isshown in Figure 10.55. which is a microphotograph of a three-stage

Figure 10.55 Microphotograph of Three Stage X-Band MMIC


CD

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32

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A\ / /~\ \l 1\ A /

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11 7 8 9 10 11f/GHz

(b )

Figure 10.56 Performance ofMMIC Amplifier of Figure 10,55 (a).Gain and noise figure of single-ended amplifier (b). Input/outputreturn loss of single-ended chip amplifier

amplifier (Suckling, 1985) covering the 7 to 11 GHz band having theperformance shown in Figure 10.56. This amplifier employs 0.7 microngate-length MESFETs with transmission line matching networks. Bothpolyimide and silicon nitride capacitors are used for tuning, blocking andbypass capacitors respectively. The amplifier was designed to allowmaximum tolerance to component value changes caused by small vari-ations in the GaAs IC production process. The amplifier can be used ineither single-ended or balanced form but gives its best input and outputreflection coefficients when in balanced form. Two or three of these chipscan be cascaded to produce well over 70 dB gain. The build time,assembly complexity and adjustments needed in a conventional hybridapproach are dramatically reduced as can be appreciated from the'statistics' of monolithic based and hybrid based equivalents (Table10.9).

The reactively matched MMIC amplifier provides the lowest noise figurewhen compared to alternative design techniques such as feedback andtraveling-wave amplifiers. For example, Figure 10.57. shows a three-stage amplifier produced by Toshiba (Hori et al, 1983) for direct broad-cast satellite receiver applications. The gatelength of the FETs in thisthree-stage design were chosen at 0.4 micron to achieve a low-noisefigure whilst the gate-width of each FET was chosen to be 200 micronto keep the overall power consumption low and the die yield high. Figure


Table 10.9 Example of Comparison of Hybrid and MonolithicAmplifiers after Pengelly, Microwave Systems News, January 1983

Parameter

Frequency (GHz)

Noise Figure (dB)

Gain (dB)

No. of wire bonds

No. of FETs

No. of substrates

No. of carriers

No. of passive chips

Volume (mm3)

Hybrid

8-18

4.5

30 ± 2

400

16

16

8

72

2048 unpackaged

Monolithic

7.5-18.5

5.2

57 ± 1.5

14

16

2

1

8

926 packaged

10.58. shows the measured frequency response of noise figure and gainof the LNA operated at a drain-to-source voltage of 4 volts and a totalcurrent of 25 mA. A minimum noise figure of 3.4 dB and a gain of 20 dBwere obtained at 11.7 to 12.2 GHz in an overall chip size of 1.5 by 3.0mm.

Moghe et al (1984) have produced a very small MMIC amplifier for the4 GHz satellite communication band which has its input matching

Figure 10.57 Three Stage Low Noise MMIC Amplifier for DirectBroadcast from Satellite Reception (Courtesy-Toshiba)


6

CD

iin

il

yS* " ^ ^ G a i n

I°11 12 1

Frequency (GHz)

25

20

15m

cf

io5

5

n

Figure 10.58 Measured Performance of DBS MMIC Amplifier(Courtesy-Toshiba)

network 'off-chip' to allow both optimum tuning and higher Q networkson alumina to be employed. The chip, which measures 0.89 x 0.55 mm,produces approximately 20 dB gain with a 1.2 dB noise figure andemploys 0.5 micron gate length, 500 micron gate width MESFETsfabricated on Si ion implanted active layers.

At higher frequencies significant strides have been made in small signalMMIC amplifier design and fabrication. For example, Hughes haveproduced a 27.5 GHz amplifier having a gain of 11.5 dB with anassociated noise figure of 4.5 dB (Anzic et al, 1984) using a two-stagedesign occupying a chip area of 1.38 sq.mm. Noguchi et al (1984) havealso produced a single-stage amplifier chip at the same frequencyemploying 0.4 micron gate length FETs with a gain of 4 dB and an output1 dB gain compression point of greater than 20 dBm.

The traveling-wave amplifier has shown a resurgence in popularity inMMIC form with a number of companies producing designs coveringmultioctaves. Three examples of such distributed amplifiers will serveto display the advances that are being made in bandwidth, performanceand chip size. Ayasli et al (1984) of Raytheon produced both one andtwo-stage 2 to 20 GHz amplifier chips having gains of 6 and 12 dBrespectively. Figure 10.59. is a microphotograph of a two-stage chip. Thesingle-stage chip measures 2.2 by 2.7 mm whilst the two-stage chipmeasures 2.2 by 5.5 mm. Thus, the gain per unit area (a figure of merit)


Figure 10.59 Microphotograph of Two Stage MMIC 2 to 20 GHzTraveling Wave Amplifier (Courtesy-Rayethon)

7

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I 6

" ^ ^

1 1 i 1 1

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*

1 1

18(GHz)

1 1 j 1

22 26

Figure 10.60 Gain Performance of Distributed 2 to 0 GHz Amplifier(Courtesy-Hughes)


is 1 dB/sq.mm. This is considerably lower than some other designtechniques particularly associated with d.c. coupled amplifiers at lowerfrequencies. However, Kennan et al (1984) have produced an MMICtraveling-wave amplifier with a gain of 6 ± 0.5 dB over 2 to 18 GHz inalmost half the chip area occupied by the Raytheon device. Schellenberget al (1984) have also fabricated distributed amplifiers covering 2 to 30GHz with chip gains of 6 ± 0.3 dB within a chip area of 3.2 sq.mm. Theperformance of this amplifier is shown in Figure 10.60. Unlike the otheramplifiers described here, this device used seven sections with eachsection employing 68 micron wide, 0.5 micron long gate FETs. The noisefigure performance of these amplifiers is improving. First amplifiershad noise figures of around 8 dB employing 0.8 micron gate length FETswhilst latest devices have noise figures of around 4 to 5 dB by employing0.4 micron FETs.

Although the traveling-wave amplifier has become the most popularmethod for producing ultra-broadband gain with reasonably low inputand output VSWRs, the feedback amplifier principle has also beenemployed widely. Rigby et al (1983) produced a decade bandwidthamplifier covering 600 MHz to 6 GHz having 6 dB gain and 4 dB noisefigure. This work has been extended to produce two-stage amplifierssuch as the one shown in Figure 10.61. This particular amplifier has again of 12 dB over the 3 to 6 GHz band with a noise figure of 5 dB. Theseamplifiers use 1 micron gate length FETs having 600 micron widths.Input VSWR is less than 1.8:1 and output VSWR less than 1.3:1allowing, for example, four of the amplifiers to be cascaded directly to

Figure 10.61 Two Stage 3 to 6 GHz MMIC Feedback Amplifier(Courtesy-Plessey)


4 m

Figure 10.62 MMIC Two Stage 6 to 18 GHz Feedback Amplifier(Courtesy-Texas Instruments)

produce nearly 50 dB gain. Pavio et al (1984) have produced similartwo-stage amplifiers covering the 6 to 18 GHz frequency range. Thesechips employ 0.5 micron length, 300 micron wide gated FETs giving thebest compromise between FET transconductance, cut-off frequency andamplifier gain flatness, VSWRs and)noise figure. Figure 10.62. shows aphotograph of the amplifier which achieves 10 dB gain and a mean noisefigure of 5.5 dB. The amplifier's 1 dB gain compression point was around20 dBm. Such chips have been used in a high dynamic range limitingamplifier having 60 dB small-signal gain (Kriz, 1984).

10.5.2 Power Amplifiers

Since 1979 there has been given a considerable amount of emphasisgiven to the realization of medium power MMIC amplifiers. Theirpopularity has not been as great as small-signal amplifiers partly due


to the poor thermal conductivity of GaAs which requires either FETsspread out over large areas or very thin (50 to 100 micron) substrates.At frequencies above 6 GHz or so the common source inductance of theFETs has to be minimized to allow the intrinsic gain of the devices to berealized. This constrains the designer to the use of through GaAs visaexcept at the lower frequencies. A number of power amplifier designtechniques have been exploited. These are:

(1) Conventional reactively matched FETs;

(2) Feedback matched FETs;

(3) Travelling wave matching; and

(4) Push-pull matching.

10.5.2.1 Reactively-matched amplifiers

A number of laboratories have reported monolithic single-ended poweramplifiers using conventional reactive matching of the gates and drains

Figure 10.63 Four Stage Monolithic Power MESFET Amplifier(Courtesy-Texas Instruments)


of the FETs (Driver et al, 1981 and 1982). Tserng et al (1982) havedeveloped a number of monolithic power amplifiers including the deviceshown in Figure 10.63. This amplifier has four stages with FETs havinggate widths of 300, 600, 1200 and 2400 microns respectively. In theseamplifiers the active layers were formed by ion implantation and thetransmission lines are all plated with 3 microns of gold to reduce circuitlosses. Figure 10.64. shows the gain and output power of the chip overthe 6.4 to 8.4 GHz frequency range. The 1 dB bandwidth was 1.6 GHzwith an output power of 1.3 watts at a gain of 32 dB. The power addedefficiency was 30%.

Driver et al (1981) have reported similar results using lumped elementmatching with interdigitated tuning capacitors. Two stage amplifiershave been reported, contained on chips measuring 2 by 4.75 mm whichuse via hole technology for the FETs. This design has produced 28 ± 0.7dBm output power over 5.7 to 11 GHz with 6 ± 0.7 dB gain. The poweradded efficiency of the amplifier was 8 to 12% over the band.

A considerable amount of work has also been completed on broadbandpower amplifiers. For example, Palmer et al (1984) have produced a 6to 18 GHz amplifier having 500 mW output power with 10.6 dB gain

34

32

30 f,§28c

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22

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RFinput = -1dBm

VD=9.0VI D = 480mAVG« -2.0VEfficiency=-30°/«

I I I I I I I I

U

6.4 6.8 7.2 7.6Frequency (GHz)

8.0 8.4

Figure 10.64 Performance of Four Stage Monolithic GaAs FETAmplifier


Figure 10.65 Monolithic 6 to 18 GHz, 0.5 Watt Amplifier(Courtesy-Texas Instruments)

with a power added efficiency of 19%. Figure 10.65. is a photograph ofthe chip showing that a 900 micron FET drives two, 600 micron FETsin parallel. The 'split' 1200 micron device was chosen to decrease sourceinductance and to diffuse heat concentration in the device. Figure 10.66shows the power performance of this amplifier in both single-ended andbalanced form.

2010 12 14

Frequency, GHz16 18

Figure 10.66 Power Performance of Single-Ended and BalancedMMIC Amplifiers


Figure 10.67 Microphotograph of Three Stage X-Band Power


son 100n

(450pm) o,?fiFETCA (300pm)

Figure 10.68 Optimized Circuit Topology ofMMIC Power Amplifier

High power levels require devices with large gate peripheries. The sizeof the FET cannot be increased indefinitely because of crosstalk, phasingand instability problems. In an effort to minimize the above effects,designers have developed divider/combiner circuits (Schellenberg,1982). Other designs (Degenford, 1982) use the 'cluster cell matching'approach where input matching is achieved at the level of individual'cell clusters' which are then partially matched at their outputs prior tocombining via quarter wavelength lines. Pavlidis et al (1983) have useda 'cluster' technique for an X-Band amplifier operating over 8 to 9 GHz.This chip is shown in Figure 10.67 and consists of three-stages of gainwith single, double, and quadruple versions of the same FET (Figure10.68) in the three stages. The amplifier achieved 15 dB gain.

Dormail et al (1983) have used reactive matching circuits for FETshaving gates of up to 4.4 mm width. However, they have departed fromthe usual type of transmission line matching by using slow-wave struc-tures. Most MMIC chip area is consumed by passive matching circuitelements. Chip area is becoming a major cost-driving factor. Slow-wavestructures or capacitively-loaded transmission lines can have effectivewavelengths one quarter that of microstrip lines at impedance levels of15 ohms or so. Thus, the 2 watt amplifier shown in Figure 10.69 occupiesan area of 7.6 sq.mm. but has a gain of 12 dB over 2 to 8 GHz with apower added efficiency of 20%.


Figure 10.69 MMIC 2 Watt Power Amplifier Employing Slow-WaveMatching Circuits (Courtesy-Raytheon)

10.5.2.2 Feedback Amplifiers

Pengelly et al (1984) have investigated the use of feedback techniquesto produce large percentage bandwidth monolithic power FET amplifi-ers in the 2 to 4 GHz region. At these frequencies conventional broad-band matching circuits would require rather large value inductors whichconsume large areas of GaAs as well as having low Q. In order to reducethe number and magnitude of matching components the high transcon-ductance of the power FET can be exploited by employing feedback. Thistechnique also reduces the sensitivity of the resultant amplifier to


Wire bond

50p 738 1.57n

2.52 n I Wire bond

O.82n"162

Figure 10.70 (a). Circuit Diagram of Monolithic S-Band Power FETAmplifier (b). Microphotograph ofMMIC Feedback Power Amplifier(Courtesy-Plessy)


variations in transistor parameters and improves the intermodulationperformance of the circuit. Figure 10.70 (a) shows the equivalent circuitof a single-stage chip having 10 dB power gain and a 800 mW outputpower at the 1 dB gain compression point over the 2.5 to 3.5 GHzfrequency range. Figure 10.70(b) shows a photograph of the amplifierwhere the FET has a gate width of 2.4 mm, thus enabling high transcon-ductance per stage. The input and output VSWRs are less than 2:1. Thechip uses silicon nitride capacitors for r.f. bypass, d.c. blocking andmatching together with CrSiO cermet resistors. Chip size is 2.3 by 4.5mm.

10.5.2.3 Traveling Wave Amplifiers

For a GaAs FET distributed amplifier it has been shown, in Chapter 5,that the gate attenuation coefficient is proportional to the gate resis-tance and the square of the frequency of operation. It is this attenuationthat limits the number of FETs that can be used in each stage. To reducethe gate-line attenuation a series capacitor can be inserted between theFET gate and the transmission line as shown in Figure 10.71. Thecapacitor reduces the effective value of CGS, resulting in a decreased gateattenuation coefficient since the latter is also proportional to the squareof CGS. The capacitor reduces the gain per device but the overallamplifier gain can be kept constant by employing more FETs per section.Moreover, the capacitor and CGS form a voltage divider allowing for anincreased signal level along the gate line. The latter results in asubstantial improvement in output power and efficiency for a distrib-

Figure 10.71 Schematic Diagram of Capacitively Coupled TravelingWave Amplifier


Figure 10.72 Microphotograph of Power Traveling Wave Amplifier(Courtesy-Plessy)

uted amplifier. Kim et al (1985) and Ayasli et al (1984) have producedMMIC amplifiers using this design technique producing 0.5 watts with4 dB gain over 2 to 21 GHz and 1 watt with 5 dB gain over 2 to 8 GHz.To provide a constant r.f. voltage across all the FET gates the values ofthe series capacitor are increased as one moves along the gate line.

Shukla et al (1985) have also produced a 10 dB gain power amplifierwithout capacitive coupling on the gate-line having over 6 GHz band-width and greater than 0.5 watt output power. The MMIC chip is shownin Figure 10.72 where the FETs are each 750/jm wide with l.Qtim gatelengths.


Stage 1I . O.8n

Interstagen . A c h i n gO.8n 3

3Q.9n

HI-

OUt15i.0n

0.8 n600pmwide FET

.Virtualground

0.3n1200 urnwide FET

Figure 10.73 Schematic Diagram of Two Stage X-Band Push-PullAmplifier

10.5.2.4 Push-Pull Amplifiers

Texas Instruments have fabricated two-stage push-pull amplifiers atX-Band together with differential or 'paraphase' amplifiers to drive thepush-pull configuration (Sokolov et al, 1980). A schematic diagram ofthe two-stage, four transistor, push-pull circuit is shown in Figure 10.73.Figure 10.74 shows a chip photograph of the GaAs IC. The seriesinductors and capacitors are integrated 'on-chip' whilst the shunt induc-tors are realized with 25 micron diameter bond-wires allowing thecenter frequency of the amplifier to be adjusted. The output stageconsists of a pair of 1.2 mm gatewidth FETs with the input stage usinga pair of 600 micron FETs. Each of the multi-cell FETs uses a plated'airbridge' for source interconnections.

Grounding is achieved in this design by using top ground planes whichare connected to the test fixture using wire-mesh.

Two advantages of the push-pull configuration are used in the design.Firstly, the push-pull arrangement is essentially a series connectioncorresponding to a total gate width at the output of 2.4 mm. This meansthat the impedance matching problem is halved over the simpler single-ended approach. Secondly, current at the fundamental frequency flowsbetween the source of each transistor and the source of its push-pullcounterpart. Coplanar grounding metallization connects all sources, sothat these r.f. currents are confined primarily to the chip's surface. Ifeach transistor pair is closely matched, then only a small fraction of thetotal r.f. source current needs to flow to true ground. Thus, connection


Figure 10.74 Two Stage Push-Pull Amplifier (Courtesy-TexasInstruments)

of the chip's ground metallization is not as crucial as in the case of asingle ended amplifier.

Since the amplifier operates in the push-pull mode, a virtual groundexists symmetrically between the two halves of the circuit (see Figure10.73). The design of the amplifier consists merely of a single-endedapproach with shunt inductors doubled in value for the push-pullimplementation.

The push-pull amplifier requires antiphase input signals with theoutput signals being combined in a 180 degree differential adder. Athree transistor MMIC X-Band differential or 'paraphase' amplifier wasdeveloped by Texas Instruments to enable the input antiphase signalsto be generated without the need for a conventional passive (and,therefore, large) 'rat-race' power divider. The paraphase amplifier is a


Balanced output

Unbalancedinput Differential pair:

two 600u.m FET's

Current source-.900/jm FET

Figure 10.75 Schematic Diagram ofX-Band Paraphase Amplifier

solid-state equivalent of circuits produced at lower frequencies usingvalves (Seely, 1958). Figure 10.75. shows a schematic of the paraphasecircuit. Two 600 micron gatewidth devices are used for the differentialpair. The unbalanced input is applied to one of the gates whilst the otheris r.f. short circuited. The balanced output is taken via matching circuits.The transistor that functions as the current source is realized by a FEThaving a total gatewidth of 900 microns. The gate of this transistor isr.f. short-circuited to ground and a shunt inductor is used at the drainto resonate the drain-to-source capacitance.

Figure 10.76 shows the realization of this amplifier. The dark bars areplated airbridge source interconnects. The push-pull amplifiers haveachieved over 1 watt output power with 10 dB gain at 9 GHz. Asmall-signal gain of 14 dB was achieved at 9.2 GHz and power addedefficiencies of 18% were measured. The paraphase amplifier had a gainof 2 to 3 dB over a lGHz bandwidth centered at 8.3 GHz with a phasedifference at its outputs of between 140 and 180 degrees. Second passdesigns and optimized fabrication techniques have improved this per-formance.

10.5.3 Oscillators

Both fixed and varactor tuned oscillators have been implemented mono-lithically. The first monolithic oscillator was reported by Joshi et al


Figure 10.76 Microphotograph ofX-Band Paraphase Amplifier(Courtesy-Texas Instruments)

(1979) which used a FET in common gate configuration. The oscillatorcircuit is shown in Figure 10.77(a) whilst Figure 10.77(b) shows themonolithic implementation of the oscillator circuit. The gate feedbackinductance is realized using a single loop inductor and the capacitivesource termination using an interdigital capacitor. A spiral inductor isconnected to the source of the FET to act both as an r.f. choke and as ad.c. return for the source. The chip measures 1.8 by 1.2 mm. Outputpower was approximately 8 mW with 4% efficiency at an output fre-quency of 13 GHz.


Figure 10.77 (a). Common Gate Circuit Configuration used for FirstMonolithic Oscillator (b). Microphotograph of Monolithic FixedTuned Oscillator (Courtesy-Plessy)

More recently, there has been considerable interest in using dielectri-cally stabilized MMIC sources as the local oscillators in DBS receivers.Hori et al (1983), for example, have designed a common source oscillator.For DBS reception a frequency stability of ±1 MHz is required over atemperature range of -40 to +80 degrees C. Hybrid MIC technology was


Dielectricresonatoro I G , D

>5on

1 R5 = 50ohmC [ Cs=0.3pF

Out Cp

MMIC chip

jTiTTjTTTl0 1 cm

Figure 10.78 (a). Circuit Diagram of Dielectrically ResonatedMMIC oscillator (b). Photograph of Dielectric Resonator OscillatorChip (1.5 X 1.5 mm) Mounted in Test Enclosure (Courtesy-Toshiba)


12

-40 -20 0 20 40 60 80Temperature Ta (°C)

Figure 10.79 Measured Characteristics ofMMIC Oscillator ofFigure 10.78 (a). Output power (Pout), oscillation frequency deviation(Afosc), and efficiency (rj) of a dielectric resonator oscillator as afunction of drain voltage (VDD) (b). Temperature dependence of theoscillation frequency deviation (Afosc) and output power (Pout) of adielectric resonator oscillator


temperature range of -40 to +80 degrees C. Hybrid MIC technology wasused to form the resonant circuit for this frequency stabilization. Thedielectric resonator is mounted on an alumina substrate and coupled toa microstripline terminated in 50 ohms. The dielectric resonator usedhad an unloaded Q of 7400, a relative dielectric constant of 36.3 and aresonant-frequency temperature coefficient of+6 ppm/degree C. Figure10.78(a) shows the circuit diagram of the oscillator where the 0.3 pFsource capacitor makes the output reflection coefficient at the drainterminal of the FET maximum under a given reflection coefficient of theresonant circuit with a loaded Q of 1000. The output matching circuitwas optimized by a non-linear analysis based on large-signal imped-ances of the FET. Figure 10.78(b) is a photograph of the MMIC mountedwith the dielectric resonator in a test jig. Figure 10.79(a) shows themeasured drain voltage dependence of output power, oscillation fre-quency deviation and efficiency of the oscillator with a nominal oscilla-tion frequency of 10.67 GHz. An output power of 10 dBm with 10%efficiency was obtained. Frequency pushing was approximately 0.2MHz/volt and the frequency pulling with a 1.5:1 VSWR was 400 KHz.Figure 10.79(b) shows the temperature dependence of frequency devia-tion and the output power. It was found that the frequency variationwas 1.2 ppm/degree C with a power variation of 4 dB over the -40 to+80 degree C range.

Tserng and Macksey (1981) produced MMIC oscillators with 'off-chip'varactor tuning diodes. With a common gate design a power output of20 mW was achieved at 10.8 GHz with a narrow tuning range and anefficiency of 8%. A common drain version gave a tuning range of 4 GHz(16 to 20 GHz) with an average output power of 10 mW. More recently,Scott et al (1984) have produced a family of monolithic oscillatorscovering 2 to 18 GHz where the varactor diodes are integrated (seeChapter 7). The oscillators all employed the common gate configurationwith gate inductors for the regenerative feedback elements. The induc-tor exhibits tunable negative impedances that are available at thesource terminal when the drain is terminated in a specific resistive load.A capacitance placed in the source terminal cancels the phase of thisavailable negative impedance allowing the circuit to oscillate. By em-ploying a varactor, the frequency of oscillation can be tuned across theavailable negative impedances. The addition of another varactor inseries with the gate inductor allows the frequencies at which thenegative impedances appear to be moved up-band as the gate varactorcapacitance is decreased. The varactor diodes were planar lateral de-vices having 2 micron anode fingers. Figure 10.80(a) shows a 4 to 7 GHzoscillator employing a 1200 micron gate width MESFET contained


7.0

6.5

6.0

£5.5o&5.0

4.0

3.5

3.0-10 -8 -6 - 4 - 2 0 2 4

Tuning voltage (volts)

Figure 10.80 (a). Microphotograph of 4 to 7 GHz MMIC VoltageControlled Oscillator (Courtesy-Texas Instruments) (b). Frequencyand Output Power as a Function ofVaractor Tuning Voltage forCircuit of Figure 10.80(a).


within a chip 3 by 2.8 mm. Figure 10.80(b) is a graph of the oscillationfrequency and output power of this circuit as a function of the tuningvoltages. Varactor capacitance ratios were typically 8:1 or greater.

10.5.4 Phase Shifters

Since the first edition of this book was published in 1982 there has beena large amount of work completed on both analogue and digital phaseshifters particularly in the USA and Europe. This work has beenstimulated by the employment of such circuits in phased array trans-mit/receive modules.

There are two basic types of phase shifter that have been employed inMMIC designs. They are the digital phase shifter using either FETs(Ayasli, 1982) or diodes (Dawson, 1984) as the switching elements andthe analogue vector modulator which usually employs FETs (Suckling,1983).

10.5.4.1 Digital Phase Shifters

MMIC digital phase shifters commonly use MESFETs as the switchingelements. The basic switch element is a single-pole, double-throw circuitwith the FET either in shunt across or in series with a transmission line.The FET switch is a three terminal device with the gate voltage control-ling the switch states. If the negative gate bias is larger than thepinch-off voltage then the switch is in its high impedance state whilstthe device will be in its low impedance state when the applied gatevoltage is zero. In either state virtually no d.c. power is required. The

-oD

5

a High resistance state b Low resistance state

Figure 10.81 Equivalent Circuits used for a Switching FET


switch is bidirectional. The equivalent circuits for the two switch statescan be represented as shown in Figure 10.81. Gate-drain and gate-source capacitances are equal because both source and drain terminalsare at ground potential. As a consequence the drain terminal is notisolated from the gate terminal and the gate circuit has to be configuredas an RF open circuit to the FET at the gate terminal. This can be doneby either connecting the control signal to the gate by a high value resistor(particularly if switch speed is not unduly fast) or by the use of a low-passfilter. The equivalent drain-source capacitance of the switch is, there-fore, CDS + CG /2 (Figure 10.81). For a typical 600 micron gate width FETCDS is approximately 0.15 pF whilst CGS is approximately 0.5 pF. Thus,the total switch capacitance is approximately 0.4 pF. This represents areactance of 50 ohms at 8 GHz. In order to realize the switching action,this capacitance must either be resonated or included in the design ofthe impedance-matching sections.

Two examples of such design techniques are the switches of Mclevige(1980) and Tajima (1984).

The phase sections that are going to be switched by the single-poledouble-throw switches can take a number of forms depending on theapplication and frequency of operation. Lumped element high/low passnetworks have been employed by Suckling (1982) to produce constantphase shift with frequency at S-Band, whilst Bambridge (1984) has usedmicrostrip lines to produce constant delay with frequency at the samefrequency. In contrast, Ayasli (1982) used loaded transmission lines toproduce constant phase shifts at X-Band frequencies.

Figure 10.82 Schematic Diagram of 4 bit Phase Shifter (after Ayasli)

5 3 PL B O §3 i

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Figure 10.84 Single-Chip 4 Bit Phase Shifter (Courtesy-Raytheon)

A schematic circuit diagram of an X-Band four-bit phase shifter is shownin Figure 10.82. The 22.5 and 45 degree bits are designed to give constantphase shifts over the band using the loaded line technique whilst the 90and 180 degree bits are designed using the switched line technique. Theloaded-line sections are composed of three-section transforming andmatching networks terminated by 1200 micron FET switches. Switch-ing between the lines of different electrical length is performed by twosingle-pole double-throw switches. In order to equalize insertion loss inall phase states the impedance of the various phase paths are adjusted.The individual phase shift ICs were reported by Ayasli (1982). Theperformance of those circuits is shown in Figure 10.83 The insertionloss data includes approximately 0.5 dB test jig loss. The phase error at10 GHz is less than 10 degrees for any bit.


O r

-6

g-9

-12

Four bit passive phase shifter

8.5

22.5

9.0 9.5 10.0Frequency (GHz)

b

10.5

Figure 10.85 Performance of Single-Chip MMIC 4 Bit Phase Shifter(a). Insertion loss for all 16 states of a four-bit passive phase shifter(no correction for jig losses has been made) (b). Phase shift versusfrequency for all 15 non-zero states of a four-bit passive phase shifter

A single-chip four-bit phase shifter produced by cascading the fourseparate circuits is shown in Figure 10.84. Chip size was 6.4 X 7.9 X 0.1mm. Figure 10.85(a) shows the insertion loss of the chip (includingapproximately 1. dB test jig losses)for all 16 phase states. Insertion loss


in the 9.5 GHz radar band was 5.1 ± 0.6 dB. Figure 10.85(b) shows thedifferential phase shift over the 9.5 to 10.5 GHz frequency range.Deviation of phase around an arbitrarily defined zero is less than ± 10degrees over a 3 GHz bandwidth.

In contrast to the X-Band phase shifter above, Bambridge et al (1984)have designed a four-bit switched line phase shifter for phased arrayradar applications at S-Band. This circuit consists of two ICs mountedin cascade. The ICs contain the matrix of FET switches used to switchfrom one length of microstrip to another. These microstrips are con-tained on the alumina substrate used to carry the ICs and providecontrol lines-this produces small ICs since no GaAs is taken up by therather long lengths of microstriplines requires in the 2.5 to 3.5 GHzband. A microphotograph of the switching chip is shown in Figure 10.86whilst Figure 10.87 shows the insertion loss and phase performance ofthe complete circuit over all 16 phase states. The worst case phase erroris 4 degrees representing less than lA LSB error (LSB-least significantbit).

10.5.4.2 Analog Phase Shifters

Unlike digital phase shifters that redirect a single signal through anumber of alternative paths (of either different transmission or reflec-tion phase or delay) an analogue phase shifter takes a single signal,divides that signal into two equal amplitude vectors, shifts the vectorsby a fixed phase with respect to each other, attenuates both vectors bypredetermined amounts and then recombines the vectors into a singleresultant. A schematic diagram of the circuit is shown in Figure10.88(a). The vector diagram for such a vector modulator is shown inFigure 10.88(b) where two vectors ± 45 degrees apart are generated andthen recombined after being attenuated relative to each other. Thistechnique will allow any phase within the resolution of the circuit to beproduced with a range of amplitudes over the 90 degree range. Theremaining three quadrants are covered by switching in 90 and 180degree digital phase shifters. An alternative approach is to producethree vectors each separated by 120 degrees (Figure 10.89). By fullyattenuating any one vector whilst controlling the relative amplitudes ofthe other two it is possible to cover the full 360 degrees without the needfor digital phase shifters.

Suckling et al (1983) have produced a complete MMIC based S-Bandvector modulator employing the first technique. A microphotograph of


Figure 10.86 MMIC S-Band Phase Shifter Switch IC(Courtesy-Plessy)

400

360

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3 240

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80

2.7 2.8 2.9 3.0 3.1 3.2 3.3Frequency (GHz)

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Frequency (GHz)

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Figure 10.87 Performance of 4 Bit MMIC S-Band Phase Shifter(a). Measured phase shift for all 16 phase states as a function offrequency (b). Insertion loss range for all 16 phase states as afunction of frequency (c). Range ofVSWRs as a function frequency forall 16 phase states


Input

+45°

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JLAttenuators

nIn-phaseactive or Ipassive U-powerdivider

-45°

Output

Combiner

Phaseshifters i Control

90°

/

/I/ ] Resultant' vector

/ IIIII - • 0 °

Figure 10.88 (a). Schematic Diagram ofO to 90 Degree VectorModulator (b). Vector Diagram for 90 Degree Vector Modulator

the complete modulator is shown in Figure 10.90(a) together with atypical phase response in Figure 10.90(b).

The vector modulator has insertion loss due to the need to fully attenu-ate one of the vectors under certain phase settings. This can be overcomeby the use of an active signal splitter prior to the phase differencenetworks which has overall gain. Such an MMIC spitter is shown inFigure 10.91. This circuit, which employs a common gate input stageand two common source output stages, has overall gain per channel of6dB.


It is possible to combine the amplifying and attenuating functions of thevector moduator by employing dual-gate FETs as in the circuit shownin Figure 10.92. Vorhaus et al (1982) produced an MMIC analogue phaseshifter by combining two dual-gate FET amplifiers, where the gain couldbe changed by applying second gate-source bias, with a Wilkinsoncombiner and extra transmission phase length in one arm of the circuit.By varying the length of this extra line length from one chip design tothe next a small family of chips was produced allowing the implemen-tation of a digital 4-bit phase shifter using analogue techniques.

10.5.5 Switches

As has been introduced in Chapter 9 and in the previous section ondigital phase shifters the MESFET can be used as an effective switchingelement. Since the FET operates as a voltage-controlled resistor with-out normal drain to source bias the device requires no drive current onthe control gate unlike a PIN diode. A number of MMICs have beendesigned using FETs as switches in both simple and more complicatedarrangements. Figure 10.93 shows a simple series FET SPDT switchproduced by Plessey which is a commercially available product. Theperformance of this device up to 2 GHz is shown in Figure 10.94. In thiscase the isolation of the switch is limited by the self capacitance of the

Phaseshifters

Input45°

+45°

Phaseshifters

-45°

Quadraturepower divider

-60°

-195°

+60°-75C

3'1 powercombiner

Output

Attenuators

Figure 10.89 360° Vector Modulator using 120° Vector Control


90 80

0.6 0.7 0.8 0.9 1.0Magnitude—**-

Figure 10.90 (a). Microphotograph ofS-Band MMIC VectorModulator (Cqurtesy-Plessy) (b). Performance of Vector Modulator


Figure 10.91 S-Band MMIC Active Splitter (Courtesy-Plessy)


FETs. Very broadband MMIC switches (both SPST and SPDT) havebeen designed by Tajima (1984). In that work, the broadband charac-teristic of the switches is accomplished using both series and shunt FETsbut without using series or shunt tuning elements. The effective source-drain capacitance of the shunt FETs is incorporated into a capacitivelyloaded transmission line (Figure 10.95). The addition of a series FET toeach branch of the SPDT switch improves the low frequency isolationwhen it is biased to its high resistance state whilst the shunt FETsbiased to their low resistance state present an open circuit at higherfrequencies when transformed by the quarter wavelength lines. Thedegradation of isolation that would occur from the series switchingelements alone is counteracted by the effect of shunt switching elementswithout the need for series tuning elements. The characteristic imped-ances and lengths of the microstrip lines connecting the switch elementsare optimized to include the effective source-drain capacitance of theshunt FETs biased at their high resistance state while maintaining aminimum insertion loss condition between the 50 ohm input and outputports over a large frequency bandwidth. Figure 10.96 shows the meas-ured performance of a d.c. to 20 GHz switch produced by Tajima et al.Chip size is 1.8 X 2.5 mm.

The dual-gate FET can also be used as a high-isolation switch using acircuit such as that shown in Figure 10.97. Unlike the previous examplesthe dual-gate FET is operated in the normal manner with drain to sourcevoltage. The disadvantages of the dual-gate FET approach are:

(1) The switch is non-reciprocal;

(2) The switch takes d.c. power in its 'ON'-state; and

Control 1

Combiner O/P

Control 2

Y777L Transmission line

CZD Resistor

Figure 10.92 Phase Shifter Employing Dual-Gate MESFETs


Figure 10.93 SPDT Switch IC Chip (Courtesy-Plessy)


Figure 10.94 Performance of MMIC SPDT Switch

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300pm FETs

500pmFETs

500pm 25pmFETs FETs

Figure 10.95 Circuit Diagram ofd.c. to 20 GHz MESFET Switch

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Figure 10.96 Measured Performance ofd.c. to 20 GHz MMIC Switch


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Figure 10.97 Dual-Gate GaAs FET Switch

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Figure 10.98 Magnitude of S-Parameters with Dual Gate FETBiased'on'and'off


(3) The device requires considerably more complicated matchingcircuits to operate over the same bandwidths as single-gateswitches.

However, the advantage of such a choice is that gain is available.Vorhaus (1981) has reported a multithrow dual-gate FET switch havingisolations in excess of 25 dB at X-Band using a novel four-sided structurewith a common source connection to ground. The ground was suppliedby introducing a via through the GaAs substrate. Figures 10.98(a), (b)and (c) illustrate the inherent bandwidth of the dual-gate FET as aswitch as well as the on-off ratio attainable with second-gate voltage(Tsai et al, 1979).

10.5.6 Mixers

Considerable work has been achieved on monolithic mixers employingboth MESFETs and diodes. Although the noise performance of thesemixers is not particularly noteworthy the advantage of being able toproduce a planar circuit capable of integration with other circuit func-tions has been an attractive driving force.

A large percentage of MMIC mixer research has been associated withthe DBS (direct broadcast by satellite) receivers being designed eitheras single or multi-chip subsystems. The most notable achievements inthis area have been by Kermarrec et al (1984) and Bastida et al (1984).Both teams of workers at LEP, France and CISE/Italtel have reportedsingle-chip 12 GHz receivers employing dual-gate FETs as mixers.

The dual-gate MESFET provides an attractive solution to mixer inte-gration since no coupler is needed to combine the RF and LO signals.Kermarrec et al have reported a mixer conversion gain of 2 dB with anoise figure of less than 10 dB. The mixer was combined with a localoscillator on one chip measuring 3 x 1 sq.mm.

Bastida et al have reported a similar circuit having 0 dB conversion gainwhen loaded into the input impedance of the following IF amplifier. Thedimension of their chip was 2.5 X 1.9 sq.mm. and the IF was approxi-mately 1 GHz.

Honjo et al (1984) have also reported on a mixer/IF amplifier combina-tion again for DBS applications. In their approach the mixer wasconnected directly to the IF amplifier without employing IF matchingcircuits. To predict the conversion gain of the mixer with the amplifier,the simplified circuit model of Figure 10.99 can be considered. In this


RF matchingnetwork

LO frequency_n_n_Ideal switch

Figure 10.99 An Approximate Operation Model for a Dual-GateFET Mixer with Buffer Amplifier

mixer the RF signal is applied to the first gate and the LO to the secondgate. Assuming that the FET drain current lDexp(j<yRFt) is switchedperfectly at 50% duty cycle by the LO signal the Fourier component at

becomes:

7i(exp{wRF-a)L0)t)

where CORF and CWLO are angular frequencies for RF and LO respectively.In the case of a single gate FET mixer, the maximum value of conversiontransconductance is approximately gm(max)/r. In Figure 10.99, assum-ing a lossless RF matching network, conversion power gain GC(G)RF) iscalculated as approximately:-

Thus for example, if gmi = gm2 = 25 mS; RLI = RLI = 100 ohms; Ro = 50ohms; CGSI = CGS2 = 0.25 pF; and CORF = 12 GHz and CWLO =11 GHz, thenthe total conversion gain is approximately 6 dB. By loading the IFamplifier FET drain with a 100 ohm resistor the output VSWR of theamplifier is low without any complicated matching networks. Figure10.100 shows the measured conversion gain and SSB noise figure forthe mixer with the buffer amplifier. The LO frequency was 10.8 GHzand the power level was 8 dBm. The mixer, in practice, had a conversion


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Figure 10.100 Measured and Calculated performance of Dual-GateFET Mixer with Buffer Amplifier

gain of around 5 dB with an SSB noise figure of less than 13 dB. Figure10.100 also shows the calculated gain which is in good agreement withthe measured results.

Schottky barrier diodes have also been integrated successfully into anumber of MMIC mixers. One of the most notable is that reported byJacomb-Hood et al (1983). In this circuit two back-to-back diodes werefed with anti-phase RF and LO signals. These signals were derived bypassing them through an integrated Lange quadrature coupler and a 90degrees phase shifting network. The anti-phase signals produce goodLO to RF port isolation. A diagram of the circuit is shown in Figure10.101. Active areas for the Schottky diodes were produced by selective

Quadraturecoupler

Signal o y r-\ i—| [—

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oscillator ' '

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^ output

1 1 Matching1 1 networks

Figure 10.101 Schematic Diagram of MMIC X-Band DiodeBalanced Mixer


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Figure 10*102 Conversion Loss Versus Frequency as a Function ofLO Power for MMIC Diode Mixer MMIC

ion implantation producing deep n+ areas. Low resistance ohmic con-tacts were fabricated by etching back to this highly doped region beforedepositing metal and alloying. The ground return for the diodes issupplied by a via through the substrate. Conversion loss versus fre-quency as a function of LO power is shown in Figure 10.102, whilstFigure 10.103 shows conversion loss as a function of IF for threedifferent LO frequencies. Noise figure at 10 GHz was approximately 6dB with isolation between the LO and RF ports being 13 dB.

At much higher frequencies the planar Schottky diode has been ex-ploited as a mixing element successfully by a number of workers overthe last few years. Perhaps the most notable work in the millimeter-wave range has been achieved by researchers at MIT (Chu et al 1981,Chu et al 1983) and Honeywell (Chao et al 1980, Bauhahn et al 1984).

J 0 r

9GHz10GHz

11GHz

100 200 300 400Frequency (MHz)

500

Figure 10.103 Conversion Loss as a Function of IF for Three


IF% groundLO inputIF, output

Schottkydiode

ground

Figure 10.104 Schematic Diagram ofMMIC Balanced 94 GHzMixer

Bauhahn et al (1984) have described a 94 GHz planar GaAs monolithicbalanced mixer. The configuration of the mixer is illustrated in Figure10.104. It consisted of a rate-race hybrid, two monolithically integrateddiodes, matching circuits and beam lead RF interconnects. The IF filter,which is off-chip, is connected to the local oscillator input line. The mixerwas relatively insensitive to local oscillator noise since the Schottkydiodes are in anti-phase with respect to this input. On the right and leftof the rat-race hybrid are filters at the sum of the local oscillator andsignal frequencies. The filters consisted of two shunt stubs, a short highimpedance transmission line and the diode capacitance. Ground for thelocal oscillator and signal frequencies was provided by an open-circuitedquarter wave stub.

The mixer diodes were processed on VPE n on n+ layers. The n+ layerhad a doping concentration of 2 X 1018 cm"3 with a thickness of 3 micronswhilst the n-layer had a doping level of 5 X 1016 cm"3 and was about 0.1microns thick. The Schottky contact was connected to the rest of thecircuit by means of an airbridge to minimize stray capacitance. Beamleads at the edge of the chip were also an integral part of the completeprocess.

The measured noise figure for the mixer is shown in Figure 10.105. Ascan be seen the results indicate that such planar diode mixers showpromise for use at such frequencies.


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Figure 10.105 Measured Noise Figure of 94 GHz MMIC Mixer

Chu et al (1985) have described their work on a monolithic dual functionmixer circuit for millimeter-wave transceiver applications. In contrastto the conventional hybrid approach the implementation of such a circuitusing circulators is not possible in a monolithic environment. Thedual-function MMIC avoids the need for double-pole double-throwswitches. The circuit, which is capable of performing either as a receiveror as a transmitter switch, operates by applying either forward orreverse bias to a pair of mixer diodes. The circuit shown in Figure 10.106

4

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Transmit

Receive

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W Antenna

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Figure 10.106 Balanced Mixer / Transceiver using Double-PoleDouble-Throw Switches (after MIT)


integrates a microstrip branch-line coupler, a radial-line stub filter,Schottky barrier diodes and tantalum pentoxide capacitors. The dimen-sions of the chips were 2 x 2 mm. The frequency of operation was 33 to36 GHz. Control is achieved by either forward or reverse bias to thediodes. If the diodes are forward biased, resistive loads are presentedto the output arms, and both signal and LO power are coupled to thediodes. The circuit operates as a balanced mixer in much the same wayas that reported previously by Chu et al (1983). When the diodes arereverse biased resistive loads are presented to the output arms of thebranch-line coupler. Since the resistive loads are identical, the reflectedwaves at the output arms of the coupler add destructively at the LO portand constructively at the antenna port. As a result the circuit functions

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o Bias 1V LO power 5mWa Bias 0V LO power 18mW

1.0 1.5 2.0IF frequency (GHz)

Figure 10.107 (a). Conversion Loss of Mixer as a Function of IFFrequency (b). Noise Figure of Mixer as a Function of IF Frequency


Return loss

Input power 150 mW

34 35Frequency, GHz

36

Figure 10.108 Insertion Loss and Return Loss of Dual FunctionMixer in Transmission Mode

as a transmitter switch, directing signal incident on the LO port to theantenna port.

When the circuit is operated as a receiver the conversion loss is asillustrated in Figure 10.107(a) with no external bias applied an an LOpower of 18 mW the conversion loss was 6.5 dB. Figure 10.107(b) alsoshows the DSB noise figure as a function of the IF frequency. The noisefigure was measured as approximately 7 dB with an IF amplifiercontribution of 2 dB.

In the transmit configuration a reverse bias was applied to the diodes.The performance of the circuit in this mode of operation is shown inFigure 10.108. The measured insertion loss was typically 2 dB over 33to 34.5 GHz. The corresponding return loss was greater than 14 dB andthe circuit was able to handle 150 mW.

10.5.7 MMICs in Modules

Over the last few years there has been a gradual move of MMIC designand application from the research laboratory into the sub system devel-opment area. This section of this chapter is devoted to a brief descriptionof two typical applications for MMICs. The first is a complete trans-mit/receive module operating at S-Band whilst the second is an imagerejection superheterodyne downconverter in the same frequency band.


\y Antenna

Power/

Driver

Amplifiers

I T

Transmit Receive

T/R switch

Low noiseamplifier

Phaseshifter

Figure 10.109 Typical Transmit/Receive Module

Figure 10.110 Photograph of Prototype S-Band TX/RX PhasedArray Module (Courtesy-Plessy)


10.5.7.1 Transmit/Receive Module

A typical transmit/receive module for phased array radar applicationsis shown in Figure 10.109. Until the present day it would have beenimpossible to justify the replacement of mechanically scanned radarswith electronically steered systems such as Aegis/Spy in the U.S. Withthe advent of MMICs it is now possible to contemplate seriously theimplementation of phased array radars because of the small size andpotential low cost of the transmit/receive modules.

The transmit/receive module of Figure 10.110 (Pengelly, 1984) consistsof a pulsed MESFET transmitter which is connected to the antennaelement via a transmit/receive switch also employing MESFETs. Thetransmitter is fed with phase-coded signals via a MESFET based digitalphase-shifter and driver amplifier stages. The radar beam shape iseffectively synthesized in space by combining the outputs of manyhundreds of such transmitters all spaced approximately one quarterwavelength apart in a regular matrix. On receive the beam is formedby passing the return signals through the digital phase shifter followingthe transmit/receive switch and low-noise preamplifier. In some phasedarray systems the phase shifted signals are then downconverted to anIF before combining the quadrature outputs.

The power output stage of the module was a lumped element matcheddiscrete MESFET having 6 mm total gate width and a conservativeoutput power of 2.5 watts. The MESFET was fabricated using viatechnology on plated-up 50 micron thick GaAs. The transmit/receiveswitch used an MMIC containing two shunt-mounted MESFETs. TheMESFETs were connected into an alumina substrate containing quar-terwavelength lines much as shown in the photograph of Figure 10.111.By employing the quarter-wavelength lines on alumina valuable GaAsarea is preserved and, hence, the number of switch MMICs is greatlyincreased per wafer. The overall sensitivity of the module on receivetogether with its spurious free dynamic range are provided by thelow-noise preamplifier. The module provides reception over a 20%bandwidth in S-Band. In order to keep the overall size of the LNA MMICwithin reasonable limits at these frequencies conventional microwavematching techniques cannot be used. In order to produce the requiredgain and noise figure a two-stage feedback amplifier was used (Figure100.112). Two of these chips were cascaded directly to provide 30 dBgain on receive. The digital phase shifter was of a design alreadydiscussed in the relevant section of this chapter (Bambridge et al, 1984).The transmission lines for the 22.5, 45, 90 and 180 degree bits were

596 Microwave Field-EfFect Transistors

Figure 10.111 Power Tx/Rx Switch Employing MMICs in ThickFilm Circuit (Courtesy-Plessy)

Figure 10.112 Microphotograph ofMMIC S-Band Low NoiseAmplifier (Courtesy-Plessy)


contained on alumina with the single-pole, double throw switchingmatrix being contained on GaAs.

All the MMICs were attached to small carriers which were intercon-nected using a thick film alumina substrate which also contained theDC feeds, control lines, transmission lines for the phase shifter andmatching circuits for the output power stage. A relatively conventionalPIN/NIP diode limiter was also contained in the RF section of the moduleto protect the MESFET preamplifier from overload and burnout.

Because there can be several thousand such elements in any one face ofthe phased array radar the control of each module from a centralcomputer has to be considered carefully. Each of the modules describedabove was controlled in phase and amplitude by a data link. The modulethus contained a thick film control substrate containing a gate array,data receiver, and decoder along with voltage conditioning and interfac-ing circuits.

The complete module measured approximately 40 by 100 by 12 mm.Figure 10.110 shows a photograph of a prototype unit indicating thepush-on RF connectors used to connect the module into the array face.

10.5.7.2 Image Rejection Receiver

If an input signal has frequency fs and the LO is at fro then the IF is ateither fs + fro or fs-fu). The image frequency is defined as the signal at2fL0-fs which produces an IF at the same frequency as the signal at fs.Depending on the relative frequencies of the RF and LO frequencies an

LNA

In-phasesplitter IF quadrature

combiner

L0 bufferamplifier Quadrature

power splitter

Mixers

Figure 10.113 Schematic Diagram of Image Rejection Receiver


image rejection receiver can employ either image frequency filtering orsignal and LO phasing to reject the image frequency. The latter is usedwhen the signal and LO are sufficiently close that image filtering isdifficult. The image rejection not only rejects spurious input signals inthe image band but also rejects the image band noise contributionthereby reducing the noise figure of the receiver by 3 dB.

In the circuit schematic of Figure 10.113 it can be shown that the 90degree phase shift introduced in the LO paths together with the quad-rature addition of the two IF signals will reject the image band.

An image rejection receiver covering 2.7 to 3.3 GHz using the aboveprinciple has been described by Beech et al (1985). The receiver consistsof a two-stage LNA MMIC followed by a lumped element passivein-phase Wilkinson divider MMIC. The LO is introduced into thereceiver via a buffer amplifier together with a passive Wilkinson dividerand 90 degree phase shift networks. The two RF and LO signals areintroduced into the balanced mixer MMIC shown in Figure 10.114. Thequadrature IF outputs from the mixers at 70 MHz are combined in alumped element hybrid quadrature combiner prior to being amplifiedby a Si IC IF amplifier. Each of the MMIC building blocks (signal LNA,LO buffer amplifier/phase shifter, dual channel mixers) are containedon small carriers with microstrip lines to interconnect the circuits. A

1

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1Figure 10.114 Microphotograph of MMIC Mixer (Courtesy-Plessey)


Figure 10.115 Photograph of Complete Image Rejection ReceiverUsing MMICs (Courtesy-Plessey)


microstrip crossover on GaAs was also used to feed the signals to themixer. The complete receiver is shown in Figure 10.115. The overall gainof the receiver is 30 dB with a noise figure of better than 4 dB. Imagerejection was measured as greater than 20 dB. This indicates the degreeof balancing, phase accuracy and internal low VSWRs in the receiver.

10.5.8 Further Levels of Integration

Three examples of complete subsystems on single GaAs chips are givenin this final section on analogue and microwave GaAs ICs. These are:-

(a) A fully integrated microwave receiver for DBS applications at 12GHz;

(b) A 20 GHz 5-bit phase shift/transmitter MMIC; and

(c) A monolithic image rejection mixer using transformer couplingand operating at S-Band.

10.5.8.1 DBS Receiver Chip

Kermarrec et al (1984) have reported on a single-chip DBS receiverMMIC for operation at 12 GHz. The receiver circuit is shown in Figure10.116. The low-noise preamplifier consists of three stages of gain andis followed by an image rejection filter. The image noise filtering is infact distributed throughout the interstage and output matching net-works of the preamplifier. The gain of the amplifier was greater than20 dB in the DBS frequency band with a noise figure of 4 dB. Imagerejection was higher than 20 dB. The preamplifier occupied a chip areaof 3 sq.mm. The dual-gate mixer has already been described in an earliersection.

The local oscillator was a common source FET circuit with seriescapacitive feedback stabilized using an off-chip dielectric resonator. Themonolithic oscillator had a frequency stability of better than 1 MHz from—20 to +80 degrees C. The LO was combined with the mixer on the samechip such that the total area occupied was 3 sq.mm.

The complete receiver chip was designed around a ground plane in thecenter of the chip where the ground plane was connected to RF groundwith three visa through the substrate. This plane also acts as anelectrical wall to shield the low-noise amplifier from the oscillator placedon each side. The complete chip consists of seven 0.7 micron gate lengthFETs, nineteen overlay capacitors, three interdigital capacitors, seven-


T Iw w v * II k

Figure 10.116 Equivalent Circuit of Complete DBS MMIC Receiver


Figure 10.117 Microphotograph of Fully Integrated MMIC DBSReceiver Chip (Courtesy-LEP)

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R.F. frequency, GHz

Figure 10.118 Conversion Gain and Noise Figure of CompleteMMIC Receiver


teen line inductances, one spiral inductance, eight GaAs resistors andthree via holes. The chip was mounted onto a coplanar circuit with acoplanar to microstrip transition to couple the dielectric resonator to thereceiver. Figure 10.117 shows a microphotograph of the chip whichmeasured 2.5 by 2.5 mm. Figure 10.118 shows the conversion gain andnoise figure as a function of frequency indicating that the overallconversion gain was 25 dB minimum with a noise figure of 4.5 dB.

10.5.8.2 20 GHz Transmit Chip

Gupta et al (1984) have reported a 20 GHz, 5-bit phase shift transmitmodule which was under development for NASA. The module wasrequired to have 5-bit phase control and gain of over 16 dB over the 17.7to 20.2 GHz frequency band. The function has been implemented as fourfunctional building blocks. These were a 5-bit passive phase shifter; atwo-stage buffer amplifier to compensate for the loss through the phaseshifter; a three-stage power amplifier and a digital interface to convertthe control signal to appropriate voltages for the phase shifter. Thebuilding blocks were first implemented as individual chips and thencombined into a single chip.

The buffer amplifier had a measured gain of 13 ± 0.75 dB over 17.7 to20.2 GHz. Measured performance of the three stage power amplifierwas 15 dB gain over 16.5 to 20.2 GHz with a saturated output power of21 dBm. The ion implant profile used for the power FETs was the sameas that used for the FETs in the 5-bit phase shifter. The chip size forthis functional block was 1.5 X 3.1 mm.

The phase shifter consisted of a cascade of five binary phase shifterswith phase increments of 11.25, 22.5, 45, 90 and 180 degrees at bandcenter. Each bit was implemented as a switched line phase shifter.FETs with 1 micron gate length were employed in a seriesshunt con-figuration to implement SPDT switches. The measured insertion lossof the phase shifter ranged between 2.5 to 4 dB. Since the SPDTswitching FETs require both true and complementary control signals,an inverter circuit was required for each of the five unit control lines tominimize interconnections. Further, the TTL input signal must beconditioned to provide 1 volt to turn the FETs 'on' and - 5 volt to turnthe FETs 'off. Five such inverters were included on the fully monolithicchip.

After successful realization of each functional block, the fully monolithictransmitter was implemented. The first of these chips had an overall


gain of greater than 12.5 dB from 17.5 to 19.5 GHz. The differentialinsertion loss between phase states was less than 0.5 dB whilst thedifferential phase shifts between each of the 32 phase states were withina few degrees of the required values. The overall size of the chip was 6.3X 4.7 mm with an anticipated yield of 20%. This circuit represents thehighest level of integration achieved for circuits operating at 20 GHz atthe time of writing.

10.5.8.3 Transformer Coupled Image Rejection Receiver

Ferguson et al of Honeywell (1984) have described an image rejectionreceiver using transformer coupled circuits such as the amplifier ofFigure 10.119. In this design the inductance of the transformer secon-dary winding is selected to resonate with the gate-to-source capacitanceof the next stage FET. The transformers have line widths of the orderof 3 microns with equal gaps to provide 'tight' coupling (of the order of0.8 or greater). The image rejection receiver used a single stage of RFgain, two LO buffer amplifiers, a fixed 90 degree phase shift, and twodouble balanced mixers. The mixers are driven with RF signals that arein phase and LO signals that are in quadrature. Figure 10.120 showsthe performance of the circuit. An LO frequency of 4 GHz was used withan IF band of 120 to 180 MHz. Image rejection of greater than 25 dBwas achieved over an Rf input from 4.12 to 4.18 GHz. The measuredconversion loss was 10 dB. The fabricated chip measured 1 X 0.7 mm.

10.5.9 Digital Circuits

Figure 10.38 shows the photomicrograph of a word generator usingdepletion mode BFL (Liechti, 1982). The circuit contains 400 transistorsand 230 diodes within a chip size of 1.6 by 1.1 mm. This circuit is capableof generating bit streams at 4 Gb/s.

Normally-off FET digital circuits can be used in all the major fields ofpossible applications such as instrumentation, telecommunications andcomputer systems.

10.5.9.1 Prescalers

GaAs ICs can be used to implement fast fixed or variable modulusprescalers well above 1 GHz and up to 10 GHz or so. There are two maintypes of static divide-by-two circuit techniques-these are the 6 NOR gate

Galliufri Arsenide Integrated Circuits 605

Figure 10.119 Transformer Coupled Amplifier

40 80 120 160 200IF frequency, MHz

Figure 10.120 Image Rejection of Monolithic Mixer usingTransformer Coupling


T flip-flop and the clock, clock bar master slave flip-flop. The former typeis implemented easily with DCFL gates and has a maximum frequencyof operation of 1/4TPD where TPD is the gate delay for a fan-out of two.The second type has a maximum frequency of operation of 1/2TPD. Thecomplementary clock pulses are generated 'on-chip' and the wholecircuit can be produced using either DCFL gates or CML (current modelogic) gates (Figure 10.121). The main performance trends of both thesetechniques are shown in Figure 10.122. Frequencies as high as 5 GHzhave been reported with the two approaches (Flahive et al, 1984 andRocchi et al, 1985). CML T-type flip-flops have also been fabricated andexhibited maximum frequencies of operation of 4 GHz at power dissipa-tions of 25 mW (Shimano et al, 1983). Using a reduced logic swing 10GHz operation can be expected. Such performance has already beenachieved with dynamic GaAs T-type flip-flops (Rocchi et al, 1983).

Of equal importance to high-speed counters are variable modulus pres-calers for use in frequency synthesizers. A 60/61 prescaler has been

VT>0

I "^DCFL 2 input NOR gate Buffer DCFL inverter

i

rReferencevoltage

3VT<0

Figure 10.121 (a). DCFL Gates (b). N-OFF CML Gates


1000

?

ssip

atio

n (rr

o

o« 1

0 1

-

0.5^mNMOS

•

I

SiCML ____ ^- 0.3^im

*?• DCFL

N-OFF CML

^ i p m D C F L

nDynamic DCFLT i l l

1 2 5 10 20Frequency (GHz)

Figure 10.122 N-OFF Flip-Flop Performances

developed which operates at 1.4 GHz with a total power dissipation of8 mW. The power consumption of this circuit is some ten times lowerthan that of similar submicron ECL circuits. The 60/61 divider is basedon a dynamic divide by 5/6 which achieved 1.5 GHz frequency ofoperation at a dissipation of 2 mW. Nagano et al (1984) have reporteda DCFL 252/256 variable modulus divider operating at 3.7 GHz with180 mW power dissipation. At 3 GHz this circuit had a power dissipationof only 42 mW which exemplifies the high performance potentiality ofGaAs N-offprescalers.

10.5.9.2 Memories

In computer systems, GaAs ICs can be used to implement data paths,processors and fast cache memories (Static Random Access Memories,SRAMS). Table 10.10 shows the characteristics of a number of GaAsSRAMs compared to the better laboratory Si circuits available. Memorycircuits are good subjects for GaAs LSI feasibility studies due to largememory cell quantities. This requires MESFETs with low power, highpacking density and good uniformity. Memory circuits also have periph-eral logic sections for read-write functions which require high speedcircuit design. Minimum access times of 1.3 nS for 1 Kbit (Yokoyami etal, 1984) and 2 nS access times for 4 Kbit (Idda et al, 1984) have beenobtained. The power dissipation per bit is about 0.2 mW for theseSRAMs. This is about one quarter the power dissipation of siliconbipolar SRAMs with approximately equal access times. For example,the characteristics of two types of SRAMs produced by Nippon Telephoneand Telegraph, Japan are shown in Table 10.11. It can be seen from this


Table 10.10 Characteristics of Fast Si and GaAs Static RandomAccess Memories

Organization(Company)

Si-4x256(NTT)

Si-4x256(NTT)

GaAs-1x1024(NTT)

GaAs-1x1024(LEP)

GaAs-1x1024(Fujitsu-HEMT)

GaAs-4x1024(NTT)

GaAs-4x1024(NTT)

MemoryAreasq. mm

9

6.25

11.6

6.25

8.7

14.7

44.8

CellArea

sq.ywm

1980

1048

3933

2622

2145

132

1332

AddressAccess

Time(nS)

1.5

0.85

1.5

3

3.4(300K)

0.9(77K)

2

4.1

Power(mW)

700

950

369

80

290

360

890

2520

Gatelength oremitter

size ( m)

1

0.5

1

0.7

1.5

1

1

DesignRules(jum)

2

1

3

3

3

1.5

1.5

table that the second version has a considerably improved performanceover the first. These improvements were due to a number of reasons:-

(1) An improved circuit configuration was chosen which was lesssensitive to FET threshold voltage variations. Source followerswere introduced driving the word lines to switch normally-on trans-fer-gate FETs.

(2) A 10 to 1 projection direct wafer stepper was used to improve thegate length uniformity over a 2 inch diameter wafer.

(3) Minimum line widths and spaces were reduced from 3/3 micronsto 1.5 microns. Chip and cell sizes were reduced to 1/2.2 and 1/3,respectively.

(4) Dislocation free LEC wafers were used and as a result thethreshold voltage standard deviation was greatly reduced to 17 mVfor enhancement mode FETs over a 2 inch diameter wafer (Figure10.123). The chip access time distribution was measured and ranged


Table 10.11 Typical Characteristics ofGaAs 4 KBit SRAMS(Courtesy-NTT)

Version

Organization

Logic

Access Time (nS)

Cycle Time (nS)

Power Dissipation (mW)

Device

Gate Length (urn)

Chip Size (mm)

Cell Size ( m)

Line Width/Space (am)

Through hole (am)

Simulated Performance

First Design

4K x 1 bit

E/D DCFL

2.8

14.0

1200

SAINT

1.0 ±0.2

5.6 x 6.0

6 2 x 6 5

3.0/3.0

2.0 x 2.0

2.15nS,0.85W

Second Design

1 K x 4 bit

E/D DCFL +source follower

2.0

6.0

900

SAINT

1.0 ±0.1

4.3 x 3.6

41 x 32.5

1.5/1.5

1.5 x 1.5

1.4nS,0.9W

from 4 to 16 nS with a typical time of 7 nS at a power dissipation of490 mW.

10.5.9.3 Gate Arrays

DCFL gate arrays are mainly attractive because of their low powerconsumption which is the limiting factor for fast silicon ECL gate arrays.

A number of workers have reported first results from reconfigurable cellarrays, (Deming et al, 1984 and Pengue et al, 1984). Deming et al havedescribed an array fabricated using 1 micron gate depletion modeMESFETs configured in BFL structures. Measured results on severalcell configurations with various device sizes yielded speed-power prod-ucts ranging from 162 fJ to 460 fJ. A 306 cell array (equivalent toapproximately 430 NOR gates) occupying a chip area of 2 X 2.8 mm wasfabricated. A 5 X 5 multiplier implemented with this array showed amultiplication time of 6.5 nsecs with an accompanying power dissipationof 722 mW. Excellent performance has also been obtained from DCFLarrays. For example, a 2K gate array with a loaded gate delay (fan-out


250r

200

> 150

E2

100

50

LEC_Vt =*280mV

crVt = 67 mV

DF LECVt=*297mV

a V t ~ 17mVN=500

Lk100 200 300 400 500 100 200 300 400 500

E-FET threshold voltage (mV)

Figure 10.123 Threshold Voltage Distribution for a Conventionaland a Dislocation-free 2 inch LEC Crystal

= 4; fan-in = 6) of 240 psec had a power consumption of 0.5 mW per gate.An 8 X 8 multiplier implemented with this 2K gate array technology hasexhibited a multiplying time of 8.5 nS with a power consumption of 400mW. A custom version of the multiplier would, however, be expected tobe almost twice as fast for the same power consumption.

10.5.9.4 A Comparison with Fast Si ICs

The classical advantage of GaAs is the factor of five times higher electronmobility over silicon. However, this factor must be modified by consid-ering the effective portion of the velocity field curve that is operative. Ina MESFET having a 1 micron gate length in the 'OFF condition inenhancement/depletion mode logic, 1.5 volts may be dropped across thegate, corresponding to a field of 12 kV/cm. This results in the electronvelocity being only TWICE that of silicon as the channel opens up. Incontrast, the full velocity advantage is realized when the gate is ON.The performance of bipolar transistors using GaAs and its derivativesdepends on diffusion times across the base. Down to base widths of 0.1microns this time is determined by mobility which can be enhanced by


grading the alloy composition in the base. Compared with Si the fullmobility advantage is available for this component of the transit time(i.e. of fT). This leads to a dominance of the collector transit time, wherethe fields are such that the carrier velocity approaches the saturationvelocity and GaAs may be somewhat unfavorable in this respect.

Design freedom in GaAs bipolar technology is given by the control in theinjection by GaAlAs alloy emitters and collectors. This allows basedoping to be increased, hence reducing base resistance and preventingunwanted injection in the sidewall of the transistor. This is a realadvantage over silicon. Further control can be exercised by a localizedimplant of boron or other species when after limited annealing theimplanted regions remain semi-insulating.

The high electron mobility transistor (HEMT) (see Chapter 11) alsoemploys GaAlAs and requires expensive high quality epitaxial layers.The higher mobility in the layer gives rise to a lower 'ON' voltage andthe higher work function of the GaAlAs gives a higher threshold voltagefor gate conduction and also reduces the parasitic source series resis-tance. These effects are marked at 77K but it is still not generallyaccepted that HEMTs have any major improvements at room tempera-ture.

As well as the obvious advantages in technological maturity held by SiICs, there are some real advantages notably in the availability ofthermal and deposited silica and its compatibility with polysilicon. Theuse of polysilicon is accepted widely in autoregistered MOS technologieswhere it acts as a mask against implantation that can be activatedduring subsequent annealing. Many modern MOS and bipolar proc-esses employ oxides for lateral isolation reducing capacitance in the sidewall and inhibiting parasitic bipolar transistor action. Ingenious proc-essing techniques allow complex structures to be fabricated with a highdegree of self-alignment so that feature sizes compatible with photoli-thography down to 1 micron can give rise to lateral features less thanhalf that value. The high solubility of acceptor and donor impuritiesfurther allows these features to be employed without unduly highcontact resistances.

Results of ring oscillators are often quoted as the circuits indicatingstate-of-the-art performance. Provided that the ring oscillators haverepresentative fan-in and fan-out as well as interconnects and cross-overs as loads, valuable information on the delay as a function of loadingfor a given power can be obtained. The first real devices for a faircomparison between different technologies are dividers. The compari-


son can be extended by the performance of such circuits as variablemodulus dividers, multiplexers and multipliers. More complex func-tions realized by gate arrays give an indication of the feasibility ofcomplex structures in a given technology at a given time.

Tables 10.12 to 10.15 give results which have been selected from anumber of recent publications. It should be noted that they do not, ingeneral, represent commercially available devices.

The ring oscillator results show GaAs to be superior in speed by a factorof four or so with these speeds being obtained at exceptionally low powerindicating the ultimate capability for VLSI. Silicon delays as low as 42psec have been obtained but at the expense of power delay product.Some NMOS results employing X-ray defined short gate lengths have

Table 10.12 Comparison of performance of Si and GaAs RingOscillators as of June 1985

Device Type

GaAs FET

GaAs FET

GaAs FET

GaAs FET

HEMT

SINTL

SiECL

SiECL

SiECL

I2L

NMOS

NMOS

MinimumFeature

Size(wm)

0.6

1.0

1.0

1.5

1.0

0.5

0.5

3

3

3

1.22

0.3

GateDelay(PS)

1523

18.527

30.7

42

12.2

42

96

83

190

290

80150

30

PowerDelaly

Product(fj)

839.5

578.5

4.3

21

13.6

20

96

83

42

15

3.62.1

45

Notes

Saturated resistor load

TiW autoregistered gate

Recessed gate

TiW gate

Saturated resistor

Super self alignedtechnology (SST)

SST

Sidewall contact (Sicos)

Sicos

Sicos

NMOS

NMOS

OrganizationYear

Cornell,1983

Avantek,1985

AT&T, 1984

Toshiba,1985

Rockwell,1983

NTT, 1983

NTT, 1983

Sony, 1984

Sony, 1984

Sony, 1985

Hitachi,1983

AT&T, 1984


not been included. For dividers, the maximum frequency of operation isclosely fought, GaAs MESFETs showing lower power consumption atpresent with silicon and GaAs competing closely for speed. The GaAsheterojunction bipolar result in Table 10.13 is almost as good as thesilicon SSI bipolar result with much smaller feature sizes.

For gate arrays, comparability is difficult. GaAs achieves similar speedsat lower power. Table 10.14 reveals that at the level of complexity of a16 X 16 multiplier Si bipolar technology reveals an edge in speed.Although CMOS is not able, at present, to compete in speed terms itsduty cycle advantage is apparent in power consumption comparisons.

For SRAMs all technologies compete in performance. At the time ofwriting, silicon technologies are, presumably, more reproducible at thefeature sizes quoted and delays are dominated by interconnect wiring.

The conclusion, looking into the future, is that advantages of GaAs forlogic will become most apparent as VLSI MESFET circuits emerge witharchitectures that reduce interconnect delays. Only then can the intrin-sic low delay and power delay products be utilized fully.

Table 10.13 Comparison of Performance of Si and GaAs Dividers asof June, 1985

Device Type

GaAs FET

HEMT

HEMT

Bipolar

Bipolar

Bipolar

Bipolar

MinimumFeature

Size(am)

1

-

1.2

3

1

1.25

1.2

fMAXGHz

6.2

5.5

5.5

6

9

6.2

8.64.5

PowermW

39

38

-

45

175

150

80

Notes

Resistor Load

- .

-

Sicos

SST,525mWfordivide-by-8fT=17GHz

ECL, 300 mW fordivide-by-8fT=11 GHz

GaAs, fT = 35 GHz

OrganizationYear

Avantek,1985

Fujitsu,1983

AT&T, 1984

Hitachi,1985

NTT, 1984

NEC, 1985

Rockwell,1984


I

•3

13

!

LI\8

I

E

Mir

1"cO

CO

CD

c

2 «£ fesCM C/5 " D CO '</

cvi o oCO CM

O) inin oo

CO LOi - CM

5! 8 R

in O) ^t

in p inT"1 1-" O

15 i5

O m o in


Table 10.15 Comparison of Performance of Si and GaAs Multipliersas of June, 1985

Device Talk

GaAs FETE/D

BipolarSST, CML

CMOS

Type

8 x 8

1 6 x 1 6

8x8

MinimumFeature

Size (fim)

1

1

1.3

Delay (nS)

7.9

7.5

10025

Power(mW)

220

2070

450

OrganizationDate

Oki,1985

NTT, 1985

Hitachi,1985

Digital GaAs IC technology will have a significant impact on the per-formance of digital signal processing systems and computers. The initialimpact will be in pre-processors in which circuits utilizing both depletion(DFET) and enhancement (EFET) mode FETs will have input andoutput signals compatible with ECL logic levels. The development of aLSI/VLSI technology with a combination of DFET and EFET deviceswill require stringent control of material growth and process parametersto produce uniform device characteristics and good process yields. Asummary of projected performance for GaAs digital ICs is given in Table10.16 (Greiling, 1984).

Table 10.16 Projected Performance for Digital GaAs IntegratedCircuits (after Greiling, 1984)

Feature

Gate loaded delay

Power Dissipation

Complexity

Preprocessor speed

A/D converter speed with 8-bit accuracy

Signal Processor Speed

Access Time of 4K Memory

Radiation tolerance

Projection

Less than 50 pS

50 to 200 microwatts

MSI through LSI

Greater than 5 GHz

Greater than 1 GBit/Sec

Greater than 1 GHz clock frequency

1 nanosecond

>107 Rads, > 1010 Rads and >1015 N/cm2


10.6 Conclusions

It has been seen in this chapter that the GaAs field effect transistor isplaying a most important role in the development of integrated circuits.Analogue microwave circuits fabricated on gallium arsenide have aperformance which is unattainable using silicon. Digital logic circuitson GaAs have a five times speed advantage over silicon at the presenttime but the massive investment in the very high speed IC (VHSIC)program in the USA will undoubtedly narrow the gap. However, thereare many promising logic architectures based on GaAs MESFETs,JFETs and MOSFETs which will progress rapidly as the technologymatures. The bibliography below is intended as a guide to furtherreading and papers not referred to in the text are also included. Thecomplexity of both analogue and digital GaAs ICs is increasing rapidly.Markets for GaAs ICs are becoming well defined and a $1500 millionmarket in the USA alone is anticipated by 1990, which assuming modestrequirements in the early 1980's infers a growth in the market in excessof 100% per annum over the next decade.

10.7 Bibliography

Abe, M., Mimura, T., Yokoyama, N. and Ishikawa, H. New technologytowards GaAs LSI/VLSI for computer applications. IEEE Trans, onMTT Vol. MTT-30, No. 7, pp.992-998, July 1982.

Alexopoulos, N.G., Maupin, J.A. and Greiling, P.T. Determination of theelectrode capacitance matrix for GaAs FETs. IEEE Trans, on MTT, Vol.MTT-28, No. 5, pp.459-466, May 1980.

Aitchison, C.S., Davies, R., Higgins, I.D., Longley, S.R., Newton, B.H.,Wells, J.F. and Williams, J.C. Lumped microwave circuits. Design Elec-tronics, October 1971, pp.30-39.

Allen, R.P.G, and Antell, G.R. Monolithic mixers for 60-80 GHz. Proc.1973 European Microwave Conference, Paper A153.

Alley, G.D. Interdigital capacitors and their application to lumped ele-ment microwave integrated circuits. IEEE Trans, Microwave TheoryTech., Vol. MTT-18,pp.l02-1033,Dec. 1970.

Antell, G.R. Monolithic mixers for millimeter wavelengths, Proc. 1971European Microwave Conference, p.C2/3:l.


Anzic, G. and Connolly, D. J. 20 and 30 GHz MMIC Technology for futurespace communication antenna systems. Technical Digest of 1984 IEEEGaAs IC Symposium, pp. 189-192, October 1984.

Araki, T. A high cut-off frequency planar Schottky diode with a stripegeometry junction. IEEE Trans, on Electron Devices, Vol. ED-25,1978,p.1091.

Asbeck, P.M. and Miller, D.L. Extended Abstracts of the 16th Interna-tional Conference on Solid State Devices and Materials, 1984, pp.343-346.

Ayasli, Y., Pucel, R.A., Fabian, W. and Vorhaus, J.L. A monolithic X-bandsingle pole, double throw bidirectional GaAs FET switch. IEEE GaAsIC Symp. Research Abstracts, Las Vegas, USA, Nov. 1980, paper 21.

Ayasli, Y., Platzker, A., Vorhaus, J. and Reynolds, L.D. A monolithicsingle-chip X-Band four-bit phase shifter. IEEE Trans, on MicrowaveTheory and Techniques, Vol. MTT-30, No. 12, pp.2201-2206, December1982.

Ayasli, Y, Reynolds, L.D., Vorhaus, J.L. and Hanes, L.K. 2-20 GHz GaAstravelling-wave amplifier. IEEE Trans, on Microwave Theory and Tech-niques, Vol. MTT-32, No. 1, pp.71-77, January 1984.

Ayasli, Y, Miller, S.W., Mozzi, R. and Hanes, L.K. Capacitively coupledtravelling-wave power amplifier. IEEE Microwave Millimeter WaveMonolithic Circuits Symposium Digest, pp.52-54, May 1984.

Bambridge, T, Lane, A. and Suckling, C.W. Active and passive phaseshifters employing GaAs MMICs. IEE Colloquium on 'ManipulatingMicrowave Signals', Digest No. 1984/108, p.6/1-6/4.

Bastida, E.M. et al. A monolithic 800 MHz bandwidth DBS front-endreceiver for mass production. 14th European Microwave ConferenceProceedings, Liege, 1984, pp.755-760.

Bauhahn, P., Contolatis, T, Abrokwah, J. and Chao, C. 94 GHz planarGaAs monolithic balanced mixer. Digest of IEEE Microwave and Milli-meter-wave Monolithic Circuits Symposium, 1984, pp.70-73.

Beech, G. et al. An S-Band image rejection receiver front-end incorpo-rating GaAs MMICs. Proceedings of 15th European Microwave Confer-ence, Paris, 1985, pp. 1019-1024.

Bollinger, D. and Fink, R. A new production technique: Ion milling. SolidState Technology, November 1980, pp. 79-84.


Brambley, D.R. and Vanner, K.C. IPAT 1979 Proceedings, LEP Consult-ants, Ediburgh 1979, pp. 47-54.

Braun, L. and Lood, D. Proc. IEEE, Vol. 54,1966, pp.1521-1527.

Brookbanks, D.M. Private Communication, 1985.

Cahana, D. A new transmission line approach for designing spiralmicrostrip inductors for microwave integrated circuits. IEEE MTT-SSymposium Digest, 1983, pp. 245-247.

Cathelin, M., Durand, G., Garant, M. and Rocchi. 5 GHz binary frequencydivision on GaAs. Electronics Letters, Vol. 16, No. 14, pp. 535-536.

Chao, C, Contolastis, A., Jamison, S.A. and Johnson, E.S. Millimeter-wave monolithic GaAs balanced mixers. 1980 GaAs IC Symposium, LasVegas, paper 32.

Ch'en, D.R. and Eisen, F.H. Ion implanted high frequency high speedGaAs integrated circuits technology. J. Vac. Sci. Technol, Vol. 16 No. 6,Nov/Dec. 1979, pp. 2054-2062.

Chu, A., Courtney, WE. and Sudbury, R.W. A 31 GHz monolithic GaAsmixer/preamplifier circuit for receiver applications. IEEE Trans, onElectron Devices, Vol. ED-28, No. 2, Feb. 1981, pp. 149-154.

Chu, A., Courtney, W.E. and Mahoney, L.J. Monolithic circuits for milli-meter-wave systems. Microwave Journal, Vol. 26, No. 2, Feb. 1983, p.28.

Chu, A. et al. Monolithic frequency doublers. Digest of IEEE Microwaveand Millimeter-wave Monolithic Circuits Symposium, 1983, pp.45-49.

Chu, A. et al. Dual function mixer circuit for millimeter-wave trans-ceiver applications. Digest of IEEE Microwave and MillimeterwaveMonolithic Circuits Symposium, 1985, pp.78-81.

Commizoli, R.B. RCA Review, Vol. 37, December 1976.

Cook, P.W. et al. Logic circuit design methodology and applications.IEEE Trans, on Electron Devices, Vol. ED-26, pp.333-346, April 1979.

Courtney, W.E. Complex permittivity of GaAs and CdTe at microwavefrequencies. IEEE Trans. Microwave Theory Tech., Vol. MTT-25,pp.697-701, Aug. 1977.

D'Asaro, L.A., Di Lorenzo, J.V. and Fukui, H. Improved performance ofGaAs microwave field effect transistors with via connections throughthe substrate. Int. Electron Devices Meeting, Digest Tech. Papers,pp.370-371,1977.


Dawson, D.E., Conti, A.L., Lee, S.H., Shade, G.F. and Dickens, L.E. Ananalog X-Band phase shifter. IEEE Microwave and Millimeter WaveMonolithic Circuits Symposium Digest, pp.6-10, May 1984.

Degenford, J.E., Freitag, R.G., Boire, D.C. and Cohn, M. BroadbandMMIC Power amplifier development. Microwave Journal, pp.89-96,March 1982.

Deming, R.N. et al. A gallium arsenide configurable cell array usingbuffered FET logic. Technical Digest of IEEE GaAs IC Symposium,1984,pp.l5-18.

Dill, H.G. Designing inductors for thin film applications. ElectronicDesign, February 1964, pp.52-59.

Dormail, J., Tajima, Y., Mozzi, R., Durschlag, M. and Morris, A.M. A 2 to8 GHz 2 watt monolithic amplifier. Technical Digest of 1983 IEEE GaAsIC Symposium, pp. 115-118, October 1983.

Driver, M.C., Wang, S.K., Przybysz, J.X. et al. Monolithic Microwaveamplifiers formed by ion implantation into LEC gallium arsenide sub-strates. IEE Trans, on Electron Devices, Vol. ED-28, No. 2, Feb. 1981,pp.191-196.

Eden, R.C., lielch, B.M. and Zucca, R. Low power GaAs digital ICs usingSchottky diode FET logic, 1977, Int. Solid State Circuits Conf. Digestof Tech. Papers, Feb. 1977, pp.68-69.

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Other Papers of Interest

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Taylor, D.M., Wilson, D.O. and Philips, D.H. Gallium arsenide review:past, present and future. IEE Proc. Vol. 127, Pt.I. No. 5, October 1980,pp.266-269.

Upadhyayula, L.C. GaAs MESFET comparators for gigabit-rateanalogto-digital converters. RCA Review, Vol. 41, No. 2, June 1980,pp.198-211.

Wieidlich, H.P., Archer, J., Pettenpaul, E. et al. A GaAs monolithicbroadband amplifier. IEEE Solid State circuits Conf. Digest Tech.Papers 1981,pp.l92-193.

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11

Other III-V Materials and Devices

11.1 Introduction

The last twenty years has seen GaAs material being used increasinglyfor many microwave devices including the field effect transistor. Thereare, however, many other compound semiconductors which should giveconsiderable gain, noise figure and higher frequency advantages overGaAs. These materials include indium phosphide (InP) and the ternaryand quaternary compounds such as GaxIni-xAs and GaxInxAsySbi-y. Ofthe ternary compounds InPAs appears to be most likely to give substan-tial frequency of operation improvement and GalnAs to give substantialgain and noise figure improvement, particularly at the higher frequen-cies. However, in order to reach operating frequencies approaching 50GHz or so narrow gate length devices are still needed and the technologyand ingenuity of the device designer then limits the device performance.

In order to substantially increase the maximum frequency of oscillationit is necessary to develop new transistor structures which, althoughhaving the advantages of the FET (that is being majority carrier de-vices), also have some of the advantages of the bipolar transistor suchas very high transconductance. One of the most promising structuresreceiving much attention at the present time is the permeable basetransistor which may ultimately have a maximum frequency of oscilla-tion greater than 1000 GHz compared with typical values of only 80 GHzfor a conventional 0.5jum gate length GaAs FET.

11.2 ThelnPMESFET

Indium phosphide (InP) has electronic properties very similar to thoseof GaAs and can therefore be used, in principle, to produce MESFETs.InP has some fundamental differences which suggest that the materialwill produce FETs with superior performance over GaAs devices. Table11.1 lists the major properties of Si, GaAs and InP, The primary perform-ance advantage results from the higher peak electron drift velocitywhich is the parameter of major importance for short gate length FET's.Maloney and Frey (1976) have shown that the frequency for unity gain,fr, for InP FETs at room temperature should be some 48% higher than


Table 11.1 Comparison of Semiconductor Material Properties

Property

Low field mobility(450°K)

Peak (threshold)velocity (450°K)

'Peak-to-valley'ratio (450°K)

Saturated driftvelocity (450°K)

Thermal conductivity(300°K)

Energy gap (300°K)

Units

cm 2 V- 1 s - 1

cms"1

-

cms- 1

Wcm"1 oC~1

eV

Material

Silicon

400

-

-

8.5 x 106

1.45

1.11

GalliumArsenide

5000

1.2 x10 7

2.2-2.4

5 x 106

0.44

1.43

IndiumPhosphide

3000

1.9 x 107

3.0-3.1

6 x 106

0.68

1.34

GaAs devices having gate lengths of l^m. Figure 11.1 shows the theo-retical fr versus gate length, Lg curves for FETs using GaAs or InPhaving gate lengths varying from 0.5 to over 5 microns. The fr advantagehas, in fact, been observed experimentally (Barrera et al, 1975) but theadvantages that were theoretically predicted initially for gain and noise

605040

30fr.GHZ

20

10

00.4

T = 300° KCarrier concentration = lO^cm"1

^ * ^ InP

GaAs ^ " ^ ^ ^ ^ " ^ ^ ^

1.0 2.0 3.0 4.0 5.0

Gate length, ms

8.0

Figure 11.1 Current Gain Cut-off Frequency Versus Gate Lengthfrom a One-Dimensional Monte Carlo Analysis for GaAs and InP

Other III-V Materials and Devices 631

figure have not been seen due to non-optimum material characteristics,buffer layer and substrate quality problems and technological problemsassociated with the low barrier characteristics of Schottky barrier gatesto InP.

Gallium arsenide FET fabrication is highly developed, indeed as hasbeen seen in the last chapter, many laboratories worldwide are currentlyworking on sophisticated analogue and digital GaAs integrated circuits.Indium phosphide technology has been unable to benefit properly fromthis extensive GaAs work because of the low Schottky barrier height ofmetal/indium phosphide structures. Not only does the gate electrode ofthe device tend to have low breakdown voltage and considerable currentleakage but non-destructive characterization of FET layers using ca-pacitance voltage (C(V)) data has not been possible. The use of novelMOS techniques has been necessary (Clarke et al, 1979) to accuratelyprofile the epitaxial layers grown for InP FETs.

Barrera and Archer (1975) have reported extensive work on InP MES-FETs, the results of which indicated many of the intrinsic properties ofthis device. Relatively large drain current can flow when the device is'pinched off' typically 0.5 mA for a fy/m gate length, 50Qam gate widthdevice. This is due to the reverse current that flows between the gateand the drain due to thermonic field emission at the perimeter of thegate. Such currents are some 1000 times greater than in the GaAs FETnot only because of the lower Schottky barrier height of the gate for InPbut also due to the surface properties of the InP.

D.C. transconductance is higher for InP FETs than for GaAs FETs andincreases with the doping of the epitaxial layer Typical values are 200mS per mm gate width for ND = 1.4 X 1017 cm~3 and 100 mS per mm forND = 6 x 1016 cm~3. GaAs FETs have a typical value of 100 mS/mm forND = 1 x 1017 cm-3.

Table 11.2 indicates the results of work conducted at Hewlett Packardin 1975 for l^m gate length FETs. Even though the current gain cut-offfrequency, fr is some 50% greater in the case of the InP device thecombined influence of the much larger drain-to-gate feedback capaci-tance, Cdg, the smaller drain to source output resistance, Rds, and thesomewhat larger input resistance, Ri + Rg + Rs, in the InP case, give riseto lower available power gain and hence lower unilateral power gaincut-off frequency, fmax since


Table 11.2 Comparison of InP and GaAs MESFETs Fabricated atHP Laboratories in 1975

Parameter Material

Current gain cut-offfrequency, h (GHz)

Mason's unilateral powergain cut-off frequencyfmax (GHz)

Noise figure for MAG at10GHzdB

Minimum noise figiure at10GHzdB

Associated gain at 10GHz, dB

Transconductance gmo,mS

InP

6 x 1016

cm"3

20

33

6

4.8

5.8

50

1017cm"3

20-24

32

9.5

6.0

5.5

84

GaAs

6 x 1016

cm"3

11

40

7.5

3.5

6.6

33

1017cm"3

13

40

6.2

3.2

7.8

53

fr/MAX ""

Table 11.3 compares the equivalent circuit element values for GaAs andInP devices of the same geometry where the component designationsare given in Figure 11.2.

The largest contribution to the decrease in the power gain of the InPFET is due to the large value of capacitance, Cdg which increasesdegenerative feedback. The roughly five times higher feedback capaci-tance Cdg in current-saturated InP MESFETs as compared to GaAs onesis mainly due to the formation of weaker Gunn domains between thegate and drain at the drain bias levels needed for drain current satura-tion. This results in the depletion layer fringing capacitance not beingso effectively decoupled at the drain.


Table 11.3 Magnitudes of Equivalent Circuit Parameters for ImPand GaAs MESFETs with Similar Geometries

Parameter

Carrier Concentration

Cgs, pF

Rgs.Q

Ri,G

Cdg, pF

Rdg,Q

gmo, rnS

Rds,Q

Rg,Q

Lg, nH

Rs,Q

Ls,nH

Rd.Q

Cds, pF

InP

6 x 1016cm"3

0.36

10,000

6.0

0.056

8,500

50

260

5.5

0.1

3.5

0.04

5.0

0.06

GaAs

6 x 1016cm~3

0.5

00

3.5

0.01

00

33

660

3.0

0

5.5

0

7.0

0.06

Figure 11.2 RF Eqivalent Circuit for the InP MESFET


The second most serious influence on power gain is that of the drain tosource resistance, Rds for InP which is half the GaAs value.

The smaller drain-to-source resistance, Rds, in the InP device is corre-lated with the generally higher drain currents found in such devices.This is caused by the resistivity of the InP substrate being lower by afactor of up to 104 for a given Cr doping than for GaAs. It has beenconcluded that no electron trapping occurs at the epitaxial to substrateinterface in InP FETs (Engelmann, et al, 1977).

As has been seen in Chapter 2 the formation of a Gunn domain at thedrain side of the channel leads to the average carrier velocity in thechannel decreasing. In the range of drain bias voltages employed forMESFETs (usually 4 to 5 volts) the effect is much stronger in GaAs thanin InP and hence the InP FET appears to have a higher tfr than GaAswhich simple theories predict (Barrera et al, 1975). The difference inthe Gunn domain formation mentioned above is related to the funda-mental difference in the carrier velocity versus electric field charac-teristic of GaAs and InP. To achieve similar Gunn domain effects in InPas in GaAs one would have to increase the drain bias levels by a factorof at least three over those for GaAs. Such action is not, at present,possible because of the breakdown voltage limits of InP Schottky gatejunctions.

Englemann and Liechti (1977) predicted that the use of Fe rather thanCr doped substrates might effect the process of Gunn domain formationand hence improve InP FET performance.

Gleason et al (1978) have produced ion-implanted InP FETs using Fedoped substrates having resistivities greater than 107 Q cm grown bythe liquid encapsulated Czochralski method. In contrast to the resultsmentioned earlier the gates of the implanted devices showed adequatebreakdown voltages and low leakage currents. Typical d.c. leakagecurrents were 5 to 10 nA at a VDS of 3V and with corresponding gate todrain breakdown values of 10 to 15 volts at Igs equal to 1/*A. Many ofthe breakdown and leakage current problems of early devices arethought to have been due to surface oxides forming prior to gatemetallization. However, the r.f. results of the ion implanted devices weredisappointing with 9.8 dB noise figure and 13.7 dB associated gain beingachieved at 8 GHz.

The use of a plasma oxidation process prior to gate metal depositiongiving reproducible low leakage gates has led to InP MESFETs beingproduced having the Plessey GAT4 geometry with a minimum noisefigure of 3.8 dB and 7 dB associated gain at 12.75 GHz. This compares


with a minimum noise figure of 2.6 dB with 6 dB associated gain for anion implanted GaAs at the same frequency.

It has been concluded by many workers that the InP MESFET has noadvantage over the GaAs device and activity is now being concentratedon the technology necessary to produce FET structures using the supe-rior properties of certain of the ternary and quaternary alloys.

11.3 ThelnPMISFET

InP has, however, not been completely forgotten as it is now forming thebasis of much intense work on MISFETs (metal insulator semiconductorfield effect transistor) specifically related to logic integrated circuitapplications.

Unlike the situation with GaAs, it has been demonstrated that a layerof mobile electrons can be induced at the surface of both p-type (Messicket al, 1978; Meiners et al, 1979a) and semi-insulating InP (Meiners etal, 1979b) by the application of a positive potential to a metal gateelectrode isolated from the semiconductor by a thin insulating film muchas shown in Figure 11.3. Normally-off enhancement mode metal-insu-lator field effect transistors on both p-type (Lile et al, 1979) and semi-insulating InP substrates have been fabricated. The devices made onSI InP have shown power gain at microwave frequencies (Meiners et al,1979b).

GaAs MISFETs or MOSFETs (Becker et al, 1965; Sugano et al. 1978)although exhibiting excellent microwave performance are limited intheir operation at very low frequencies due to the high density of states

IsolationEtch Source Drain Semi-insulating

InP substrate

n-layer Au-Ge/Ni Silicon Dioxide Ohmic contact

Figure 11.3 InP MISFET Structure


at the GaAs to insulator interface, resulting in fixed charge densities.InP MISFETs exhibit much lower charge densities allowing the surfacepotential to be changed by over 1 volt compared to 0.4V for GaAs(Messick, 1979; Messick, 1976). MIS technology also offers the attrac-tions of high dynamic range since the positive gate bias which is requiredto produce a surface layer of mobile electrons in a normally-off MESFET,is limited only by the dielectric breakdown voltage of the insulator inthe MISFET. Thus InP MISFET technology apart from being a promis-ing one for analogue microwave applications is also most useful for anintegrated logic approach similar to NMOS on Si.

The procedures employed for the formation of the gate insulators(Hasegawa et al, 1975; Zeisse et al, 1977) as well as some of theproperties of the insulator dielectrics used are outlined in Tables 11.4and 11.5. It may be seen, for example, that the pyrolytic insulatorsproduced using chemical vapor deposition have a higher breakdownvoltage than those dielectrics produced using anodization of the GaAs.

The results of tuned power gain measurements for both GaAs and InPMISFETs have been reported by Messick (1979) as a function of fre-quency. The gains of the MISFETs which had gate lengths of 4/um andgate widths of 260/an were very similar to those of commercially avail-able 4jum gate length MESFETs. Figure 11.4 shows the gain resultswhere the bias conditions for the GaAs FETs were individually opti-mized for maximum power gain.

Noise figure results for the GaAs and InP MISFETs are compared withthe commercially available 4/um gate length GaAs MESFET in Figure11.5, where it may be seen that the MESFET has a 2 dB lower noisefigure, typically. The reason for the degradation in MISFET noise figureis probably due to a combination of ohmic contact value, epitaxial layer

Table 11A Gate Insulation Processes

Type of FET

GaAs Schottky gate

GaAs/Anodic oxide insulated gate

GaAs/pyrolytic Six0yNz insulated gate

InP/Pyrolytic SiO2 insulated gate

Gate Insulator Process

No insulator present

Wet chemical anodization achieved atroom temperature

Chemical vapor deposition at 600°C usingN2l NH3 and SiH4

Chemical vapor deposition at 310°C usingN2, O2 and SiH4


Table 11.5 Gate Insulator Properties

Material

Anodic insulator on GaAs

Pyrolytic SixOyN2 on GaAs

PyrolyticSiO2onlnP

Properties

O.ijwm thickness, growth time: 2 to 4 mins; 20-40Vbreakdown voltage; leakage current at 10V is 10~12 to10~10 A/mm2. Surface state density = 1012 cm2 eV~1.

O.i^m thickness, growth time: 180-300 mins; 50-100Vbreakdown voltage; leakage current at 10V is 10"12

A/mm2. Surface state densit = 10~12 cm2 eV~1.

0.12jim thickness, growth time: 20-80 mins; 50-100Vbreakdown voltage; leakage current at 10V is 10~12 to10~11 A/mm2; surface state density = 1011 cm2 eV"1.

quality, gate insulator quality and the different gate biasing associatedwith each device. Certainly at microwave frequencies the surface statesassociated with the insulator are unable to follow the impressed gatesignal. In this respect the InP MISFET appears to be preferable forapplications requiring low as well as high frequency operation since thisdevice has a lower surface state density and in devices fabricated to dateusing silicon dioxide (SiO2) as the insulator full drain modulation bygate action down to 100 Hz has been demonstrated.

A recent paper reported the performance of an Al-SiO2-InP MISFET asa power amplifier at 9 GHz (Armand et al, 1983). The output power perunit gate width obtained by the MISFETs was 3.5 watts/mm with 4dBgain at 9 GHz. With the superior thermal conductivity of InP comparedto GaAs and its higher electon saturation velocity there is a continuedinterest in the InP MISFET. Thus, considerable effort has been put intothe development of ultrahigh mobility layers particularly recently usingmetal-organic chemical vapor deposition (MOCVD). For example, Zhuet al (1985) have reported the use of low-pressure MOCVD to producehigh quality InP with room temperature and 77°K mobilities as high as5360 cmW-s and 131,000 cmW-s respectively. The surface morphol-ogy of such layers has been shown to be dependent on the rate of growth.Zhu et al have found that a growth rate of 8 microns per hour gives highquality surfaces suitable for FET fabrication.

11.4 Ternary and Quaternary Compounds for MESFETs

As we have seen in this monograph the amount of effort afforded to GaAsFET device technology and circuit design has been considerable. Thiseffort has shown that in order to justify the development costs involved


14.0

12.0

S 10.0

I 8.0

1 6.0

4.0

2.0

i

•

0 0.5

O DO

D

• o

1.0 2.0

Frequency, GHz

5.0

O GaAsSchottky

D GaAs Anodic MIS

A GaAs/SixOvN,MIS

• lnP/SiO?MIS

Gate lengths = 4ym

Figure 11.4 Power Gain Versus Frequency for MISFETs (afterMessick)

any new material which is considered as a contender to GaAs must havesome strong performance advantages.

Table 11.6 shows some of the important material parameters of a varietyof ternary and quaternary materials which have considerable advan-tages over GaAs in terms of peak electron velocity. All the materialswith the exception of InP have a higher mobility than GaAs leading to

Fig

ure

, dB

.8z

12

10

8

6

A

2

1

! D •

oI ®

.0 1.5 2.0

Frequency, GHz

0

3.0

o GaAs Schottky

• GaAs Anodic MIS

D GaAs/SixOvNzMIS

• InP/SiaMIS

Gate lengths = A^m

Figure 11.5 Noise Figure Versus Frequency for MISFETs (afterMessick)

Tab

le 1

1.6

Impr

orta

nt T

erna

ry a

nd Q

uate

rnar

y C

ompo

und

Cha

ract

eris

tics

CD a

Mat

eria

l

Ga

As

InP

Ga.

47ln

.53A

s

lnP

.8A

s.2

Ga.

27ln

.73P

.4A

s.6

Ga.

5ln.

5As.

96S

b.09

Lo

w F

ield

Mo

bili

ty,

cm

2

v-1s-

1

4500

3815

8875

5283

7041

9377

Pea

k V

eloc

ity10

7cm

s~1

1.86

2.6

2.2

2.8

2.7

2.2

Sat

urat

edV

eloc

ity10

7cm

s"1

1.33

1.84

1.43

1.85

1.77

1.41

Die

lect

ricC

onst

ant

12.9

12.3

13.7

3

12.7

13.2

13.8

Ene

rgy

Gap

eV

1.43

9

1.34

0

0.71

7

1.10

1

0.88

9

0.70

8

Sat

urat

ion

Fie

ldk

Vc

m"1 2.

96

4.82

1.61

3.50

2.51

1.50

6 I 00 CO


higher cut-off frequencies and shorter switching times since it may beshown that the cut-off frequency is given by

where ju is the electron mobility in the channel, Lg is the gate length ais the thickness of the epitaxial layer, Vp is the pinch-off voltage, VM isthe built-in voltage of the gate, Vg is the applied gate bias. W, thedepletion width is given by

\K-vg)H.2

where q is the electronic charge and ND is the donor concentration.

The switching time, r is given by

2

* 1 1 . 3

where VD is the applied drain voltage.

The properties of the materials, detailed in Table 11.6 have been usedto predict the performance of MESFETs fabricated on the materialsusing the one dimensional FET model of Pucel et al (1975). Golio andTrew (1980) have shown, for example, that Ga0.27In0.73P0.4As0.6should have a 58% higher available gain at minimum noise bias at 20GHz than GaAs.

Referring to the basic small signal model of a FET (Figure 11.2) Table11.7 shows the predictions of the Pucel model for a GaAs FET (Golio etal, 1980). Parameters such as Cgs and gm are in good agreement betweenmeasurement and theory indicating that the predicted fr should beaccurate.

The values of Ls, Lg and LD in Figure 11.2 are assumed to be 0.05 nH,0.1 nH and 0.1 nH respectively which are representative of values forchip FETs. The gate resistance, Rg, is expressed as:

3NtgLg


Table 11.7 Comparison of Small Signal Equivalent Circuit ElementValues Predicted and Obtained Experimentally

Parameter

gm (mS)

Cgs(pF)

Cds (pF)

Cd g (pF)

Rds (Q)

Fti(Q)

RT (GHZ)

Model

35.6

0.468

0.08

0.05

3170

3.24

12.1

Measured

33

0.5

0.06

-

660

3.5

11

where

Pg is the gate metal resistivity (Qcm)

Wg is the total gate width (cm)

N is the number of gate fingers

tg is the gate metallization thickness (cm), and

Lg is the gate length (cm)

The source resistance, Rs. is given by:

11.5

where

a is the channel thickness (cm)

p m is the bulk material resistivity (cm)

S is the source length (cm)

LgS is the gate source-to-source spacing (cm)

Re is the specific contact resistance in Qcm2 given by

LgS is the gate-to-source spacing (cm) given by


10011.6

where ND is the doping concentration (cm"3).

The drain resistance, Rd, is expressed by:

B-coth lRm m^gd11.7

where Lgd is the gate-to-drain spacing (in cm). Expressions for the otherelement values and the noise figure predictions come directly fromPuceFs work (1975).

The built-in voltage of the Schottky barrier gate, Vbi, is given by

3 q11.8

where

Eg is the energy gap

k is the Boltzmann's constant (1.38 x 10 Zd J/K)-23

Table 11.8 Pucel Model Predictions for some Ternary andQuaternary Materials when the FETs are Biased for Minimum NoiseFigure

Material

GaAs

InP

Ga.47ln.53As

lnP.8As.2

Ga.27ln.73P.4AS.6

Ga.5ln.5As.9eSb.09

gm, mS

21.4

24.5

24.5

27.8

27.8

24.5

Cgs, pF

0.207

0.186

0.219

0.200

0.207

0.220

Rds

11600

8070

16900

7680

10800

17400

fr,GHz

16.4

20.9

17.9

22.1

21.4

17.7

Fmin at20GHz

dB

1.726

1.924

0.977

1.585

1.236

0.935

Gavat20GHz

dB

2.99

4.00

4.03

4.59

4.75

4.01


GalnPAs

InPAs

lnP,Ga!nAs,GalnAsSb

GaAs

2>'3.0

I8 2.0o

§1.0

GalnPAsGalnAsGalnAsSb

14 16 18 20 22 24 26Frequency, GHz

(a)

14 16 18 20 22 24 26 28 30Frequency, GHz

(b)

Figure 11.6 (a). Predicted Available Gain as a Function ofFrequency (b). Predicted Minimum Noise Figure as a Function ofFrequency (after Golio)

T is the temperature (°K)

Nc is the density of states (m~ )

Vbi is therefore directly related to the technology and the material used.

Using the above information equivalent circuit models for ljum gatelength FETs have been predicted for the various alloys used as the activelayers. Table 11.8 shows the predictions whilst Figure 11.6(a) and (b)show graphically the calculated advantages in terms of available gainand minimum noise figure. The realization of the noise figure predictedfor GaAs itself has not yet been achieved partially due to substrateeffects (Eastman et al, 1979) but noise figures close to 2 dB have beenachieved at 18 GHz for 0.5/an gate length GaAs FETs (Butlin, privatecommunication). What Figures 11.6 (a) and (b) and Table 11.8 do show,however, is that there are substantial benefits to be gained at the higherfrequencies by fabricating MESFET structures on Gao.47Ino.53As or onGao.27lno.73Po.4ASo.6. Interestingly the predicted performance of InPFETs shown in Figure 11.6(a) and (b) is as found in practice-some smallimprovement in gain but a degradation in noise figure over the GaAsdevice.

Gao.47Ino.53As grown lattice matched onto InP has a measured roomtemperature mobility of 11,000 cm2 V"1 s"1 as compared to a value of7000 cm2 V-1 s"1 for GaAs of the same doping level of 1016 cm'3. Figure


101 1015 1016

Net electron concentration ( c m 3 )

Figure 11.7Room Temperature Mobility of In.53Ga.47As (LatticeMatched to InP and GaAs as a Function of Net ElectronConcentration (after Morkoc et al)

11.7 shows the mobility of Ga.047In0.53As over the electron concentrationrange of 1014 to 1017 cm"3 representing data from several laboratories.

The difficulty with fabricating Schottky barrier FETs on Ga.47In.53 As isassociated with the low built-in voltage of the Schottky gate. Fromequation 11.8 and Table 11.6 the built-in potential is calculated to be 0.3

Source Gate

InP

DrainAu overlay

AuGe/Ni/Au

S.I. InP

Figure 11.8 InO.53GaO.47As FETEmploying a n InP Layer underSchottky Barrier Gate (after Morkoc et al)


eV for a carrier concentration of 1 x 1017 cm~3 at room temperature foraluminum gated devices. The equivalent value for GaAs is 0.7 to 0.8 eV.The small potential of Gao.47Ino.53As results in a very thin barrier whichgives rise to electron tunnelling and thus to large leakage currentsbetween gate and source. Methods to reduce this leakage current havebeen proposed including the growth of a very thin (500A typically) layerof Ino.53Gao.47 having a net concentration of 1015 cm~3 between theSchottky barrier and the channel region thus increasing the depletionwidth (from Equation 11.2). The barrier height can also be increased bymaking this thin layer n- InP (Morkoc et al, 1979). Such a FET structureis shown in Figure 11.8 where the n- layer is shown to be etched awaybetween the gate and source and drain areas.

Recently, Itoh (1985) has described work at Cornell University, USA onthe performance of AlInAs/GalnAs modulation doped FETs latticedmatched to InP. The epilayer structure used consisted of an undoped1000 Angstrom AlInAs buffer layer, a 800 Angstrom undoped GalnAslayer containing the two-dimensional electron gas (see Section 7), 100Angstrom undoped AlInAs spacer layer, a 200 Angstrom n+ (2 x 1018

cm"3) AlInAs layer, a 200 Angstrom undoped AlInAs layer and a 150Angstrom undoped GalnAs cap layer, sequentially grown on a semiinsulating InP substrate using molecular beam epitaxy (Figure 11.9).The FETs produced had gate lengths of 1 micron and gate widthsbetween 200 and 280 microns. At 77°K the intrinsic transconductanceof the FETs was 345 mS per millimetre of gate width. This value waswell over twice as high as that reported by Pearsall et al (1983). Betterperformance is expected from such devices with reductions in gatelength and reduced source resistance.

Source Gate Drain A

GalnAs ''*: \ ffijl^ /HZ. 159i-AIInAs _ _ 2 0 °n-AIInAs 200r AlInAs 100GalnAs 2 PEG 800

i-AIInAs 1000

SI. InP

Figure 11.9 AlInAs I GalnAs MODFET


Tungstengrating

nCollector/contact \

Tungstengrating

Base contact

Emitter contact

(a)

Protonbombarded

(SI)GaAs

Collector contact

, Emitter contact \

n* n(b)

Figure 11.10 The Permeable Base Transistor

11.5 Permeable Base transistor

The permeable base transistor consists of a very thin grating embeddedinside a single crystal of gallium arsenide. The grating forms a Schottkybarrier with the GaAs and is used to increase or decrease the potentialwhich occurs in the semiconductor which is between the grating lines.The permeable base transistor (PBT) has the advantages of the FET-inbeing a majority carrier device as well as having the higher current gainproperties of barrier controlled devices.

A drawing of the PBT is shown in Figure 11.10(a) together with afabricated device in Figure 11.10(b). The device consists of four layers,the n+ substrate, the n-type emitter layer, the metal (tungsten) gratingfilm and the n-type collector layer. Electrons flow from the n+ layer tothe emitter where they are constrained by the proton bombarded iso-lated region to flow vertically upwards through the grating to thecollector region. The metal base contact connected to the grating isbrought out to the top surface of the device.

The theory of operation of the PBT can be understood by considering asmall cross-section of the device which includes three fingers of thetungsten grating (Figure ll.ll(a)). The grating is sandwiched inside ann-layer whose carrier level is such that the zero biased depletion widthof the 'base' Schottky barrier is larger than the openings in the grating.The electronic potential as one moves along the line XX' in Figure11. ll(a) will be that of back to back Schottky diodes. As one moves alongthe line Y-Y' through the grating gaps the potential will increase as the


EmitterBase

Collector

(a)

= VCf = 0

•> Diffusion current- Drift current

Ey

(d)

v_

VBE = OE >O Low bias

VBE > O High biasVCE > O Low bias

Figure 11.11 Theory of Peremable Base Transistor

metal grating is approached and go through a maximum in the plane ofthe metal grating as shown in Figure ll.ll(b), where the maximumpotential will be less than the corresponding Schottky barrier height.This barrier height will depend on the carrier concentration, the spacingbetween the grating fingers, the base thickness and the Schottky built-involtage. Applying a small positive bias to the collector of the PBT as inFigure ll.ll(c) results in a small collector current flow because of thebarrier between the gratings. The current can be considered to be dueto drift and diffusion components which are nearly equal when thebarrier is relatively large. If positive bias is now applied between baseand emitter as in Figure ll.ll(d) the drift component of the emittercurrent is reduced and the collector current and transconductanceincrease rapidly. At higher forward bias the barrier will be overcome inthe center of the gaps and current flow will be space charge limited(Figure ll.ll(e)). Because the device uses an extremely fine gratingembedded in a semiconductor of the correct carrier concentration the


high current densities that are present are barrier controlled resultingin large transconductance and maximum frequency of oscillation.

The PBT has been simulated numerically by Alley et al (1979) usingfinite difference methods to solve the simultaneous equations resultingfrom a two-dimensional numerical analysis. If the device is designed sothat the grating gaps are small compared to the zero-biased depletionwidth of the n-type layer, the base metallization thickness is madeapproximately 5% of this depletion width at the largest operatingvoltage, high transconductance and output resistance are achieved.Assuming that the grating fingers have a low resistance leads to a highfr and high f max.

For example, a device with 2000 Angstrom (A) grating gaps, 2000Agrating fingers a 200A thick grating and an n-region carrier concentra-tion of 1 X 1016 cm"3 will have the calculated collector current densityversus collector to emitter voltage characteristic of Figure 11.12.

It is also possible to calculate the current density within the grating gapsas a function of the base to emitter voltage. In this respect there are twodistinct regions. Firstly as VBE is increased from zero the currentincreases exponentially. At larger values of VBE the net negative chargein the middle of the gaps exceeds the positive charge forming a negativespace charge. The current density in the middle of the gaps is thenproportional to VBE3/2. The current density close to the grating still

A/c

m

1%

Cur

rer

8000

7000

6000

5000

4000

3000

2000

1000

Grating gaps = 2000 ANo. = 1016 cm-3

0.2 0.4 0.6 0.8

Collector-emitter voltage (volts)

Base-emitterbias (volts)

^ _ ^ 0 . 5

^ - 0.45

^ 0.4

_ _ - ^0.35

0.30.25

1.0 1.2

Figure 11.12 Permeable Base Transistor Collector Characteristics


Gai

n, d

B2422

20

18

16

14

12

10

8

6

4

2oU1

sN

SS

ss

NS

N

\

No = 10* cm-3 x

Grating width and gap = 2000 kGrating thickness = 200 A

10 100

(Log scale) frequency, GHz

\MAG

. \1000

Figure 11.13 Theoretical Maximum Stable and Available Gains fora Permeable Base Transistor

continues to rise exponentially. The large non-linearity between base-emitter voltage and collector current results in values of transconduc-tance normalized to collector current density of approximately 8 mS A"1

cm2, It is possible to determine the elements of a simple small signalequivalent circuit (neglecting parasitic components)-for example, thebase to emitter resistance being the slope of the IB to VBE curve and thecollector to emitter resistance being the slope of the Ic to VCE curve(Bozler and Alley, 1980).

Results of calculations based on such an equivalent circuit for thegeometry mentioned previously are shown in Figure 11.13.

The calculated value of the unit current gain frequency

is 88 GHz and from Figure 11.13 an fmax of 400 GHz is predicted.

Since the first PBT was reported at the 1979 Cornell Conference (Alleyet al, 1979) much work has been achieved to allow more reproducibledevice performance. Recently, Nichols (1985) has reported the routinemanufacture of PBTs using metal organic chemical vapor deposition(MOCVD) to grow the GaAs layers beneath and above the gratings.


0.9

1 1 ••1 1 aa

0.015pF 4

• ••a

^ 4 3 2

—•

Figure 11.14 EquivalentCircuit of Permeable Base Transistor (MIT,1985)

MOCVD does not leave chlorine as a contaminant in the devices whichpreviously used chloride vapor phase epitaxy. By 'cleaning up' the wholedevice fabrication process transistors have been produced with consis-tent performance over many wafers. An equivalent circuit of a PBTusing Si as the dopant in the active region with a grating periodicity of3200 Angstroms is shown in Figure 11.14. The maximum stable gain ofthese devices at 18 GHz was 18 dB and 14 dB gain has been achievedat 26.5 GHz. An fr of 33 GHz with an fmax of 100 GHz has been obtainedexperimentally.

11.6 Ballistic Electron Transistors

Much theoretical work has been recently done on a new mode ofoperation of FET structures (Eastman et al, 1980; Shur et al, 1979). Thismode of operation depends on the fact that under certain conditions themean free path of carriers in the semiconductor becomes larger than thelength of the active region of the device itself. Thus the velocity of theelectrons can become considerably higher than the peak electron veloc-ity associated with normal 'collision-dominated' GaAs devices. Thiselectron motion is referred to as ^ballistic' since, at least to a first orderapproximation, the electron velocity is due to the acceleration caused bythe applied electric field.

The mobility, for example, of electrons in high purity,GaAs is approxi-mately 150,000 cm2 V-1s~1 at a temperature of 77°K giving a mean freepath of approximately l.S^m. This distance is much larger than state-


of-the-art high microwave frequency FET gate lengths which are lessthan 0.2/mi.

Now, the switching time of a ballistic electron transistor r is

Lr = 11.9

where L is the gate length in the case of a normal FET and veff, theeffective electron velocity is given by

where n0 is the doping density, q is the electronic charge and j is thecurrent density in the channel. The current density is given by

where U is the electric potential between the electrodes and m* is theelectronic effective mass.

The power consumed during the switching time T is given by

P = jUS 11.12

where S is the cross section of the active region. Thus from equations11.9 and 11.11

11.13qU

andi r

The power delay product

r U ' 1 4

T 11.15= qnoULS


Equation 11.15 can be rewritten as

_ 0.1602V• L* Snn

101 11.16

where PT is in femtojoules, u is in volts, L is in microns and n0 is in cm""3.

Now a typical value of U is 0.1 volt, L is l//m and S is ljum2 so that theswitching time and power delay product for GaAs can be estimated fromEquations 11.9 to 11.16 as r = 0.879 picoseconds and Pr s 0.16 femto-joules for n0 = 1015 cm"3. Such figures of merit are considerably betterthan those for conventional GaAs MESFET logic and rival the valuesexpected for Josephson junction logic elements (Hernel, 1974).

The above theory based on the work of Shur and Eastman assumesstrictly that the device is two terminal. However the agreement of thistheory with the Monte Carlo simulations of low doped FETs by Rees etal (1977) is fair.

A simple one dimensional model for the FET can be used to calculatethe current-voltage relationship under the ballistic regime (Shur et al,1979). Consider Figure 11.15 where the region under the gate is dividedinto a depletion region and the channel.

The drain to source voltage Vbs is assumed to be smaller than thedifference VM-VG where VM is the built-in voltage of the Schottky gateand VG is the applied gate voltage. Also VDS is assumed to be less thanthe ideal pinch-off voltage Vpo which is the voltage necessary to fullydeplete the region under the complete gate length L. In this context Upois defined as

Source'///////////A

* L 'IGate |

7////////////////A_•Depleted region ! Ao

Drain

Y//////////A

Figure 11.15 Simple Model to Predict Ballistic Electron TransportProperties of GaAs MESFET


2eoe11.17

This expression may be seen to be analogous to the normal pinch-offvoltage Vpo of a FET, which has already been derived in Chapter 2, andis given by

PO'_qn0A

'^7 11.18

where A is the thickness of the active layer.

In the ballistic case the width Ao of the depletion layer under the gateis independent of the distance along the gate length L as depicted inFigure 11.15 and

11.19

and the current density in the channel is given by

10*

103

o

10* I0.01 0.1 1.0

Voltage, volts

— T = 300*K

-x T = 77°K

Theory

No = 1015cm-3

L = 0.47Mm

Figure 11.16 Measured and Theoretical Electron Current Density asa Function of Applied Bias (after Eastman et al)


11.20

As a result the drain to source current is

where W is the gate width, which yields

This equation may be compared with equation 2.3 of Chapter 2.

Further work has shown that in n+ - n -n + and n+-p-n+ GaAs struc-tures ballistic transport of electrons can occur at room temperature. Forexample, Figure 11.16 shows the measured and calculated current-volt-age characteristics of a 2 terminal n+-p-n+ structure fabricated byEastman et al (1980) where the net acceptor level was 1015 cm"3 and thestructure was 0.47/*m long. There is no current until the applied voltageexceeds the so-called punch-through voltage (which is given by the sameexpression as equation 11.17 but where L is now the diode length).

As soon as punch through occurs the current flow increases sharply.Above approximately 0.5 volt applied voltage the measured currentdensities deviate from the ballistic theory due to the ability of theelectrons to transfer, for example, to valleys in the (111) direction if theywere initially traveling in the (100) direction.

Most of the theoretical assessment to date on ballistic electron transportis related to the exploitation of the resultant devices in high speed logic

Source |

n+-GaAsn+-AlGaAs

72DEG

Gate /

Undoped GaAs

1 Drain

1018cm~3~500J1O18cm~3~5OO/5 . 1 i m?

—jUndopedAIGaAs

Figure 11.17 Schematic of the Structure of a Typical HEMT(TEGFET)


circuits. However, the periodic structure of the permeable base transis-tor dealt with earlier in this Chapter is almost exactly what is neededto induce ballistic transport due to the small grating gaps and geometry.Thus the outcome of successful device fabrication and the charac-terization of these structures will be followed with great interest in thenext few years as it will lead to the application of such devices in higherfrequency and faster speed circuits.

11.7 Heterostructure Transistors

It has already been shown in Section 4 of this chapter that the combi-nation of ternary and quaternary compounds (for example, GaAsxPi-x,AlxGai-xAs, GaxIni-xAsyPi-y) has led to the fabrication of high perform-ance devices. One of these is the heterostructure bipolar transistorwhere the emitter is formed in a wide band gap semiconductor and thisstructure promises maximum frequencies of oscillation of 100 GHz andswitching times of 10 ps (Kroemer, 1982).

In 1978 Dingle realized the first modulation doped superlattice in whichalternate layers of GaAs and AlxGai-xAs are used. Because electronshave a higher affinity for GaAs, free electrons in the AlxGai-xAs layersare transferred to the non-doped GaAs layer where they form a quasitwo-dimensional Fermi gas (Stormer, 1979). The quasi two dimensionalelectron gas (2DEG) accumulating at the heterojunction interface showsextremely high mobility especially at low temperatures. The mobilityenhancement behaviour is interpreted as being due to the separation ofelectrons from their parent donor impurities. Such spatial separationof electrons and impurities is not limited to superlattices as singleheterojunctions also display the same property. The growth of anundoped AlGaAs "spacer layer" between the undoped GaAs and then-doped AlGaAs enhances the electron mobility. The thickness of this"spacer layer" is typically 20 to 100 Angstroms. Figure 11.17 shows across-sectional view of a MBE grown GaAs/AlGaAs heterostructure.The layer structure consists of n+-GaAs (500 Angstroms), n+-AlGaAs(500 Angstroms), AlGaAs spacer (100 Angstroms) on an undoped semi-insulating GaAs substrates. The surface n+ GaAs layer is adopted toimprove the ohmic contacts and to shield the thin n+-AlGaAs layer fromthe effects of surface depletion. The undoped AlGaAs spacer layerseparates the 2DEG from parent-donor impurities as first proposed byDelagebeaudeuf (1982).


10

9

8

°7

t>

I32 2

1

A

\HEMT

GoAs FET ^ * * - ^ _

i i _j

0 100 200 300Temperature (°K)

Figure 11.18 Comparison of Electron Mobility of2DEG and GaAsFET Layers

11.7.1 Room Temperature Properties

At room temperature there are two types of electrons in the heterostruc-tures-low mobility electrons of AlGaAs and high mobility electrons atthe interface Typical Hall mobilities at 300K are between 8000 and 9000cmW.s at carrier concentrations of around 7 X 1011 cm. Hiyamizu et al(1982) have reported 2DEG mobilities as high as 9000 cmW.s which istwice as high as that of conventional GaAs MESFETs. Figure 11.18shows the mobility enhancement of the 2DEG in comparison to a normalGaAs layer.

11.7.2 Low Temperature Properties

Figure 11.19 shows the electron mobility as a function of temperature.As temperature is decreased, electron mobility increases dramaticallyand reaches 121000 cmW s at 77°K due to a reduction in the ionised-impurity scattering effect (Hiyamizu, 1982). Below 77°K further increases in mobility take place with values as high as 2 x 106 cm2 /V.sbeing reported at 5°K. Although these improved mobilities would leadto the belief that the microwave performance of such 2DEG devices will


sec)

r-CU

Mob

ility

2 000000

1000 000

500 000

200000

100000

50000

20000

10000

5 000

1 000

- 0 -

CD—

"o -

I

^0^1984

1982HNA

1981 ^ \° O^cw, Y)

1980 \ 6

1979 ^ ^ * M

1978 ^ ^

VPE-UD J*

1 I I l in ! 1 i i 1 1 m l 1 I I2 5 10 20 50 100 200 240

Temperature (K)

Progress in HEMT layer mobilities as a functionof temperature and time

Figure 11.19 Progress In HEMT Layer Mobilities as a Function ofTemperature and Time

be superior to that of GaAs MESFETs using equivalent gate lengths, itshould be remembered that FET performance does not depend solely onmobility but also on velocity. Recently Drummond et al (1982) haveestimated, by Monte Carlo calculations, that the effective electron veloc-ity of the two dimensional electron gas is only 60 percent higher thanthat in bulk n-doped GaAs at 300°K and only twice as high at 77°K. Thisis because the mobility of the 2DEG becomes field dependent when theelectric field in the FET channel is substantially less than the electricfield required to saturate the drift velocity. Additionally in short-gatelength FETs with gate lengths less than one micron the electron velocityovershoots its steady-state value. Figure 11.20 compares the effectiveelectron velocity of electrons under a sub-micron gate for both GaAsFETs and HEMTs at 70°K and 300°K. The peak electron velocity of theHEMT at 77°K is less than 3 times that of the GaAs FET.


I3uCD•£ 2

Gate (0.6jnm). Channel distance

Figure 11.20 Electron Velocities and Overshoots in FET GaAs andHEMT (TEGFET) AlGaAs Layers at 300 and 77°K

Source

n + -Ga

'-

Gate

AS \hfi~-*

n-AiGaAs

undoped GaAs

S.I. GaAs

Drain

2x1Olflcm"3-6Oo£

~600£

-*-Au

^_2DEG

Figure 11.21 Schematic of the Structure of a E-HEMT withRecessed Gate


T'1.2eV

I

jf//////S/y

Metal

Surfacedepletion

Interfacedepletion

Ionizeddonors

/ ^

1:n-AIGaAs 2--

X2DEG

2 Ey

n-GaAs

Figure 11.22 (a). Energy Band Diagram for D-HEMT (b). EnergyBand Diagram for E-HEMT

Figure 11.19 also shows the progress made in the low temperaturemobility of heterostructures in various laboratories since 1978. Itshould be noted that the best results have been produced in MBE grownlayers which is thought to be due to the lower background impurityconcentration in layers grown using that technique as against thosegrown using MOCVD. It is very interesting to speculate on the upperlimit of 2DEG mobility. One million cm2/V.s was reached in 1982 andover two million cmW.s in 1984.

Depletion mode and enhancement mode HEMTs were first reported byMimura et al (1980,1981). Figure 11.21 shows the cross-sectional view


of a E-HEMT. Again it can be seen that an n+ layer is used to producelow ohmic contacts with the heterostructure and the layer was removedin the gate region to eliminate 2DEG under the gate. Figure 11.22 showsthe energy-band diagram of the D-and E-HEMTs in thermal equilib-rium, i.e. without any applied bias. The n-type AlGaAs layer of theD-HEMT is completely depleted by two mechanisms. Firstly, surfacedepletion results from trapping of free electrons by surface states andsecondly, interface depletion results from the transfer of electrons intothe undoped GaAs. The Fermi level of the gate metal is matched to thepinning point, which is 1.2 eV below the conduction band. With areduced AlGaAs layer thickness the electrons, supplied by donors in theAlGaAs layer, are insufficient to pin the surface Fermi level. Thus, thespace charge region is able to extend into the undoped GaAs layerresulting in band bending in the upwards direction. Hence, the twodimensional electron gas disappears. If a positive voltage, VGS, higherthan some threshold voltage is applied to the gate, electrons will accu-mulate at the interface and a 2DEG is formed, as shown by the dottedlines in Figure 11.22. The transistor so formed is an enhancement modedevice.

11.7.3 Current-Voltage and Capacitance-Voltage Characteristics

It is possible to model the dependence of the Fermi level on the gatevoltage and the finite width of the 2DEG by the use of a charge controlmodel. The I-V characteristics can be produced from a piecewise linearapproximation for the electron velocity which takes into account thedecrease of the low-field mobility discussed previously with the appliedelectric field. This feature of the theory is especially important for theoperation of E-HEMTs at 77°K. Also of importance for both microwaveand high-speed applications of such devices is the calculation of small-signal gate-to-source and gate to-drain capacitances.

Lee et al (1983) have shown that the saturated drain-to-source voltage,VDS, of a 2DEG FET is given by:

VDS=V'G+Vsl-(V'G2+VS]2y+IDS(Rs+RD) 11.22

and the saturated drain current is given by:


hs = 1811-(S2RS

2VS12 11.23

where

'C = VG-VG-VOFF 11.24

and

11.25

V'G is the gate voltage minus the threshold voltage; Rs and RD are thesource and drain resistances; s is the permittivity of AlGaAs;/* is the lowfield mobility of the 2DEG; W is the total gate width of length L; d is the

25 -

20

o Experimental— Theory

I"15

10

5

-0.8 -0.4 0 0.4 0.8Gate-to-source voltage, V55

o Experimental_— Theory

1.0

-0.8 -0.4 0 0.4 0.8Gate-to-source voltage, VQ5

b

1.0

Figure 11.23 Drain Saturation Current Versus Gate-to-SourceVoltage for (a) D-HEMT, (b) E-HEMT


total thickness of AlGaAs beneath the gate and Ad is a correction factorto take into account the effective distance from the 2DEG to the gate.Fs is the critical electric field for velocity saturation.

To test the accuracy of the model Lee et al have fabricated both nor-mally-off and normally-on HEMTs. The gate widths were 145 micronsin both cases with lengths of 1 micron. The heterostructures used tofabricate these FETs were grown by molecular beam epitaxy using a 1micron undoped GaAs layer, a 60 Angstrom undoped AlGaAs layer anda 600 Angstrom n-type AlGaAs layer doped with Si to a level of 1018

cm~3. The 600 Angstrom layer was recessed to 350 Angstroms for theD-HEMTs and to 250 Angstroms for the E-HEMTs. The calculated andexperimental saturated drain currents at room temperature as a func-tion of gate voltage are shown in Figure 11.23(a) and 11.23(b). Themeasured transconductance for the D-HEMT at 300°K was 225 mS permillimetre of gate-width with a source resistance of approximately 10ohms.

The small signal gate-to-source capacitance, CGS, can be calculated bydifferentiating the total charge, QT, beneath the gate in the Shockleyregime with respect to gate-to-source voltage.

QT =W\ qnsdxJo

n - 2 6

— ~ ^ n T7 2 \TVGS ~VG7 \TVGS ~VGD

where

" (d + Ad)

Then

dVGS

VGS(VGS+2VGD) 11-27= 2

~3

Also,


0 0.2 0.4 0.6 0.8 1.0Drain-to-source voltage (Vds/Vs1)

a

-10

0 0.2 0.4 0.6 0.8 1.0Drain-to-source voltage (Vds/Vsi)

b

Figure 11.24 Normalized Gate-to-Source and Gate-to-DrainCapacitances Versus Normalized Drain-to-Source Voltage as aFunction of Normalized Gate-to-Source Voltage

dVtGD

VGD(VGD+2VGS)

(VGS+VGD)2

11.28

Figures 11.24(a) and 11.24(b) show the normalized capacitances, CGS/C0

and CGD/CO as a function of normalized drain-to-source voltage, VDS/VSI

with the normalized gate voltage, VGSVSI as a variable parameter.


Au overlayOJjLim TiPtAu AuGeNiAugate / ^^ contacts

! 5/im |Semi-insulating GaAs

19.50(10.70)

o—VW—Rg

19.50 :(15.20):

0.25p *.r(o.3ip)Tcgs

1.050(2.50)

Values in bracketscorrespond toGaAs MESFET

Figure 11.25 (a). TEGFET Structure (TCSF) (b). EquivalentCircuits of GaAs MESFET and AlGaAs TEGFET

11.7.4 Transistor Characteristics

Considerable work has been achieved to date on the fabrication andcharacterization of HEMTs (TEGFETS) by Thomson-CSF. In 1981,Laviron et al reported a 0.8 micron gate length TEGFET having a noisefigure of 2.3 dB with an associated gain of 10.3 dB at 10 GHz. Morerecently, Linh et al (1983) have reported 0.55 micron gate length TEG-FETs with 1.26 dB noise figures and 12 dB associated gains at the samefrequency.

By using equation 2.73 of Chapter 2, the fitting factor for a GaAlAsTEGFET can be calculated to be as low as 0.15 compared to a value ofaround 0.27 for the GaAs MESFET. The work of Le Brun et al (1983)has resulted in equivalent circuit models for TEGFETs such as theexample shown in Figure 11.25, where a 0.7 micron TEGFET is com-pared with an equivalent gate length MESFET. It can be noted that thevalue of the gate resistance, RG, for the TEGFET is considerably higherthan that for the MESFET. This is not thought to be a consequence of


16 -CD

§12

Noisefigure

'81 *82 '83Year

'84 '85

Figure 11.26 Noise Figure and Associated Gain for HEMT(TEGFET) as a Function of Time at 10 GHz

the technology and hence can be improved. The output resistance, Ro,is much lower for the HEMT than for the MESFET and this feature mayresult from the quality of the undoped material in which the 2DEGoccurs. Since Ro directly affects the maximum available gain from thedevice improvements in materials technology may increase this parame-ter value.

60

I 5 0aa>aE40

tois

e t

o Room temperature (25°C)• Cooled to -45°C

i i

^ ^ - ^ - ^

1 1 1 1 1

\

3.4 3.6 4.2Frequency, GHz

Figure 11.27 Typical Noise Performance of ThermoelectricallyCooled 2DEGLNA


7

"Dg

| 2

0

Theory• Experimental

r \ iw

- v12

10

8 S

4 2

2n

10 20 40 60 100Frequency, GHz

Figure 11.28 Noise Figure and Gain of0.25jum Gate-Length HEMT(TRW transistor)

2 DEGUndoped GaAs

-n+GaAs.n* AIGaAs (1018/cc)

— AIGaAs spacer (20

a HEMT structure

0.3 nH 0.9 |0.01p 30.27p

4.64.8 ds 0.06p

)0.02nH

b Equivalent circuit

Figure 11.29 Cross-Section and Equivalent Circuit of0.25jum GateLength HEMT (Courtesy-G.E.)


Figure 11.26 shows the trend in noise figure and associated gain ex-pected with the HEMT in the near future. This figure relates to theperformance of the device at 300°K. The reported performance of the2DEG device at 120°K is 0.25 dB noise figure with an associated gain of15 dB at 10 GHz.

A number of papers have been published on the application of HEMTsin low-noise amplifiers at frequencies up to 40 GHz. Mochizuki et al(1985), for example, have described low-noise amplifiers employingthermoelectric cooling down to — 45°C. Typical data for amplifiers de-signed for the satellite communications band of 3.7 to 4.2 GHz are shownin Figure 11.27. From measured data the noise temperature at 4 GHzwas 48.7K at room temperature and 36K under cooling. These figuresrepresent the lowest noise temperatures produced with FETs.

At higher frequencies, Sholley et al (1985) have reported HEMT ampli-fiers at 36 to 40 GHz having noise figures of approximately 4 dB withassociated gains of 15 dB. The HEMTs had gate lengths of 0.25 micron.The noise figure and associated gain of the devices are shown in Figure11.28.

Also, recently, Chao et al (1985) have reported the results of 0.25 microngate length HEMTs produced on molecular beam epitaxial layers. Fig-ure 11.29(a) shows the device structure whilst Figure 11.29(b) shows theequivalent circuit of a measured device. Mobilities at 77°K were 50,000cmW-sec with 2DEG concentration of 1012 cm"2. Ohmic contacts hadresistances of 0.1 ohm mm.

DC transconductances were 430 mS/mm (extrinsic) and 580 mS/mm(intrinsic) at 300°K. FTS were 80 GHz by extrapolation from 2 to 18GHz S-parameter measurements. Measured maximum available tunedgains were 15.4 dB at 18 GHz, 11.9 dB at 30 GHz and 5.7 dB at 60 GHz.Room temperature noise figures were 1.2 dB at 18 GHz with an associ-ated gain of 11.6 dB and 1.8 dB at 30 GHz with an associated gain of 7dB. The expected noise figure at 60 GHz was less than 3.5 dB. Toshibahave also recently reported a 0.9 dB noise figure at 18 GHz with anassociated gain of 9 dB. It can be concluded that the main differencebetween 0.25 micron gated MESFETs and HEMTs is that the HEMThas a much higher bias current for lowest noise figure with, therefore,higher gain (4 dB higher at 18 GHz, 3 dB higher at 40 GHz). The HEMTis also an inherently broader band device with quite a broad range ofdrain currents for low-noise figure.

These observations have been reinforced by Derewonko (1985) who hasdescribed work on the application of HEMTs in low-noise amplifier


CDX>

3.5

3.0

£2.5g>X2.0in

o= 1.5

11.0

0.5

0

@ April 1985• (300°K)

TRW(0.2 5ji)

- A1

Rockwell (0.5a)

TRW(0.35LI ) +TRWJ[0.35Li)

"•^GE(0.25ji)•Toshiba

GE (0.25ji)

I . I

10I 1

15 20 30 40 50 60Frequency (GHz)

Figure 11.30 Best Reported Noise Performance ofHEMTs at RoomTemperature

modules. The devices employed were 0.35 micron gate length with 2micron source-drain spacing. Mushroom Ti-Al gates were used to reducegate resistance. Transconductances at room temperature of 300 mS/mmare measured for 62 micron gate width FETs having saturated drain-to-source currents of between 8 and 15 mA. The room temperatureperformances of these devices were noise figures of 1.4 and 2 dB at 17and 25 GHz respectively with corresponding associated gains of 12 and9 dB. When the temperature was reduced to 215°K the noise figure at17 GHz was reduced to 0.8 dB with an associated gain of 13 dB.

Using these devices hybrid prematched amplifiers have been produced,using lumped inductors and capacitors, over the frequency range of 18to 26 GHz, 19 to 20 GHz and 20 to 40 GHz. Gains were 9 ± 1 dB (with2.5 to 2.8 dB noise figure), 11.4 ± 0.5 dB (with 2 to 2.5 dB noise figure)and 5 dB respectively.

Noise resistance for the HEMT is lower than for equivalent gatelength/width MESFETs and decreases quite rapidly with frequencyincrease making the design of the low-noise amplifiers easier than withan equivalent gate length MESFET. Gain and noise figure variationswith temperature, however, are somewhat worse than for a MESFET,the actual figure being dependent on the AlGaAs spacer layer thickness.


| i 2la

ble

a>oEDE8E

n

6

42

0

0.25jjm F E T - A . \

0.1 urn FET-"" \

0.1jum HEMT-^ \

1 10 40Frequency,

\ \ \

100 200 ^00GHz

Figure 11.31 Projected MAGs of Ultrashort Gate-Length MESFETsand HEMTs at 300K

Figure 11.30 is a summary curve of minimum noise figures of HEMTsas at April 1985 as a function of frequency and gate length. Thisindicates that the projected noise figure for HEMTs having 0.25 microngates is 3 dB at 60 GHz.

Smith et al (1985) have reported the output power potential performanceof HEMTs. Power densities of 0.32 watts/mm have been produced at 30GHz for 0.25 micron gate length devices which also had maximum poweradded efficiencies of 26%. The HEMTs had lower gate-to-drain break-

a

o

-o

tion

a

rop

ag

Q_

o•aoa

ow

e

a

pee

d-

120

100

80

60

40

20

o

• • Propagation delay_o—o Speed-power product

r//

— /p/

rf

13.6 pS &<•-*—

) 1 2 3 4VDD (volt)

Figure 11.32 Speed Power Performance of HEMT Ring-Oscillator(Rockwell)


down voltages than equivalent geometry MESFETs and the breakdownexhibited a 'soft' characteristic allowing a reverse leakage current of 1mA/mm gate periphery to flow at approximately 9 volt.

The future for the HEMT appears very promising. In the laboratory fmaxand fr approximately doubled between 1983 and 1985 (Chao, 1983).Continued improvement of the HEMT is expected as there are a numberof promising ideas which have yet to be explored, as well as a numberof basic underlying physical advantages of the HEMT structure, includ-ing higher effective electron velocity. A summary of the expected per-formance from both 0.1 micron MESFET and HEMT transistors isshown in Figure 11.31. It can be seen that it is expected that 0.1 micronHEMTs will ultimately be able to produce maximum available gains ofover 12 dB at 100 GHz compared with 6 dB for the GaAs FET.

11.7.5 High Speed Digital ICs

HEMTs have attracted considerable attention from a number of workerssince 1981 for their application in ultra high speed ICs (Tung et al, 1982;Abe et al, 1982 and Lee et al, 1983). The speeds of HEMT ring oscillatorsdemonstrated by several laboratories have already exceeded the highestspeeds achieved by all the other semiconductor technologies. For exam-ple, Lee et al (1983) have reported a ring oscillator speed of 12.2 pS at aspeed power product of 13.7fJ at room temperature. Figure 11.32 showsthe speed power product of a ring oscillator produced by Rockwell. At aVDD of 1.5 volt the propagation delay is only 13.6 pS and over a VDD range

1000

if)ex.

o100

1 de

l

I 10o

I 1

-

'75

Fin~Fout- 1

o Si MOSFET0 Si BIPOLARo HEMT

^ OGaAs MESFET

l I l'80 '85 *90

Year

Figure 11.33 Ring Oscillator Delay as a Function of Time (afterDiLorenzo)


Table 11.9 Comparison of Ring Oscillator Delays and Powers

Device

HEMT

GaAsMESFET

HEMT

HJBT

Temp.(K)

30077

30077

30077

300

GateLength

(microns)

0.70.7

0.40.4

0.8-1.00.8-1.0

Emitter-1 .2x5

PropagationDelay(PS)

17.39.3

15.09.9

11.38.5

40.0

Power PerGate

(mm/gate)

1.34.5

1.235

2.02.6

6.0

Company

AT&TAT&T

NTTNTT

HoneywellHoneywell

Rockwell

of 1.5 to 4 volts the propagation delay was between 13.6 and 24.2 pS.These speeds are comparable to the best speeds obtainable from Joseph-son junction devices at 4°K! Lee et al have also reported divide-by-fourcircuits using two T-connected D-type flip-flops operated in direct cou-pled-FET-logic. The best result for a 1.4 micron gate length was divisionat 2.6 GHz at room temperature at a VDD of 0.7 volt with a total chippower consumption of 6.7 mW. When the device was cooled down to—70°C the circuit operated up to 3.54 GHz with a power consumptionper gate of only 0.21 mW. Decreasing the gate lengths to 1.1 micronresulted in room temperature frequency division up to 3.48 GHz with apower dissipation of 0.47 mW per gate. This corresponded to a propa-gation delay of 57 pS and a power delay product of 27 fJ. This resultshould be compared directly to the best reported GaAs DCFL frequencydividers employing enhancement mode MESFETs where a propagationdelay of 66 pS and power dissipation of 1.2 mW per gate was reportedby Ohmori et al (1981). These latter circuits used 0.66 micron gatelength FETs.

Recently Di Lorenzo (1985) has published comparative results forHEMTs and other competing technologies. In Figure 11.33 ring oscilla-tor propagation delays as a function of time are shown for selectedtechnologies. Recently both GaAs MESFETs and HEMT ring oscillatorshave demonstrated propagation delays below 10 psec. Table 11.9 listspower dissipation associated with these delays. Room temperature datasuggest HEMT ICs have a slight edge over MESFETs at 300K but at77K HEMT ICs have a factor often lower power consumption compared


20

No>

C Q0> ODCJ

2? 6

#ATT 0.7pm (77k)

#ATTFujitsu 0.5pm •

( 7 7 k ) ATT (0.7pm)ATT» o

GaAs D C F L j ^ o 0 Fujitsu

^• " GaAsDCEL

i l l i

1pm (77k)

H J B T Rock

GaAs

well

BFL

10 20 50 100Total power (mW)

200

Figure 11.34 Performance of HEMT Dividers Compared to OtherTechnologies

to MESFETs at room temperature. No comparative data for MESFETsexists at 77K. Figure 11.34 compares the performance of HEMT fre-quency dividers. Again it is clear that 77K HEMTs are superior in bothspeed and power consumption. However, at room temperature theperformance of GaAs MESFETs is similar to HEMT ICs and the highestfrequency room temperature divider is a GaAlAs heterojunction bipolar

caiEu\

ces:

<

100

10

1

0 1

V^ \\ \ NMOS \

( CMOS V ^ 4 - ^ J

I\

-HEMT(77K)HEMT

0.01

"*—————*7 x^ V Bipolar J

GaAs V \V MESFET N3 r.

1k 3 yy//

projection •sywtffc0.1 1

Power dissipation (W)

Static ram4K NMOS(ATT)

<

) s^%A

#^16k

10

Figure 11.35 Access Time versus Power Dissipation for SRAMs


circuit from Rockwell. The data in Figure 11.34 should be taken asrepresentative of the state-of-the-art at the time of writing. Most of thework on more complex HEMT circuits has been done at Fujitsu (Abe,1985). In Figure 11.35 the access time of HEMT IK and 4K SRAMs arecompared to GaAs MESFET and silicon technologies. It should be notedthat Si bipolar technology is very competitive having achieved approxi-mately 2 nsec access time for a 4K SRAM with 2 to 3 watts of dissipatedpower. Note also the NMOS point at 5 nsec and 2 watt dissipation.Shown also are projected results for HEMT SRAM with 0.5 microngate-lengths and 1.5 micron design rules, which, if achieved, clearlydefine 77K HEMT SRAMs as the circuits for future high speed mainframe computers.

11.8 Traveling Wave FETs

Transmission line structures, as has been demonstrated by the use oftraveling wave tubes in radar sytems, can have very low losses, closecontrol of phasing and uniform properties over wide frequency ranges(Mclver, 1965). The high frequency performance of a MESFET is limitedby the magnitude of its input (gate-to-source) capacitance. A transmis-

Figure 11.36 Photograph of a 3mm Long Traveling Wave Field


sion line can be used to combine a number of FETs in parallel so thatthe limitation in bandwidth due to this capacitance (and the drain-to-source "capacitance) is avoided (see Chapter 5).

Only small dimensions can be used in semiconductor devices to avoidunnecessarily large chip size. Transmission line structures of a fewmillimeters length are commonly used in traveling wave amplifiers andalso in traveling wave FETs (Podgorski et al, 1982). A traveling waveFET developed by Holden and Oxley (1984) is shown in Figure 11.36. Itconsists of a very wide gate FET (2 to 7 mm) structure in which wavespropagate across the width of the device using the source, gate and drainelectrodes (or extensions of them) as microstrip transmission lines. Dueto the active nature of its substrate a large depletion capacitance ispresent under the gate line. In order to keep the waves on the gate anddrain traveling together and, therefore, driving the transistor continu-ously across its width, it is necessary to distribute capacitors along thedrain, which are connected to the earthed source line by overlays.

In comparison, in the traveling wave amplifier approach, the slow waveson the gate are balanced by making the drain transmission line longerthan the gate transmission line between the distinctly separate activeelements. By extending familiar transmission line theory to a numberof coupled lines with a common ground plane it has been found, for thecase of the source, gate and drain lines, that three modes travel in theforward direction and three travel in the reverse direction. If the linesare terminated at the ends, giving boundary conditions, then the totalsolution will be formed from a linear combination of all these modes.That there should be three modes in each direction can be understood

Source o-

Gate o-

Drain o-

Figure 11.37 Equivalent Circuit Diagram of a Differential Elementof Three Coupled Microstrip Lines


Overlaycapacitoron drain line

T-gate

Sourceelectrode

Figure 11.38 Detail of the Traveling Wave FET Construction

by separating the lines widely apart. Under these conditions eachindependent transmission line will carry a single mode in each direction.As the lines are brought together the fields couple and a new set of threenormal modes appear in the conventional way.

11.8.1 Coupled Active Lines

In order to model distributed transistors the active components associ-ated with the gate channel region have to be incorporated. Because thecoupled lines are modeled by equivalent circuits it is possible to incor-porate lumped element models representing a 'per unit length' of theFET into a distributed form of the intrinsic model of the complete FET.In the equivalent circuit of Figure 11.37 the length of the differentialelement is taken as being small in comparison with the wavelengths inquestion.

11.8.2 The Transistor

The traveling-wave FET was designed firstly by H.D. Rees at R.S.R.E.,Malvern, England. The device may be regarded as a 'stretched' FETwith expanded geometry, to allow for source and drain transmission


lines and a T-section gate as shown in Figure 11.36. Figure 11.38 showsthe basic layout of the traveling wave FET (TWF).

All the electrodes are parallel with periodic feeds connecting source anddrain to the active regions near to the gate. The large depletion capaci-tance of the active device has to be compensated and this is done in theTWF by periodically arranging capacitor pads on the drain connected tothe source via an overlay conductor. The spacing of these capacitors issmall compared with the propagation wavelength. Using coupled linetheory it is possible to evaluate the various propagation modes of thestructure. Inspection of the propagation parameters shows that thereis a mode between source and drain that allows the growth of a wave asit travels across the device. That such a growing wave can exist is dueto the active nature of the device, and the fact that the amplified powerwhich appears on the drain electrode is fed back into the lossy gateelectrode via mutual inductance. This inductance is enhanced deliber-ately in the TWF by separating the main source and drain transmissionelectrodes from the intrinsic FET structure around the gate to leave gapsin the metallization where the magnetic field can penetrate. It shouldbe noted that the gate and drain voltages in this mode are virtually inanti-phase so that the mode drives the device continuously as it passesdown the transmission line and so draws power. In both of the otherpossible modes the gate and drain lines are in-phase so that the deviceis not driven and power is simply dissipated in the device and transmis-sion line parasitics.

By making a very wide (in conventional FET terms) TWF and excitingthe growing wave, the voltage on gate and drain will continue to grow

1 0 r

3mm, 0.6jum

7mm

20Frequency. GHz \ 3mm, conventional

Figure 11.39 Theoretical Performance Predictions for the TWFShowing Variation in Gate Length (jum) and Gate Width (mm)


so that gain will increase monotonically with device width and iseventually limited by non-linear effects. In order to achieve optimumperformance the gate and drain have to be well matched and fed inanti-phase. The impedance of the growing wave is approximately 20ohms (to ground on each line). It is difficult to achieve these feedconditions over a wide bandwidth. Any impedance mismatches willreflect the growing wave. The TWF is reciprocal and a growing wavereflected at the far end will continue to grow on its return producingTabry-Perot' type oscillation and possible instability. Such oscillationsare a prominent feature of TWF operation and are the ultimate limit onperformance. Even if perfect matching can be achieved it is necessaryto fabricate gates of 0.7 micron gate length with widths in excess of 10mm in order to obtain useful gain (over 10 dB) over 1 to 20 GHz. Typicaltheoretical predictions for different TWF configurations are shown inFigure 11.39.

TWFs have been fabricated (Oxley et al, 1984) using the same tech-niques for conventional FETs and ICs. A standard etched channeltechnology was adopted to reduce source resistance. As in conventionalFETs this parasitic resistance has an influence on both the gain andnoise performance of the device. Unlike conventional transistors, how-ever, the TWF consists of one gate stripe, up to 10 mm long which resultsin high gate resistance. To overcome this a T gate technology wasadopted whereby the upper 'arm' of the T is some 10 microns widereducing the gate resistance to less than 10 ohm/mm.

11.9 Conclusions

This final chapter has attempted to give the reader a brief introductionto field effect transistor structures using either materials other thanGaAs or different operating principles to improve the performance of orextend the useful frequency range of these three terminal solid statedevices. Technologies such as molecular beam epitaxy and ion implan-tation have already had considerable impact on the formation of newdevices such as the high electron mobility transistor with which veryrespectable performances are now being achieved up to 60 GHz. Thegrowth of ternary and quaternary compounds for FET structures con-tinually improves as lattice matching and growth conditions are morefully understood. The improved material layers will, during the nextfew years, influence the design of new transistors with higher transcon-ductances than present MESFETs. Inevitably, many of the new devicestructures will, through yield difficulties, fall by the wayside but im-proved layer growth and lithographic techniques will allow the improve-


ment of MESFETs and HEMTs to performance levels which wereunimaginable even a few years ago.

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Index

ABCD matrix, 212Absorption stabilization, 361Acceptor levels, 4Active layer, 128Active loads, 476,477Added gate delays, 519Airbridge, 100,533Algorithms, 213Alumina substrate, 421AM noise spectra, 345Amplifier

Balanced, 226Broadband, 203,268Distributed, 238Feedback, 231,487,558Low-frequency, 483MMIC, 547Power, 552Push-pull, 562Reactively-matched, 553Reflection, 277Small-signal, 546Traveling-wave, 238,549,560

Annealing, 145Arsenic trichloride, 135Associated gain, 161Auger analysis, 541Avalanching, 118

BBalanced amplifiers, 226Balanced mixer, 300Ballistic electron transistors, 650Band structure, 1Base, 646Beam leads, 534BFL, 505Binary sealer, 440Bipolar transistor, 58Boltzmann's constant, 2, 39Broadband amplifier, 203, 268Bubbler system

Double, 136Single, 136

Buffer layer, 127,130Built-in voltage, 642Bypass capacitors, 426

CapacitanceFeedback, 38Gate-to-channel, 36Matrix, 522

Capacitance voltage, 660Capacitors, 473

Interdigitated, 473Overlay, 473

Carrier concentr., 128,133,146,532Cascode connection, 65Cavity stabilization, 360Channel capacitance, 86,429Channel current, 28Channel resistance, 30, 87, 429Characteristic impedance, 469Chirp, 392Chloride transport, 135Chromium-doped, 133Clock frequency, 501CML, 606Cofired ceramic, 404Collector, 647Combining techniques, 272Common-Gate, 258Computer-aided design

Frequency input, 214Non-linear, 213

Conduction Band, 2Constant gain circles, 185Contact, 5,10

Rectifying, 8Resistance, 30Schottky, 8

Controlled source, 89Conversion gain, 293, 324Conversion transconductance, 294Coplanar, 478


Correlation factor, 41Coupled active lines, 675Cross-talk, 423Crystals, 1Current generator, 304Current voltage, 660Currents, 11

Hole, 11Cut-off frequency, 35CVD, 127Czochralski growth, 142

DDBS receiver, 600DC analysis, 510DC Parameters, 22DCFL, 506, 606DCFL Gates, 606Deep implant, 162Density

Electron, 20Depletion layer, 17,32Depletion-mode logic, 505Dielectric crossovers, 100Dielectric resonator, 368, 370,569Diffused-gate, 15Diffusion noise, 40Diffusion potential, 11Digital circuits, 497Digital packaging, 423Digital phase shifters, 571Dipole layer, 6Discriminator, 359,446Dislocation free, 608Dislocation free wafers, 143Distributed components, 478Distributed elements, 198Doping density, 20Doppler frequency, 392Drain line attenuations, 244Drain mixer, 300Drain-to-gate, 34Drift velocity, 15,629Dual gate FET, 58,63,435Dual gate mixer, 315Dual-gate GaAs FET switch, 585Dynamic switching energy, 499

EEffective dielectric constants, 481Effective gate length, 23Effective inductance, 469Electron beam lithography, 526Electron drift velocity, 20

Electronic tuning, 377Emitter, 646Energy bands, 1Energy gap, 2Enhancement mode FETs, 144Enhancement-mode logic, 506Epitaxial layers, 127Epoxies, 406Equivalent crcuit, 34,57, 83,162,190, 203,322, 633

Small signal, 36

Fan-in, 503Fan-out, 503Fast Fourier transformation, 216Feedback Amplifiers, 231,558Feedback capacitance, 38Fermi level, 6FET models, 66FET noise sources, 458Fiberoptic, 457Flip-chip, 105,350Float-off, 162FM noise spectra, 345Four-bit phase shifter, 574Fourier transformation, 216Frequency doubler, 323Frequency multiplication, 320Frequency of oscillation, 38

GGaAs, 111

Thermal conductivity, 111Gain, 38

Associated, 161Maximum available, 38

Gain control, 68Gate, 17Gate arrays, 609Gate capacitance, 162Gate mixer, 290Gate propagation delay, 497Gate-priority, 163Gate-to-channel, 36Gate-to-drain

Avalanching, 117Gate-to-Source, 17,34

Resistance (Rs), 28Getsinger's formula, 479Glass-to-metal, 418Grating, 646Gunn domain, 22, 56, 87, 202, 632

Index 685

Gunn effect, 89Gunn oscillator, 333

HHall mobility, 128,153, 656Hard fired ceramic, 404Harmonic balance, 90HEMT, 611

Depletion, 660Digital ICs, 670Divider, 672EC, 664Enhancement mode, 659Low temperature, 656Noise figure, 667Ring oscillators, 671Room temperature, 656

Heterojunction, 12High electron mobility transistor, 611High frequency analysis, 513Hole currents, 11

IC packages, 418Ideality parameter, 25Image rejection, 598Image rejection mixer, 318IMPATT, 333Impedance mapping, 338Impedance receiver, 457Impurity semiconductors, 4Inductors, 466

Ribbon, 466Single-loop, 466Spiral, 466Underpassed connection, 466

Ingot, 143InP, 634Input conductance, 56,202Insertion loss, 69Integrated optoelectronic, 457Interconnection, 545Interdigitated capacitor, 473Intermetallic compounds, 5Intermodulation products, 95Internal matching, 268Intrinsic gate delay, 523Ion implantation, 127

FET processing, 169FETs, 158

Ion implanted FETs, 158Ion milling, 543Ionic crystals, 1

Junction gate FET, 507

Large signal parameters, 265Lattice, 39Level-shifting diodes, 511Lift-off, 162Liquid phase epitaxy, 127Load-line, 256Logic gate, 501Logic swing, 502Low-pass, 268Lumped element, 194, 267Lumped elements, 466

MMatching, 192Matrix

ABCD, 212Techniques, 212

Maximum available gain, 38Maximum channel

Current, 23Opening factor, 23

MBE, 659Memories, 607Mercury probe, 133Mesa process, 530MESFET, 15,21,22Metal alkyl-hydride, 137Microdefects, 143Microstrip line loss, 480Microwave leadless chip carrier, 421Microwave packaging, 418Millimeter-wave, 589Minimum noise figure, 41MISFET, 635Mixers, 586Mixing products, 288MMIC, 569MMICS-Band, 596MMICs in modules, 593Mobility, 16,147,650, 659Modeling, 83Modulation doped superlattice, 655Molecular beam epitaxy, 127,140Monolithic microwave circuit, 466MOSFET, 635Multilayer ceramic carrier, 424Multiplexer, 460, 521Multipliers, 521Multiport packages, 422


Nn-type semiconductors, 3Negative components, 214Negative resistance, 334, 389Network synthesis, 219NMOS, 612Noise, 303,305

AM, 353Figure, 161,250Figure circles, 199FM, 353Minimum figure, 41Single-sideband, 356Spectra, 345

Noise spectral density, 459Non-linear, 88,90NOR, 514NOR gate, 506Normally'on', 505

oOhmic contact, 163Ohmics-priority, 163Optical receiver chip, 460Optimization, 214Optimum reflection coefficient, 189Organometallic chemistry, 127Oscillators

Broadband, 341Common-gate, 569Dielectric resonators, 368,566Free-running, 345Gunn, 333MMIC, 569Noise, 352Output power, 350Pulsed RF, 392Ring, 612Stabilized, 359Steady-state, 340,341Tunable, 341Varactor tuning, 378YIG tuned, 386

Osciplier, 450Out-diffusion, 131Output power, 82

p-type semiconductors, 3Package modeling, 407Packages, 403Parameters

DC, 22

Ideality, 25Paraphase, 562Parasitics, 105,190PECVD, 541Peripheral power density, 348Permeable base transistor, 646Phase shifts, 439

Analog, 576Digital, 571Four-bit, 574

Pinch-off voltage, 22,130, 652Planar diodes, 481Plasma etching, 542Polyimide, 532Power amplifiers, 552Power FET, 261Power supply induced transients, 424Pre-matching, 403Prescalers, 604Propagation delays, 499Pulsed operation, 274Pulsed RF oscillators, 392Punch-through, 384Push-pull, 454, 562

QQ value, 473Quarter wavelength, 433Quarterwave impedance transformers, 267Quaternary compound, 637

RReactively-matched amplifiers, 553Recessed channel, 165Rectifying contact, 8Reflection amplifiers, 277Reflection stabilization, 361Resistance

thermal, 112Resistors, 476,534

Cerment, 536Richardson constant, 26Rieke diagram, 368Ring oscillators, 612Room temperature, 656

sS-Band, 598S-Parameters, 64, 84,177,192, 259, 264,336

One-port, 214SAINT, 509SAINT FET, 164Satellite valleys, 40

Index 687

Saturated drain current, 22Saturation, 350Saturation velocity, 17Schottky barrier diodes, 588Schottky contact, 8,13Schottky gate diode, 27,90,481Schottky junction, 26Schottky-Diode FET logic, 506SDFL, 506Self-alignment gate technology, 162semiconductors, 4,15

Impurity, 4n-type, 3p-type, 3

Short gate length, 21Silicon chip carrier, 424Silicon nitride, 539Single gate FET, 65Small-signal amplifier, 546Smith Chart, 181,337Source admittance, 57,202Source lead inductance, 106Source-to-drain

Burnout, 117Spacer layer, 655SPDT Switch, 583Specific contact resistance, 641Speed-power product, 497Spurious free dynamic range, 271Stability circles, 182, 390Stabilization

Absorption, 361Cavity, 360Reflection, 361Transmission cavity, 361

Static RAMs, 519Switches, 579Switching FET, 571Switching time, 35Synthesis, 219

Transfer characteristics, 130Transfer gain, 459Transformer coupled circuits, 454Transmission cavity stabilization, 361Transmission lines, 479Transmit chip, 603Transmit/receive module, 595Traveling wave amplifier, 238,549, 560Traveling wave FETs, 673Tri-level photoresist, 164Tunable oscillators, 341Two dimensional electron gas , 655

uUndoped substrates, 154Unilateral power gain, 38Up-conversion, 320

Valence band, 2Vapor phase epitaxy, 135Varactor tuning, 378Vector modulation, 445, 578Vias, 103,534VLSI, 615Voltage, 217

Built-in, 25,642,652Capacitance, 660Current, 660Pinch-off, 22,130Punch-through, 654

wWafers, 608Wideband model, 65Wire bond inductances, 191Wire bonded, 102,407

YYIG tuned oscillators, 386

Ternary compound, 637Thermal conductivity of GaAs, 111Thermal impedance, 110Thermal redistribution, 151Thermal resistance, 112Threshold voltage distribution, 610Ti-W silicide, 163Tolerance analysis, 212Total gate delay, 525Transconductance, 28,159Transducer power gain, 184

Microwave Field-effect Transistors Theory- Design and Applications (3rd Edition)

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Transcript of Microwave Field-effect Transistors Theory- Design and Applications (3rd Edition)