The RF Power Behind Design Innovation

Power density in active devices is increasing according to thedemands of transistor users. Appli-cations in commercial wireless,avionics, broadcast, industrial, andmedical systems are pushing theenvelope for solid-state power, withgrowing requirements for higheroutput power levels from fewer out-put-stage devices. At Freescale Semi-conductor, supplying high-perform-ance radio frequency (RF) andmicrowave transistors for theseapplications is only part of the chal-lenge, as the company backs itsdevices with unparalleled capabili-ties in characterization, packaging,and applications engineering.

Freescale Semiconductor enjoys arich heritage in fabricating and sellingboth discrete and integrated RF semi-conductors. Last year, the companyintroduced its seventh generation ofsilicon RF laterally diffused metal-oxide-semiconductor (LDMOS) inthe form of the HV7 process, with theoutput power and linearity perform-ance through 3.8 GHz needed forWiMAX infrastructure applications.They have also announced a high-voltage version of this process, oper-ating at 48 V, for industrial, scientific,and medical (ISM) applications.Freescale has also extended its high-power GaAs PHEMT device perform-

ance to 6 GHz, for WiMAX amplifierapplications.

More recently, the companyannounced the first two-stage radio-frequency integrated circuits (RF ICs)capable of delivering 100 W outputpower. When driven by Freescale’scost-effective MMG3005N general-purpose amplifier (GPA), theMWE6IC9100N and MW7IC18100N RF ICs form a complete 100-Wpower-amplifier solution for wirelessbase stations operating at 900 and1800 MHz.

While the performance levels ofthese discrete and integrated RF pow-er devices are outstanding, puttingthe devices into the hands of theircustomers is only the beginning. Eachshipped device is supported by thecompany’s “service-in-waiting” per-sonnel with diversified expertise intesting, modeling, packaging, andapplications support.

RF Power Characterization Load-pull (LP) measurement tech-

niques have been increasing in popu-

EXTENSIVE EXPERTISE AND EXPERIENCE IN CHARACTERIZATION, MODELING,PACKAGING, AND APPLICATIONS SUPPORT BACKS A LONG-TIME LEADER IN

RF POWER DISCRETE AND INTEGRATED-CIRCUIT (IC) DEVICES.

PAUL HART Manager,World Wide Applications e-mail: Paul.Hart@freescale.com

DAVE ABDO Director of Packaging

e-mail:Dave.Abdo@freescale.com

PETER AAEN Manager, RF Modeling

e-mail:Peter.Aaen@freescale.com

BASIM NOORI Manager,RF Power Characterization

e-mail:Basim.Noori@freescale.com

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LOAD PULL SERVICESLP Enhancements

Modeling• Model generation

• Verification and validation

Applications• New product introduction

• Customer support

Device Technology• Finger selection•• Lot sensitivity

Packaging• Material sensitivity

• Thermal impact evaluation

IC Design• New product introduction

• Die evaluation

Discrete Design• New product introduction

• Die evaluation

1. Freescale Semiconductor’s

load-pull services include meas-

urements, modeling, and appli-

cations support.

MICROWAVE DESIGN

larity in recent years. RF power ampli-fiers are generally characterized usingsuch techniques to determine theparametric values of, for example,peak output power, gain and efficien-cy under various complex load condi-tions presented at the device referenceplane. The use of multiple complexmodulated signals in the same meas-urement environment is also becom-ing increasingly commonplace. For amanufacturer of high power RF semi-conductors, the difficulty in character-izing the products accurately is com-pounded by the fact that the devicedevelopment must be carried out onlarge periphery devices, typically 60mm, presenting terminal impedancesin the sub-0.5-Ω region and with qual-ity factors (Qs) in the range of 8 to 10.

For the past several years, the RFdivision of Freescale has developedseveral accuracy-enhancementmethodologies and a multitude ofautomated custom measurement tech-niques. The division has well equippedhigh reflection (high gamma) load-pulllabs capable of covering frequenciesfrom 250 MHz to 8 GHz and powerlevels as high as 100 W CW (500 Wpulsed) which service the company’sGaAs, GaN and LDMOS device,modeling, applications, and other

functional groups (Fig. 1). Freescale’ssystems are capable of performingadvanced measurements on deviceswith impedances of 0.5 Ω and less. Toenable such advancements, the com-pany has developed a series of special-ized test fixtures with optimum imped-ance transformation ratiostransitioning a 50-Ω system character-istic impedance to the low impedancesrequired for load-pull measurementsof high power transistors.

In addition to the fixture-based sys-tems, Freescale also uses on-waferload-pull systems based on commercialwafer-probe equipment which is usedmainly for device research and devel-opment, as well as modeling. The on-wafer load-pull system features aunique three dimensional anti-vibra-tion mechanism to minimize the effectsof tuner vibration, thereby minimizingprobe-to-wafer contact damage.

The accuracy of the Freescale Semi-conductor load-pull systems typicallyshows transducer gain differential,Gt, of less than 0.25 dB at maxi-mum gamma (0.93 to 0.95 or theedge of the Smith Chart) and less than0.1 dB inside the measurementregion.1 This level of accuracy is inpart achieved by the use of precision7-mm coaxial connectors at all meas-

urement reference planes. These con-nectors exhibit typical VSWR of lessthan 1.008:1 at 2 GHz. The centercontact resistance of less than 0.1 mΩand excellent calibration characteris-tics, with unit-to-unit impedancevariation of less than 0.1 percent andphase variation of less than 0.21 deg.at 18 GHz also contribute to excel-lent measurement accuracy.

A thru-reflect-line (TRL) calibra-tion is used with the vector networkanalyzer (VNA) in conjunction withthe load-pull test system to achievesource match of better than 45 dB.2 Incontrast to other VNA calibrationapproaches, such as the short-open-load-thru (SOLT) method, a TRL cali-bration is not burdened by the para-sitic circuit elements (inherentadditional capacitances and induc-tances) of the calibration load stan-dard at high frequencies.

Typically, 5000 to 6000 impedancepoints are characterized for each tunerto ensure a uniform distribution acrossthe source and load impedance planes.A high density of points is requiredwhen evaluating large peripheryunmatched devices, which are verysensitive to minimal impedancechanges owing to their low terminalimpedances. Such a high density maynot be required in the assessment ofthe relatively high impedance produc-tion parts containing package match-

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Typical scalar load-pull system set-up

CW randomtwo-tonemultitone

Scalar reflectioncoefficient and Gt

Large signal input imedance

AM-AMAM-PM

ACP andharmonics

CCDFEVMACPIQ

7 mm

Power delivered to the load

Pavs

Pref VNA

R A B

25-100 W

Spectrumanalyzer

VSA

sourcetuner

Loadtuner

Pdel

High-power load Drain and gate

bias supply networkSource string Load string

7 mm 7 mm

Impedance location of pulsed, modulated, and CW signals

Frequency 2.140 to 2.140 GHz

CWM

od_S

igna

lPu

lse_3

dB

CWIS95

Pulsed

2. A typical load-pull measurement setup at Freescale includes programmable power supplies, vector network

analyzer (VNA), vector signal analyzer (VSA), and supporting hardware3. © 2006 IEEE. Reprinted with permission.

3. This plot shows the optimum load impedance

locations on the Smith Chart for CW, IS-95, and

pulsed modulation formats3. © 2006 IEEE. Reprinted

with permission.

ing elements. In this case, asparse load-pull evaluationmay be conducted.

A typical load-pull setup isshown in Fig. 2. Load-pullsystems at Freescale are usedto evaluate a device’s peakpulse power compression,AM-to-AM conversion, AM-to-PM conversion, frequencyresponse and large-signaldevice input impedance. Thesystems can also be used formeasurements of complex sig-nals to ascertain the averageand peak power, adjacent-channel power (ACP), fortwo-tone and multi-tone test-ing of intermodulation distor-tion (IMD), and to assess thedevice behavior under differ-ent loading conditions withEDGE signals. Freescale also conductscomplementary-cumulative-density-function (CCDF) analysis of devicesignal power. The CCDF testing iscommon to second-generation (2G)and third-generation (3G) wirelessmeasurements. The requirement toperform measurements of CW,pulsed, and modulated signals comesfrom the fact that these signals exertdifferent thermal loading on thedevice and, consequently, the opti-mum load impedance for each modu-lation format is also different, asshown in Fig. 3.3 In addition to thisextensive measurement capa-bility, Freescale has developedvaluable data import and postprocessing tools to enable theuser to analyze rapidly thebehavior of the device undertest (DUT) in two-dimensionalor three-dimensional planes(Fig. 4).

A pulsed VNA load-pulltechnique is used for measur-ing a wide range of Freescale’spower transistors, includingthe 170-W WCDMA deviceMRF7S21170H. The load-pull power contours for thedevice show a pulsed output

power at 1-dB compression of betterthan +53 dBm (200 W) and gain of19.94 dB at 2.14 GHz (Fig. 5). Armedwith this knowledge, the final match-ing network design of theMRF7S21170H becomes a straight-forward exercise: a choice in load andsource impedances is made in order tooptimize power density, gain, efficien-cy, and a synthesizable matching net-work simultaneously.

Modeling Power DevicesThe design of RF power amplifiers

(PAs) for modern communications and

broadcast systems, industrial,scientific, and medical applica-tions, and the avionics andradar markets is a significantchallenge. Designers arerequired to meet goals forimproved energy efficiencyfrom the RF PA, while simulta-neously meeting stringent reg-ulatory requirements (e.g., forlinearity), and demands forlower-cost amplifiers.

Traditional amplifierdesigns based on the Class ABmode of operation are beingsupplanted by designapproaches to achieve higherefficiency, using architecturessuch as Doherty and EnvelopeTracking, and perhaps bymore inherently nonlinearmodes of operation, such as

amplifiers with Class D, E, F, and oth-er operating modes. These conflictingdemands for higher efficiency, higherlinearity, and lower cost mean that thedesigner is faced with making a multi-dimensional compromise. This is anextremely difficult task to accomplishusing empirically based or “cut-and-try” approaches. The designer mustturn to computer-aided-design (CAD)techniques and circuit simulation tooptimize the design. This increaseduse of CAD methods for RF power-amplifier design places a greaterreliance on the availability of accurate

transistor models for simula-tion. More and more compa-nies are relying on CADmethodologies to reducetime-to-market dramatically,and to increase the robustnessof the design in the face ofprocess and manufacturingvariations. For semiconduc-tor vendors, the ability toprovide accurate, nonlinear,electro-thermal models in atimely fashion has become animportant differentiatorbetween alternate suppliers.

Power-amplifier designerschoosing from among

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4. This three-dimensional plot shows the PAE performance of a device under

Class AB operating conditions (in blue) versus under Class F operating condi-

tions (in red).

5. These swept load-pull power contours were made for a 170-W WCDMA

device MRF7S21170H. The results show pulsed output power at 1-dB com-

pression of better than +53 dBm (200 W) and gain of 19.94 dB at 2.14 GHz.

MICROWAVE DESIGN

Freescale’s extensive lineup of high-power RF transistors are supportedby the comprehensive experience ofFreescale’s RF Modeling team, and animpressive selection of nonlinear elec-tro-thermal transistor models. Themodels, which are available onlinefrom the company’s RF High PowerModel Library atwww.freescale.com/rf/models supporta wide range of CAD software tools.For maximum flexibility, Freescaleworks with a large number of soft-ware suppliers (known as “ModelPartners”) to ensure the portability oftheir device models with popularCAD tools. Supported CAD toolsinclude Agilent EEsof’s ADS™,Microwave Office™ from AdvancedWave Research (AWR), AnalogDesign Tools™ from APLAC (now anAWR company), Ansoft Designer™from Ansoft, and Genesys™ fromEagleware-Elanix tools (now part ofAgilent Technologies).

A typical discrete RF transistorwith in-package matching networks isillustrated in Fig. 6. The matchingnetworks are included to improve theease-of-use of the product, and its per-formance, by transforming the lowinput and output impedances of thetransistor die to more practical levels.These matching networks are con-

structed with small diameter bondingwires and metal–oxide–semiconduc-tor (MOS) capacitors; in the largestRF/microwave power transistorsthere are between 100 to 200 bond-wires and several MOS capacitors alldensely packed into the package cavi-ty. For high-power RF IC products,the matching networks are construct-ed using on-chip spiral inductors,capacitors, and transmission lines.

The matching networks introducevery high-Q resonances that providethe necessary impedance transforma-tion. Slight changes to the bond-wirearrays can result in frequency shifts ofthese resonances that may adverselyalter the characteristics of the match-ing network. In many applications,bond-wires are considered to be para-sitic elements as they only serve as ameans to provide a conductive inter-connection between the leads of thepackage and the semiconductordevices contained within it. However,within RF power transistors they arenot parasitic elements, they are anintegral part of the design and theymust be modeled accurately.

High-power RF and microwavesemiconductor transistors are gener-ally enclosed in air-cavity or over-molded plastic packages. Thesepackages protect the internal circuit-ry from the external environment,and they aid in the removal of heatgenerated in the active area of thetransistor. In addition, these pack-ages also serve as components of thelow-loss matching network. Transis-tors used for wireless infrastructureapplications generate some of thelargest heat fluxes amongst all semi-conductor devices and it is importantthat the effects of this self-heating areincorporated into the nonlinear tran-sistor model.

The development of nonlinear elec-tro-thermal models for these pack-aged transistors taxes the most sophis-ticated measurement and simulationtechniques available.4 The number ofissues that must be addressed in a suc-cessful realization of a model include

RF Design Innovation

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A Supplement to Microwaves & RF/May 2007 Sponsored by Freescale Semiconductor

G1 G2

G1 G2

G1 G2

G3

G3

G3

Package gate side

Package drain side

MOS1

MOS1

MOS1

Integratedcapacitor

Lm1

Lm1

Lm1

Lm2

Lm2

Lm2

Shunt-L

Shunt-L

Shunt-L

Extrinsic shell Thermalsub-network

Source Extrinsic network

Gateextrinsicnetwork

Drain manifold/Bond-pad

Intrinsic model

Gate manifold/Bond-pad

DrainExtrinsic network

PdissRth th

Qg dIg I

7. An illustration of the

segmented approach to

model development, in

which a packaged tran-

sistor is considered as a

system that can be bro-

ken down into smaller

components.

Ceramic

E

6. A view of a high-power LDMOS transistor, with

the lid removed to show the complexity of the

internal matching networks and the LDMOS die.2

© 2006 IEEE. Reprinted with permission.

the electromagnetic (EM)interactions between the ele-ments of the matching net-works, and between the bond-wire arrays in the package;thermal management; the self-consistent integration of thethermal model with the electri-cal model of the device; andthe construction of the nonlin-ear model of the transistoritself.

Freescale has adopted a seg-mented approach to modeldevelopment,5, 6 in which apackaged transistor is consid-ered as a system that can bebroken down into smallercomponents, as shown in Fig.7. Each of the components ismodeled separately, and thenthe separate model contribu-tions are integrated into a single mod-el representing the packaged device.This approach eases the computation-al load and reduces the complexity ofthe modeling task, and features char-acterization of inter-component cou-pling, which is included in the finalmodel for improved accuracy.

At the heart of the packaged tran-sistor model is the nonlinear model ofthe intrinsic transistor. This is extract-ed from bias-dependent S-parametermeasurements that are made underpulsed conditions to create an isother-mal environment. Sophisticated de-embedding techniques are used todescribe and remove the manifold andextrinsic components, enabling thenonlinear model to be extracted.Freescale uses both the Root modeland the MET (‘Motorola Electro-Thermal’) model for the nonlinearmodel description.6 The thermal com-ponent for the MET model is deter-mined from measurements made overa range of die temperatures, and it iscoupled self-consistently with thenonlinear electrical model. The METmodel is the de facto standard nonlin-ear model for RF power transistors inthe common CAD tools.

The models for the passive compo-

nents in the in-package matching net-works are determined from linear S-parameter measurements and electro-magnetic simulations.5 The thermal

model for the package andheatsink is found from meas-urements using high precisioninfrared (IR) microscopymeasurements,7 in which thetemperature of the transistordie can be determined whileunder RF drive.

After a model has been gen-erated, the final process of val-idating the model begins, bycomparing the model predic-tions against an independentset of measurements that havenot been used in the modelgeneration. Freescale hasdeveloped a proven methodfor validating its large-signalmodels, based on its load-pullmeasurement capabilities.Essentially, CAD tools areused to simulate the environ-

ment seen by a high-power device dur-ing load-pull testing. Measured load-pull S-parameter data for a DUT atfundamental and harmonic frequen-

MICROWAVE DESIGN

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60

40

25

15

2020

35 40 45

50

45

35

40–40

–60

–80

–20

3015 101 10220 25

50 35 40 45 500

MeasuredModel

MeasuredModel

MeasuredModel

MeasuredModel

(a) (b)

(c) (d)

Outp

ut p

ower

—rrdB

m

Input power—rr dBm

Input power—r dBm

IMD3

—dB

c

Output power PEP—W

PAE—

perc

enta

ge

Output power—rr dBm

Tran

sduc

er g

ain—

dB

9. Measurement and simulations at 865 MHz of output power (a), IM3 (b), PAE (c), and Gt (d) when the source

is matched and the impedance presented to the load is set of maximum PAE. © 2007 Cambridge University

Press. Reprinted with permission.

Imag

inar

y pa

rt o

f im

peda

nce—

Ω

2.5

1.5

0.5

–0.5

–1.0

–2.0

–2.5

–1.5

2.0

1.0

0

0 0.5 1.0 2.0 3.0 4.0 5.01.5 2.5 3.5 4.5—Ω

MeasuredModel

8. Power-added efficiency contours of the power transistor under single-tone

pulsed excitation at 865 MHz. © 2007 Cambridge University Press. Reprinted

with permission.

MICROWAVE DESIGN

cies are synchronized to present loadimpedances during a nonlinear har-monic balance simulation. The coordi-nation of measurement and modelingcapabilities helps optimize the modelto match the measured results.

An example of the model validationis shown in Figs. 8 and 9 for a siliconLDMOS transistor similar to that inFig. 6.4 This device has been designedfor N-CDMA, GSM, and GSM-EDGE base-station applications in the860- and 960-MHz bands, and in atypical GSM application with 28 Vsupply and a quiescent drain current of1200 mA, this transistor is capable ofdelivering 160 W CW power at 1 dBcompression. The transistor comprisesthree active die, with a total gateperiphery of about 270 mm. An inputmatching network is included in thepackage: this is a T-network using 78bond-wires and MOS capacitors.Models of the constituent componentsare derived as described earlier, and acomplete model is then constructedfrom these parts. The validation con-sists of large-signal one- and two-tonesimulations, performed under pulsedconditions to provide an isothermalenvironment. Load-pull measure-ments using the same thermal condi-tions and input and output loads areperformed, and compared against thesimulations. Measurements and simu-lations of the output power, third-order intermodulation distortion(IM3), power-added efficiency (PAE),and transducer gain are shown in Figs.8 and 9. These power sweep or drive-up measurements were performed

with the packaged transistor tuned atthe output for maximum power-addedefficiency, and maximum output pow-er, respectively. The measured and sim-ulated results are in good agreementover range of the test conditions.

Packed In PlasticHigh-power RF and microwave

semiconductor transistors are general-ly enclosed within over-molded plastic(OMP) or air-cavity packages. Tran-sistors used for high-power RF andmicrowave applications dissipate sub-stantial amounts of power and conse-quently operate at high junction tem-peratures. During the design of apackage, stringent thermal-mechani-cal design practices are followed toensure that the package can dissipatethe substantial heat-flux generated bythe transistor while not degrading itselectrical performance. In addition,the package must be rugged and havehigh mechanical strength to operatereliably within, for example, cellularbase stations and broadcast systems.

Photographs of typical air-cavityand OMP packages are shown in Fig.10. The internal components of thetransistor within the plastic packageare over-molded with a low-loss plas-tic material. The majority of highpower transistor packages generallyhave two or four leads, although newmulti-stage high power RF ICs thatincorporate higher functionality havemore leads. The packages aredesigned for the leads to rest on top ofthe microstrip transmission lines on aprinted-circuit board (PCB). The

back side of the flange contacts theheatsink of the power amplifier form-ing a conductive electrical connectionto the bottom conductor of themicrostrip and a conductive thermalconnection to the heatsink, whichenables heat to flow away from thepackaged transistor.

The air-cavity package is the mostexpensive component of an assembledpower transistor, attributable to thematerials used in its construction.Since the power transistor is one ofthe most expensive components in aRF power amplifier, these air-cavitypackages are often a target for costreduction through design and materi-al developments.

Over the past six years, Freescalehas systematically re-engineered air-cavity package designs with newmaterials to improve performanceand decrease the package cost. In2004, Freescale made a change to theheatsink materials in their packages,resulting in 15-to-35-percentimprovement in thermal performance.With this improvement, the industryquickly adopted this improved pack-age design.8

Freescale has driven further costreductions in the package with theinnovative development of plastic-packaging techniques for high-powerRF transistors. Using an OMP pack-age solution, Freescale is able to offerRF transistors with power levels ofover 130 W at 2.1 GHz, with per-formance rivaling that of a metal-ceramic air-cavity product. To date,over 30 million RF power transistorshave been delivered in over-moldedpackages. Further, Freescale offersmore than a dozen different packageoutlines and lead configurations in theOMP package technology, enabling avariety of power RF IC products.

These OMP transistors are fullycompatible with traditional high-power RF applications. The funda-mental design of the package, itsmaterials, and the manufacturingprocess derive from Freescale’s legacyof innovations in high-power automo-

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10. Several example photographs of air-cavity and over-molded plastic packages are shown on the left and

right halves of the figure.

tive and industrial packages designedfor the most demanding environmen-tal conditions. These are packagesdesigned to achieve mean timebetween failures (MTBF) in excess of1900 years. The OMP housings fea-ture tighter mechanical toleranceswith significant tolerance improve-ments (as much as 50 percent) overtraditional air-cavity packages. Thetight dimensional tolerances andexcellent moisture-sensitivity-level(MSL) rating make these packagesideally suited for automated PCBmanufacturing at the amplifier sub-assembly level.

As with the air-cavity housings, theOMP packages can operate reliably atdevice junction temperatures above+200ºC. An integrated copper heatsink provides excellent thermal resist-ance and heat dissipation, and thepackages support lead-free (RoHS)interconnect processing, with an MSLrating of 3 or better in a +260ºCreflow solder process. For those con-cerned with standards com-pliance, the OMP packagesare registered with JEDEC.

Freescale evaluates theperformance of its differentpackage types in a speciallyconfigured thermal-analysislab. The thermal perform-ance of a packaged transistoris a major factor in the system-levelcooling required for a complete wire-less base transceiver station (BTS). Theability of the package to dissipate heatis determined by its thermal resist-ance—the temperature differencebetween two points due to the powerthat is being dissipated.

To obtain the thermal resistance ofa packaged transistor, Freescale hasdeveloped a rigorous methodology,9

using an infrared (IR) microscopy isused to measure the temperature onthe transistor die while it is operatingunder realistic termination imped-ances and signal excitation. With thismicroscope, the temperature distribu-tion across the die can be viewed as afunction of power level, bias level,

matching condition, frequency, andeven by the selected modulationscheme, such as WCDMA or IS–95. Aphotograph of an IR image of a tran-sistor dissipating 60 W power isshown in Fig. 11.

Using IR microscopy, the maximumdie surface temperature in the meas-urement field can be located. Duringthe thermal measurements the tem-perature at the bottom of the pack-aged transistor can be determined andeasily monitored by a thermocouplelocated directly beneath the transis-tor’s active cell, or heat-generatingarea, as illustrated in Fig. 12. A hole isdrilled in the ceramic lid of the transis-tor, or the lid is removed to allow anunimpeded view of the surface of thedie. For OMP packages, the moldcompound can be etched away untilthe surface of the die is exposed.

Applications EngineeringFreescale’s four-tiered support

structure for its high-power RF

devices includes inventive and experi-enced applications engineers whoassist customers with circuit designand troubleshooting for a wide rangeof requirements in commercial indus-trial, medical, avionics, broadcast,and cellular infrastructure applica-tions. This role has become a necessityas the system-level complexity ofmodern RF power amplifiers hasincreased while the typical designcycle times have decreased dramati-cally. Freescale’s RF applications teamfocuses closely on these complexitiesand how devices are used in customerapplications to facilitate a rapid andseamless integration of Freescale’stransistors into customer designs.

To facilitate faster customer designcycles, Freescale’s applications teamhas recently begun developing demon-stration circuits of optimized RFdevice line-ups for specific, high-vol-ume applications, such as GSM,CDMA, WCDMA, TD-SCDMA, andWiMAX. These system-level circuitsare designed to demonstrate the per-formance of the entire RF line-upusing realistic space constraints, com-mon and economical RF components,and typical assembly procedures suchas solder reflow, surface-mount, ordevice-clamping methods. Additional-ly, circuit-level efficiency and linearityenhancement techniques such asDoherty-combining and analog pre-distortion (APD) approaches areincorporated when possible for cus-tomers to understand the benefits ofdifferent design methods. The goal isto create RF line-up demonstrators for

MICROWAVE DESIGN

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11. Thermal imaging of an RF tran-

sistor dissipating 60 W is illustrated.

Temperature variation across the die

is indicated by changing colors. ©

2007 Cambridge University Press.

Reprinted with permission.

13. This GSM demonstration circuit features the

model MMG3005 GPA driving the MW71C18100N

high-power RF IC.

Plastic clamp

Transistor

HeatsinkThermocouple

Ceramic lid

12. An illustration of the test-fixture used to deter-

mine the thermal resistance of a packaged transis-

tor. The opening in the clamp and ceramic lid allow

the IR microscope to have an unimpeded view of

the die. The thermocouple is machined into the

heatsink and positioned to be beneath the active

device heat-generation area. © 2007 Cambridge

University Press. Reprinted with permission.

MICROWAVE DESIGN

common applications that can be easi-ly incorporated into customer systems.

One example of a line-up demon-stration circuit is shown in Fig. 13.This circuit was created to demon-strate a complete 1800-MHz GSMlineup consisting of the MMG3005GPA driving the MW7IC18100Nhigh-power RF IC. The MMG3005 isa Class A biased InGaP HBT with +30dBm-rated output power at 1 dB com-pression. The MW7IC18100N is anHV7 LDMOS two-stage RF IC with100 W (+50 dBm) rated output powerat 1 dB compression. Together, thesetwo devices create a high-performance1800 MHz GSM line-up with nearly50 dB of gain, 37 percent line-up effi-ciency, and 1.5 percent EVM perform-ance at +46 dBm output power, asshown in Figs. 14 and 15. The low-cost plastic packaging, compact circuitlayout, and minimal use of RF compo-nents make this applications line-up anideal solution for the cost-sensitiveGSM market.

Figure 16 shows the typical per-formance of an RF line-up demon-stration circuit that was created forthe emerging TD-SCDMA market inThe People’s Republic of China. Thiscircuit consists of the MW6IC2215NRF IC driving the MRF6S21100Hdiscrete transistor. The MW6

IC2215N is an HV6 LDMOS two-stage RF IC and the MRF6S21100His an HV6 LDMOS discrete ceramictransistor. These devices have ratedoutput power at 1 dB compression of15 W and 100 W, respectively. Whileneither of these devices was targetedspecifically for the TD-SCDMA mar-ket, when evaluated together theydemonstrate excellent six-carrierTD-SCDMA performance. At +38dBm output power, the line-up gainis 43 dB, the uncorrected adjacentchannel power is –51.4 dBc, and theuncorrected alternate-channel poweris –52.3 dBc. These performance lev-els are achieved with an industry-leading line-up efficiency of nearly15 percent.

In addition to line-up demonstra-tion circuits, circuit-design assistance,and system troubleshooting,Freescale’s applications engineeringgroup works closely with the model-ing and measurement teams to fullycharacterize the large-signal behaviorof Freescale’s RF power products.With these four groups in RF charac-terization, modeling, packaging andapplications engineering, Freescale ismuch more than a device supplier—it’s a company that offers a compre-hensive set of tools to aid in the suc-cess of its customers.

REFERENCES1. J. Sevic, “Basic Verification of Power Load-pull Systems,” Maury Microwave Corp.,Ontario, CA, Application Note 5C-055.2. G.F. Engen and C. Hoer, “Thru-Reflect-Line:An improved Technique for Calibrating the DualSix-Port Automatic Network Analyzer,” IEEETransactions on Microwave Theory & Tech-niques, Vol. MTT-27, No. 12, December 1979.3. Noori et al., “Load-Pull Measurements UsingModulated Signals,” 36th European MicrowaveConference, 2006. 4. P.H. Aaen, J.A. Pla, and J. Wood, Modelingand Characterization of RF and MicrowavePower FETs, Cambridge University Press: UK,2007. 5. P.H. Aaen, J.A. Pla, and C.A. Balanis, “Model-ing techniques suitable for CAD-based design ofinternal matching networks of high-powerRF/microwave transistors,” IEEE Trans.Microwave Theory and Tech., Vol. 54 (7), pp.3052-3059, July 2006.6. W.R. Curtice, J.A. Pla, D. Bridges, T. Liang,and E.E. Shumate, “A new dynamic electro-ther-mal nonlinear model for silicon RF LDMOSFETs”, in IEEE International Microwave Sym-posium Digest, Anaheim, CA, pp 419-422, June1999.7. M. Mahalingam and E. Mares, Thermal Mea-surement Methodology of RF Power Amplifiers,Freescale Semiconductor, Inc., 2004.www.freescale.com/files/rfif/doc/appnote/AN1955.pdf8. M. Mahalingam, M. McCloskey, V.Viswanathan, “Low Rth Device Packaging forHigh Power RF LDMOS Transistors for Cellularand 3G Base Station Use,” in Microwave Prod-uct Digest, p. 18, May 2003.9. M. Mahalingam and E. Mares, “Infrared Tem-perature Characterization of High Power RFDevices,” Proceedings of IEEE MTT-S Interna-tional Microwave Symposium, May 2001.

www.freescale.com/rfpower

RF Design Innovation

WHITEpaper

A Supplement to Microwaves & RF/May 2007 Sponsored by Freescale Semiconductor

(Demo-Fixture) MMG3005N driving MW71C 18100NGSM-Edge 5 V/500 mA 28 V/215 mA 28 V/800 mA

–40

–9028 30 32 34 36 38 40 42 44 46 48 50

Pout—dBm

4

–6

1805 MHz1840 MHz1880 MHz

–45

–50

–55

–60

–65

–70

–75

–80

–85

3

2

1

0

–1

–2

–3

–4

–5

600 kHz

EVM

400 kHz

(Demo Fixture) MW61C2215N Driving MRF6S21100H6-Carrier TD-SCDMA 2017.5 MHz 28 V/95 mA 28 V/170 mA 28 V/600 mA

50

028 29 30 31 32 33 34 35 36 37 38 39 40

–60

–55

–50

–45

–40

45

40

35

30

25

20

15

10

5

—dBm

Gain

S-R Alt 1R

S-R Alt 2

PAE

Gain (dB)PAE (%)

Alt 1_L (dBc)Alt1_U (dBc)

Alt2_L (dBc)Alt2_U (dBc)

15. These curves plot the measured spectral

regrowth and EVM performance of the GSM dem-

onstration board.

(Demo-Fixture) MMG3005N driving MW71C 18100NGSM-Edge 5 V/500 mA 28 V/215 mA 28 V/800 mA

50

028 30 32 34 36 38 40 42 44 46 48 50

Pout—dBm

20

–30

45

40

35

30

25

20

15

10

5

15

10

5

0

–5

–10

–15

–20

–25

Gain

P.A.E.A

IRL

1805 MHz1840 MHz1880 MHz

14. These curves show the performance of the GSM

demonstration board at 1805, 1840, and 1880

MHz.

16. Although the individual parts were not origi-

nally designed for TD-SCDMA performance, they

combine for this demonstrator circuit to provide

this gain, efficiency, and spectral-regrowth

performance.