Microwave Application Laboratory · Microwave Application Laboratory Transmission Line Theory...
Transcript of Microwave Application Laboratory · Microwave Application Laboratory Transmission Line Theory...
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Signal Integrity in Signal Integrity in High Speed Test SystemHigh Speed Test System
HaiHai--Young LeeYoung [email protected]
031)219-2367
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21 Century Electrical Engineering21 Century Electrical EngineeringSignal Signal --> Wave> Wave
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New ParadigmNew Paradigm
Long wavelengthShort wavelength
High frequency
High Resolution
High Data Rate
Low frequency
Low Resolution
Low Data Rate
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ContentsContents
BackgroundTime-domain vs. Freq.-domain
Transmission Line Theory
Network Analysis
Signal IntegrityS/I Introduction
S/I Parameter
S/I Degradation Component
Examples
Summary
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ContentsContents
BackgroundTime-domain vs. Freq.-domain
Transmission Line Theory
Network Analysis
Signal IntegrityS/I Introduction
S/I Parameter
S/I Degradation Component
Examples
Summary
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Digital signals are composed of an infinite number of sinusoidal functions – the Fourier series
The Fourier series is shown in its progression to approximate a The Fourier series is shown in its progression to approximate a square wavesquare wave
Square wave : for and for
1 2 3 4 5
0=Y 0<<− xπ π−<< x01=Y)
12)12sin(
77sin
55sin
33sin(sin2
21
⋅⋅⋅+++
+⋅⋅⋅+++++=m
xmxxxxYπ
0π− π π2 π3
1
1+2 1+2+3
1+2+3+41+2+3+4+5
TimeTime--domain vs. Freq.domain vs. Freq.--domaindomain
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20dB/decade 0.35
Tr
PwT
Tr
40dB/decade
1 3 5 7 9
Harmonic Number
1
T
The amplitude of the sinusoid components are used to construct the “frequency envelope” – Output of FT
TimeTime--domain vs. Freq.domain vs. Freq.--domaindomain
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TimeTime--domain vs. Freq.domain vs. Freq.--domaindomain
S-parameter ( Freq. )
S11(Reflectance)S11(Reflectance)
S22(Reflectance)S22(Reflectance)
S21(Transparency)S21(Transparency)
PortPort--11 PortPort--22
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Time Domain Reflectometry
Module
(Agilent 54754 TDR Module)
TDR Measurement Results of Various Microstrip Line (20, 50, 70 ohm)
TDR MeasurementTDR Measurement
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TDR MeasurementTDR Measurement
TDR – Typical System
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TDR
Reference
(Inductive)
(50Ω)
(Capacitive)
TDR MeasurementTDR Measurement
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TDR MeasurementTDR Measurement
t
x(t)
A 0.9A
0.1A
%10t %90trisett τ=− %10%90
)()1()( / tueAtx t τ−−=
ττττ 195.2105.03.2 =−=r
rdBf
τπτ35.0
21
3 ≅= 21 rrr τττ +≅
10 ps => 35 GHz20 ps => 17.5 GHz50 ps => 7 GHz
Actual Step Signal
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1.25 ns
0.25 ns 2.75 ns
TDR
TDT MeasurementTDT Measurement
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TimeTime--domain vs. Freq.domain vs. Freq.--domaindomain
Eye diagram ( Time Overlap )
200 Mbps 400 Mbps 800 Mbps
1.6 Gbps 3.2 Gbps 6.4 Gbps
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ContentsContents
BackgroundTime-domain vs. Freq.-domain
Transmission Line Theory
Network Analysis
Signal IntegrityS/I Introduction
S/I Parameter
S/I Degradation Component
Example
Summary
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Transmission LineTransmission Line
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Transmission LineTransmission LineExample(PCB) Integrated Circuit
Stripline
W
Cross section view taken here
Microstrip
PCB substrate
via
T
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Transmission Line Theory
Microwave Network Analysis
Extension of
Circuit Theory
Specialization of
Maxwell’s Equation
length ~ λ
Basic CircuitTheory
FieldTheory
▶ Phase velocity of wave
kff
Tvp
ωλπ
πλλ====
22
Transmission Line ParameterTransmission Line Parameter
Wave(rWave(r, t), t)Signal(tSignal(t))
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i (z, t)
v (z, t)+
-Δz
R Δz L ΔzG Δz C Δz
Δz
i (z+Δz, t)
v (z+ Δz,t)+
-
i (z, t)
v (z, t)
Transmission Line ParameterTransmission Line Parameter
CjGLjRLjRZ
ωω
γω
++
=+
=0
-0
0-0
00 I
VIV ++
−==Z
LCβωvp
1==
LCjωjβαγ =+=
CLZ =0
Incident WaveIncident Wave Reflected WaveReflected Wave
zz--variationvariation
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Return Loss
Standing Wave Ratio
Input Impedance of Line Length L
dBlog20 Γ−=RL
Γ−Γ+
==11
VV
min
axmSWR
[ ][ ]
0
02
2
00
00 1
1VV
)(I)(V
ZZZZ
lLj
Lj
lLjLj
LjLj
in
L
LeeZ
eeeeZ
LLZ
+−
=Γ−
−
−+
−+
Γ−Γ+
=Γ−Γ+
=−−
= β
β
ββ
ββ
LjZZLjZZZZ
L
Lin β
βtantan
0
00 +
+=
Transmission Line ParameterTransmission Line Parameter
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Example of Transmission LineExample of Transmission Line
Transmission line (No Reflection)
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Reflection
Low ImpedanceLow Impedance High ImpedanceHigh Impedance
Example of Transmission LineExample of Transmission Line
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Compare of two transmission
Example of Transmission LineExample of Transmission Line
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Special Case to Remember
Zo ZoVs
Zs
ZoVs
Zs
ZoVs
Zs
Terminated in Zo
Short Circuit
Open Circuit
0=+−
=ΓOO
OO
ZZZZ
100
−=+−
=ΓO
O
ZZ
1=+∞−∞
=ΓO
O
ZZ
Transmission Line ParameterTransmission Line Parameter
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Initial Voltage and Current
Transmission Line ParameterTransmission Line Parameter
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I1V1
short → inductor↑ (ω,l) ↓capacitor ← open
Low frequency
High frequency
Termination at High Frequency
Transmission Line ParameterTransmission Line Parameter
V2
V1=V2, I1=I2
I2
I1V1 V2
I2
V1≠V2, I1 ≠ I2
Z(ω)
l
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⎟⎠⎞
⎜⎝⎛
+⎟⎟⎠
⎞⎜⎜⎝
⎛
+=
T0.8W5.98Hln
1.41487Z
ro ε
⎟⎠⎞
⎜⎝⎛
+⎟⎟⎠
⎞⎜⎜⎝
⎛=
2.1T1.68W4Hln60Z
ro ε
⎟⎠⎞
⎜⎝⎛
+⎟⎟⎠
⎞⎜⎜⎝
⎛
+=
T0.8W5.98Hln
20.80560Z
ro ε
T
H
W
HB
W
W
HB
Stripline
Embedded Microstrip
Example of Transmission Line on PCBMicrostrip
Transmission LineTransmission Line
)/,(1 HWt rd ε, , )2
,(tan0
1 ZRacδα
)(2 rdt ε, , )2
,(tan0
2 ZRacδα
)(3 rdt ε, , )2
,(tan0
3 ZRacδα
rε
rε
rε
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Cross-Section Fields
Stripline
EmbeddedMicrostrip
Microstrip
Transmission LineTransmission Line
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ContentsContents
BackgroundTime-domain vs. Freq.-domain
Transmission Line Theory
Network Analysis
Signal IntegrityS/I Introduction
S/I Parameter
S/I Degradation Component
Example
Summary
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Circuitnetworkconcept
Microwaveanalysis &
design
Global quantities I,V,P.
Microwave network theory
[Z] [Y] [ABCD]
[S]
+V1-
+V2-
I1 I2
Port 1 Port 2
[?]
Microwave Network Analysis with Scattering Matrix
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Why [S] ?Why [S] ?
Signal(VSignal(V, I) are not directly, I) are not directlymeasurable.measurable.
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Impedance and Admittance MatrixGeneralize Z concept to N-port
Arbitrary N-port Network
t2 t3
t4
tN
V1+, I1
+
t1V1-, I1
-
VN+,IN
+ VN-, IN
-
V2+, I2
+
V2-, I2
-
[ ] [ ][ ]IZV
I
II
ZZZ
ZZZZZ
V
VV
NNNNN
N
N
=
⎥⎥⎥⎥
⎦
⎤
⎢⎢⎢⎢
⎣
⎡
⎥⎥⎥⎥
⎦
⎤
⎢⎢⎢⎢
⎣
⎡
=
⎥⎥⎥⎥
⎦
⎤
⎢⎢⎢⎢
⎣
⎡
M
L
OM
L
M 2
1
21
2221
11211
2
1
[ ] [ ][ ]VYI
V
VV
YYY
YYYYY
I
II
NNNNN
N
N
=
⎥⎥⎥⎥
⎦
⎤
⎢⎢⎢⎢
⎣
⎡
⎥⎥⎥⎥
⎦
⎤
⎢⎢⎢⎢
⎣
⎡
=
⎥⎥⎥⎥
⎦
⎤
⎢⎢⎢⎢
⎣
⎡
M
L
OM
L
M 2
1
21
2221
11211
2
1
[ ] [ ] 1−= ZY
Microwave Network AnalysisMicrowave Network Analysis
ZrefZref=Open=Open
ZrefZref=Short=Short
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Scattering MatrixIn accordance with direct measurementIncident, reflected & transmitted WaveEasy to achieve impedance matching at high frequency
[ ] [ ][ ]+−
+
+
+
−
−
−
=
⎥⎥⎥⎥⎥
⎦
⎤
⎢⎢⎢⎢⎢
⎣
⎡
⎥⎥⎥⎥
⎦
⎤
⎢⎢⎢⎢
⎣
⎡
=
⎥⎥⎥⎥⎥
⎦
⎤
⎢⎢⎢⎢⎢
⎣
⎡
VSV
2
1
21
2221
11211
2
1
NNNNN
N
N V
V
V
SSS
SSSSS
V
V
V
MOM
M
L
M
jkfor 0 ≠=
+
−
+
=kVj
iij V
VS
▶ Sii: Reflection coefficient▶ Sji: Transmission coefficient
Microwave Network AnalysisMicrowave Network Analysis
ZrefZref==ZoZo=50(Ohm)=50(Ohm)
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Input reflection coefficient with the output port terminatedby a matched load
Output reflection coefficient with the input port terminatedby a matched load
Forward transmission (insertion) gain with the output port terminated in a matched load
Reverse transmission (insertion) gain withthe input port terminated in a matched load
0a2abS
1
111 ==
0a1abS
2
222 ==
0a2abS
1
221 ==
0a1abS
2
112 ==
OL ZZ =
OS ZZ =
OL ZZ =
OS ZZ =
⎟⎟⎠
⎞⎜⎜⎝
⎛⎟⎟⎠
⎞⎜⎜⎝
⎛=⎟⎟
⎠
⎞⎜⎜⎝
⎛
aa
SSSS
bb
2
1
2221
1211
2
1
Scattering ParameterScattering Parameter
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inputnetworktheonincidentPowerinputnetworkthefromreflectedPower=2
11S
outputnetworktheonincidentPoweroutputnetworkthefromreflectedPower=2
22S
sourcefromavailablePowerloadtodeliveredPower
ZZ
O
O=221S
SourceandloadwithgainpowerTransducer ZO=
212S SourceandloadwithgainpowertransducerReverse ZO=
Scattering ParameterScattering Parameter
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Advantage of S-parameterS-parameters are simply measured with the device embedded between a 50 Ω Transmission lines. ( Don’t require high frequency open, short )
S-parameters can be measured on a device located at some distancefrom the measurement transducer.
S-parameters are simply gains and reflection coefficients, both familiarquantities to engineers.
Simple relationship between the variables and various power waves(power gain and mismatch loss)
Scattering ParameterScattering Parameter
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ContentsContents
BackgroundTime-domain vs. Freq.-domain
Transmission Line Theory
Network Analysis
Signal IntegrityS/I Introduction
S/I Parameter
S/I Degradation Component
Examples
Summary
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What is Signal Integrity(SI)What is Signal Integrity(SI)
An Engineering PracticeThat ensures all signals transmitted are received correctly
That ensures signals do not interfere with one another in a way to degrade reception
That ensures signal do not damage any device
That ensures signal do not pollute the electromagnetic spectrum
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TransmitterTransmitter
InterconnectInterconnect
ReceiverReceiver
TransistorsTransistorsSourcesSourcesPassivesPassivesMemoryMemory
Circuit elementsCircuit elementsTransmission linesTransmission linesS S –– parameter blocksparameter blocks
TransistorsTransistorsPassivesPassivesMemoryMemory
Parade of frequency challenges each generation of technologySI encompasses a conglomerate of electrical engineering disciplines
Components of High speed DesignComponents of High speed Design
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SI BudgetsSI Budgets
A SI budget is a technique used to report timing and voltage margins in terms of constituent voltage and timing components for all configurations and conditions of a particular bus design
The budget is often represented in a spread sheet
= B2 = B2 –– (C2+D2+E2) (C2+D2+E2) …… Cell formulaCell formula
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ContentsContents
BackgroundTime-domain vs. Freq.-domain
Transmission Line Theory
Network Analysis
Signal IntegrityS/I Introduction
S/I ParameterSkew, Jitter, Ringback, X-talk, Freq. Dependent-R, Parasitic, Mismatch, P/I
S/I Degradation Component
Example
Summary
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Transmit clock Transmit clock at device at device aa
Receive clock at Receive clock at device device aa
Clock SkewClock Skew
Clock SkewClock Skew : pin-to-pin variation in the timing of input clock at each agent(source & destination) on a busThe net effect of clock skew is that it can
Reduce the total delay that signals are allowed to have for a given frequency targetRequire larger minimum signal delays in order to avoid logic errors
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Source of clock skewSource of clock skewClock skew is cause by :
Variation between the clock driver circuits in a given partVariation in the loading between different agents on the busVariation in interconnect characteristicsVariation in electrical lengths. What is electrical length?
Clo
ck
Drive
r
a
b
0z
LCτd
drvT
drvT
0z
τd
LC
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Ideal clockIdeal clock
Clock with Cycle Clock with Cycle to Cycle Jitterto Cycle Jitter
Clock JitterClock Jitter
Bar graphBar graphOf each cycle timeOf each cycle time
Pulse width(ideal)
Pulse width(Actual)
Jitter + Skew = Clock uncertainty for setup
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Good Transmission Line Bad Transmission Line
Jitter : Any deviations of a clock’s output
transitions from their ideal positions.
Clock JitterClock Jitter
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Exchanging data between synchronized digital machines
Causes of Jitter
Noise of emanates from
source itself
Mechanical vibration
Amplifier self-noise
Inter-Symbol Interference
(ISI)
Power supply
Clock JitterClock Jitter
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CLOCKCLOCK@@clkclk inputinput
CLOCK(a)CLOCK(a)@@clkclk outputoutput
CLOCK(a) @ aCLOCK(a) @ a
DATA DATA @ a@ a
DATA DATA @ b@ b
CLOCK(b)CLOCK(b)@@clkclk outputoutput
CLOCK(b) CLOCK(b) @ b@ b
cycleT)(_ aclkdrvT
)(_ aclkpropT
drvT
propT )(_ bclkdrvT
marginT
cycleT
)(_ bclkpropT
jitterT
0)(_)(_)(_)(_ =−−−−−−−++ aclkdrvaclkporpdrvpropmarginsetupjitterbclkpropbclkcycle TTTTTTTTTTdrv
Setup Timing Diagram & Loop AnalysisSetup Timing Diagram & Loop Analysis
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Skew & Jitter ExampleSkew & Jitter Example
100 MHz busMinimum clock period = 10 ns
GivenMaximum skew = 250 psMaximum edge-edge jitter = 250 ps
Calculate the minimum effective clock period :minimum effective period =
minimum period – maximum skew – maximum jittermin effective period = 10.0 ns – 0.25 ns –0.25 ns = 9.5 ns
Therefore, maximum delay allowed for silicon plus interconnect is 9.5 ns
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Ringback is defined as the amount of voltage that “rings” back toward the threshold voltage.
Cause : Buffer unstability
Effect : Trigger falsely, thewrong data will be latchedinto the receiver circuit
RingbackRingback
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Ideal eye diagram Example
Ringback
RingbackRingback
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Crosstalk Induced NoiseCrosstalk Induced Noise
Voltage Profile of Coupled NoiseNear end crosstalk is always positive
Currents from Lm and Cm always add and flow into the node
For PCB’s, the far end crosstalk is “usually” negative
Current due to Lm larger that current due to Cm
Note that far end crosstalk can be positive
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Graphical Explanation
Crosstalk Induced NoiseCrosstalk Induced Noise
Far end of currentTerminated at T=TD
Near end of currentTerminated at T=2TD
VZo
Time= TD
Zo
12
V
Time=TD
Zo Zo
V
Time=2TD
Zo Zo
VZo
Near end crosstalk pulse at T=0(Inear)
Far end crosstalk pulse at T=0(Ifar)
Time=0
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Creating a Crosstalk ModelCreating a Crosstalk ModelEquivalent Circuit
Line 1 Line 2
C1G C2G
C12
2211
12
LLLK =
K1 K1C12(1) C12(2)
C1G(1) C1G(2)
C2G(1) C2G(2)
L11(1)
L22(1)
L11(2)
L22(2)
Line 1
Line 2
K1 C12(N)
C1G(N)
C2G(N)
L11(N)
L22(N)
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Crosstalk SimulationCrosstalk Simulation
• S-Parameter : Simple 3-Coupled Line
2 4 6 8 10
-60
-50
-40
-30
-20
-10
0
Frequency [GHz]
Transmission Far-Crosstalk Near-Crosstalk Reflection
Port 1
Port 2
Port 3 Port 4
Term50ohm
Term 50ohm
D = 50mm
D = 50mm
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Crosstalk SimulationCrosstalk Simulation
• Time-Domain Simulation
Source
Near
Trans Far
Term 50ohm
Term 50ohm
Pulse : 2.85GBps
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Crosstalk SimulationCrosstalk Simulation
• Time-Domain Simulation
Source
Near
Trans Far
Term 50ohm
Term 50ohm
Pulse : 5GBps
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Crosstalk SimulationCrosstalk Simulation
• Time-Domain Simulation versus Bit-Rates
Pulse : 1GBps Pulse : 2.85GBps
Pulse : 5GBps Pulse : 10GBps
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The total resistance curve will stay at approximately the DC value until the skin depth is less than the conductor thickness,then it will vary with f
40
35
30
25
20
15
10
5
0
1 2 3 4 5 6
Resis
tance O
hm
s
Frequency, GHz
Tline parameter terms
)( fRRR ACDCtot +=
)( fRRR SO +=
RO ~ resistance/unit length RS ~ resistance/sqrt(freq)/unit length
Frequency Dependent ResistanceFrequency Dependent Resistance
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Dielectric lossesClassic model of dielectric losses derived from damped oscillations of electric dipoles in the material aligning
Dielectric constant becomes complex with losses
PWB board manufacturers specify this was a parameter called “Loss Tangent” or Tanδ
The real portion is the typical dielectric constant, the imaginary portion represents the losses, or the conductivity of the dielectric
'
""'
εεδεεε =⇒−= Tanj
"21 επρ
σ fdielectric
dielectric ==
Frequency Dependent ResistanceFrequency Dependent Resistance
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Applying Frequency Dependent EffectsApplying Frequency Dependent Effects
AC losses will degrade BOTH the amplitude and the edge rate
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Frequency Domain Contents of Square Waveform
Filtering Effects of Parasitic Filtering Effects of Parasitic ‘‘LL’’
20dB/decade 0.35
Tr
PwT
Tr
40dB/decade
1 3 5 7 9
Harmonic Number
1
T
TermTerm1
TermTerm2
LL1
TLINTL1
Parasitic
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Filtering Effects of Parasitic Filtering Effects of Parasitic ‘‘LL’’
TermTerm1
TermTerm2TLIN
TL1
No Cut-off Frequency
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Cut-off Frequency 500MHz
Filtering Effects of Parasitic Filtering Effects of Parasitic ‘‘LL’’
TermTerm1
TermTerm2
LL1
TLINTL1
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Cut-off Frequency 200MHz
Filtering Effects of Parasitic Filtering Effects of Parasitic ‘‘LL’’
TermTerm1
TermTerm2
LL1
TLINTL1
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Cut-off Frequency 100MHz
Filtering Effects of Parasitic Filtering Effects of Parasitic ‘‘LL’’
TermTerm1
TermTerm2
LL1
TLINTL1
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Reflection by Impedance MismatchingReflection by Impedance Mismatching
High Impedance <-> Low Impedance
High Z0High Z0
Low Z0Low Z0
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Reflection by Impedance MismatchingReflection by Impedance Mismatching
•Matching Line, Pulse : 0.5Gbps
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.00
1
2
3
4
5
Time [nsec]
Original Pulse Transmission
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
-0.4
-0.2
0.0
0.2
0.4
Frequency [GHz]
Transmission
T-DomainF-Domain
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Reflection by Impedance MismatchingReflection by Impedance Mismatching
•Moderate Mis-Matching, Pulse : 0.5Gbps
Inse
rtion
Los
s [d
B]
T-DomainF-Domain
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Reflection by Impedance MismatchingReflection by Impedance Mismatching
•Severe Mis-Matching, Pulse : 0.5Gbps
Mag
nitu
de [V
]
0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50-10
-8
-6
-4
-2
0
Frequency [GHz]
Transmission
T-DomainF-Domain
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ContentsContents
BackgroundTime-domain vs. Freq.-domain
Network Analysis
Signal IntegrityS/I Introduction
S/I Parameter
S/I Degradation Component
Example
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High speed circuit designHigh speed circuit designHigh speed means rapid rise timesRise time degradation is a major concernRise time degradation is caused by :
Signal lossConductor and dielectric loss
Impedance discontinuitiesVias, connectors, material changes, manufacturing defects
Performance limiters
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ViaViaDefinition
Vertical connections between layers made by drilling a small hole and filling it with conductive material
Capacitor Chip ChipVias
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Via TypesVia Types
Through Hole Via Blind Via Step Via
Buried Via Stacked Via
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Via TypesVia Types
Laser generated via Plasma generated via Photo-defined via
Cond. ink filled via Micro via Plated-through hole via
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Through Hole ViaThrough Hole ViaBarrel : conductive cylinder filling the drilled holePad : connects the barrel to the component/plane/traceAnti-pad : clearance hole between via and no-connect metal layer
Trace connected to pad on layer1
Via Pad
Trace connected to pad on layer2
Via Barrel
Anti-pad
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Via Via ParasiticsParasitics
Capacitance to groundD1
D2
C : capacitance of viaD1 : diameter of pad surrounding viaD2 : diameter of anti-pad T : PCB thickness h
d
nH
L : inductance of viah : via lengthd : barrel diameter
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Via Via ParasiticsParasitics
Field Plot – 2GHz
Microstrip line
Stripline
Microstrip line
Stripline
via
via
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Via Via ParasiticsParasitics
Frequency Domain
2 4 6 8 10-20
-16
-12
-8
-4
0
S21 S11
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Via Via ParasiticsParasitics
Time-domain
2 4 6 80 10
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
-0.8
0.8
time, nsec
vout
va
Clock : 200 Mbps
2 4 6 80 10
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
-0.8
0.8
time, nsec
vout
va
Clock : 500 Mbps
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0.5 1.0 1.50.0 2.0
-0.5
-0.4
-0.3
-0.2
-0.1
0.0
0.1
0.2
0.3
0.4
0.5
-0.6
0.6
time, nsec
vout
va
0.5 1.0 1.50.0 2.0
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
-0.8
0.8
time, nsec
vout
va
Via Via ParasiticsParasitics
Time-domain
Clock : 1 Gbps Clock : 2 Gbps
Microwave Application LaboratoryMicrowave Application Laboratory
Connector effectsConnector effectsSeries / mutual inductance
Wire of the connector : the signal pathSeries L slows edgeComplicated coupling induced noise
Shunt / Mutual capacitanceSlows the system edge rateReduces impedance discontinuity at connector
Connector crosstalkBecause of geometry, mutual L has larger effect than mutual C
Microwave Application LaboratoryMicrowave Application Laboratory
Connector effectsConnector effects
Series Inductance
(round)
(square)
Approximation of mutual L between 2 connector pins
r << l r : radius of round wire
l : length
P : perimeter of rectangular wire
S : center-to-center spacing
l : length
Microwave Application LaboratoryMicrowave Application Laboratory
Connector effectsConnector effects
Inductive Coupling in Connector Pin Fields
32 12 22 21 23
dIdI dIV L L Ldt dt dt
= + +
Voltage induced on pin 2 due to current changes in 1,2, and 3
Voltage induced on pin 2 in case of odd and even switching
2 22 21 23( ) dIV L L Ld t
= + + 2 22 21 23( ) dIV L L Ldt
= − −
Switching in phase Switching out of phase with 1 and 3
Microwave Application LaboratoryMicrowave Application Laboratory
Connector effectsConnector effects
The current through the signal pins must return to thesource through the ground/pwr pins
Return current in connector
Microwave Application LaboratoryMicrowave Application Laboratory
Connector effectsConnector effects
0 0
0 0 02Z sL Z sLZ sL Z Z sL
+ −Γ = =
+ + +
0
0
2 12 1
ZZ sL sτ
Τ = =+ +
Effects of series L on signal transmission
s jϖ↔
02L Zτ =
1 1 1( )2 1LV s
s sτ⎛ ⎞= ⎜ ⎟+⎝ ⎠ ( )/1( ) 1 ( )
2t
LV t e U tτ−⎡ ⎤= −⎣ ⎦
02.2 /riset L Zτ≈ ≈
Step Response:
Equivalent risetime:
0Z
0Z 0Z( )LV t
0Z
L
( )U t
Microwave Application LaboratoryMicrowave Application Laboratory
Connector effectsConnector effects
10 0
10 0
( ) //( ) // 1sC Z Z ssC Z Z s
ττ
−
−
− −Γ = =
+ +1
01
0 0
( ) // 1/ 2( ) // 1
sC ZZ sC Z sτ
−
−Τ = =+ +
Effect of shunt C on risetime
s jϖ↔
0 2CZτ =
1/ 2 1( )1LV s
s sτ=
+ ( )/1( ) 1 ( )2
tLV t e U tτ−⎡ ⎤= −⎣ ⎦
02.2riset CZτ≈ ≈
0
Step Response:
Equivalent risetime:
Z
0Z 0Z( )LV t
0ZC
( )U t
Microwave Application LaboratoryMicrowave Application Laboratory
Connecter effectsConnecter effectsConnector pin patterns
G S S S S S S S S P•P and G pins far from signals: maximized noise.
•Pin to pin signal crosstalk huge.
•Cheap… so small!
G S P S G S P S G S P S G S P S G•P and G pins next to each signal.
•Signal pins shielded from each other.
•70% bigger than “worst” option.
G S S P S S G S S P S S G•P and G pins closer to signals.
•Pin to pin signal crosstalk smaller
•30% bigger than the “worst” option.
G P S G P S G P S G P S G P S G P •Power and ground pins next to every signal.
•Signal pins shielded from each other.
•P and G pins adjacent which reduces their L more.
Worst
Even better
Better
Best
2)2)3)3)
4)4)
1)1)
Microwave Application LaboratoryMicrowave Application Laboratory
Cable TypesCable Types
Coax CableCoax Cable
UnshieldedUnshieldedTwisted PairTwisted Pair
ShieldedShieldedTwisted PairTwisted Pair
Ribbon or FPCRibbon or FPC
Microwave Application LaboratoryMicrowave Application Laboratory
Problem of CablingProblem of Cabling
Cable = Antenna & Circuit Element
Microwave Application LaboratoryMicrowave Application Laboratory
Radiation & InductionRadiation & Induction
Radiation : D ~ several times of l - far-field EMI radiation
Induction : D ~ faction of l - near-field EMI radiation
Conduction : Source and Receptor are connected by metal
Microwave Application LaboratoryMicrowave Application Laboratory
Common Mode RadiationCommon Mode RadiationConduction current + Displacement current
External multi-path exist
Wire ModeWire Mode
Common ModeCommon Mode
Microwave Application LaboratoryMicrowave Application Laboratory
ContentsContents
BackgroundTime-domain vs. Freq.-domain
Network Analysis
Signal IntegrityS/I Introduction
S/I Parameter
S/I Degradation Component
Examples
Microwave Application LaboratoryMicrowave Application Laboratory
Effects of Test Socket at S.I.Effects of Test Socket at S.I.
• Test Socket TypesBGA Type Socket
Spring Probe
Microwave Application LaboratoryMicrowave Application Laboratory
Effects of Test Socket at S.I.Effects of Test Socket at S.I.
• Test Socket TypesTSOP Type Socket
Various contact designs available
Competitive development cost
Compact design for maximum board density
Micro-spring
Microwave Application LaboratoryMicrowave Application Laboratory
Self Inductance : 1.126 nHMutual Inductance : 0.3 nHCapacitance : 0.21 pF1dB IL : DC ~ 6.3 GHz (Single Pin)
: DC ~ 14.5 GHz (GSG)
Socket Pin ShapeTest Socket(closed)
Test Socket(open)
Performance of New RF Test SocketPerformance of New RF Test Socket
Microwave Application LaboratoryMicrowave Application Laboratory
Effects of Test Socket at S.I.Effects of Test Socket at S.I.
• Test Socket TypesRubber Contact type
Rubber Gold Powder
Ball Contacting
Or Pin
Microwave Application LaboratoryMicrowave Application Laboratory
Comparison of SComparison of S--parameterparameter
Yamaich SocketAt 600 MHz, S11 = -13 dB
S21 = -1 dB
(S11) (S21)
Johnstech SocketAt 5.6 GHz, S11 = -10 dB
S21 = -1 dB
- - - - - : Yamaich: Johnstech
Microwave Application LaboratoryMicrowave Application Laboratory
S11 S21
Three Pins of GSG ConfigurationHP 8510C Network AnalyzerHP Eesof MDS
Test FixtureResonance
IL : 1 dB @14.5 GHz
Measurement & FittingMeasurement & Fitting
Microwave Application LaboratoryMicrowave Application Laboratory
Signal IntegritySignal Integrity
I_ProbeI_Probe2
RR12R=50 Ohm
ItPulseSRC1
Period=p nsecWidth=w nsecFall=0 nsecRise=0 nsecEdge=linearDelay=0 nsecI_High=10 mAI_Low=0 mA
I_ProbeI_Probe1
MutualMutual3
Inductor2="L8"Inductor1="L7"M=1.65 nHK=
MUTIND
CC24C=0.405 pF
CC23C=0.405 pF
RR11R=0.02 Ohm
RR10R=0.02 Ohm
CC22C=0.11 pF
CC21C=0.405 pF
CC20C=0.11 pF
LL8
R=L=2.65 nH
LL7
R=L=2.65 nH
CC19C=0.405 pF
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.80.0 2.0
-10
-8
-6
-4
-2
0
-12
2
time, nsec
I_Pr
obe1
.i, m
AI_
Prob
e2.i,
mA
321 97 8
654
Microwave Application LaboratoryMicrowave Application Laboratory
Effects of Test Socket at S.I.Effects of Test Socket at S.I.
• Time-Domain Simulation
1-Array 2-Array
Mag
nitu
de [V
]
All Source Pulse Bit-Rate : 1.6GBps
Microwave Application LaboratoryMicrowave Application Laboratory
Effects of Test Socket at S.I.Effects of Test Socket at S.I.
• Time-Domain Simulation
3-Array
Mag
nitu
de [V
]
1-Array Rising Time : 110ps , 4.98V
2-Array Rising Time : 180ps , 4.95V
3-Array Rising Time : 230ps , 4.90V
Crosstalk and Mutual Inductance
Increased Inductance
Increased Rising Time, Increased Reflection
All Source Pulse Bit-Rate : 1.6GBps
Microwave Application LaboratoryMicrowave Application Laboratory
Effects of Test Socket at S.I.Effects of Test Socket at S.I.
• Rubber Contact Type
Pin Inductance 0.24nH
Pin Resistor 1mOhm
1-Array 2-Array 3-Array
Mutual Inductance(Pin12) 0.06 nH
Mutual Inductance(Pin12) 0.06 nH
Mutual Inductance(Pin13) 0.03 nH
Spacing Distance : 1mm Spacing Distance : 1mm
Powder Length : ex) 1mm
Microwave Application LaboratoryMicrowave Application Laboratory
Effects of Test Socket at S.I.Effects of Test Socket at S.I.
• Time-Domain Simulation
1-Array 2-Array
All Source Pulse Bit-Rate : 1.6GBps
Mag
nitu
de [V
]
0 200 400 600 800 1000 12000
1
2
3
4
5
Mag
nitu
de [V
]
Time [psec]
Source Rev1 TDR
Microwave Application LaboratoryMicrowave Application Laboratory
Effects of Test Socket at S.I.Effects of Test Socket at S.I.
• Time-Domain Simulation
3-Array
1-Array Rising Time : 62.5ps , 4.9V
2-Array Rising Time : 62.5ps , 4.9V
3-Array Rising Time : 62.5ps , 4.9V
All Source Pulse Bit-Rate : 1.6GBps
0 200 400 600 800 1000 12000
1
2
3
4
5
Time [psec]
Source Rev1 Rev2 Rev3 TDR
NO Difference!!
Because of Lower Inductance than The Others
Microwave Application LaboratoryMicrowave Application Laboratory
Low Voltage Differential SignalsLow Voltage Differential Signals•CM Noise EMS
Ideal Diff. Waveformon LVDS
High power & freq.
Common Mode Noise
Distorted Diff. Waveform due
to Common Mode Noise
on LVDS
Common Mode Range
Differential Input Threshold
Error Area
Error Area
Microwave Application LaboratoryMicrowave Application Laboratory
Analysis of EMS on High Speed LVDS SystemAnalysis of EMS on High Speed LVDS System
LVDS Driver Receiver
Typical Bit Rate 600 Mbps 600 Mbps
Diff. Input Threshold - ± 100 Mv
Common Mode Range - ± 2.4 V
BCI Probe
Frequency Range 800 ~ 2100 MHz
Amplifier & Signal Generator
Noise Source Freq. 1.97 GHz
Amp Output Power 20 ~ 25 dBm
• Setup for High Speed Single LVDS EMS Test
Microwave Application LaboratoryMicrowave Application Laboratory
LVDS BER Results w/ Noise Environment LVDS BER Results w/ Noise Environment • 600 Mbps , Time: 3 Hour., Accumulative Compared bits: 6.379*10^12
• Noise Source: 1.97 GHz, AM modulation (Depth: 80%, Rate: 1 KHz)
Conv. CLCPW
dBmAccum.
BER
1.492e-004
8.763e-006
8.142e-013
0
Accum.
Comp. Bits
Accum.
Error
Time Eye
Opening
Amplitude Eye Opening
22 6.379e+012
6.379e+012
6.379e+012
0.613 UI
6.379e+012
1.7V
21
9.517e+008
5.589e+007
5
0.659 UI 1.75V
20 0.662 UI 1.81V
N/A 0 0.841 UI 1.9V
Microwave Application LaboratoryMicrowave Application Laboratory
LVDS BER Results w/ Noise EnvironmentLVDS BER Results w/ Noise Environment• Eye Opening Tests (Conventional Diff. Cable)
No noise 20 dBm Noise Power at Power Amp.
21 dBm Noise Power at Power Amp. 22 dBm Noise Power at Power Amp.
Microwave Application LaboratoryMicrowave Application Laboratory
ContentsContents
BackgroundTime-domain vs. Freq.-domainNetwork Analysis
Signal IntegrityS/I IntroductionS/I ParameterS/I Degradation Component
ApplicationSummary
Microwave Application LaboratoryMicrowave Application Laboratory
SummarySummary
Backgrounds
Wave Behaviors of High Speed Test Systems
Network Analysis of High Speed Signaling
S-Parameter and TDR Measurements
Signal Integrity
Concept of SI
SI Parameter – Skew, Jitter, X-talk, Loss, etc.
Effect of Vias, Cables, Connectors
Some SI Examples
Microwave Application LaboratoryMicrowave Application Laboratory
CoCo--design of Analog and Digitaldesign of Analog and Digital
XX