MICROPROCESSORS & INTERFACING (A1423 Unit-V Serial Data ... - WordPress… · In asynchronous mode...

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C.Lokanath ReddyAssistant Professor

[email protected]

Department of Electronics and Communication Engineering

MICROPROCESSORS & INTERFACING (A1423)Unit-V

Serial Data Transfer SchemesAdvanced Microprocessors

VARDHAMAN COLLEGE OF ENGINEERING(AUTONOMOUS)

Shamshabad, Hyderabad - 501218

Microprocessors & Interfacing (A1423)

UNIT-V

C.LOKANATH REDDY2

Serial Data Transfer Schemes

Asynchronous and Synchronous Data Transfer Schemes

8251 USART Architecture and Interfacing

RS-232 Serial Data Standard

RS-423A and RS-422A

Sample Program of Serial Data Transfer

Advanced Microprocessors Introduction to 80286

Salient features of 80386

Real and Protected mode Segmentation

Paging

mailto:[email protected]

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Serial Communication

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Most of the microprocessors are designed for parallel

communication.

In parallel communication number of lines required to

transfer data depend on the number of bits to be

transmitted.

For transmitting data over long distance, using

parallel communication is impractical due to the

increase in cost of cabling.

In such cases serial communication is used.

In serial communication one bit is transferred at a

time over a single line.


Classification

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Serial communication can be classified on the

basis how transmission occurs.

1. Simplex: Hardware such that data transfer takes

place in only one direction.

2. Half Duplex: allows the data transfer in both

direction but not simultaneously.

3. Full Duplex: allows the data transfer in both direction

simultaneously.

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Transmission Formats

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The data in the serial communication may be

sent in two formats:

1. Asynchronous

2. Synchronous


Asynchronous

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Asynchronous formats are character oriented.

In this type the bits or character or data word are sent

at constant rate, but characters can come at any

rate(asynchronously) as long as they do not overlap.

When no character are being sent a line stays high at

logic1 called mark, logic0 is called space.

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Asynchronous Cont..

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The beginning of a character is indicated by start bit which is always low.

This is used to synchronize the transmitter and receiver.

After the start bit the data bits are sent with least significant bit first followed by one or more stop bits(active high).

The stop bits indicate the end of character. Different system use 1, 1 ½ or 2 stop bits. The combination of start but, character and stop bits

is known as frame. The start and stop bits carry no information, but are

required because of asynchronous nature of data.


Synchronous

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The start and stop bits in each frame of asynchronous

format represents wasted overhead bytes that reduce

overall character rate.

These start and stop bits can be eliminated by

synchronizing receiver and transmitter.

They can be synchronized by having a common clock

signal.

Such a communication is called synchronous serial

communication.

In this transmission synchronous bits are inserted

instead of start and stop bits

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Synchronous

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The data rate can be expressed as bit/sec or character/sec.

The term bit/sec is also called baud rate.


Transmission Formats

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S.No Asynchronous Synchronous

1. Transmitters and receivers are

not synchronized by clock.

Transmitters and receivers are

synchronized by clock.

2. Bits of data are transmitted at

constant rate.

Data bits are transmitted with

synchronization of clock.

3. Character may arrive at any rate

at receiver.

Character is received at constant

rate.

4. Data transfer is character

oriented.

Data transfer takes place in blocks

5. Start and stop bits are required to

establish communication of each

character.

Start and stop bits are not required to

establish communication of each

character. Synchronization bits are

required to transfer the data block.

6. Used in low-speed transmission

at about speed less than 20

Kbits/sec.

Used in high speed transmissions.

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8251- Universal Synchronous Asynchronous

Receiver-Transmitter(USART)

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To implement serial communication in microprocessor

system we need basically two devices:

1. Parallel to Serial Converter

2. Serial to Parallel Converter

To transmit byte data it is necessary to convert byte

into eight serial bits.

This can be done by using the parallel to serial

converter.

Similarly at the reception these serial bits must be

converted into parallel 8-bit data.

The serial to parallel converter is used to convert

serial data bits into parallel data.



Receiver-Transmitter(USART) Cont..

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The devices are designed for this purpose are called

universal synchronous asynchronous receiver-

transmitter.

These devices are software programmable for

number of data bits, parity and number of stop bits.

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Data Bus Buffer: This bidirectional 8-bit buffer is used to interface

8251 to the system data bus. Along with the data, control word, command words

and status information are also transferred through the Data Bus Buffer.

Read/Write Control Logic: This functional block accepts inputs from the system

control bus and generates control signals for over all operation.

It contains the control word register and command word register that stores the various control formats for the device functional definitions.

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Transmit Buffer:

The transmit buffer accepts parallel data from CPU,

adds the appropriate framing information, serializes

it and transmits it on the TxD pin on the failing edge

of

Transmit Control:

It manages all activities associated with the

transmission of serial data.

It accepts and issues signals both externally and

internally to accomplish this function.

TxC




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Receiver Buffer:

The receiver buffer accepts serial data on the RxD

line, coverts this serial data to parallel formats,

checks for bits or characters that are unique to the

communication technique and sends an

“assembled” character to CPU.

Receiver Control:

It manages all activities associated with the

receiving of serial data.

Along with data reception, it does false start bit

detection, parity error detection, framing error

detection, sync detection and break detection.

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Modem Control:

The 8251 has set of control inputs and outputs that

can be used to simplify the interface to almost any

modem.


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Data Bus(D0-D7): This pin allows transfer of data bytes between CPU and the 8251A.

Read : A low on this input allows CPU to read data or status byte from 8251A.

Write : A low on this input allows CPU to write data or command word to 8251A.

Clock(CLK): The CLK input is used to generate internal device timing.

RESET: A high on this input forces 8251A into an “IDLE” mode.

RD

WR




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Control/Data(C/ ): This input in conjunction with the

and the inputs informs the 8251A that the word

on the DATA BUS is either a data character, control

word or status information.

D WR

RD

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Chip Select( ): A low on this input allows

communication between CPU and 8251A.

Modem Control Signals

The 8251A has a set of control inputs and outputs

that can be used to simplify the interface to almost

any modem.

Data Set Ready( ): This input signal is used to

test modem conditions such as Data Set Ready.

Data Terminal Ready( ): This output signal is

used to tell modem that Data terminal is ready

CS

DSR

DTR




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Request to Send( ): This output signal is asserted

to begin transmission.

Clear to Send( ): A low on this input enables the

8251A to transmit serial data if the TxE bit in the

command byte is set to one.

Transmitter Signals

Transmit Data(TxD): This output signal outputs a

composite serial stream of data on the falling edge

of TxC.

RTS

CTS

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Transmitter Ready( TxRDY): This output signal

indicates the CPU that the transmitter is ready to

accept a data character.

Transmitter Empty(TxE): This output signal indicates

that the transmitter has no character to transmit.

Transmitter Clock(TxC): This clock input controls the

rate at which the character is to be transmitted.




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Receiver Signals

Receiver Data(RxD): This input receives a

composite serial stream of data on the raising edge

of RxC.

Receiver Ready(RxRDY): This output indicates that

8251A contains a character that is ready to be input

to the CPU.

Receiver Clock(RxC): This clock input controls the

rate at which the character is to be received.

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Sync/ Break Detect(SYNDET/BD): This pin is used

in synchronous mode for detection of synchronous

characters and may be used as input or output.

In asynchronous mode this pin goes high if receiver

line stays low for more than 2 character times. It

then indicates a break in the data stream.




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8251A Control Words: The control words defines the

complete functional definition of 8251A and they must be

loaded before any transmission or reception.

The control words of 8251A are split into two formats:

1. Mode Instruction

2. Command Instruction

Mode Instruction:

The instruction can be considered as four 2-bit fields

The first 2-bit field (D1-D0) determines whether the

USART is to operate in the synchronous(00) or

asynchronous mode.

In the asynchronous mode, this field determines the

division factor for clock to decide baud rate.

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Mode Instruction:




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Mode Instruction: The second 2-bit field (D3-D2) determines number of data

bits in character. With this 2-bit field we can set characterlength from 5-bits to 8-bits.

The third 2-bit field (D5-D4) controls the parity generation.The parity bit is added to the data pins only if parity isenabled.

The last field (D7-D6) has two meanings depending onwhether operation is to be in the synchronous orasynchronous mode.

For asynchronous mode(D1 D0≠00) it controls the numberof STOP bits to be transmitted with the character.

In synchronous mode(D1 D0=00) this field controls thesynchronizing process.

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It decides whether to operate with external or

internal synchronization and whether to transmit

single synchronizing character or two synchronizing

characters.

Command Instruction: After the mode instruction,

command character should be issued to the USART.

It controls the operation of the USART within the basic

frame work established by the mode instruction.

It does function such as:

1. Enable Transmit/ Receive

2. Error Reset

3. Modem Control




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Command Instruction:

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8251A Status Word: In the data communication systems

it is often necessary to examine the “status” of the

transmitter and receiver.

It is also necessary for CPU to know if any error has

occurred during communication.

The 8251A allow the programmer to read information

from the status register any time during functional

operation


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Error Definitions:1. Parity Error: At the time of transmission of data an

even or odd parity bit is inserted in the data stream.At the receiver end, if parity of the character doesnot match with the pre-defined parity, parity erroroccurs.

2. Overrun Error: In the receiver section receivedcharacter is stored in the receiver buffer. The CPU issupposed to read this character before reception ofnext character. But if CPU fails in reading thecharacter loaded in the receiver buffer, the next thereceived character replaces the previous one andthe OVERRUN Error occurs.




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Error Definitions:

3. Framing Error: If valid stop bit is not detected at the

end of each character framing error occurs.

All these errors when occur set the corresponding

bits in the status register.

These error bits are reset by setting ER bit in the

command instruction.

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Interfacing 8251A to 8086 in I/O Mapped I/O Mode

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Problem: Design the hardware interface circuit for

interfacing 8251 with 8086. Set the 8251A in

asynchronous mode as transmitter and receiver with

even parity enable, 2 stop bits, 8-bit character length,

frequency 160 kHz and baud rate 10 K.

a. Write an ALP to transmit 100 bytes of data string at

location 2000:5000H.

b. Write an ALP to receive 100 bytes of data string and

store it at location 3000:4000H.



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Solution: Asynchronous Mode Control Word

Command Word for Transmission

D7 D6 D5 D4 D3 D2 D1 D0

=0FEH1 1 1 1 1 1 1 0

2 Stop

Bits

Even Parity

Enabled

8- bit

Format

CLK scaled

by 16

D7 D6 D5 D4 D3 D2 D1 D0

=11H0 0 0 1 0 0 0 1

EH IR RTS ER SBRK RxE DTR TxEN



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ALP to initialize 8251 and transmit 100 bytes of data

ASSUME CS:CODE

CODE SEGMENT

START: MOV AX,2000H

MOV DS,AX ; DS points to byte string segment

MOV SI,5000H ; SI points to byte string

MOV CL,64H ; Length of string in CL (hex)

MOV AL,0FEH ; Mode control word to

OUT 0FEH,AL ; D0–D7

MOV AX,11H ; Load command word

OUT 0FE,AL ; to transmit enable and error reset

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WAIT: IN AL,0FEH ; Read status

AND AL,01H ; Check transmitter enable

JZ WAIT ; bit, if zero wait for the transmitter to be ready

MOV AL,[SI] ; If ready, first byte of string data

OUT 0FCH, AL ; is transmitted

INC SI ; Point to next byte

DEC CL ; Decrement counter

JNZ WAIT ; If CL is not zero, go for next byte

MOV AH,4CH : If CL is zero, return to DOS

INT 21H

CODE ENDS

END START



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b. Write an ALP to receive 100 bytes of data string and

store it at location 3000:4000H.

Command Word for Receiving

D7 D6 D5 D4 D3 D2 D1 D0

=14H0 0 0 1 0 1 0 0

EH IR RTS ER SBRK RxE DTR TxEN

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An ALP to initialize 8251 and receive 100 bytes of dataASSUME CS:CODE

CODE SEGMENT

START : MOV AX,3000H

MOV DS,AX ; Data segment set to 3000H

MOV SI,4000H ; Pointer to destination offset

MOV CL,64H ; Byte count in CL

MOV AL,7EH ; Only one stop bit for

OUT 0FEH,AL ; receiver is set

MOV AL,14H ; Load command word to enable

OUT 0FEH,AL ; the receiver and disable transmitter



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NXTBT : IN AL,0FEH ; Read status

AND AL,38H ; Check FE, OE and PE

JZ READY ; If zero, jump to READY

MOV AL,14H ; If not zero, clear them

OUT 0FEH,AL

READY: IN AL,0FEH ; Check RXRDY.

AND AL,02H ; if receiver is not ready

JZ READY ; wait

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IN AL,0FCH ; If it is ready,

MOV [SI],AL ; receive the character

INC SI ; Increment pointer to next byte

DEC CL ; Decrement counter

JNZ NXTBT ; Repeat, if CL is not zero

MOV AH,4CH

INT 21H

CODE ENDS

END START


20- AND 60-mA Current Loops

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In teletypewriters or other current-signal systems,

some manufactures use a nominal current of 20mA to

represent a 1, or mark and no current to represent a

space or 0.

Other manufactures use a nominal current of 60mA to

represent a 1 and no current to represent 0.

The actual current in a specific system may be

considerably different from the nominal value.

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RS-232C Serial Data Standard

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In response to the need for signals and handshake

standards between DTE(Data Terminal Equipment) and

DCE(Data Circuit-Terminating Equipment), the

Electronic Industries Association (EIA) introduced EIA

standard RS-232 in 1962.

It is widely accepted for single ended data

transmission over short distances with low data rates.

This standard describes the function of 25 signals and

handshake pins for serial data transfer



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The voltage level +3V to +15V is defined as logic0;

from -3V to -15V is defined as logic1.

The timing and control signals are compatible with TTL

level(Transistor-Transistor Logic).

Because of the incompatibility of the data lines with

the TTL level, voltage translators called LINE DRIVERS

and LINE RECEIVERS are required to interface TTL

level with RS-232 signals.

The line driver, MC1488 converts logic 1 into

approximately 9V.

These levels at the receiving end are again converted

by the line receiver MC1489 into TTL compatible level.

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RS-423A

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A major problem with RS-232C is that it can onlytransmit data reliably for about 50ft(16.4m) at itsmaximum rate of 20,000Bd.If longer lines are used the transmission rate has to bedrastically reduced.This limitation is caused by the open signal lines witha single common ground that are used to RS-232C.Another EIA standard which is an improvement overRS-232C is RS-423A.This standard specifies a low impedance single-endedsignal which can be sent over 50Ω coaxial cable andpartially terminated at the receiving end to preventreflections.

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RS-423A

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RS-422A

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A still newer standard for serial data transfer, RS-422A

specifies that each signal will be sent differentially over

two adjacent wires in a ribbon cable or a twisted pair of

wires.

The term differential in this standard means that signal

voltage is developed between the two signal lines rather

than between a signal line and ground as in RS-232C

and RS-423A.

In RS-422A a logic high is transmitted by making the

„b‟ line more positive than the „a‟ line and vice versa.

The voltage difference between two lines must be

greater than 0.4V but less than 12V.

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Features of 80286 Microprocessor

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It is a 16-bit processor.

It has 24-bit address bus.

It can be operated at 3 different clock speeds:

i. 8MHz ii. 10MHz iii. 12.5MHz

It includes special instructions to support operating system.

It has a 68-pin flat package.

It contains four separate processing units:

a. Bus Unit (BU) b. Address Unit (AU)

c. Instruction Unit (IU) d. Execution Unit (EU)

It contains virtual memory management circuitry and

protection circuitry.

It is first microprocessor designed for use as CPU in a

multi-user computer.


Register Organization of 80286

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80286 CPU consists of same set of registers as in

8086:

I. Eight 16-bit general purpose registers

II. Four 16-bit segment registers

III. Status and control registers

IV. Instruction pointer

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Register Organization of 80286 Cont..

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Flag Register of 80286

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Flag Register of 80286 Cont..

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The flag register bits OF, AF, CF, PF, ZF, DF, SF are called status flags. They are modified based on the result of execution of logical and arithmetic instructions.

The Trap Flag (TF) and Interrupt Flag (IF) are called the control flags, as they are used for controlling machine operation.

The additional flags that are available in 80286 are:

IOPL (I/O Privilege Field)

NT (Nested Task Flag)


Machine Status Word of 80286

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The bits PE, MP, EM, TS come under the upper 16-

bits of flag register.

These lower 4-bits of the upper flag register together

are called the machine status word.

I. PE (Protection Enable)

II. MP (Monitor Processor Extension)

III. EM (Process Extension Emulator)

IV. TS (Task Switch)

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Machine Status Word of 80286

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The bits PE, MP, EM, TS come under the upper 16-

bits of flag register.

These lower 4-bits of the upper flag register together

are called the machine status word.

I. PE (Protection Enable)

II. MP (Monitor Processor Extension)

III. EM (Process Extension Emulator)

IV. TS (Task Switch)


Internal Block Diagram for 80286

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Internal Block Diagram for 80286 Cont..

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Address Unit: It consists of segment registers, offset adder and physical address

adder. The 80286 is operated in two addressing modes:

Real Address Mode Protected virtual Address Mode

In real address mode,

Responsible for calculating the 20-bit physical addresses basedon the 16-bit contents of segment register and a 16-bit offset.

A23-A20 address lines are ignored and A19-A0 are used toaccess up to 1MB physical memory.

In protected virtual address mode,

Functions as a complete Memory Management Unit (MMU).

All 24 address lines are used to access up to 16MB of physicalmemory.



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Bus Unit: It includes address latches and data transceivers, bus

interface and control circuitry, instruction pre-fetches and a 6byte instruction queue.

The address latches and drivers transmit the physical addresscomputed in the address unit to the Bus unit through theaddress bus A23-A0.

One major function of bus unit is to fetch instruction bytesfrom the memory.

The instructions are fetched in advance and stored in a 6-bytepre-fetch queue for faster execution of instructions. Thisphenomenon is called instruction pipelining.

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Bus Unit: When one instruction is being executed, the next instruction is

pre-fetched, decoded and kept ready for execution by the pre-fetcher module.

The pre-fetcher module is controlled by the bus control module.

These pre-fetched instructions are arranged in 6 byte pre-fetchqueue.

This enhances the speed of execution.

The processor extension interface module takes care ofcommunication between the CPU and coprocessor.



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Instruction Unit: It includes an instruction decoder and 3 decoded

instruction queue.

The 6-byte pre-fetch queue forwards the instructions arranged in it to the instruction unit (IU).

The instruction unit accepts instructions from the pre-fetch queue and an instruction decoder decodes them one by one.

The instruction unit decodes up to 3 pre-fetched instructions and holds them in the queue.

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Execution Unit: It includes the ALU, registers and the control unit.

The output of decoding circuit drives a control unit in theexecution unit.

The execution unit executes the instructions from the decodedinstruction queue and sends the data over the data bus.

The registers consist of general purpose registers, segmentregisters, index registers, pointer registers, flag registers and 16-bit machine status word (MSW) register.

The ALU performs the arithmetic and logical operations.


Pin Diagram for 80286

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Pin Description for 80286

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70

COD Machine Cycle

0 0 Interrupt acknowledge

cycle

0 1 Memory read cycle

1 0 I/O cycle

1 1 Instruction fetch cycle

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Real Address Mode of 80286

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Protected Virtual Address Mode of 80286

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The concept of virtual memory is implemented using physical

memory that CPU can directly access and secondary memory

that is used to store data and program.

The program or data required for execution is fetched from

secondary memory to physical memory.

The process of fetching the required segment or data from the

secondary memory to physical memory is called swapping.

The process of storing back the partial results or data back to the

secondary memory is called un-swapping.

The virtual memory is allotted per task. 80286 is able to address

1GB of virtual memory per task.

The instructions like JUMP and CALL are taken care by

swapping and un-swapping procedures.


Protected Virtual Address Mode of 80286

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The huge programs are divided into smaller segments or pages which

are arranged in appropriate sequence and are swapped in or out of

primary memory as per requirements, for complete execution of

program.

The segments or pages divided are associated with a data structure

called as a descriptor.

The descriptor contains information about the segment or page.

A set of descriptors in a sequence describes the complete program. Set

of descriptors is called descriptor table.

All the descriptor tables are prepared and managed by the operating

system. There are different descriptors for different segments. Eg: data

segment descriptor for data segment, code segment descriptor for code

segment, etc.

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Physical Address Calculation in PVAM

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In protected mode, 80286 support virtual memory. Its virtual address

consists of a 16-bit selector and 16-bit offset. The Memory Management

Unit (MMU) uses 14 MSB‟s of selector to access a descriptor for required

segment in a table of descriptors.

The descriptor contains :

1. 24-bit physical base address

2. the privilege level

3. segment limit

4. segment type

It also stores the information, if the segment is present in the physical

memory or not at an instant of time. Also the information about the

segment if it was swapped in past, is also stored in the descriptor.

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A segment with lower privilege level is not allowed to

access the segment with higher privilege level to offer

protection of the segment from unauthorized

accesses.

The segment base address is a 24-bit pointer that

addresses the first location in the segment. This 24-bit

segment base address is added with 16-bit offset to

calculate a 24-bit physical address.

The descriptors are automatically referred by the CPU

when a segment register is loaded with a selector.


80386-The 32-Bit Processor

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The 16-bit word length of 80286 put limitations on

its operating speed.

However, the development of advanced applications

and technology demanded high speed machines,

with a more powerful instruction set and all the

above features of 80286.

Also as we have noted earlier, although 80286 can

be operated in both real and protected virtual mode,

the procedure of switching from real to protected

mode involves a lot of overheads.

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80386-The 32-Bit Processor Cont..

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In due course of time, the semi conductor

technology could support the fabrication of a CPU

with a 32-bit word size and higher operating

frequency, resulting in a higher speed of operation.

Thus the 32-bit processor 80386 was born.

In the first 32-bit processor 80386, designers have

tried to overcome the limitations of 80286.



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SALIENT FEATURES OF 80386DX:

The 80386DX is a 32-bit processor that supports, 8-bit/16-bit/32-bit data operands.

The 80386 instructions set is upward compatible with all itspredecessors.

The 80386 can run 8086 applications under protectedmode in its virtual 8086 mode of operation.

The memory management section of 80386 supports thevirtual memory, paging and four levels of protection,maintaining full compatibility with 80286.

The concept of paging which is introduced in 80386,enables it to organize the available physical memory intopages of size 4 Kbytes each, under the segmentedmemory.

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SALIENT FEATURES OF 80386DX:

The 80386 has an on-chip address translation cache.

The 80386 is available in another version----

80386SX----which has identical architecture as

80386DX with the difference that it has only a 16-bit

data bus and 24-bit address bus.

The low cost, low power version of 80386 may be

used in a number of application.

80386DX is available in a 132-pin grid array package

and has 20 MHz and 33 MHz versions.


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The internal architecture of 80386 is divided into threesections viz., central processing unit, memorymanagement unit and bus interface unit

The central processing unit is further divided into executionunit and instruction unit.

The execution unit has eight general purpose and eightspecial purpose registers which are either used forhandling data or calculating offset addresses.

The instruction unit decodes the opcode bytes receivedfrom the 16-byte instruction code queue and arrangesthem into a 3-instruction decoded-instruction queue, afterdecoding them so as to pass it to the control section forderiving the necessary control signals.

The barrel shifter increases the speed of all shift and rotateoperations.

Architecture of 80386

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The multiple/divide logic implements the bit-shift-

rotate algorithms to complete the operations in

minimum time.

Even 32-bit multiplications can be executed within

one microsecond by the multiply/divide logic.

The Memory Management Unit (MMU) consists of

a segmentation unit and a paging unit.

The segmentation unit allows the use of two

address components, viz. segment and offset for

relocability and sharing of code and data.

Architecture of 80386 Cont..


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The segmentation unit allows a maximum size of

4 Gbytes segments.

The paging unit organizes the physical memory in

terms of 4 Kbytes size each.

The paging unit works under the control of the

segmentation unit, i.e. each segment is further

divided into pages.

The virtual memory is also organized in terms of

segments and pages by the memory

management unit.


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The segmentation unit provides a four level protectionmechanism for protecting and isolating the system‟scode and data from those of the application program.

The paging unit converts linear addresses intophysical addresses.

The control and attribute PLA checks the privileges atthe page level.

Each of the pages maintains the paging information ofthe task.

The limit and attribute PLA checks segment limits andattributes at segment level to avoid invalid accessesto code and data in the memory segments.


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The bus control unit has a prioritizes to resolve

the priority of the various bus requests.

This controls the access of the bus.

The address driver drives the bus enable and

address signals A0-A31 .

The pipeline and dynamic bus sizing units handle

the related control signals.

The data buffers interface the internal data bus

with the system bus.



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The 80386 has eight 32-bit general purpose registers

which may even be used either as 8-bit or 16-bit

registers.

A 32-bit register, known as an extended register, is

represented by the register name with prefix E.

For example, a 32-bit register corresponding to AX is

EAX, similarly that corresponding to BX is EBX etc.

The AX now represents the lower of the 32-bit register

EAX.

While AH and AL have the same meaning as in the

case of 8086.

Register Organization of 80386

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The 80386 has eight 32-bit general purpose registerswhich may even be used either as 8-bit or 16-bitregisters.

Similarly, the registers BX,CX and DX have their 8-bit,16-bit and 32-bit representations.

The 16-bit registers BP,SP,SI and DI in thearchitecture of 8086, are now available with theirextended size of 32 bits and are named as EBP, ESP,ESI and EDI.

However, the names BP, SP, SI and DI represent thelower 16-bits of their counterparts, and can be usedas independent 16-bit registers.

The six segment registers available in 80386 are CS,SS, DS, ES, FS and GS.



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The CS and SS are the code and the stack

segment registers respectively, while DS,ES,FS,

and GS are the four data segment registers.

The use of these segment registers will be clear

when we study the physical address formation in

different modes.

A 16-bit or lower size registers are used by 16-bit

addressing, but the 32-bit addressing modes may

use all the register widths, i.e. 8,16 or 32 bits.


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The flag register of 80386 is a 32-bit register.

Out of the 32-bits, Intel has reserved bits D18 to D31,

D15,D5 and D3, While D1 is always set at 1.

The lower 15 bits (D0-D14) of this flag register are

exactly the same as the 80286 flag registers, right

from their position to the corresponding functions.

Only two extra new flags are added to the 80286 flag

register to derive the flag register of 80386 flag

register to derive the flag register of 80386. These are

the VM and RF flags.

Flag Register of 80386


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Virtual Mode Flag

If this flag is set, the 80386 enters the virtual 8086

mode within the protected mode.

This is to be set, the 80386 enters the virtual

8086 mode within the protected mode.

In this mode, if any privileged instruction is

executed an exception 13 is generated.

This bit can be set using the IRET instruction or

any task switch operation only in the protected

mode.


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Resume Flag

This Flag is used with the debug register breakpoints.

It is checked at the starting of every instruction cycle and ifit is set, any debug fault is ignored during the instructioncycle.

The RF is automatically reset after successful execution ofevery instruction, except for the IRET and POPFinstructions.

Also, it is not cleared automatically after the successfulexecution of JMP, CALL and INT instructions causing atask switch.

These instructions are used to set the RF to the valuespecified by the memory data available at the stack.

IOPL Flag bits indicate the privilege level of the current IOoperations.



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Internal 80386 Register Diagram

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Segment Descriptors

The segment descriptor registers of 80386 are not

available for programmers, rather, they are internally

used to store the descriptor information, like

attributes, limit and base addresses of segments.

The six segment registers have corresponding six 73-

bit descriptor registers.

Each of them contains 32-bit base address, 32-bit

base limit and 9-bit attributes. These are automatically

loaded when the corresponding segment registers are

loaded with selectors.

Internal 80386 Register Diagram Cont..


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Control Registers

The 80386 has three 32-bit control registers CR0,

CR2 and CR3 to hold global machine status

independent of the executed task.

The load and store instructions are available to

access these registers.

The control register CR1 is reserved for use in

future Intel processors.


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System Address Registers

Four special registers are defined to refer to the

descriptor tables supported by 80386.

The 80386 supports four types of descriptor table,

viz. global descriptor table (GDT), interrupt

descriptor table (IDT), local descriptor table (LDT)

and task state segment descriptor (TSS).



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Debug and Test Registers

Intel has provide a set of 8 debug registers forhardware debugging.

Out of these eight registers DR0 to DR7, two registersDR4and DR5are Intel reserved.

The initial four registers DR0to DR3 store fourprogram controllable breakpoint addresses, whileDR6 and DR 7 respectively hold breakpoint statusand breakpoint control information.

Two more test register are provided by 80386 forpage.

caching namely test control and test status register.


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After reset, the 80386 starts from memory locationFFFFFFF0H under the real address mode.

In the real mode, 80386 works as a fast 8086 with 32-bit registers and data types.

caching namely test control and test status register.

In real mode, the default operand size is 16 bit but 32-bit operands and addressing modes may be used withthe help of override prefixes.

The segment size in real mode is 64k, hence the 32-bit effective addressing must be less than0000FFFFFH. The real mode initializes the 80386and prepares it for protected mode.

Real Addressing Mode of 80386


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In the real mode, the 80386 can address at the most1Mbytes of physical memory using address lines A0-A19.

Paging unit is disabled in real addressing mode, andhence the real addresses are the same as thephysical addresses.

To form a physical memory address, appropriatesegment registers contents (16-bits) are shifted left byfour positions and then added to the 16-bit offsetaddress formed using one of the addressing modes,in the same way as in the 80386 real address mode.

The segment in 80386 real mode can be read, writeor executed, i.e. no protection is available.

Memory Addressing in Real Mode

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Any fetch or access past the end of the segment

limit generate exception 13 in real address mode.

The segments in 80386 real mode may be

overlapped or non-overlapped.

The interrupt vector table of 80386 has been

allocated 1Kbyte space starting from 00000H to

003FFH

Memory Addressing in Real Mode


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Physical Address Formation in Real Mode of 80386

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All the capabilities of 80386 are available for

utilization in its protected mode of operation.

The 80386 in protected mode support all the

software written for 80286 and 8086 to be

executed under the control of memory

management and protection abilities of 80386.

The protected mode allows the use of additional

instruction, addressing modes and capabilities of

80386.

Protected Mode of 80386


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In short, the segmentation scheme is a way of offering

protection to different types of data and code.

The 80386 also utilizes the three types of segment

descriptor tables as the 80286 does.

However, there are slight differences between the

80386 and the 80286 descriptor structures.

Again, associated with each descriptor, there are the

corresponding descriptor table registers, which are

manipulated by the operating system to ensure the

correct operation of the processor, and hence the

correct execution of the program.

Segmentation of 80386

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The three types of the 80386 descriptor tables are

listed as follows:

Global Descriptor Table(GDT)

Local Descriptor Table(LDT)

Interrupt Descriptor Table(IDT)

Their respective significances are also similar to

the corresponding descriptor table significances

in 80286.

Segmentation of 80386


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Paging is one of the memory management techniques used forvirtual memory multitasking operating system.

The segmentation scheme may divide the physical memory intoa variable size segments but the paging divides the memory intoa fixed size pages.

The segments are supposed to be the logical segments of theprogram, but the pages do not have any logical relation with theprogram.

The pages are just fixed size portions of the program module ordata.

The advantage of paging scheme is that the complete segmentof a task need not be in the physical memory at any time.

Only a few pages of the segments, which are required currentlyfor the execution need to be available in the physical memory.

Paging of 80386

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Thus the memory requirement of the task issubstantially reduced, relinquishing the availablememory for other tasks.

Whenever the other pages of task are required forexecution, they may be fetched from the secondarystorage.

The previous page which are executed, need not beavailable in the memory, and hence the spaceoccupied by them may be relinquished for other tasks.

Thus paging mechanism provides an effectivetechnique to manage the physical memory formultitasking systems.

Paging of 80386 Cont..


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Paging Unit

The paging unit of 80386 uses a two level tablemechanism to convert a linear address providedby segmentation unit into physical addresses.

The paging unit converts the complete map of atask into pages, each of size 4K. The task isfurther handled in terms of its page, rather thansegments.

The paging unit handles every task in terms ofthree components namely page directory, pagetables and page itself.


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Paging Descriptor Base Register

The control register CR2 is used to store the 32-

bit linear address at which the previous page fault

was detected.

The CR3is used as page directory physical base

address register, to store the physical starting

address of the page directory.



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Paging Directory

This is at the most 4Kbytes in size. Each directory

entry is of 4 bytes, thus a total of 1024 entries are

allowed in a directory.

The upper 10 bits of the linear address are used

as an index to the corresponding page directory

entry.

The page directory entries point to page tables.


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Page Tables

Each page table is of 4Kbytes in size and many contain amaximum of 1024 entries.

The page table entries contain the starting address of thepage and the statistical information about the page.

The upper 20 bit page frame address is combined with thelower 12 bit of the linear address.

The address bits A12-A21 are used to select the 1024page table entries.

The page table can be shared between the tasks.

The P bit of the above entries indicate, if the entry can beused in address translation.

If P=1, the entry can be used in address translation,otherwise it cannot be used.



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Page Tables

The P bit of the currently executed page is alwayshigh.

The accessed bit A is set by 80386 before anyaccess to the page.

If A=1, the page is accessed, else un-accessed.

The D bit ( Dirty bit) is set before a write operationto the page is carried out. The D-bit is undefinedfor page director entries.

The OS reserved bits are defined by the operatingsystem software.


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Page Tables

The User / Supervisor (U/S) bit and read/write bit are

used to provide protection. These bits are decoded to

provide protection under the 4 level protection model.

The level 0 is supposed to have the highest privilege,

while the level 3 is supposed to have the least

privilege.

This protection provide by the paging unit is

transparent to the segmentation unit.


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