MicroprocessorsMicroprocessors

AMD HammerAMD Hammer

AMD’s High Stakes RISC EntryAMD’s High Stakes RISC Entry

May 2May 2ndnd, 2002, 2002

AMD HammerAMD Hammer

For all the usual reasons, AMD feels that it For all the usual reasons, AMD feels that it must address 64-bit computing.must address 64-bit computing.

AMD has decided NOT to follow IntelAMD has decided NOT to follow Intel Instead it will generate its own 64-bit Instead it will generate its own 64-bit

version of the ia32 architecture.version of the ia32 architecture. The general name is HammerThe general name is Hammer Sledge-hammer, the first chip, soon!Sledge-hammer, the first chip, soon! A reference for full information:A reference for full information: http://www.amd.com/us-en/assets/content_typehttp://www.amd.com/us-en/assets/content_type//

DownloadableAssets/MPF_Hammer_Presentation.PDownloadableAssets/MPF_Hammer_Presentation.PDFDF

Public SpecificationPublic Specification

All aspects of this chip developed in All aspects of this chip developed in publicpublic

Announced at Linux WorldAnnounced at Linux WorldUses GNU/Linux as native 64-bit OSUses GNU/Linux as native 64-bit OSPublic specification at Public specification at www.x86-64.orgwww.x86-64.orgX86-64 is the official designationX86-64 is the official designation

Hammer is like Pentium (wi different Hammer is like Pentium (wi different models)models)

X86-64 is like ia32 or ia64 (architecture)X86-64 is like ia32 or ia64 (architecture)

Hammer BasicsHammer Basics

In the same way that the 386 extended In the same way that the 386 extended the 286 architecture from 16 to 32 bits, the 286 architecture from 16 to 32 bits, Hammer extends from 32-64 bits.Hammer extends from 32-64 bits.

This is NOT a new architectureThis is NOT a new architectureHammer is 100% upwards compatible Hammer is 100% upwards compatible

with the ia32, and can run any ia32 with the ia32, and can run any ia32 program unchanged.program unchanged.

And the ia32 program will run fast, And the ia32 program will run fast, getting many of the benefits of the getting many of the benefits of the hammer.hammer.

The Move to 64-bitThe Move to 64-bit

EnhancementsEnhancementsAdd 8 new integer registersAdd 8 new integer registersAdd PC relative addressingAdd PC relative addressingAdd full support for SSE/SSEII floating-Add full support for SSE/SSEII floating-

pointpointIncluding 16 registersIncluding 16 registers

Additional registers added with prefixesAdditional registers added with prefixesPrefixes specify addressing modesPrefixes specify addressing modesPrefixes specify additional registersPrefixes specify additional registers

64-bit Addressing64-bit Addressing

48-bit virtual addresses48-bit virtual addressesAs opposed to 32-bit on ia32As opposed to 32-bit on ia32Allows 256 terabytes of virtual memoryAllows 256 terabytes of virtual memory(but not a full 64 bits, though this could be (but not a full 64 bits, though this could be

added relatively easily later, since added relatively easily later, since addresses are always handled in 64 bit addresses are always handled in 64 bit registers)registers)

40-bit physical addresses40-bit physical addressesAs opposed to 32-bit on ia32As opposed to 32-bit on ia32Allows for one terabyte (1000 gig) phys Allows for one terabyte (1000 gig) phys

memmem

Register StructureRegister Structure

16 SSE Floating-Point registers 128-bits16 SSE Floating-Point registers 128-bits16 integer registers16 integer registers

E.g. RAXE.g. RAXLow 32 bits is EAXLow 32 bits is EAXLow 16 bits is AX (and also AH, AL)Low 16 bits is AX (and also AH, AL)

Extra registers are R8-R15Extra registers are R8-R158 x87 registers for compatibility (80 8 x87 registers for compatibility (80

bits)bits)One 64-bit program counterOne 64-bit program counter

Low order 32 bits is EIPLow order 32 bits is EIP

Advantages of CISC and RISCAdvantages of CISC and RISC

Code density of CISCCode density of CISCRegister usage and ABI models of Register usage and ABI models of

RISCRISCEasy application of standard Easy application of standard

optimization algorithms.optimization algorithms.

SpecInt 2000 Code SpecInt 2000 Code GenerationGeneration

Code size grows less than 10%Code size grows less than 10%Due mostly to instruction prefixesDue mostly to instruction prefixes

Static instruction count shrinks by 10%Static instruction count shrinks by 10%Dynamic instruction count shrinks by 5%Dynamic instruction count shrinks by 5%Dynanic load/store count shrinks by 20%Dynanic load/store count shrinks by 20%All without specific code optimizationsAll without specific code optimizations

Summary (AMD advertising Summary (AMD advertising ))

Processor is fully x86 capableProcessor is fully x86 capableFull native performance with 32-bit appsFull native performance with 32-bit appsFull compatibility (BIOS, OS, Drivers)Full compatibility (BIOS, OS, Drivers)

Flexible deploymentFlexible deploymentBest in class 32-bit x86 performanceBest in class 32-bit x86 performanceExcellent 64-bit instruction execution Excellent 64-bit instruction execution

when neededwhen neededServer/Workstation/Desktop/MobileServer/Workstation/Desktop/Mobile

Share common architecture, OS, etcShare common architecture, OS, etc

ArchitectureArchitecture

Nine pipelines (3 fpt, 3 integer, 3 address)Nine pipelines (3 fpt, 3 integer, 3 address) Integer pipeline has 12 stages (very deep)Integer pipeline has 12 stages (very deep)Accurate branch predictionAccurate branch prediction

A lot of effort put in here!A lot of effort put in here!Large TLB (virtual memory lookup table)Large TLB (virtual memory lookup table)

512 entries for data512 entries for data512 entries for instructions512 entries for instructions

Integrated memory controllerIntegrated memory controller

MemoryMemory

All memory is ECC protectedAll memory is ECC protectedL1 Data cacheL1 Data cacheL2 cacheL2 cacheDRAMDRAM

ECC stands for error correcting codeECC stands for error correcting codeDetect all 2 bit errorsDetect all 2 bit errorsAuto-correct any single bit errorAuto-correct any single bit error

Useful for server/critical applicationsUseful for server/critical applications

Input-Output and Multi-Input-Output and Multi-ProcessingProcessing

Very high bandwidth I/OVery high bandwidth I/OPlanned for server applicationsPlanned for server applications

Multi-processing built inMulti-processing built inCan have 2-8 processorsCan have 2-8 processorsMemory appears flat and fully coherentMemory appears flat and fully coherent25 gigabytes/second between 25 gigabytes/second between

processorsprocessors8 gigabytes/second to/from memory8 gigabytes/second to/from memory

ConclusionConclusion

AMD and Intel go head to headAMD and Intel go head to headBut with totally different technologiesBut with totally different technologiesFascinating Fascinating

Many other references on netMany other references on netDo google search for AMD HammerDo google search for AMD HammerA good non-AMD reference isA good non-AMD reference is

http://www.anandtech.com/showdoc.html?http://www.anandtech.com/showdoc.html?i=1546i=1546