Microprocessor system architectures – IA32 introduction Jakub Yaghob.
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Transcript of Microprocessor system architectures – IA32 introduction Jakub Yaghob.
![Page 1: Microprocessor system architectures – IA32 introduction Jakub Yaghob.](https://reader035.fdocuments.us/reader035/viewer/2022062517/56649f0b5503460f94c1e7b9/html5/thumbnails/1.jpg)
Microprocessor system architectures –
IA32 introduction
Jakub Yaghob
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Architectures
IA-32 Today commonly used AMD64/Intel 64
AMD has attempted to widen IA-32 to 64 bits, very unseemly extended in the system part
IA-64 Very complicated application and system architecture,
coming from HP PA-RISC, used in servers Maybe some others
E.g. SPARC v8+v9, ARM, PowerPC
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IA-32 part content
Modes of operation Memory management: segmentation Memory management: paging Multitasking Exception and interrupt handling Debugging and performance monitoring Compatibility modes Advanced parts (multiprocessing, caches,
virtualization)
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What is system architecture?
System architecture Application architecture System control registers System data structures System instructions
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System architecture overview 32b - I
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System architecture overview 32b - II
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System architecture overview 64b - I
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System architecture overview 64b - II
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System architecture overview 64b - III
Model specific registers
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Operating modes - I Protected mode
Native for i386+ processors Full 32-bit mode with system resources protection
Real mode Backward compatibility with 8086-80286 No protection Starting mode for CPU
Virtual 8086 mode Running inside the protected mode “Simulation” of the real mode
System management mode Transparent mechanism for implementing power management Activation of an external system interrupt pin Separate address space
Long/IA-32e mode Compatibility and full 64-bit mode
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Operating modes - II
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Operating modes - III
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System flags in EFLAGS/RFLAGS
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Memory management system registers
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Control registers – CR0
PE – Protection Enable MP – Monitor coProcessor EM – EMulation TS – Task Switched ET – Extension Type NE – Numeric Error
WP – Write Protect AM – Alignment Mask NW – Not Write-through CD – Cache Disabled PG - PaGing
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Effects of EM, MP and TS
Coprocessor emulation Context-switch support
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Control registers – CR2 and CR3
Paging
PWT – Page-level Writes Transparent PCD – Page-level Cache Disable
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Control registers – CR4 Extension
VME – Virtual-8086 Mode Extensions PVI – Protected-mode Virtual Interrupts TSD – Time Stamp Disable DE – Debugging Extensions PSE – Page Size Extensions PAE – Physical Address Extension MCE – Machine-Check Enable PGE – Page Global Enable PCE – Performance-monitoring Counter
Enable OSFXSR – Operating System support for
FXSAVE, FXRSTOR
OSXMMEXCPT – OS support for unmasked SIMD floating-point EXCePTion
VMXE – VMX Enable SMXE – SMX Enable FSGSBASE – Enable instructions
RDxSBASE, WRxSBASE (x=F/G) PCIDE – Enable PCID OSXSAVE – XSAVE and Processor
Extended States-Enable Bit SMEP – Enable supervisor-mode
execution prevention
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Extended Control Registers – XCR0
Paging
x87 – x87 state supported by CPU, must be 1, otherwise #GP
SSE – MXCSR and XMM registers supported by XSAVE/XRESTOR
AVX – AVX instructions, XSAVE/XRESTOR handle AVX state
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System instructions
LLDT, SLDT LGDT, SGDT LTR, STR LIDT, SIDT MOV CRn LMSW, SMSW CLTS ARPL, LAR, LSL VERR, VERW MOV DRn INVD, WBINVD
INVLPG HLT LOCK (Prefix) RSM RDMSR, WRMSR RDPMC, RDTSC , RDTSCP IN, OUT, INS, OUTS CLI, STI IRET XSETBV, XGETBV