Microprocessor Performance

EEET2039 Embedded System Design

Microprocessor Performance

Professor: Paul Beckett

Student: Wilson Castillo Bautista

Email: [email protected]

Subject Code: EEET2039 Embedded Systems Design

Course Code: MC047

Master of Engineering (Information Technology)

Melbourne, September 19th, 2006

2 of 32

Melbourne, 19th September, 2006

Professor: Paul Becket

Assignment1: Microprocessor Performance

)

Student: Wilson Castillo (s3143667)

Subject: EEET2039 Embedded Systems Design

RMIT University © 2006

School of Electrical and Computer Engineering

Table of Contents

Microprocessor Performance ...............................................................................................................5

1 Introduction ......................................................................................................................................5

2 Scope.................................................................................................................................................5

3 Assembler Code...............................................................................................................................6

4 Cycles calculations. ........................................................................................................................6

5 Evaluation Performance ................................................................................................................7

5.1 68HC12 ....................................................................................................................................7

5.2 6805..........................................................................................................................................9

5.3 8051........................................................................................................................................10

5.4 DCS89C420...........................................................................................................................11

5.5 ST62 ........................................................................................................................................12

5.6 AT90S8515 .............................................................................................................................13

5.7 PIC12C5X ..............................................................................................................................15

5.8 TMS370...................................................................................................................................16

5.9 C166.......................................................................................................................................18

6 Performance Comparison ...........................................................................................................19

6.1 Time........................................................................................................................................19

6.2 Memory .................................................................................................................................20

7 Conclusions.....................................................................................................................................21

8 References ......................................................................................................................................23

9 Annex – Assembler List 68HC12 ...................................................................................................24

10 Annex – Assembler List 68HC05 ...............................................................................................25

11 Annex – Assembler List 80C51.................................................................................................26

12 Annex – Assembler List DS89C420 ..........................................................................................27

13 Annex – Assembler List PIC12C5X...........................................................................................28

14 Annex – Assembler List C166 ...................................................................................................29

15 Annex – Compilation of bubble C program for ARM processor......................................30

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Table of Figures

Figure 1: CPU Execution time in function of Clock cycle time .......................................................5

Figure 2: CPU Execution time in function of Clock rate ...................................................................6

Figure 3: Bubble sort algorithm and its implementation in C. (Beckett, P., EEET2039,

Embedded System Lecture Notes) ......................................................................................................6

Figure 4: Performance Comparison (time).......................................................................................19

Figure 5: Memory Comparison............................................................................................................20

Figure 6: Assembler list for 68HC12 .....................................................................................................24

Figure 7: Assembler list for 68HC12 .....................................................................................................25

Figure 8: Assembler list for 8051...........................................................................................................26

Figure 9: Assembler list for DS89C420 .................................................................................................27

Figure 10: Assembler list for PIC12C5X ...............................................................................................28

Figure 11: Assembler list for C166........................................................................................................29

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Table of tables

Table 1: Pseudo-code to calculate number of instructions. (Beckett, P., EEET2039,

Embedded System Lecture Notes) ......................................................................................................7

Table 2: Assembler code for 68HC12...................................................................................................8

Table 3: Cycles Calculations for 68HC12 ............................................................................................8

Table 4: Assembler code for 68HC05...................................................................................................9

Table 5: Cycles Calculations for for 68HC05 ....................................................................................10

Table 6: Assembler code for 8051 ......................................................................................................10

Table 7: Cycles Calculations for 8051................................................................................................11

Table 8: Assembler code for DCS89C420 .........................................................................................12

Table 9: Cycles Calculations for DCS89C420...................................................................................12

Table 10: Assembler code for ST62 .....................................................................................................13

Table 11: Cycles Calculations for ST62 ..............................................................................................13

Table 12: Assembler code for AT90S8515..........................................................................................14

Table 13: Cycles Calculations for AT90S8515 ...................................................................................15

Table 14: Assembler code for PIC12C5X...........................................................................................16

Table 15: Cycles Calculations for PIC12C5X ....................................................................................16

Table 16: Assembler code for TMS370 ...............................................................................................17

Table 17: Cycles Calculations for TMS370.........................................................................................17

Table 18: Assembler code for C166 ...................................................................................................18

Table 19: Cycles Calculations for TMS370.........................................................................................19

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Microprocessor Performance

1 Introduction

Microprocessors are everywhere around the world and more precisely they are in every

embedded system that we can imagine. Moreover, they are the main component to look

at when you are evaluating a system or when you are planning to create a new one. For

instance, evaluating microprocessor performance gives the designer a better sense to

select the device that fits the requirements of a embedded system design. However,

assessing performance of a microprocessor can be in some way challenging (Patterson

and Hennessy, 2005). This report will evaluate performance of ten different processors.

2 Scope

This report will evaluate the performance of the following 10 different processors:

� 68HC12

� 6805

� 8051

� DS89C420

� ST62

� AT90S8515

� PIC12C5xx

� TMS370

� Siemens C166

� ARM7

The way to measure performance can be defined differently. For this report point of view

the way of measuring performance will be done using time as measurement unit. For

instance, every processor will be evaluated in the amount of time that it takes to execute a

program. The following formula will be used to evaluate execution time (Patterson and

Hennessy, 2005):

= x CPU execution time CPU clock cycles

Clock cycletime for a program for a program

Figure 1: CPU Execution time in function of Clock cycle time

Alternatively, it could be defined in the following way.

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= CPU execution time CPU clock cycles for a program

Clock rate for a program

Figure 2: CPU Execution time in function of Clock rate

The program in this case is the bubble sort algorithm:

Figure 3: Bubble sort algorithm and its implementation in C. (Beckett, P., EEET2039, Embedded System Lecture

Notes)

3 Assembler Code

The way to evaluate performance between different processors is to take a program and

translate into its assembly code. In this particular case to take the bubble sort algorithm,

written in C code. However, “coding in assembler is an art” (Becket, P., EEET2039

Embedded System Design Lecture, 11th September). For instance, one of the factors that

affect execution time is the assembler code and this is done by the programmer.

4 Cycles calculations.

In order to calculate the number of cycles per program it is necessary to get the number of

cycles per instruction. Using the following table it is possible to get the total number of

cycles that the bubble sort algorithm takes in each processor.

Line Label Pseudo Code Cycles/

PseudoCode Cycles Calculation

1 START: load i, 1; Zvar =ZVar

2 _L5

3 compare i, sizeof(Data) AVar =AVar*SzData

4 branch to _L1, if i>=sizeof(Data)

BVar BVarN =BVar*1+BVarN*(SzData-1)

5 clear j CVar =CVar*(SzData-1)

6 _L4

void main (void){

unsigned char i, j;

unsigned char Data[7] = {7,6,3,4,5,2,1};

unsigned char tmp;

for (i=1; i<sizeof(Data); i++){

for (j=0; j+i<sizeof(Data); j++){

if (Data[j+1] < Data[j]){

tmp = Data[j];

Data[j] = Data[j+1];

Data[j+1] = tmp;

}

}

}

}

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7 compare i+j, sizeof(Data) DVar =DVar*(NumIterations+SzData-1)

8 branch to _L2, if (i+j)>=sizeof(Data)

EVar EVarN =EVarN*NumIterations+EVar*(SzData-1)

9 compare Data[j], Data[j+1] FVar =FVar*NumIterations

10 branch to _L3, if Data[i]<=Data[j+1]

GVar =GVarN*NumSwaps+GVar*(NumIterations-NumSwaps)

11 swap Data[j+1], Data[j] HVar =HVar*NumSwaps

12 _L3

13 increment j IVar =IVar*NumIterations

14 branch to _L4 JVar =JVar*NumIterations

15 _L2

16 increment i KVar =KVar*(NumIterations-1)

17 branch to _L5 LVar =LVar*(NumIterations-1)

18 _L1

19 branch to _L1 MVar =MVar

Table 1: Pseudo-code to calculate number of instructions. (Beckett, P., EEET2039, Embedded System Lecture

Notes)

Where:

( )( ) 1

1

NumIterations 21Sizeof Data

i

i

−

=

= =∑ and

xVarN ⇔ means cycles value when the branch is not taken.

SzData = 7, seven numbers to be ordered.

For the purpose of this report the numbers where organized in the following way

{7,6,3,4,5,2,1}. For instance:

NumSwaps = 18

5 Evaluation Performance

As it had been described before evaluating performance of a system could be done

through different ways. However, this report will focus in execution time of the bubble sort

algorithm showed in Figure 3.

The following are the results per microprocessor:

5.1 68HC12

µ= =1

Clock Cycle Time * 2 21

sMhz

Line Label/Var Instruction Description Bytes Cycles

1 ORG $0000 ;RAM Memory

2 Var_i: FCB 0 ;HC12 1

3 Var_j: FCB 0 1

4 Var_temp: FCB 0 1

5 Data: FCB 7,6,3,4,5,2,1

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6 EndData:

7 SzData: EQU (EndData-Data)

8 ORG $FF00 ;ROM Memory

BYTES MEMORY RAM 3

9 START:

10 BSort:

11 LDAA #1 ;i = 1 2 1

12 STAA Var_i ; 2 2

13 _L5: LDAA Var_i ; 2 3

14 CMPA #SzData ;if (i<SzData) 2 1

15 BGE _L1 ; { 2 3/1

16 CLR Var_j ; j=0 3 3

17 _L4: LDAA Var_j ; 2 3

18 ADDA Var_i ; 2 3

19 CMPA #SzData ; i+j 2 1

20 BGE _L2 ; if (i+j<SzData) 2 3/1

21 LDAB Var_j ; { 2 3

22 LDX #Data ; 3 2

23 ABX ; 2 2

24 LDAA 0,X ; X = &Data[j] 3 3

25 LDAB 1,X ; A = Data[j] 3 3

26 CBA ; B = Data[j+1] 2 2

27 BLO _L3 ; if (A>B) 2 3/1

28 STAA 1,X ; { Unsigned 3 3

29 STAB ,X ; A->B 3 3

30 _L3: INC Var_j ; B->A } 3 4

31 BRA _L4 ; j++ 3 3

32 _L2: INC Var_i ; } 3 4

33 BRA _L5 ; i++ 2 3

34 _L1: BRA _L1 ; } 2 3

35 ORG $FFFE ;

36 FDB START ;reset vector

;set to start program

BYTES MEMORY ROM 57

Table 2: Assembler code for 68HC12

Line Label Pseudo Code Cycles/Var Cycles/Var Total

1 START: load i, 1; Zvar 3 3

2 _L5

3 compare i, sizeof(Data) A 4 28

4 branch to _L1, if i>=sizeof(Data) B 3 BN 1 9

5 clear j CVar 3 18

6 _L4

7 compare i+j, sizeof(Data) DVar 7 189

8 branch to _L2, if (i+j)>=sizeof(Data) EVar 3 EVarN 1 39

9 compare Data[j], Data[j+1] FVar 15 315

10 branch to _L3, if Data[i]<=Data[j+1] GVar 3 GVarN 1 27

11 swap Data[j+1], Data[j] HVar 6 108

12 _L3

13 increment j IVar 4 84

14 branch to _L4 JVar 3 63

15 _L2

16 increment i KVar 4 80

17 branch to _L5 LVar 3 60

18 _L1

19 branch to _L1 MVar 3 3

Total Cycles 1026

Table 3: Cycles Calculations for 68HC12

CPU Execution Time = 1026 * 2µs = 2.052ms

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5.2 6805

µ= =1


sMhz


ORG $0000 ;68HC05

1 Var_i DB $0 1

2 Var_j DB $0 1

3 temp DB $0 1

4 temp2 DB $0 1

5 Data DB 7,2,3,4,5,6,1

6 EndData DB $0

7 SzData EQU EndData - Data

BYTES MEMORY RAM 4

8 ORG $FF00

9 START LDA #1 ;i=1 2 2

10 STA Var_i 2 4

11 _L5 LDA Var_i ;A=i 2 3

12 CMP #SzData ;i-SzData 2 3

13 BHS _L1 ;if i>= SzData finish 2 3/1

14 CLR Var_j ;j=0 2 5

15 LDX #Data ;X=Data[0] 2 2

16 _L4 LDA Var_j ;A=j 2 3

17 ADD Var_i ;i+j 2 3

18 CMP #SzData ;(i+j) - SzData 2 3

19 BHS _L2 ;if (i+j)>= SzData, _L2 2 3/1

20 LDA ,X ;A=Data[j] 1 3

21 INCX ;X=Data[j+1] 1 3

22 CMP ,X ;Data[j]-Data[j+1] 1 3

23 BLS _L3 ;if Data[j]>Data[j+1], _L2

2 3/1

24 LDA ,X ;A=Data[j+1] 1 3

25 STA temp ;temp=Data[j+1] 1 3

26 DECX ;X=Data[j] 1 3

27 LDA ,X ;A=Data[j] 1 3

28 STA temp2 ;temp2=Data[j] 1 3

29 LDX temp ;Data[j]=temp 2 3

30 INCX ;X=Data[j+1] 1 3

31 LDX temp2 ;Data[j+1]=temp2 2 3

32 _L3 INC Var_j ;j+1 2 5

33 BRA _L4 2 3

34 _L2 INC Var_i ;i+1 2 5

35 BRA _L5 2 3

36 _L1 BRA _L1 ;end 2 3

37 BYTES MEMORY ROM 47

Table 4: Assembler code for 68HC05



2 _L5



5 clear j CVar 7 42

6 _L4


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)









12 _L3



15 _L2



18 _L1


Total Cycles 1360

Table 5: Cycles Calculations for for 68HC05


5.3 8051

µ= =1

Clock Cycle Time *12 121

sMhz


1 Var_i EQU R2 1

2 Var_j EQU R3 1

3 PtrData EQU 5 1

4 Data FCB 7,6,3,4,5,2,1

5 EndData

6 SzData EQU (EndData-Data)

7 MEMORY RAM BYTES 3

8 START:

MOV Var_i, #1 ;i=1 2 1

9 _L5 MOV A, Var_i ;A=Var_i e.g. A<-i 1 1

10 CLR C ; Clear Carry 1 1

11 SUB A, #SzDATA ; i-SzDATA 2 2

12 JNC _L1 2 3

13 MOV Var_j, #0 ;j=0 2 2

14 _L4 MOV A, Var_j ;A<-j 1 1

15 ADD A, Var_i ;i+j 1 1

16 CLR C ;Clear Carry 1 1

17 SUB A, #SzDATA ;(i+j) - SzDATA 2 2

18 JNC _L2 ;{ 2 3

19 MOV A, Var_j ;A<-j 1 1

20 MOV @PrtData, #Data 2 2

21 ADD A, PrtData ;Data[j] 1 1

22 INC PrtData ;Data[j+1] 1 1

23 SUB A, @PrtData ;Data[j]-Data[j+1] 1 2

24 JC _L3 2 3

25 XCH A, @PrtData ;A<->Data[j+1] 1 3

26 DEC PrtData ;Data[j] 1 1

27 MOV @PrtData, A ;Data[j]<-A 1 1

28 _L3 INC Var_j ;j++ 1 1

29 SJMP _L4 ;} 2 3

30 _L2 INC Var_i ;i++ 1 1

31 SJMP _L5 ;} 2 3

32 _L1 SJMP _L1 2 3


Table 6: Assembler code for 8051

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)







2 _L5



5 clear j CVar 2 12

6 _L4






12 _L3



15 _L2



18 _L1


Total Cycles 755

Table 7: Cycles Calculations for 8051


5.4 DCS89C420

µ= =1


sMhz


1 Var_i EQU R2 1

2 Var_j EQU R3 1

3 PtrData EQU 5 1

4 Data FCB 7,6,3,4,5,2,1

5 EndData



8 START:

MOV Var_i, #1 ;i=1 2 1

9 _L5 MOV A, Var_i ;A=Var_i e.g. A<-i 1 1

10 CLR C ; Clear Carry 1 1

11 SUB A, #SzDATA ; i-SzDATA 2 2

12 JNC _L1 2 3

13 MOV Var_j, #0 ;j=0 2 2

14 _L4 MOV A, Var_j ;A<-j 1 1


16 CLR C ;Clear Carry 1 1

17 SUB A, #SzDATA ;(i+j) - SzDATA 2 2

18 JNC _L2 ;{ 2 3

19 MOV A, Var_j ;A<-j 1 1

20 MOV @PrtData, #Data 2 2

21 ADD A, PrtData ;Data[j] 1 1

22 INC PrtData ;Data[j+1] 1 1

23 SUB A, @PrtData ;Data[j]-Data[j+1] 1 2

24 JC _L3 2 3

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25 XCH A, @PrtData ;A<->Data[j+1] 1 3

26 DEC PrtData ;Data[j] 1 1

27 MOV @PrtData, A ;Data[j]<-A 1 1

28 _L3 INC Var_j ;j++ 1 1

29 SJMP _L4 ;} 2 3

30 _L2 INC Var_i ;i++ 1 1

31 SJMP _L5 ;} 2 3

32 _L1 SJMP _L1 2 3


Table 8: Assembler code for DCS89C420



2 _L5



5 clear j CVar 2 12

6 _L4






12 _L3



15 _L2



18 _L1


Total Cycles 755

Table 9: Cycles Calculations for DCS89C420


5.5 ST62

µ= =1

Clock Cycle Time *13 13.1

sMhz


1 Var_i EQU 84H 1

2 Var_j EQU 85H 1

3 temp EQU 86H 1

4 temp2 EQU 87H 1

3 PtrData EQU 5

4 Data FCB 7,6,3,4,5,2,1

5 EndData



8 START:

LDI Var_i,1 ;i=1 3 4

9 _L5 LDA, Var_i ;A=Var_i e.g. A<-i 2 4

10 SUBI A, #SzData ; i-SzDATA 2 4

12 JRNC _L1 1 2

LD X, #Data 1 4

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13 CLR Var_j ;j=0 3 4

14 _L4 LDA, Var_j ;A<-j 2 4


17 SUBI A, #SzData ;(i+j) - SzDATA 2 4

18 JRNC _L2 ;{ 1 2

19 LDA, (X) ;A<-j 1 4

20 LD temp, A 2 4

21 INC X ;Data[j] 1 4

22 LDA, (X) ;Data[j+1] 1 4

23 SUBA, temp ;Data[j]-Data[j+1] 2 4

24 JRNC _L3 1 2

25 LDA, (X) ;A<->Data[j+1] 1 4

26 LD temp2,A ;Data[j] 2 4

27 LD A,temp ;Data[j]<-A 2 4

28 LD(X),A 1 4

29 DEC X 1 4

30 LD A, temp2 2 4

31 LD(X),A 1 4

32 INC X 1 4

33 _L3 INC Var_j ;j++ 2 4

34 JP _L4 ;} 2 4

35 _L2 INC Var_i ;i++ 2 4

36 JP _L5 ;} 2 4

37 _L1 JP _L1 2 4

BYTES MEMORY ROM 48

Table 10: Assembler code for ST62



2 _L5



5 clear j CVar 8 48

6 _L4






12 _L3



15 _L2



18 _L1


Total Cycles 1870

Table 11: Cycles Calculations for ST62


5.6 AT90S8515

µ= =1


sMhz

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1 .DEF Var_i = R16 1

2 .DEF Var_j = R17 1

3 .DEF temp = R18 1

4 .DEF temp2 = R19 1

5 .DEF Ylow = R28 1

6 .DEF Yhigh = R29 1

7 BYTES MEMORY RAM 6

8 .DSEG

9 ORG 0x20

10 Data: .DB 1,5,4,3,2,6,7

11 SzDATA EQU (DataEnd-Data)

12 .CSED Bytes Cycles

13 ORG 0x20

14 START:

15 LDI Var_i, 1 ;i=1 2 1

16 _L5 CPI Var_i, SzDATA ;i - SzDATA 2 1

17 BRSH _L1 ;if (i >= SzDATA) 2 1/2

18 CLR Var_j ;j=0 2 1

19 LDI Ylow, low(Data) ;Y = Addres Data 2 1

20 LDI Yhigh, High(Data) 2 1

21 _L4 MOV temp, Var_j ;temp = j 2 1

22 ADD temp, var_i ;i+j 2 1

23 CPI temp, SzDATA ;(i+j) - SzDATA 2 1

24 BRSH _L2 ;if ((i+j)<= SzDATA) 2 1/2

25 LD temp, Y+ ;temp = Data[j] 2 2

26 LD temp2, Y ;temp2 = Data[j+1] 2 2

27 CP temp, temp2 ;Data[j]-Data[j+1] 2 1

28 BRLO _L3 ;if (Data[j] >= Data[j+1])

2 1/2

29 ST Y, temp ;Data[j+1] = Data[j] 2 2

30 ST -Y, temp2 ;Data[j] = Data[j+1] 2 2

31 LD temp, Y+ ;Increment Y 2 2

32 _L3 INC Var_j ;j++ 2 1

33 RJMP _L4 ;} 2 2

34 _L2 INC Var_i ;i++ 2 1

35 RJMP _L5 ;} 2 2

36 _L1 RJMP _L1 ;End 2 2

BYTES MEMORY ROM 44

Table 12: Assembler code for AT90S8515



2 _L5

3 Compare i, sizeof(Data) A 1 7


5 clear j CVar 3 18

6 _L4

7 Compare i+j, sizeof(Data) DVar 3 81


9 Compare Data[j], Data[j+1] FVar 5 105



12 _L3



15 _L2



18 _L1

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Total Cycles 510

Table 13: Cycles Calculations for AT90S8515


5.7 PIC12C5X

µ= =1


sMhz


1 Var_i EQU 07H 1

2 Var_j EQU 08H 1

3 temp EQU 09H 1

4 temp2 EQU 0AH 1

5 FSR EQU 04H 1

6 INDR EQU 00H 1


W EQU H'0000'

F EQU H'0001'

INDF EQU H'0000'

C EQU H'0000'

Z EQU H'0002'

DC EQU H'0001'

STATUS EQU H'0003'

8 DATA

9 ORG 0x20

10 Data: .DB 1,5,4,3,2,6,7

11 SzDATA EQU (DataEnd-Data)

12 Bytes Cycles

14 START:

15 MOVLW #1 ;i=1 1.5 1

MOVWF Var_i 1.5 1

16 _L5 MOVLW #SzData ;i - SzDATA 1.5 1

SUBWF Var_i,W 1.5 1

17 BTFSZ STATUS,C ;if (i >= SzDATA) 1.5 1

GOTO _L1 1.5 1

18 CLRF Var_j ;j=0 1.5 1

21 _L4 MOVF Var_j,W ;temp = j 1.5 1

22 ADDWF Var_i,W ;i+j 1.5 1

MOVWF temp 1.5 1

MOVLW #Data 1.5 1

MOVWF FSR 1.5 1

MOVLW #SzData 1.5 1

23 SUBWF temp,W ;(i+j) - SzDATA 1.5 1

24 BTFSS STATUS,C ;if ((i+j)<= SzDATA) 1.5 1

GOTO _L2 1.5 1

25 MOVF FSR,W 1.5 1

26 INC FSR,F 1.5 1

27 SUBWF FSR,W 1.5 1

28 BTFSS STATUS,C 1.5 1

29 GOTO _L3 1.5 1

30 MOVF FSR,W 1.5 1

31 MOVWF temp ;temp = Data[j] 1.5 1

DECF FSR,F ;temp2 = Data[j+1] 1.5 1

MOVF FSR,W ;Data[j]-Data[j+1] 1.5 1

MOVWF temp2 ;if (Data[j] >= Data[j+1])

1.5 1

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MOVF temp,W ;Data[j+1] = Data[j] 1.5 1

MOVWF FSR ;Data[j] = Data[j+1] 1.5 1

DECF FSR,F 1.5 1

MOVF temp,W 1.5 1

MOVWF FSR 1.5 1

INCF FSR,F 1.5 1

32 _L3 INCF Var_j,F ;j++ 1.5 1

33 GOTO _L4 ;} 1.5 1

34 _L2 INCF Var_i,F ;i++ 1.5 1

35 GOTO _L5 ;} 1.5 1

36 _L1 GOTO _L1 ;End 1.5 1

BYTES MEMORY ROM 55.5

Table 14: Assembler code for PIC12C5X

Line Label Seudo Code Cycles/Var Cycles/Var Total


2 _L5



5 clear j CVar 1 6

6 _L4






12 _L3



15 _L2



18 _L1


Total Cycles 686

Table 15: Cycles Calculations for PIC12C5X


5.8 TMS370

µ= =1


sMhz


1

2 Var_i .EQU R2 1

3 Var_j .EQU R3 1

4 temp .EQU R4 1

5 Data: FCB 7,6,3,4,5,2,1

6 EndData:

7 SzData: EQU (EndData-Data)

8


10 START:

11 BSort:

12 MOV #1, Var_i ;i = 1 3 8

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13 _L5: CMP #SzData, Var_i ;if (i<SzData) 3 8

14 JNC _L1 ; { 2 5/7

15 MOV #0, Var_j ; j=0 3 10

16 _L4: MOV Var_j, A ; 2 7

17 ADD Var_i, A ; 2 7

18 CMP #SzData, A ; i+j 2 6

19 JNC _L2 ; if (i+j<SzData) 2 5/7

20 MOV Var_j, B ; { 2 7

21 MOV *Data[B],A ; 3 12

22 MOV A, temp ; 2 7

23 INC B ; X = &Data[j] 1 8

24 MOV *Data[B],A ; A = Data[j] 3 12

25 SUB temp, A ; B = Data[j+1] 2 7

26 JNC _L3 ; if (A>B) 2 5/7

27 MOV *Data[B],A ; { Unsigned 3 12

28 MOV A, temp2 ; A->B 2 7

29 MOV temp, A 2 7

30 MOV A, *Data[B] 3 12

31 DEC B 1 8

32 MOV temp2,A 2 7

33 MOV A, *Data[B] 3 12

34 INC B 1 8

35 _L3: INC Var_j ; B->A } 2 6

36 JMP _L4 ; j++ 2 7

37 _L2: INC Var_i ; } 2 6

38 JMP _L5 ; i++ 2 7

39 _L1: JMP _L1 ; } 2 7

BYTES MEMORY ROM 61

Table 16: Assembler code for TMS370

Line Label Seudo Code Cycles/Var Cycles/Var Total


2 _L5



5 clear j CVar 10 60

6 _L4






12 _L3



15 _L2



18 _L1


Total Cycles 3926

Table 17: Cycles Calculations for TMS370


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5.9 C166

µ= =1


sMhz


1

2 C100 SECTION DATA BYTE

3 Var_i EQU RL0 1

4 Var_j EQU RH0 1

5 temp EQU RL1 1

6 temp2 EQU RH1 1

7 index EQU R3 2

BYTES MEMORY RAM 5

8 DataB: DB 7,6,3,4,5,2,1

9 EndData:

10 SzData EQU (EndData-DataB)

11 C100 ENDS

12 NCODE CGROUP StartCode

13 StartCode SECTION CODE WORD 'NCODE'

14

15 MyFunc PROC NEAR

16 PUBLIC MyFunc

17 STARTC: LABEL

18 MOVB Var_i, #1 2 4

19 _L5:

20 CMPB Var_i,#SzData 2 4

21 JMPR CC_UGE, _L1 2 8

22 MOVB Var_j, #0 2 4

23 MOV index, #DataB 4 2

24 _L4:

25 MOVB temp, Var_j 2 4

26 ADDB temp, Var_i 2 4

27 CMPB temp, #SzData 2 4

28 JMPR cc_UGE, _L2 2 6

29 MOVB temp, [index+] 2 2

31 CMPB temp, [index] 2 3

32 JMPR cc_ULE, _L3 2 8

33 MOVB temp2, [index] 2 3

35 MOVB [index], temp 2 4

36 MOVB [-index], temp2 2 4

37 MOV temp, [index+] 2 4

38 _L3: LABEL

39 ADDB Var_j, #1 2 4

JMPR cc_UC, _L4 2 8

_L2: LABEL

ADDB Var_i, #1 2 4

JMPR cc_UC, _L5 2 8

_L1:

JMPR cc_UC, _L1 2 8

MyFunc ENDP

StartCode ENDS

END

BYTES MEMORY ROM 44

Table 18: Assembler code for C166

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2 _L5



5 clear j CVar 6 36

6 _L4






12 _L3



15 _L2



18 _L1


Total Cycles 1716

Table 19: Cycles Calculations for TMS370


6 Performance Comparison

6.1 Time

Performance Comparison (Execution Time)

0.000

5.000

10.000

15.000

20.000

25.000

30.000

68HC12

6805

8051

DS89

C42

0

ST62

AT90S85

15

PIC12

C5x

x

TMS37

0

Siem

ens C16

6

ARM

7

Microprocessor

Tim

e (

ms)

ExecutionTime(ms)

Figure 4: Performance Comparison (time)

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6.2 Memory

Memory Comparison

0

10

20

30

40

50

60

70

68HC12

6805

8051

DS89

C420

ST62

AT90S85

15

PIC12

C5x

x

TMS37

0

Siem

ens

C16

6

ARM

7

Microprocessor

By

tes

ROM(Bytes)

RAM(Bytes)

Figure 5: Memory Comparison

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7 Conclusions

The codification of each program was in certain way challenge because its processor has

it own architecture and its own set of instructions.

Generally, in each processor assessed in this report was possible to translate the high level

language into machine code. Furthermore each processor, has its own set of instruction

which could be categorized in the following way (Stallings, W., 2006):

� Data processing: Through this instructions is possible to perform arithmetic and logic

instruction.

� Data Storage: The way to store information into memory

� Data movement: instruction that allow movement of data input and output.

� Control: instructions to test and execute branch.

There are some processors which their instruction set allows easily the implementation of

the algorithm. Furthermore, they have a set of instructions that allow data manipulation in

a easier way. For example the DS89C420 and 8051 were the two that had less numbers of

program ROM. It means that the instructions for moving data (specially swapping) are very

useful. Indeed, DS89C420 is one of the processor which executed the program faster.

Addressing is the next factor that affects the performance of a processor. Despite the fact

that there are different types of addressing, not every processor has the same kind of

instruction to access memory data. Generally, seven different types of addressing can be

defined (Stallings, W., 2006):

� Immediate

� Direct

� Indirect

� Register

� Register Indirect

� Displacement

� Stack

In addressing mode it is possible to define that there were some microprocessors which

their instruction set allow and effective way of implementing and executing the for loop.

Instruction execution is always performed in the same way. No matters which architecture

is being used, the process is always the same (Stallings, W., 2006):

� Fetch Instruction

� Interpret Instruction

� Fetch Data

� Process Data

� Write Data

The key point to execute faster a set of instructions for each processor is its the architecture.

For instance, depending of the architecture it is possible to define a RISC or a CISC set of

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instructions. However, generally speaking RISC architecture are in certain way more

complex that CISC architecture. The main reason of that is that RISC processor should have

a large amount of auxiliary registers in order to support the reduced number of instruction

sets.

Another aspect that affect performance has to do with the kind of architecture

implemented, Von Neuman or Harvard, The main reason is the memory implemented in

each machine; in one hand Von Neuman architecture has only one memory for data and

program and in the other hand Harvard architecture has different memory for data and

memory program.

However, nowadays is not possible to define if a processor has only one specific

architecture. Indeed, is it possible to get RISC processor with some CISC characteristics and

vice versa.

The most important factor to improve performance in some processors (ARM) is the

instruction pipelining. Pipelining allows processor to execute in “parallel” various

instructions. However, there are some aspects that should be taken into considering when

you are designing an application with those processors (Evans, J. and Eckhouse, R.):

� Pipeline Hazards: It is related with conflict resolution, procedural dependences and

data dependences.

� Data Stalls: It occurs when the processor has to deal with data writing or reading

previously storage data and this data is not available for the microprocessor.

� Brach Effects: It is related with pipeline refilling because a branch was taken.

In conclusion it is possible to evaluate many different aspects of each processor but is the

real application work who will define which processor is better for certain kind of taks.

(Evans, J. and Eckhouse, R.). However, the activity developed in this report allows to get a

initial sense of the main advantages or disadvantages of using a microprocessor for a

specific application.

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8 References

Atmel Corporation 2000, AT90S8515 - 8-Bit AVR Microcontroller, www.atmel.com , San Jose.

Atmel Corporation 1999, ARM7TDMI (Thumb) DataSheet, www.atmel.com, San Jose

Beckett, P 2006, Embedded Systems Design, course notes from EEET2039, RMIT University,

Melbourne.

Dallas Semiconductor 2005, DS89C420 Ultra-High Speed Microcontroller, www.maxim-

ic.com

Evans, JS and EckHouse RH 1999, Alpha Risc Architecture for programmers, Prentice Hall,

New Jersey.

Freescale semiconductor 2006, CPU12 Reference Manual, www.freescale.com

Infineon Technologies 2001, Instruction Set Manual for the C166 Family of Infineon 16-Bit

single-chip microcontrollers, www.infineon.com. München.

Intel Corporation, MCS® 51 1994, Microcontroller Family User’s Manual, Intel Corporation.

Illinois.

Microchip Technology Inc.1999, PIC12C5XX 8-Pin, 8-Bit CMOS Microcontrollers,

www.microchip.com, Chandler.

Motorola, 1999. MC68HC05 Technical Data, Motorola, East Kilbridge.

Patterson DA and Hennesy J L 2005, Computer Organization and Design, 3rd Edition,

Morgan Kaufmann Publishers, San Francisco.

Patterson DA and Hennesy J L 1998, Computer Organization and Design, 2nd Edition,

Morgan Kaufmann Publishers, San Francisco.

SGS-Thomson Microelectronics 1993, ST62 – ST63 Programming Manual.

Stallings, W 2006, Computer Organization and Architecture Designing for Performance, 7th

Edition, Prentice Hall, New Jersey.

Texas Instruments 1996, TMS370 Microcontroller Family User’s Guide, www.ti.com

Texas Instruments 1996, TMS370 and TMS370C8 8 Bit Microcontroller Family Optimizing C

Compiler User’s Guide, www.ti.com

Wunderlich C 2006. “C166: Call-segmented to a ram-address does not work”, start up

assembly code for C166 using Keil Software, 18 August, “Keil Discussion Forum” , viewed

September 11, 2006, www.keil.com/forum/docs/thread8211.asp.

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9 Annex – Assembler List 68HC12

The simulator used to test the assembler code was:

Micro-IDE Version 2.16m

www.bipom.com

Figure 6: Assembler list for 68HC12

DUNFIELD 68HC12 ASSEMBLER: bubble PAGE: 1 0000 1 ORG $0000 0000 00 2 Var_i: FCB 0 0001 00 3 Var_j: FCB 0 0002 00 4 Var_temp: FCB 0 0003 07 06 03 04 05 02 + 5 Data: FCB 7,6,3,4,5,2,1 000A 6 EndData: 000A 7 ;SzData: EQU (EndData-Data) 0003 8 SzData: EQU 3 FF00 9 ORG $FF00 FF00 10 START: FF00 11 BSort: FF00 86 01 12 LDAA #1 FF02 5A 00 13 STAA Var_i FF04 96 00 14 _L5: LDAA Var_i FF06 81 03 15 CMPA #SzData FF08 2C 28 16 BGE _L1 FF0A 79 00 01 17 CLR Var_j FF0D 96 01 18 _L4: LDAA Var_j FF0F 9B 00 19 ADDA Var_i FF11 81 03 20 CMPA #SzData FF13 2C 18 21 BGE _L2 FF15 D6 01 22 LDAB Var_j FF17 CE 00 03 23 LDX #Data FF1A 1A E5 24 ABX FF1C A6 00 25 LDAA 0,X FF1E E6 01 26 LDAB 1,X FF20 18 17 27 CBA FF22 25 04 28 BLO _L3 FF24 6A 01 29 STAA 1,X FF26 6B 00 30 STAB ,X FF28 72 00 01 31 _L3: INC Var_j FF2B 20 E0 32 BRA _L4 FF2D 72 00 00 33 _L2: INC Var_i FF30 20 D2 34 BRA _L5 FF32 20 FE 35 _L1: BRA _L1 FFFE 36 ORG $FFFE FFFE FF 00 37 FDB START DUNFIELD 68HC12 ASSEMBLER: bubble PAGE: 2 SYMBOL TABLE: BSORT -FF00 DATA -0003 ENDDATA -000A START -FF00 SZDATA -0003 VAR_I -0000 VAR_J -0001 VAR_TEMP-0002 _L1 -FF32 _L2 -FF2D _L3 -FF28 _L4 -FF0D _L5 -FF04

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10 Annex – Assembler List 68HC05


68HCx05 Cross Assembler Program Version 2.4

www.tec-i.com

Figure 7: Assembler list for 68HC12

Page 1 Date: 09/09/2006 Time:12:16:44 a.m. The Engineers Collaborative, Inc. WASM05 V2.2 68HC05 Cross Assembler V2.1 (C)1986-1997 0000 ORG $0000 0000 00 Var_i DB $0 0001 00 Var_j DB $0 0002 00 temp DB $0 0003 00 temp2 DB $0 0004 07020304 Data DB 7,2,3,4,5,6,1 050601 000B 00 EndData DB $0 0007 SzData EQU EndData - Data FF00 ORG $FF00 FF00 A601 [2 , 2] START LDA #1 FF02 B700 [4 , 6] STA Var_i FF04 B600 [3 , 9] _L5 LDA Var_i FF06 A107 [2 , 11] CMP #SzData FF08 2425 [3 , 14] BHS _L1 FF0A 3F01 [5 , 19] CLR Var_j FF0C AE04 [2 , 21] LDX #Data FF0E B601 [3 , 24] _L4 LDA Var_j FF10 BB00 [3 , 27] ADD Var_i FF12 A107 [2 , 29] CMP #SzData FF14 2415 [3 , 32] BHS _L2 FF16 F6 [3 , 35] LDA ,X FF17 5C [3 , 38] INCX FF18 F1 [3 , 41] CMP ,X FF19 230C [3 , 44] BLS _L3 FF1B F6 [3 , 47] LDA ,X FF1C B702 [4 , 51] STA temp FF1E 5A [3 , 54] DECX FF1F F6 [3 , 57] LDA ,X FF20 B703 [4 , 61] STA temp2 FF22 BE02 [3 , 64] LDX temp FF24 5C [3 , 67] INCX FF25 BE03 [3 , 70] LDX temp2 FF27 3C01 [5 , 75] _L3 INC Var_j FF29 20E3 [3 , 78] BRA _L4 FF2B 3C00 [5 , 83] _L2 INC Var_i FF2D 20D5 [3 , 86] BRA _L5 FF2F 20FE [3 , 89] _L1 BRA _L1 *** Symbol Table *** _L1 FF2F _L2 FF2B _L3 FF27 _L4 FF0E _L5 FF04 Data 0004 EndData 000B START FF00 SzData 0007 temp 0002 temp2 0003 Var_i 0000 Var_j 0001

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11 Annex – Assembler List 80C51



www.bipom.com

Figure 8: Assembler list for 8051

DUNFIELD 8051 ASSEMBLER: BUBBLE~1 PAGE: 1 0003 1 Var_i EQU 03h 0004 2 Var_j EQU 04h 0000 07 06 03 04 05 02 + 3 Data DB 7,6,3,4,5,2,1 0007 00 4 EndData DB 0 0007 5 SzData EQU (EndData-Data) 0000 6 ORG 00H ; Reset 0000 02 00 60 7 LJMP START 0060 8 ORG 60H ; start of program 0060 9 START: 0060 75 03 01 10 MOV Var_i,#1 0063 11 _L5: 0063 E5 03 12 MOV A,Var_i 0065 C3 13 CLR C 0066 94 07 14 SUBB A,#SzData 0068 50 20 15 JNC _L1 006A 75 04 00 16 MOV Var_j,#0 006D 17 _L4: 006D E5 04 18 MOV A,Var_j 006F 25 03 19 ADD A,Var_i 0071 C3 20 CLR C 0072 94 07 21 SUBB A,#SzData 0074 50 10 22 JNC _L2 0076 E5 04 23 MOV A,Var_j 0078 76 00 24 MOV @R0,#Data 007A 28 25 ADD A,R0 007B 08 26 INC R0 007C 96 27 SUBB A,@R0 007D 40 03 28 JC _L3 007F C6 29 XCH A,@R0 0080 18 30 DEC R0 0081 F6 31 MOV @R0,A 0082 32 _L3: 0082 05 04 33 INC Var_j 0084 80 E7 34 SJMP _L4 0086 35 _L2: 0086 05 03 36 INC Var_i 0088 80 D9 37 SJMP _L5 008A 38 _L1: 008A 80 FE 39 SJMP _L1

DUNFIELD 8051 ASSEMBLER: BUBBLE~1 PAGE: 2 SYMBOL TABLE: DATA -0000 ENDDATA -0007 START -0060 SZDATA -0007 VAR_I -0003 VAR_J -0004 _L1 -008A _L2 -0086 _L3 -0082 _L4 -006D _L5 -0063

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12 Annex – Assembler List DS89C420



www.bipom.com

Figure 9: Assembler list for DS89C420

DUNFIELD DS89C420 ASSEMBLER: BUBBLE~1 PAGE: 1 0003 1 Var_i EQU 03h 0004 2 Var_j EQU 04h 0000 07 06 03 04 05 02 + 3 Data DB 7,6,3,4,5,2,1 0007 00 4 EndData DB 0 0007 5 SzData EQU (EndData-Data) 0000 6 ORG 00H ; Reset 0000 02 00 60 7 LJMP START 0060 8 ORG 60H ; start of program 0060 9 START: 0060 75 03 01 10 MOV Var_i,#1 0063 11 _L5: 0063 E5 03 12 MOV A,Var_i 0065 C3 13 CLR C 0066 94 07 14 SUBB A,#SzData 0068 50 20 15 JNC _L1 006A 75 04 00 16 MOV Var_j,#0 006D 17 _L4: 006D E5 04 18 MOV A,Var_j 006F 25 03 19 ADD A,Var_i 0071 C3 20 CLR C 0072 94 07 21 SUBB A,#SzData 0074 50 10 22 JNC _L2 0076 E5 04 23 MOV A,Var_j 0078 76 00 24 MOV @R0,#Data 007A 28 25 ADD A,R0 007B 08 26 INC R0 007C 96 27 SUBB A,@R0 007D 40 03 28 JC _L3 007F C6 29 XCH A,@R0 0080 18 30 DEC R0 0081 F6 31 MOV @R0,A 0082 32 _L3: 0082 05 04 33 INC Var_j 0084 80 E7 34 SJMP _L4 0086 35 _L2: 0086 05 03 36 INC Var_i 0088 80 D9 37 SJMP _L5 008A 38 _L1: 008A 80 FE 39 SJMP _L1


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13 Annex – Assembler List PIC12C5X


MPLAB IDE Version 7.40.00.00

www.microchip.com

Figure 10: Assembler list for PIC12C5X

DUNFIELD DS89C420 ASSEMBLER: BUBBLE~1 PAGE: 1 0003 1 Var_i EQU 03h 0004 2 Var_j EQU 04h 0000 07 06 03 04 05 02 + 3 Data DB 7,6,3,4,5,2,1 0007 00 4 EndData DB 0 0007 5 SzData EQU (EndData-Data) 0000 6 ORG 00H ; Reset 0000 02 00 60 7 LJMP START 0060 8 ORG 60H ; start of program 0060 9 START: 0060 75 03 01 10 MOV Var_i,#1 0063 11 _L5: 0063 E5 03 12 MOV A,Var_i 0065 C3 13 CLR C 0066 94 07 14 SUBB A,#SzData 0068 50 20 15 JNC _L1 006A 75 04 00 16 MOV Var_j,#0 006D 17 _L4: 006D E5 04 18 MOV A,Var_j 006F 25 03 19 ADD A,Var_i 0071 C3 20 CLR C 0072 94 07 21 SUBB A,#SzData 0074 50 10 22 JNC _L2 0076 E5 04 23 MOV A,Var_j 0078 76 00 24 MOV @R0,#Data 007A 28 25 ADD A,R0 007B 08 26 INC R0 007C 96 27 SUBB A,@R0 007D 40 03 28 JC _L3 007F C6 29 XCH A,@R0 0080 18 30 DEC R0 0081 F6 31 MOV @R0,A 0082 32 _L3: 0082 05 04 33 INC Var_j 0084 80 E7 34 SJMP _L4 0086 35 _L2: 0086 05 03 36 INC Var_i 0088 80 D9 37 SJMP _L5 008A 38 _L1: 008A 80 FE 39 SJMP _L1


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14 Annex – Assembler List C166

The simulator used to test the assembler code was: µvision3 V3.30a - www.keil.com

Figure 11: Assembler list for C166

A166 MACRO ASSEMBLER BUBBLEC166ASM 09/09/2006 19:59:02 PAGE 1

MACRO ASSEMBLER A166 V5.20

OBJECT MODULE PLACED IN BubbleC166Asm.OBJ

ASSEMBLER INVOKED BY: C:\Keil\C166\BIN\A166.EXE BubbleC166Asm.asm SEGMENTED MOD167 SET(SMALL) DEBUG

EP

LOC OBJ LINE SOURCE

4 NAME MYASM

5

-------- 6 C100 SECTION DATA BYTE

7 Var_i EQU RL0

8 Var_j EQU RH0

9 temp EQU RL1

10 temp2 EQU RH1

11 index EQU R3

00000000 07060304 12 DataB: DB 7,6,3,4,5,2,1

00000004 050201 12

13 EndData:

0007 14 SzData EQU (EndData-DataB)

-------- 15 C100 ENDS

19 NCODE CGROUP StartCode

-------- 25 StartCode SECTION CODE WORD 'NCODE'

26

27 MyFunc PROC NEAR

28 PUBLIC MyFunc

32 STARTC: LABEL

00000000 E110 33 MOVB Var_i, #1

35 _L5:

00000002 4907 36 CMPB Var_i,#SzData

00000004 9D12 37 JMPR CC_UGE, _L1

00000006 E101 39 MOVB Var_j, #0

00000008 F2F3???? R 40 MOV index, DataB

41 _L4:

0000000C F121 42 MOVB temp, Var_j

0000000E 0120 43 ADDB temp, Var_i

00000010 4927 44 CMPB temp, #SzData

00000012 9D09 45 JMPR cc_UGE, _L2

00000014 9923 46 MOVB temp, [index+]

00000016 492B 47 CMPB temp, [index]

00000018 FD04 48 JMPR cc_ULE, _L3

0000001A A933 49 MOVB temp2, [index]

0000001C B923 50 MOVB [index], temp

0000001E 8933 51 MOVB [-index], temp2

00000020 9923 52 MOV temp, [index+]

53 _L3: LABEL

00000022 0911 54 ADDB Var_j, #1

00000024 0DF3 55 JMPR cc_UC, _L4


56 _L2: LABEL

00000026 0901 57 ADDB Var_i, #1

00000028 0DEC 58 JMPR cc_UC, _L5

59 _L1:

0000002A 0DFF 60 JMPR cc_UC, _L1

64 MyFunc ENDP

-------- 66 StartCode ENDS

67 END


SYMBOL TABLE LISTING

------ ----- -------

N A M E TYPE VALUE I ATTRIBUTES

C100 . . . . . . . ---- ---- R SECTION

DATAB. . . . . . . BYTE 0H R SEC=C100

ENDDATA. . . . . . BYTE 7H R SEC=C100

MYASM. . . . . . . ---- ----

MYFUNC . . . . . . NEAR 0H R PUB SEC=STARTCODE

NCODE. . . . . . . ---- ---- GROUP

STARTC . . . . . . NEAR 0H R SEC=STARTCODE

STARTCODE. . . . . ---- ---- R SECTION

SZDATA . . . . . . DATA3 7H A

_L1. . . . . . . . NEAR 2AH R SEC=STARTCODE

_L2. . . . . . . . NEAR 26H R SEC=STARTCODE


_L4. . . . . . . . NEAR CH R SEC=STARTCODE


ASSEMBLY COMPLETE. 1 WARNING(S), 0 ERROR(S)

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15 Annex – Compilation of bubble C program for ARM processor.

The simulator used to test the assembler code was: µvision3 V3.30a - www.keil.com

ARM COMPILER V2.54a, bubble 31/08/06 22:47:21 PAGE 1 ARM COMPILER V2.54a, COMPILATION OF MODULE bubble OBJECT MODULE PLACED IN bubble.OBJ COMPILER INVOKED BY: C:\KEIL\ARM\BIN\ca.exe bubble.c SYMBOLS CODE DEBUG stmt level source 1 #include <stdio.h> 2 #include <stdlib.h> 3 4 5 void main (void) 6 { 7 1 int i, j; 8 1 int Data[] = {23,53,67,89,89,99,123}; 9 1 unsigned int tmp; 10 1 for (i=0; i<sizeof(Data)-1; i++) 11 1 { 12 2 for (j=0; j<sizeof(Data)-1-i; j++) 13 2 { 14 3 if (Data[j+1] < Data[j]) 15 3 { 16 4 tmp = Data[j]; 17 4 Data[j] = Data[j+1]; 18 4 Data[j+1] = tmp; 19 4 } 20 3 } 21 2 } 22 1 } 23 24 25 26 void BubbleSort (void) 27 { 28 1 29 1 } 30 31 ARM COMPILER V2.54a, bubble 31/08/06 22:47:21 PAGE 2 ASSEMBLY LISTING OF GENERATED OBJECT CODE *** EXTERNALS: EXTERN NUMBER (__startup) *** PUBLICS: PUBLIC main PUBLIC BubbleSort?T *** DATA SEGMENT '?CON?bubble': 00000000 ?tpl?0001: 00000000 BEGIN_INIT 00000000 00000017 DD 0x17 00000004 00000035 DD 0x35 00000008 00000043 DD 0x43 0000000C 00000059 DD 0x59 00000010 00000059 DD 0x59 00000014 00000063 DD 0x63 00000018 0000007B DD 0x7B 0000001C END_INIT *** CODE SEGMENT '?PR?main?bubble': 5: void main (void) 00000000 B500 PUSH {LR} 00000002 B087 SUB R13,#0x1C 6: { 00000004 ; SCOPE-START 8: int Data[] = {23,53,67,89,89,99,123}; 00000004 4800 LDR R1,=?tpl?0001 ; ?tpl?0001 00000006 A800 ADD R0,R13,#0x0

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00000008 221C MOV R2,#0x1C 0000000A L_13: 0000000A 780B LDRB R3,[R1,#0x0] 0000000C 7003 STRB R3,[R0,#0x0] 0000000E 1C49 ADD R1,R1,#0x1 00000010 1C40 ADD R0,R0,#0x1 00000012 1E52 SUB R2,R2,#0x1 00000014 D1F9 BNE L_13 ; T=0x0000000A 10: for (i=0; i<sizeof(Data)-1; i++) 00000016 2000 MOV R0,#0x0 00000018 ---- Variable 'i' assigned to Register 'R0' ---- 12: for (j=0; j<sizeof(Data)-1-i; j++) 00000018 L_10: 00000018 2100 MOV R1,#0x0 0000001A ---- Variable 'j' assigned to Register 'R1' ---- 0000001A E015 B L_8 ; T=0x00000048 0000001C L_9: 14: if (Data[j+1] < Data[j]) 0000001C 1C0B MOV R3,R1 ; j 0000001E 009B LSL R3,R3,#0x2 ; j 00000020 AC00 ADD R4,R13,#0x0 00000022 58E5 LDR R5,[R4,R3] 00000024 AA01 ADD R2,R13,#0x4 00000026 58D2 LDR R2,[R2,R3] 00000028 42AA CMP R2,R5 0000002A DA0C BGE L_6 ; T=0x00000046 16: tmp = Data[j]; 0000002C ---- Variable 'tmp' assigned to Register 'R5' ---- 17: Data[j] = Data[j+1]; 0000002C 1C0B MOV R3,R1 ; j 0000002E 009B LSL R3,R3,#0x2 ; j 00000030 AA01 ADD R2,R13,#0x4 00000032 58D2 LDR R2,[R2,R3] 00000034 1C0C MOV R4,R1 ; j 00000036 00A4 LSL R4,R4,#0x2 ; j ARM COMPILER V2.54a, bubble 31/08/06 22:47:21 PAGE 3 00000038 AB00 ADD R3,R13,#0x0 0000003A 511A STR R2,[R3,R4] 18: Data[j+1] = tmp; 0000003C 1C2A MOV R2,R5 ; tmp 0000003E 1C0C MOV R4,R1 ; j 00000040 00A4 LSL R4,R4,#0x2 ; j 00000042 AB01 ADD R3,R13,#0x4 00000044 511A STR R2,[R3,R4] 20: } 00000046 L_6: 00000046 3101 ADD R1,#0x1 00000048 L_8: 00000048 1C02 MOV R2,R0 ; i 0000004A 231B MOV R3,#0x1B 0000004C 1A9B SUB R3,R2 ; i 0000004E 1C0A MOV R2,R1 ; j 00000050 429A CMP R2,R3 ; j 00000052 DBE3 BLT L_9 ; T=0x0000001C 21: } 00000054 3001 ADD R0,#0x1 00000056 1C01 MOV R1,R0 ; i 00000058 291B CMP R1,#0x1B ; i 0000005A DBDD BLT L_10 ; T=0x00000018 0000005C ; SCOPE-END 22: } 0000005C B007 ADD R13,#0x1C 0000005E BC08 POP {R3} 00000060 4718 BX R3 00000062 ENDP ; 'main' *** CODE SEGMENT '?PR?BubbleSort?T?bubble': 29: } 00000000 4770 BX R14 00000002 ENDP ; 'BubbleSort?T' ARM COMPILER V2.54a, bubble 31/08/06 22:47:21 PAGE 4 Name Class Space Type Offset Size

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--------------------------------------------------------------------------- ldiv_t . . . . . . . . . . . . . . . . type struct ----- 8 rem. . . . . . . . . . . . . . . . . member long 000000H 4 quot . . . . . . . . . . . . . . . . member long 000004H 4 _ldiv_t. . . . . . . . . . . . . . . . *tag* struct ----- 8 rem. . . . . . . . . . . . . . . . . member long 000000H 4 quot . . . . . . . . . . . . . . . . member long 000004H 4 div_t. . . . . . . . . . . . . . . . . type struct ----- 8 rem. . . . . . . . . . . . . . . . . member int 000000H 4 quot . . . . . . . . . . . . . . . . member int 000004H 4 _div_t . . . . . . . . . . . . . . . . *tag* struct ----- 8 rem. . . . . . . . . . . . . . . . . member int 000000H 4 quot . . . . . . . . . . . . . . . . member int 000004H 4 wchar_t. . . . . . . . . . . . . . . . type uchar ----- 1 size_t . . . . . . . . . . . . . . . . type uint ----- 4 main . . . . . . . . . . . . . . . . . public code funct 000000H i. . . . . . . . . . . . . . . . . . *reg* int ----- 4 j. . . . . . . . . . . . . . . . . . *reg* int ----- 4 Data . . . . . . . . . . . . . . . . auto data array 000000H 28 tmp. . . . . . . . . . . . . . . . . *reg* uint ----- 4 BubbleSort?T . . . . . . . . . . . . . public code funct 000000H ?tpl?0001. . . . . . . . . . . . . . . static const array 000000H 28 Module Information Static ---------------------------------- code size = ------ data size = ------ const size = 28 End of Module Information. ARM COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)

Microprocessor Performance

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Transcript of Microprocessor Performance