MICROCONTROLLER 8051BY: PROF. PRANJALI ULHESDCE, WARDHA

INTRODUCTION The 8051 is the original member of the MCS®-51 family,

and is the core for all MCS-51 devices. The features ofthe 8051 core are: 8-bit CPU optimized for control applications Extensive Boolean processing (single-bit logic) capabilities 64K Program Memory address space 64K Data Memory address space 4K bytes of on-chip Program Memory 128 bytes of on-chip Data RAM 32 bidirectional and individually addressable I/O lines Two 16-bit timer/counters Full duplex UART 6-source/5-vector interrupt structure with two priority levels On-chip clock oscillator

MCS -51(8051) ARCHITECTURE

ARCHITECTURE Block diagram of 8051 consist of CPU Two memory sections (Data and Program) Input/output ports Special function registers Control logic

These all elements communicates using 8 bit data bus, know as internal data bus

PIN-OUT OF 8051

PIN-OUT 8051 consist of 40 pin Many pins of 8051 are used for more than one function The alternate functions are shown with green colour.

CPU(CENTRAL PROCESSING UNIT) It consists of 8 bit arithmetic and logic unit Associated with registers like A,B,PSW,SP. It consist of 16 bit program counter and data pointer It also contains set of special function registers ALU performs arithmetic as well as logic function on 8 bit

variables Arithmetic operations such as addition, subtraction,

multiplication and division Logic operations such as AND,OR,XOR, rotate etc.

ON-CHIP DATA MEMORY AND REGISTER BANK 8051 consist of 128 byte

internal RAM It is organized into three

areas Working Registers Bit Addressable General Purpose First 32 bytes from 00H to

1FH are working registers. They are divided into 4 banks

of 8 registers from R0 to R7 At a time only 1 bank is in

use, bits RS0 and RS1 in PSW determine the bank in current use.

When register bank is not selected then can be used as general purpose RAM.

ON-CHIP DATA MEMORY AND REGISTER BANK 8051 provides 16 bytes of bit addressable area It occupies RAM byte addresses from 20H to 2FH forming

128 addressable bits. The RAM area from 30H to 7FH are called as general

purpose RAM.

ON- CHIP PROGRAM MEMORY 8051 has 4k byte internal

ROM from 0000H to 0FFFH It is inbuilt and

programmed by manufacturer

It cannot be erased or altered after fabrication

If the program exceed above 0FFFH then 8051 automatically fetch code bytes from external program memory.

INPUT/OUTPUT PORTS 8051 has 32 I/O pins as 4

eight bit parallel Port (P0,P1,P2 and P3) All ports are bidirectional They consist of latch,

output driver and input buffer.

Port 0 and 2 of output driver and port 0 of input buffers are used in access to external memory

Pins of port3 are multifunctional.

INPUT/OUTPUT PORTS

REGISTER SET Register A (accumulator) It is an 8 bit register, which holds operand and receives

result of arithmetic instruction. It can also be source or destination for logical operations. Register B In addition to accumulator, an 8 bit B-register is available

as general purpose register.

REGISTER SET

STACK AND STACK POINTER Stack pointer is used to hold

internal RAM address that is called top of stack

It is 8 bit wide It is incremented before data

is stored during PUSH and CALL

It is decremented after data is restored during POP and RET instructions

It can reside anywhere on chip RAM

Stack pointer is initialized 07 h after reset.

Stack location begin at location 08h

DATA POINTER (DPTR) It consists of High byte (DPH)

and low byte (DPL) Its function is to hold 16 bit

address It can be used as 16 bit data

register or two 8 bit registers It does not have single

internal address.

PROGRAM COUNTER 8051 has 16 bit program counter Which holds address of memory location from which next

instructions is to be fetched It can address up to 64k of memory It automatically increments to point next instruction in

program sequence PC is only register that does not have internal address.

SPECIAL FUNCTION REGISTERS (SFRS) Like other microprocessors Intel

family 8051 uses memory mapped I/O through special function registers that in implemented above 128 bytes of RAM

The figure shows special fubction bit addresses

It shows all 4 I/O ports , CPU registers, interrupt control registers, time/counter etc

The power control is performed between 80H and FFH

SPECIAL FUNCTION REGISTERS (SFRS)

8051 OSCILLATOR AND CLOCK All internal operations are

synchronized with help of clock signal.

Clock signal is generated using oscillator circuit.

The minimum and maximum operating frequencies for 8051 are typically 1 mhz to 16 mhz.

A machine cycle of 8051 consists of 6 states from s1 to s6,divided int two phases p1 & p2.

Thus a m/c cycle consist of 12 oscillator periods from s1p1 to s6p2 in 1µsec.

During m/c arithmetic and logical operations takes place in p1 and internal register to register in p2.

ALE is activated twice a m/c cycle for user accessible as external reference

(ALE is activated during s1p2 and s2p1, s4p2 and s5p1.

8051 OSCILLATOR AND CLOCK Execution of one cycle instruction begins at s1p2, when

instruction is latched into instruction register. If it is two byte instruction second instruction is read during s4. If it is one byte instruction there is still fetch at s4 but byte read is

ignored and pc Is not incremented. Most instruction execute in one cycle, but mul, div are instructions

that take two cycles to complete. Normally two bytes are fetched during every m/c cycle, only for

MOVX it takes 1 byte , 2 cycle for external memory.

EXTERNAL DATA AND PROGRAM MEMORY 8051 has internal data and

code memory with limited memory

Memory may not be sufficient for some applications

So their is need to connect external ROM/EPROM and RAM to 8051

To increase capacity of memory

ROM is used as program memory

RAM is used as data memory

EXTERNAL PROGRAM MEMORY In 8051 when EA pin connected

to Vcc program fetches addresses from 0000h to 0FFFh are directed to internal ROM

From 1000h to FFFFh are directed to external ROM/EPROM

And if EA pin is grounded all addresses fetched by program from 0000h to FFFFh are directed to external ROM/EPROM

PSEN signal is used to activate output enable signal of ROM/EPROM

Port 0 is used as multiplexed address/bus

Initial T –cycle gives lower order 8 bit address and later used as data bus

8bit lower address is latched using ALE signal

EXTERNAL PROGRAM MEMORY• Port 2 provides higher order 8 bit address• The lower part of program stores the vector addresses for various vectors interrupt routine•Each interrupt is assigned with fixed location• from figure we can see•When the interrupt does not use the location it is used as general purpose memory.

•Instruction to access external ROM/Program memory•MOVC A,@A +DTPR•MOVC A,@A +PC

EXTERNAL DATA MEMORY 8051 can address upto 64k

bytes of external memory MOVX instruction is used to

access external data memory. Internal memory is divided

into three blocks lower 128 bytes , upper 128bytes and SFRS

Upper block and SFRS occupy same address space 80h to FFh

Upper is accessible by indirect addressing only

SFRs is accessed by direct addressing

Lower is accessed by direct as well as indirect addressing

EXTERNAL DATA MEMORY Circuit diagram shows

connectivity with external data memory.

Multiplexed address/data bus is provided by external port 0, external latch and ALE

Port 2 gives higher order sddress bus

RD and WR signals selects memory read and memory write operations

EXTERNAL DATA MEMORY

TIMERS/COUNTERS AND THEIR PROGRAMMING 8051 has 16 bit Timer/counter

registers: Timer 0 and Timer 1 both can be used either as timers or counters

If it is used as timer it will be incremented after each m/c cycle and the count rate is 1/12 of oscillator frequency.

If frequency is 12 MHZ then timer clock frequency will be 1 MHZ.

If it is used as counter it will be incremented in response to 1-0 transition its corresponding external input it takes two m/c cycles so count rate is 1/24

Timers and counters are controlled by TR!/0 bits in TCON

Gate bits in TMOD and INT1/0 input pins of 8051

C/T bit register decides the operation 0 for timer selection and 1 for counter

TIMER 0 AND TIMER 1