Mic ARM Training
Transcript of Mic ARM Training
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T H E A R C H I T E C T U R E F O R T H E D I G I T A L W O R L D
The ARM Architecture
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ARM Ltd
Founded in November 1990 Spun out of Acorn Computers
Designs the ARM range of RISC processor cores
Licenses ARM core designs to semiconductorpartners who fabricate and sell to their customers. ARM does not fabricate silicon itself
Also develop technologies to assist with the
design-in of the ARM architecture Software tools, boards, debug hardware, application
software, bus architectures, peripherals etc
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ARM Partnership Model
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ARM Powered Products
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ARM provides hard and soft views to licencees RTL and synthesis flows GDSII layout
Licencees have the right to use hard or soft views of the IP soft views include gate level netlists hard views are DSMs
OEMs must use hard views to protect ARM IP
Intellectual Property
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Development of the
ARM Architecture
SA-110
ARM7TDMI
4T
1
Halfword
and signed
halfword /
byte support
System
mode
Thumb
instruction
set
2
4
ARM9TDMI
SA-1110
ARM720T ARM940T
Improved
ARM/Thumb
Interworking
CLZ
5TE
Saturated maths
DSP multiply-
accumulate
instructions
XScale
ARM1020E
ARM9E-S
ARM966E-S
3
Early ARMarchitectures
ARM9EJ-S
5TEJ
ARM7EJ-S
ARM926EJ-S
Jazelle
Java bytecode
execution
6
ARM1136EJ-S
ARM1026EJ-S
SIMD Instructions
Multi-processing
V6 Memoryarchitecture (VMSA)
Unaligned data
support
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ARM7TDMI Processor Core
Current low-end ARM core for applications like digital mobile phones
TDMI T: Thumb, 16-bit compressed instruction set D: on-chip Debug support, enabling the processor to halt in response to a
debug request M: enhanced Multiplier, yield a full 64-bit result, high performance
I: EmbeddedICE hardware Von Neumann architecture
3-stage pipeline
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ARM7TDMI Processor Core
The ARM is a 32-bit architecture.
When used in relation to the ARM: Byte means 8 bits Halfword means 16 bits (two
bytes) Word means 32 bits (four bytes)
Most ARMs implement two
instruction sets 32-bit ARM Instruction Set 16-bit Thumb Instruction Set
Jazelle cores can also execute
Java bytecode
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Processor Modes
The ARM has seven basic operating modes:
User: unprivileged mode under which most tasks run
FIQ : entered when a high priority (fast) interrupt is raised
IRQ : entered when a low priority (normal) interrupt is raised
Supervisor: entered on reset and when a Software Interrupt
instruction is executed
Abort : used to handle memory access violations
Undef: used to handle undefined instructions
System : privileged mode using the same registers as user mode
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The Registers
ARM has 37 registers all of which are 32-bits long. 1 dedicated program counter 1 dedicated current program status register 5 dedicated saved program status registers 30 general purpose registers
The current processor mode governs which of several banks is
accessible. Each mode can access a particular set ofr0-r12 registers a particularr13 (the stack pointer, sp) and r14 (the link register, lr) the program counter, r15 (pc)
the current program status register, cpsr
Privileged modes (except System) can also access a particularspsr(saved program status register)
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Register Organization Summary
User
mode
r0-r7,
r15,
and
cpsr
r8
r9
r10
r11
r12
r13 (sp)
r14 (lr)
spsr
FIQ
r8
r9
r10
r11
r12
r13 (sp)
r14 (lr)
r15 (pc)
cpsr
r0
r1
r2
r3
r4
r5
r6
r7
User
r13 (sp)
r14 (lr)
spsr
IRQ
User
mode
r0-r12,
r15,
and
cpsr
r13 (sp)
r14 (lr)
spsr
Undef
User
mode
r0-r12,
r15,
and
cpsr
r13 (sp)
r14 (lr)
spsr
SVC
User
mode
r0-r12,
r15,
and
cpsr
r13 (sp)
r14 (lr)
spsr
Abort
User
mode
r0-r12,
r15,
and
cpsr
Thumb stateLow registers
Thumb stateHigh registers
Note: System mode uses the User mode register set
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Program Status Registers
Condition code flags N =Negative result from ALU Z = Zero result from ALU C = ALU operation Carried out
V = ALU operation oVerflowed
Sticky Overflow flag - Q flag Architecture 5TE/J only Indicates if saturation has occurred
J bit Architecture 5TEJ only J = 1: Processor in Jazelle state
Interrupt Disable bits. I = 1: Disables the IRQ. F = 1: Disables the FIQ.
T Bit Architecture xT only T = 0: Processor in ARM state T = 1: Processor in Thumb state
Mode bits Specify the processor mode
2731
N Z C V
28 67
I F T mode
1623
815
5 4 024
f s x c
U n d e f i n e d
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When the processor is executing in ARM state: All instructions are 32 bits wide All instructions must be word aligned Therefore the pc value is stored in bits [31:2] with bits [1:0] undefined (as
instruction cannot be halfword or byte aligned).
When the processor is executing in Thumb state: All instructions are 16 bits wide All instructions must be halfword aligned Therefore the pc value is stored in bits [31:1] with bit [0] undefined (as
instruction cannot be byte aligned).
When the processor is executing in Jazelle state: All instructions are 8 bits wide Processor performs a word access to read 4 instructions at once
Program Counter (r15)
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Vector Table
Exception Handling
When an exception occurs, the ARM: Copies CPSR into SPSR_ Sets appropriate CPSR bits
Change to ARM state Change to exception mode Disable interrupts (if appropriate)
Stores the return address in LR_ Sets PC to vector address
To return, exception handler needs to: Restore CPSR from SPSR_ Restore PC from LR_
This can only be done in ARM state.
Vector table can be at
0xFFFF0000 on ARM720T
and on ARM9/10 family
devices
FIQ
IRQ
(Reserved)
Data Abort
Prefetch Abort
Software Interrupt
Undefined Instruction
Reset
0x1C
0x18
0x14
0x10
0x0C
0x08
0x04
0x00
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Example ARM-based System
16 bit RAM
8 bit ROM
32 bit RAM
ARMCore
I/OPeripherals
Interrupt
Controller
nFIQnIRQ
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AMBA
Br
idge
Timer
On-chipRAM
ARM
InterruptController
Remap/Pause
TIC
Arbiter
Bus InterfaceExternalROM
ExternalRAM
Reset
System Bus Peripheral Bus
AMBA Advanced Microcontroller Bus Architecture
ADK Complete AMBA Design Kit
ACT AMBA Compliance Testbench
PrimeCell ARMs AMBA compliant peripherals
AHB or ASB APB
ExternalBus
Interface
Decoder
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The RealView Product Families
Debug Tools
AXD (part of ADS)
Trace Debug Tools
Multi-ICE
Multi-Trace
Platforms
ARMulator (part of ADS)
Integrator Family
Compilation Tools
ARM Developer Suite (ADS)
Compilers (C/C++ ARM & Thumb),
Linker & Utilities
RealView Compilation Tools (RVCT) RealView Debugger (RVD)
RealView ICE (RVI)
RealView Trace (RVT)
RealView ARMulator ISS
(RVISS)
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ARM Debug Architecture
ARM
core
ETM
TAP
controller
Trace PortJTAG port
Ethernet
Debugger (+ optional
trace tools)
EmbeddedICE Logic Provides breakpoints and processor/systemaccess
JTAG interface (ICE) Converts debugger commands to JTAG
signals
Embedded trace Macrocell (ETM) Compresses real-time instruction and dataaccess trace
Contains ICE features (trigger & filter logic)
Trace port analyzer (TPA) Captures trace in a deep buffer
EmbeddedICE
Logic
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LPC 2478
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0x0000 0000
Flash Memory
0x4000 0000
Reserved for on-chip
Static Ram and
Special Registers
Boot Block
AHB PeripheralsAPB Peripherals
0x8000 0000
0xE000 0000
0xF000 0000
LPC2478 Memory Map
4.0 GB
External Static and
Dynamic Memory
2.0 GB
0.0 GB
0xFFFF FFFF
0xDFF FFFF
Ethernet w/DMA & USB (OTG, OHCI w PHY)
Timers, PWM, I2C, SPI, I2S, UARTs, CAN,
SSP, DAC, ADC
Memory mapped I/O Flash sector sizes from 4 kB to 32 kB Flash = 100,000 write- erase cycles Boot Block supports
In-Application Programming In-System Programming
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LPC2478System Functions
Internal Reference Clock (IRC)
External Clock ( X1/X2) Real Time Clock (RTXC1/RTXC2) Phase-Locked Loop Peripheral & CPU Clock Power Control For Each Peripheral
Power-On/Reset Brown-Out Detection
PC24 8
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LPC2478Clock Subsystem
Main
Oscillator
RTCOscillator
PLL
Watchdog
Timer
Real TimeClock
ARM7TDMI-S
APB
Peripherals
USB Block
EthernetBlock
Other AHB
Peripherals
Internal
R/C
Oscillator
system
clock selectBypass
Synchro-
nizer
watchdog
clock select
RTC clock
select
RTC
Prescaler
cclk
External
Ethernet
PHY
25 or
50 MHz
pclk
CPU
Clock
Divider
USB
Clock
Divider
usbclk
(48 MHz)
wdclk
rtcclk
Perpipheral
ClockGenerator
pllclk
System clock (PLLCLK) can bederived from three sources Main crystal (1MHz to 20MHz) Internal RC oscillator (IRC)
Factory Trimmed to +/-1%
Real time clock (RTC)
CPU clock (CCLK) can be separate
from the APB peripherals CCLK can be higher or lower than the
APB peripherals
Independent peripheral clocks
Watchdog Timer has a separate
clock selector mux
CCLK & PLLCLK
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MainOscillator
RTCOscillator
PLL
Watchdog
Timer
Real Time
Clock
ARM7TDMI-S
APB
Peripherals
USB Block
EthernetBlock
Other AHBPeripherals
InternalR/C
Oscillator
systemclock select
BypassSynchro-
nizer
watchdogclock select
RTC clockselect
RTCPrescaler
cclk
External
Ethernet
PHY
25 or50 MHz
pclk
CPU
ClockDivider
USBClock
Divider
usbclk(48 MHz)
wdclk
rtcclk
PerpipheralClock
Generator
pllclk
LPC2478
Clock Subsystem
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Independent Peripheral Clocks (PCLK)
PCLKSELx allows
four individual clock
selections for each
peripheral
LPC2478
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LPC2478Power Control
Idle Mode clock to the core is stopped Execution of instructions is suspended until an interrupt or reset occurs
Sleep Mode PLL is turned off Processor state and registers, peripheral registers and RAM values are
preserved
Flash is left in standby mode LPC2478 resumes operation when certain types of interrupts not requiring a
clock occur or a reset happens
Power down Mode All clocks except for the RTC* are turned off Flash memory is turned off
Minimal power consumption LPC2478 wakes up when certain types of interrupts not requiring clock occur or
a reset
* RTC clock pins and VBAT pin connected and RTC mode enabled
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Power Control for each Peripheral
The PCONP Register determines if a peripheral is switched on or off
0 = Off 1 = On
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I/O Pin Selection
Each I/O pin can be used for one of several functions
Example:P0.2 = TXD0 (UART0 TXD)
P0.3 = RXD0 (UART0 RXD)
Other pin selects are GPIO
PINSEL0 =0x00000050