Methods of Advanced Copper Electroplating:

Prashanth G

UID: 3913834

Methods of Advanced Copper Electroplating:

Introduction: Copper has replaced Aluminum in several of the interconnect metallization techniques in recent years.

The replacement of Aluminum with Copper is motivated by its higher conductivity which leads to lower

resistance copper lines. In Copper metallization, there are several ways to deposit Copper onto the

wafer. One common method which has gained popularity in recent years is Electroplating of copper. In

Electroplating, the copper is treated as the anode and the wafer itself becomes the cathode.

Performance enhancement using Copper Wires: The performance of an integrated circuit is greatly affected by the interconnecting wires which conduct

the current. The effects not only include mere resistance as a factor. There are other considerations

such as the parasitic capacitance effects, driving current through a large capacitive load such as a clock

tree and sometimes the RC delay of the wire itself. This varying need of the process requirement

(Rosenberg, et al., 2000) goads us to replace the current Al with Cu.

Fig 1: Simulation of high end Large Chip CPU performance with and without hierarchical wiring and fat lines As an example of the resistivity of Copper to be less than that of Al, we shall consider the following case.

“The values of Cu/liner of about 0.5 ohms/link (<0.25 ohms/via) are about 2.5 times less than values for

Al(Cu)/W and show very tight distributions” (Rosenberg, et al., 2000)

Fig 2: comparative via resistance between Cu/liner and Al(Cu)/W technologies. Note the 2.5 times improvement and tighter distribution with Cu. (diagram reproduced from IBM (Rosenberg, et al., 2000))

Fig 3: Relative resistivity change with decreasing metal line width between Cu and Al(Cu) metallurgies. The main effect is the metal liner in each case, which may not scale with thickness, thus leading to increased relative resistivity. Experimentally, however, the liner does scale in Cu wiring

Another important factor to consider when we compare the metal deposition by CVD, PVD and by

electroplating is that the electroplating techniques provide better surface smoothness compared to the

CVD and PVD processes. Of course, this depends on the tools used, and other fabrication processes. (1).

Processing of Copper Interconnects: Like Al, Cu does not form an oxide, which makes Copper more prone to corrosion and adhesion

problems. However, this same property of Cu makes it a good-to-use metal for interconnects and vias.

In the simplest form, the electroplating is done by connecting the wafer to the cathode of the system

and the Copper (source) is connected to the anode of the system. This system is immersed into an

electrolyte. Typically, the electrolyte used would be CuSO4.

Fig 4: Schematic diagram of a Copper electroplating system. Reproduced from Journal of Micromechanics and MicroEngineering (Gau, et al., 2000) A conventional solution for Cu electroplating contains several electrolytes and additives. The roles which

these electrolytes and additives play are to control plating process and obtain good deposition quality. A

fundamental understanding of these substances roles is still deficient.

A traditional Cu electroplating solution usually contains 60–150 g/l of CuSO4•5H2O, 80–150 mI/l of H2SO4

50–150 ppm of HCl and some chemical additives. The copper(II) and sulfate solution dissociates in the

highly acidified solution to produce Cu2+ and SO42- ions. The silicon substrate (cathode) is connected to a

negative potential, at which Cu2+ reduction occurs. The copper electrode (99.95% Cu, 0.05% P) (anode) is

connected to a positive potential, copper metal is oxidized to produce Cu2+ions and dissolved in the

solution. The film properties are studied by altering concentrations of electroplating solution and

current density (1–4 A/dm2). The deposited copper film is characterized by using scanning electron

microscopy for morphology inspection and thickness measurement. The crystal structure is examined by

using x-ray diffraction. In addition, the effects of chemical additives of thiourea, polyethylene glycol, and

hydroxyl amine sulfate on Cu electroplating are described.

Bath additives can be used to improve film properties. Sulfuric Acid is the most commonly used additive

to cupric sulfate. Increasing the H2SO4 concentration decreases the Cu2+ diffusion and causes to

increase in polarization.

Fig 5: Copper resistivity as a function of current density for various bath concentrations (After (Gau, et al., 2000))

Fig 6: Dependence of film resistivity on concentration of sulfuric acid. The concentration of cupric sulfate is kept at 90g/l and current density is 2.4A/dm2 More complex arrangements can also be used depending on the feature size used in the wafer. The

Damascene Copper plating uses a thin copper seed which covers the complete wafer surface. Small

amounts of organic additives can increase the plating rate in features relative to the planar surface,

when added in the proper concentrations. The observed differential plating kinetics are better known as

superfilling, superconformal, or bottom-up plating. Typical copper-sulfate-based electroplating solutions

contain small amounts of chloride ions, polyethers such as polyethylene glycol (PEG) and polypropylene

glycol (PPG) as a suppressor additive, a sulfur-based organic molecule such as bis(sodiumsulfopropyl)

disulfide (SPS) as an accelerator or brightening agent, and in most cases an aromatic nitrogen-based

molecule or polymer that acts as a leveling agent to produce mirrorlike plated surfaces (Vereecken,

Binstead, Deligianni, & Andricacos, 2005).

Fig 7: �Reac ons at the copper/electrolyte interface in copper sulfate pla ng baths containing Cl , SPS [bis(sulfopropyl)disulfide: S(CH2)3SO3H)2] or MPS [mercaptopropane sulfonic acid: HS(CH2)3SO3H] as accelerator and a polyether suppressor molecule [H((CH2)xO)yOH]. The deprotonated MPS thiol group is indicated as ‘‘thiolate’’ in the formula. Reproduced from (Vereecken, Binstead, Deligianni, & Andricacos, 2005)

Other basic methods for Cu film deposition (Wong, et al., 1998) can also be used for copper deposition

depending on the design requirements.

To fabricate devices with relatively larger feature sizes (>25 µm line width and 50 µm spacing between

lines) a sub-etch process is made use of. In this process, a very thin film of Cu is deposited. The

deposition method can be either evaporation or sputtering. This film is photopatterned with a resist

followed by a wet etch to remove the unwanted Copper (Fig 8). However, the wet-etching introduces

some undercutting which becomes a limitaion for defining sharper features on the wafer. Few of the Dry

etching techniques can overcome this limitation, but the process proves to be expensive.

Another method of Cu film deposition is metal stencil liftoff (Fig 8b). In this method of Cu deposition, the

photo resist first defines the pattern. Several metal layers consisting of diffusion barrier and a conductor

are then evaporated over the substrate. This evaporation happens in the line of sight regime, and hence

the step coverage obtained is not satisfactory. This process of Liftoff was successfully used for IBM’s

S/390 series of computers (Wong, et al., 1998)

In the third method, a thin film of Chromium (200 Å) is deposited first. This layer of Chromium acts as an

adhesion layer between copper conductor and the dielectric. After the above step, a layer of electrically

conducting Copper is deposited by sputtering, followed by a photopatterning process. This is shown in

Fig 8c.

The fourth method of Cu deposition is the Damascene process. In this method, first, features are formed

on the wafer by defining the openings on the dielectric by photopatterns. These openings are then

backfilled with metal. And excess metal is removed by planarization step.

Fig 8: Different metallization techniques. (a) Sub-Etch, (b) lift-off, (c) plate-through mask, (d) damascene Courtesy: ©Metallization by plating for high performance multi chip modules, IBM. Damascene electroplating is ideally suited for the fabrication of interconnect structures, since it allows

inlaying of metal simultaneously in via holes and overlying line trenches (1).

There are some obvious advantages in using electroplated Copper for the metallization and interconnect

fabrication. Those are (1),

Plated Copper has a more desirable metallurgical structure, such as more ductility, the metal is equi-

axial, and it has a lower stress coefficient. The efficiency in filling the trenches and vias in electroplating

process is very high compared to conventional techniques. The processing time for plating is lesser thus

providing us with a much higher throughput. Plating is a relatively low cost process compared to

conventional deposition techniques considering the tools raw materials and maintenance. The

processing temperature of electroplating Cu is relatively lower than the PVD and CVD processes. (1)

Methods of Copper Electroplating: There are several approaches in electroplating Copper. (1)

Trench Filling (followed by wafer thinning) Metal bonding and bottom up filling One side plating and bottom up filling

Trench filling is particularly useful in for high aspect ratio devices. The advantage in using trench filling is;

easy wafer handling. That is, All the processes can be carried on by regular thick wafers and the thinning

process is done at the end. One disadvantage of this process is that the deep dry etching of the wafer

depends on the via size. That is, the larger the via, the higher the etch rate. This process is briefed in Fig

9.

Fig 9: Trench filling before wafer thinning. (a) Trench etching (b) Cu electroplating to fill the trenches (c) substrate thinning until the plugs are exposed. Courtesy: Journal of Micromechanics and Microengineering For Metal Bonding and bottom up filling, Slicon wafers with a patterned Si3N4 layer on the back are

etched in a KOH solution to form 100-140 µm thick membranes. The membranes are designed to

accommodate a large number of vias. A second wafer with a copper seed layer on top is coated with a

positive photoresist layer. This wafer is bonded to the wafers containing the vias by applying a small

pressure on the two wafers and by baking the stack. (1)

One Side Plating and Bottom Up Filling: The evaporation characteristic has a convenient characteristic that the evaporated metal cannot reach

deeply inside the vias, as in sputtering technique, due to higher deposition vacuum. As a result, the

copper islands are formed near the bottom of the vias and grow quickly.

The table below provides the key requirements for through mask plating.

Fig 10: key requirements for through mask plating (1)

Reliability Concerns for Copper Metallization: It is necessary to establish a sound reliability before utilizing the new process in any design environment.

There have been several experiments conducted to get a smoother Copper plating on the substrate and

to measure its current carrying capability.

One important problem with the Copper electroplating is that it can easily diffuse through both Si and

SiO2. This introduces an energy level deep into the bandgap of the substrate – which can be fatal for the

device being fabricated (1). One way to overcome this limitation is to deposit a barrier layer to avoid Cu

from diffusing into the substrate.

The largest defect contributors in plating through resist are surface contamination and resist

delamination. Surface contamination can be caused by photoresist residues, fingerprints, foreign

particles, and metal flakes from the plating fixtures. To minimize particle contamination, all thin film

processing is done in class 100 or better clean-room environment. Plating tanks are constructed with

inert polymeric materials, and plating solutions are constantly filtered with micron- or submicron-size

particle filters. Extraneous plated metal due to resist delamination and cracking is avoided by choosing

proper photoresist and optimizing postdeveloped baking conditions.

Capping of Plated Copper: (Wong, Kaja, & DeHaven, 1998)

For many polyimides, it is desirable to have a layer of adhesion promoter over the plated copper before

coating with polymer. Copper can react chemically with these adhesion promoters as well as with

polyimide precursors containing free acid groups. Therefore, it is necessary to protect the plated copper

with a thin layer of capping material. After testing of different candidate materials, electrolessly

deposited cobalt- phosphorus (CoP) was selected as the capping layer [31]. One concern in using a

capping layer is that the copper and the cap will react during subsequent annealing, resulting in

degradation of the electrical properties of the copper. Figure 11 shows the percentage change in the

resistance of copper with a CoP layer after simulation of two polyimide cure cycles. The resistance

change in the metal stack is negligible; the presence of both positive and negative values suggests that

the changes observed are the result of measurement error. The use of less-reactive polyimide dielectrics

to make the capping layer unnecessary is currently under development

Fig 11: Electromigration lifetimes (for 20% increase in resistance) for Al(Cu) versus Cu 0.3 µm lines illustrating the large improvement in the Cu technology at indicated stress conditions. (Rosenberg, Edelstein, Hu, & Rodbell, 2000) For intrinsic wire reliability, the Cu electromigration resistance for the plated Cu was confirmed to be

orders of magnitude better than that of Ti/Al(Cu)/Ti, as reported The Cu lifetime improvement at chip-

use tempaertatures would be greaterbased on higher activation energy measured for the Cu wires.

Apart from the simplicity of the tooling and maintenance, a proper Cu electroplating contributes to

improved reliability of the resulting Damascene Cu interconnects.

There is another method for obtaining smoother a practical need for electrochemical polishing arises

because electrodeposition processes fill features with sizes that typically span at east an order of

magnitude even within a single level of metallization. For this and other reasons, the overburden of the

deposited film may be much larger than the smallest feature size, as shown in Figure 12.

Figure 12: Schematic diagram illustrating that the overburden thickness of an electrodeposited film may be much larger than the smallest feature width. Commonly, the overburden is thicker than average above the smallest features, and dishing below the average overburden thickness is observed above the wide features. The bump over the small features and the dish size are strongly dependent on the electrochemical deposition process. Courtesy: (West, Deligianni, & Andricacos, 2005)

For example, even for the 100-nm node, it is common that more than one lm of copper must be

electrodeposited, and the topography above the largest figures may exhibit dishing. This extra copper

must be removed in a subsequent processing step. For this reason, alternative designs such as

electrochemical mechanical deposition, in which mechanical removal is coupled with the

electrodeposition process, reducing the overburden significantly, have been proposed. At present,

chemical mechanical planarization (CMP) is the primary method used for removing the overburden, and

the removal rate is controlled in part by the mechanical force applied during the polishing step. CMP

may also be employed in the same step to remove the liner material overlying the dielectric. Thus,

electrochemical methods for the removal of liner films such as Ta or TaN may also be of interest.

Nevertheless, the present paper focuses on copper. In the near future, the ability to achieve acceptable

polishing rates with CMP may be compromised by the introduction of low-dielectric-constant materials

that do not have the requisite mechanical properties to withstand large mechanical forces during CMP.

Alternative metal-removal methods should enable high dissolution rates without subjecting the

substrate to excessively large pressures. Electrochemical dissolution methods, either as a CMP

replacement or a complement to CMP, have received a fair amount of recent attention [8–16].

Depending on bath temperature, electrolyte composition, applied voltage, and fluid flow,

electrochemical removal rates may be anticipated to correspond to current densities between 10 and

100 mA/cm 2 . Assuming that the dissolution product is Cu 2þ and that a 100% current efficiency is

achieved, the etch rate u can be related to current density through an application of Faraday’s law:

FIVu m

2

where Vm is the molar volume of copper, i is the current density, and F is Faraday’s constant (96,487

coulombs per mole).

Conclusion: Copper Electroplating has raised a lot of expectations as a new technology in interconnect metallization

techniques for fabricating low cost – and a reliable metallization technique. There are still challenges in

the field, to obtain a better interconnect. Various experiments are being conducted to find out new

ways of electroplating copper and some of the experiments are used to manufacture chips

commercially. Nevertheless, still more literatures are awaited which would shed more light on the

feasibilities and vagaries of electroplating technology.

Bibliography 1. Filling Mechanism in Microvia metallization by copper electroplating. Wei-Ping Dow, Ming-Yao Yen, Sian-Zong Liao, Yong-Da Chiu, Hsiao-Chung Huang. 2008, http://elsevier.com/locate/electacta, pp. 8228-8237. 2. Rosenberg, R, et al. Copper Metallization for high Performance Silicon Technology. New York : Annual Reviews, 2000.

3. Seah, C H, et al. Characterization of Electroplated Copper films for three dimensional advanced packaging. Singapore : Institute of MicroElectronics, 2004. 4. Metallization by plating for high performance chip modules. Wong, K. K. H, Kaja, S. and DeHaven, P. W. 5, New York : IBM, 1998, Vol. 42. 10.1147/rd.425.0587. 5. Campbell, Stephen A. Fabrication Engineering at the Micro and Nanoscale. New york : Oxford University Press, 2008. ISBN 978-0-19-532017-6. 6. Copper Electroplating for future ultralarge scale integration interconnection. Gau, W. C., et al. 2, s.l. : J. Vac Sci Technology, 2000, Vol. 18. 7. Through Wafer Copper Electroplating for three dimensional interconnects. Nguyen, N. T, et al. Netherlands : Journal of Micromechanics and MicroEngineering, 2002. 8. Damascene copper electroplating for chip interconnections . Andricacos, P. C., et al. New York : IBM, 1998. 0018-8646/98. 9. The Chemistry of additives in Decamescene copper plating. Vereecken, P. M., et al. 2005, IBM Journal of RES. & DEV. 10. Electrochemical planarization of Interconnect Metallization. West, A. C., Deligianni, H. and Andricacos, P. C. New York : IBM Journal of Research and Development, 2005.