MetalMUMPs Process Flow Stafford Johnson Advanced Development Engineering Manager.
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Transcript of MetalMUMPs Process Flow Stafford Johnson Advanced Development Engineering Manager.
![Page 1: MetalMUMPs Process Flow Stafford Johnson Advanced Development Engineering Manager.](https://reader036.fdocuments.us/reader036/viewer/2022062803/56649cb75503460f9497ccb1/html5/thumbnails/1.jpg)
MetalMUMPsMetalMUMPsProcess Flow Process Flow
Stafford Johnson
Advanced Development Engineering Manager
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MetalMUMPs ProcessMetalMUMPs Process
(1) Electroplated nickel is used as the primary structural material and electrical interconnect layer
(2) Doped polysilicon can be used for resistors, additional mechanical structures, and/or cross-over electrical routing.
(3) Silicon nitride is used as an electrical isolation layer
(4) Deposited oxide (PSG) is used for the sacrificial layers
(5) A trench layer in the silicon substrate can be incorporated for additional thermal and electrical isolation
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MetalMUMPs ProcessMetalMUMPs Process
FIGURE 1.2. A 2m thick oxide (Isolation Oxide) is grown on the surface of the starting n-type (100) silicon wafer. This is followed by deposition of a 0.5m thick sacrificial phosphosilicate glass (PSG) layer (Oxide 1).
Oxide 1 Deposited
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MetalMUMPs ProcessMetalMUMPs Process
FIGURE 1.3 The wafers are coated with UV-sensitive photoresist and lithographically patterned by exposing to UV light through the first level mask (OXIDE1), and then developing it. The photoresist in exposed areas is removed, leaving behind a patterned photoresist mask for etching. Wet chemical etching is used to remove the unwanted sacrificial PSG. After the etch, the photoresist is chemically stripped.
Oxide 1 Patterned
Mask Level: OXIDE1
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MetalMUMPs ProcessMetalMUMPs Process
FIGURE 1.4. A 0.35m layer of silicon nitride (Nitride 1) is deposited, followed immediately by the deposition of a 0.7m layer of polysilicon (Poly).
Nitride 1 and Poly Deposited
Mask Level: OXIDE1
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MetalMUMPs ProcessMetalMUMPs Process
FIGURE 1.5. The wafers are coated with photoresist and the second level (POLY) is lithographically patterned. Reactive ion etching (RIE) is used to remove the unwanted polysilicon. After the etch is completed, the photoresist is removed.
Poly Patterned
Mask Level: POLY
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MetalMUMPs ProcessMetalMUMPs Process
FIGURE 1.6. A second 0.35m layer of silicon nitride (Nitride 2) is deposited.
Nitride 2 Deposited
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MetalMUMPs ProcessMetalMUMPs Process
FIGURE 1.7. The wafers are coated with photoresist and the third level (NITRHOLE) is lithographically patterned. RIE etching is performed to remove both Nitride 2 and Nitride 1 from the patterned areas. After the etch is complete, the photoresist is removed. Note: Nitride 1 will remain anywhere NITRHOLE is patterned over Poly.
Nitride(s) Patterned
Mask Level: NITRHOLE
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MetalMUMPs ProcessMetalMUMPs Process
FIGURE 1.8. A second sacrificial layer (Oxide 2), 1.1m of PSG, is deposited and annealed at 1050C for 1 hour.
Oxide 2 Deposited
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MetalMUMPs ProcessMetalMUMPs Process
FIGURE 1.9. The wafer is coated with photoresist and the fourth mask level (METANCH) is lithographically patterned. The Oxide 2 is wet etched and a thin metal layer (Anchor Metal) consisting of 10nm Cr + 25nm Pt is deposited. A liftoff process is used to remove the photoresist and leave Anchor Metal only in the bottom of the Oxide 2 openings formed from the METANCH mask level.
Oxide 2 Patterned and Anchor Metal Dep
Mask Level: METANCH
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MetalMUMPs ProcessMetalMUMPs Process
FIGURE 1.10 The Plating base layer, consisting of 500nm Cu + 50nm Ti is deposited. (Not shown). The wafers are coated with a thick layer of photoresist and patterned with the fifth mask level (METAL). This process forms a patterned stencil for the electroplated Metal layer.
Plating Base Dep and Plating Stencil Patterned
Mask Level: METAL
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MetalMUMPs ProcessMetalMUMPs Process
FIGURE 1.11. Nickel is electroplated to a nominal thickness of 20m into the patterned resist stencil. A 0.5m gold layer is then immediately electroplated on top of the nickel layer. This forms the Metal layer.
Metal Plated
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MetalMUMPs ProcessMetalMUMPs Process
FIGURE 1.12. The photoresist stencil is then chemically removed.
Plating Stencil Removed
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MetalMUMPs ProcessMetalMUMPs Process
FIGURE 1.13. The wafers are coated with photoresist and patterned with a “bloated” version of the sixth mask level (GOLDOVP) to remove Plating Base in the regions where Sidewall Metal is desired. The Plating Base is chemically removed from the unpatterned regions, and the photoresist is stripped. The wafers are coated with photoresist and patterned with an “un-bloated” version of the sixth mask level (GOLDOVP) to define a resist stencil in the regions of Metal where electroplated Sidewall Metal is desired.
Gold Over Plating Stencil Patterned
Mask Level: GOLDOVP
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MetalMUMPs ProcessMetalMUMPs Process
FIGURE 1.14. A 1-3m gold layer (Sidewall Metal) is electroplated using the GOLDOVP photoresist mask as a stencil.
Gold Over Plating
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MetalMUMPs ProcessMetalMUMPs Process
FIGURE 1.15. The GOLDOVP resist stencil is stripped.
Gold Over Plating Stencil Removed
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MetalMUMPs ProcessMetalMUMPs Process
FIGURE 1.16. Plating Base is chemically stripped in the first step of the release process. In the second step of the release process, a 49% HF solution is used to remove the PSG sacrificial layers (Oxide 1 and Oxide 2) and the Isolation Oxide layer over the trench areas.
Plating Base and Sacrificial Oxides Removed
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MetalMUMPs ProcessMetalMUMPs Process
FIGURE 1.17. In the final step of the release process, a KOH silicon etch is used to form a 25m deep trench in the silicon substrate in the areas defined by the OXIDE1 and NITRHOLE mask levels. A protective coating is applied, wafers are diced, cleane, sorted and shipped to customer.
Trench Formed – Silicon Etched
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MetalMUMPs Published PaperMetalMUMPs Published Paper
• Two Movable Plate Nitride Loaded MEMS Variable Capacitor
– Maher Bakri- Kassem and Raafat R. Mansour University of Waterloo
– A MEMS variable capacitor having two movable plates loaded with a Nitride layer is proposed. A trench in the silicon substrate underneath the capacitor is used to decrease the parasitic capacitance. The use of an insulation dielectric layer on the bottom plate of the MEMS capacitor increases the capacitor’s tuning range and eliminates sticktion. The tuning range was measured and found to be 280% at 1 GHz. The achievable tuning range far exceeds that of the traditional parallel plate MEMS variable capacitors. The proposed MEMS variable capacitor is built using the MetalMUMPs process.
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MetalMUMPs Published PaperMetalMUMPs Published Paper
• Two Movable Plate Nitride Loaded MEMS Variable Capacitor – Maher Bakri- Kassem and Raafat R. Mansour
University of Waterloo
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Poly/Nickel powered gripperPoly/Nickel powered gripper
• Tethering 0% effective as indicated previously by JDSU
• Same tether as other grippers and parts – placement along bottom only was ineffective
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Parts for assemblyParts for assembly
• 100% successful tethering
• 0% success parts removal with gripper
• 100% successful tether break with probe and part release
• No successful assembly yet
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Parts for assemblyParts for assembly
• Nitride with poly rib tether was 100% effective– Poly rib
– Nitride hole
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MetalMUMPs Bistable RelayMetalMUMPs Bistable Relay
Contacts
Disengage actuators
Engage actuators
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Thermal actuatorThermal actuator
Polysilicon heater
Electroplated nickel actuator
• Structural layers can be electrically insulated from thermal heaters
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Shuttle MotionShuttle Motion
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What Can You Make in MetalMUMPs?What Can You Make in MetalMUMPs?Copper Cross Connect SwitchCopper Cross Connect Switch
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