Mentor Graphics Solutions Enable Fast, Efficient Designs ...€¦ · Mentor Graphics FPGA Design...
Transcript of Mentor Graphics Solutions Enable Fast, Efficient Designs ...€¦ · Mentor Graphics FPGA Design...
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Mentor Graphics Solutions Enable Fast, Efficient Designs for Altera’s FPGAs
Fall 2004
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Agenda
FPGA design challengesMentor Graphics comprehensive FPGA design solutionsUnique tools address the full range of complex device- and system-level challenges
— HDL Designer Series— ModelSim— Precision Synthesis — I/O Designer
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Complex FPGA Systems Demand New Design Approaches
High-end FPGA/FPSoC- Complex timing- Physical timing problems- IP integration- HW/SW design- Complex debug- Prototyping- SDC constraints- C-based design- PCB integration issues- Team design
Mainstream / Ready-to-use FPGA/PLDs
-Synthesize
-Place & Route
-Simulate/Debug
Low-cost toolsPush-button flow
Sophisticated tools ASIC-like flow
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Mentor Graphics FPGA Design Flow
Most comprehensive in the industry
Incorporates complex FPGA design aspects
– Embedded systems
– RTL simulation and synthesis including incremental synthesis
– Physical timing closure
– Integrated (FPGA/ PCB) systems design
““Mentor Graphics led commercial EDA vendors in serving the FPGA design
community. They beat out all other commercial vendors in a range of
categories, including a clear vision of the future.””
(EEDesign, June 6, 2004, based on FPGA EDA study conducted by EE Times)
Altera SOPC, Fall 20044
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Some Mentor Graphics FPGA Design Product Names
FPGA Advantage®— Complete FPGA design
environmentHDL Designer Series™
— Design creation, reuse, management, documentation, and design flow control environment
ModelSim®— HDL simulation
Precision® Synthesis— RTL synthesis — Physical synthesis
Catapult™ C Synthesis— Algorithmic, untimed C/C++
synthesis for FPGA/ASIC LeonardoSpectrum™
— FPGA and ASIC synthesis
Seamless™— Hardware/Software co-verification
environmentXRAY® Debugger
— Software debug for embedded processors
Inventra™ IP— IP cores for faster, reliable time to
marketNucleus™
— RTOS family of embedded software
HyperLynx ®— SI and EMC analysis suite
I/O Designer™— Integrated systems design,
enabling concurrent FPGA-on-board design
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FPGA Advantage The FPGA Design Flow
HDL Designer SeriesHDL Design
ModelSimSimulation
Precision SynthesisSynthesis
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HDL Designer Series: Design Creation
Interface-based design (IBD)— Structural design definition— Synthesis properties
specified for flow — Aids documentation
Block diagramText entryState machineFlow chartTruth tableModuleWare
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HDL Designer Series: Team Design Environment
BBB
CC
AA
A B C
FPGA design teams — 1, 5, 10+ engineers— Blocks designed
separately but in context of entire design
— Version control
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HDL Designer Series:Design Visualization & Documentation
Design structure Block diagrams
Interface-based design
State diagrams
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ModelSim 6.0 Verification Environment
Standards:VHDL, Verilog, SystemVerilog,PSL, SystemC
TestbenchAutomation
Coverage-DrivenVerification
Integrated DebugEnvironment
Assertion-Based
Verification
System-LevelDesign
Most widely used simulator in the world— #1 in Mixed-HDL simulation
Only unified verification environment supporting all major standards
— VHDL, Verilog, SystemVerilog, SystemC and PSL
Complete path from simulation to “Scalable Verification”Dedicated to high-performance Powerful and easy-to-useAward-winning Technical SupportBest price/feature/performance
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ModelSim 6.0 Verification Highlights
Add Verilog PSL to existing VHDL supportFunctional coverage
— Based on PSL SystemC enhancementsMore performanceMore SystemVerilog
— Nearly all design constructs— DPI
Highly intelligent GUIShipping now (August 2004)
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ModelSim 6.0 Modernized GUI
GUIGUISupport for new methodologies— Assertion browser supports control
and debugging with ABV — Functional coverage browser
provides loading, control and reporting of functional coverage directives
ModelSim is recognized as having best native GUI in the industry…
— Best interactive debugger— All-in-one— Language Independent— Tcl/tk expandability
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ModelSim 6.0 Improved User Interface
New window layout
Reorganized display of data
Uses fewer windows
Improved window manager
More efficient use of screen real estate
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Precision Synthesis:Integrated Logical & Physical Synthesis
Synthesis Rules &Libraries
TimingConstraints
RTLSourceCode
PhysicalConstraints
PhysicalRules &Libraries
PrecisionSynthesis
RTLSynthesis
PhysicalSynthesis
Combined Netlist & Detail Placement
Productivity enhancing synthesis tool suite
— RTL + Physical
Addresses design challenges of advanced, complex devices
— Predictable design schedules— Reduced number of design
iterations— Achieves timing closure
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Precision RTL SynthesisEase of use and competitive quality of results (QoR)
— Incremental timing analysis allows rapid constraint debug iterationsEliminates the need to re-run synthesis, or even a full static timing analysis again
— Fewer design iterationsPrecision RTL finds and incrementally fixes timing closure issues, early
— Easy migration from ASICsStandard SDC constraint file format
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Precision Physical Synthesis
The market leader that integrates RTL and Physical domain knowledge
— Reduces design iterations by linking physical data with logic synthesis
— Improves timing convergence by enhancing design analysis with ease of use
Intelligent and easy-to-use timing analysisCross-probe between RTL code, schematic, physical and timing views
— Improves performance by interactively optimizing the placed design
Supports Altera devices beginning with May 2004 release
— Stratix, Stratix GX and Cyclone
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Why Precision Physical Synthesis?
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Traditional approach to timing convergence
— Iterative methodsWriting/re-writing RTL codeModifying constraints/attributesMultiple synthesis runsMultiple P&R runs
— Floorplanning
With Precision Physical— Faster time to performance
Uses exact knowledge of placement / physical delays
— Fast, incremental, deterministicPlacement optimization based on physical delaysAvailable resources guide optimization
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Traditional Floorplanning Fails
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LUT Register
LE Boundary LAB Boundary400ps
1ps*
800ps
500ps
Delay is not a regular function of distance at a detailed placement level
*Stratix-specific delay values
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I/O Designer: Concurrent FPGA-PCB Design
I/O Designer
FPGA Device Libraries
Synthesis
FPGA Place & Route tools
HDL Design
Simulation
P&R Pin Map
P&R Constraints
Constraints
VHDL or Verilog Functional Symbol
PCB Symbol and Schematic
Schematic Entry
PCB Layout
Device Geometry &
Symbol LibrariesFPGA Design Flow
PCB Flow
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I/O Designer: Productivity
Automatic FPGA – PCB symbol integration
— Eliminates symbol creation and maintenance costs
— Eliminates man-weeks of effort
— Eliminates manual data entry issues
— Promotes correct by construction
$0
$5,000
$10,000
$15,000
$20,000
0 500 1,000 1,500 2,000
FPGA Pins
Symbol Creation
30 IO Iterations
2010
$0
$5,000
$10,000
$15,000
$20,000
0 500 1,000 1,500 2,000
FPGA Pins
Symbol Creation
30 IO Iterations
2010
02468
101214161820
0 500 1,000 1,500 2,000
FPGA Pins
Days
Symbol Creation
30 IO Iterations20
10
02468
101214161820
0 500 1,000 1,500 2,000
FPGA Pins
Days
Symbol Creation
30 IO Iterations20
10
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I/O Designer: Serial versus ConcurrentTraditional Flow:
FPGADesign
PCBDesign
PCBDesign
FPGA Design
FPGA Design
PCBDesign
Initial Integration Pin Change time
I/O Designer Flow:
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I/O Design
FPGA Design
PCB Design
I/O Design
PCB Design
FPGA Design
Time to market savings
timeInitial Integration Pin Change
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I/O Designer: PCB Manufacturing Optimizations
Multi-component, view-driven I/O design and optimization
— Minimize crossovers— Unravel busses— Assign compatible I/O
standards across multiple FPGAs
— PCB design leads FPGADrives FPGA design flow
— FPGA leads PCBPCB floorplanning drives PCB design flow
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Design Project Saving > 1 Month per complex FPGA on a PCB
PCB
Optimized IOFPGA 1 FPGA 2
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Summary
Mentor Graphics has all the tools you need to handle your next advanced Altera FPGA design
— HDL Designer
— ModelSim
— Precision Synthesis
— I/O Designer
Industry leading toolsUnique functionalitySignificant productivity gains
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To Learn More
Go to http://www.mentor.comVisit the Mentor Graphics Booth
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