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Introducere in Sisteme Micro-Electro-Mecanice (MEMS)

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Micro-Electro-Mechanical Systems (MEMS) is the integration of mechanical elements,sensors, actuators, and electronics on a common silicon substrate throughmicrofabrication technology. While the electronics are fabricated using integrated circuit(IC) process sequences (e.g., CMOS, Bipolar, or BICMOS processes), themicromechanical components are fabricated using compatible "micromachining"processes that selectively etch away parts of the silicon wafer or add new structural layersto form the mechanical and electromechanical devices.

MEMS promises to revolutionize nearly every product category by bringing togethersilicon-based microelectronics with micromachining technology, making possible therealization of completesystems-on-a-chip. MEMS is an enabling technology allowingthe development of smart products, augmenting the computational ability ofmicroelectronics with the perception and control capabilities of microsensors andmicroactuators and expanding the space of possible designs and applications.Microelectronic integrated circuits can be thought of as the "brains" of a system andMEMS augments this decision-making capability with "eyes" and "arms", to allowmicrosystems to sense and control the environment. Sensors gather information from theenvironment through measuring mechanical, thermal, biological, chemical, optical, and

magnetic phenomena. The electronics then process the information derived from thesensors and through some decision making capability direct the actuators to respond bymoving, positioning, regulating, pumping, and filtering, thereby controlling theenvironment for some desired outcome or purpose. Because MEMS devices aremanufactured using batch fabrication techniques similar to those used for integratedcircuits, unprecedented levels of functionality, reliability, and sophistication can beplaced on a small silicon chip at a relatively low cost.

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Fabricating MEMS and Nanotechnology

MEMS and Nano devices are extremelysmall -- for example, MEMS and

Nanotechnology has made possibleelectrically-driven motors smaller than thediameter of a human hair (right) -- butMEMS and Nanotechnology is not primarilyabout size.MEMS and Nanotechnology is also notabout making things out of silicon, eventhough silicon possesses excellent materials properties, which make it an attractive choicefor many high-performance mechanical applications; for example, the strength-to-weightratio for silicon is higher than many other engineering materials which allows very high-bandwidth mechanical devices to be realized.

Ghidul incepatorului pentru fabricarea MEMS

This guide is intended for people new to microelectromechanical systems (MEMS)technology. It gives a brief overview of the technology and some of the methods used tocreate microstructures. The guide is not intended as a comprehensive, all inclusive,description which is pointless anyway as the technology continues to develop. It ismerely a short introduction to the basic fundamentals of the technology. If you areexperienced in MEMS, you may not find much new information here.MEMS technology is based on a number of tools and methodologies, which are used toform small structures with dimensions in the micrometer scale (one millionth of a meter).Significant parts of the technology has been adopted from integrated circuit (IC)technology. For instance, almost all devices are build on wafers of silicon, like ICs. Thestructures are realized in thin films of materials, like ICs. They are patterned usingphotolithographic methods, like ICs. There are however several processes that are notderived from IC technology, and as the technology continues to grow the gap with ICtechnology also grows.

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There are three basic building blocks in MEMS technology, which are the ability todeposit thin films of material on a substrate, to apply a patterned mask on top of the filmsby photolithograpic imaging, and to etch the films selectively to the mask. A MEMSprocess is usually a structured sequence of these operations to form actual devices. Pleasefollow the links below to read more about deposition, lithography and etching.

Deposition processesLithography

Etching processes

Deposition Processes

MEMS Thin Film Deposition Processes

One of the basic building blocks in MEMS processing is the ability to deposit thin filmsof material. In this text we assume a thin film to have a thickness anywhere between a

few nanometer to about 100 micrometer. The film can subsequently be locally etchedusing processes described in theLithographyandEtchingsections of this guide.MEMS deposition technology can be classified in two groups:

1. Depositions that happen because of achemical reaction: Chemical Vapor Deposition (CVD) Electrodeposition Epitaxy Thermal oxidation

These processes exploit the creation of solid materials directly from chemicalreactions in gas and/or liquid compositions or with the substrate material. Thesolid material is usually not the only product formed by the reaction. Byproducts

can include gases, liquids and even other solids.2. Depositions that happen because of aphysical reaction:

Physical Vapor Deposition (PVD) Casting

Common for all these processes are that the material deposited is physicallymoved on to the substrate. In other words, there is no chemical reaction whichforms the material on the substrate. This is not completely correct for castingprocesses, though it is more convenient to think of them that way.

This is by no means an exhaustive list since technologies evolve continuously.

Chemical Vapor Deposition (CVD)

In this process, the substrate is placed inside a reactor to which a number of gases aresupplied. The fundamental principle of the process is that a chemical reaction takes placebetween the source gases. The product of that reaction is a solid material with condenseson all surfaces inside the reactor.The two most important CVD technologies in MEMS are theLowPressure CVD(LPCVD) andPlasmaEnhanced CVD (PECVD). The LPCVD process produces layerswith excellent uniformity of thickness and material characteristics. The main problemswith the process are the high deposition temperature (higher than 600C) and the

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relatively slow deposition rate. The PECVD process can operate at lower temperatures(down to 300 C) thanks to the extra energy supplied to the gas molecules by the plasmain the reactor. However, the quality of the films tend to be inferior to processes running athigher temperatures. Secondly, most PECVD deposition systems can only deposit thematerial on one side of the wafers on 1 to 4 wafers at a time. LPCVD systems deposit

films on both sides of at least 25 wafers at a time. A schematic diagram of a typicalLPCVD reactor is shown in the figure below.

Figure 1:Typical hot-wall LPCVD reactor.

When do I want to use CVD?

CVD processes are ideal to use when you want a thin film with good step coverage. A

variety of materials can be deposited with this technology, however, some of them areless popular with fabs because of hazardous byproducts formed during processing. Thequality of the material varies from process to process, however a good rule of thumb isthat higher process temperature yields a material with higher quality and less defects.

Electrodeposition

This process is also known as "electroplating" and is typically restricted to electricallyconductive materials. There are basically two technologies for plating: Electroplating andElectroless plating. In the electroplating process the substrate is placed in a liquidsolution (electrolyte). When an electrical potential is applied between a conducting areaon the substrate and a counter electrode (usually platinum) in the liquid, a chemical redoxprocess takes place resulting in the formation of a layer of material on the substrate andusually some gas generation at the counter electrode.In the electroless plating process a more complex chemical solution is used, in whichdeposition happens spontaneously on any surface which forms a sufficiently highelectrochemical potential with the solution. This process is desirable since it does notrequire any external electrical potential and contact to the substrate during processing.Unfortunately, it is also more difficult to control with regards to film thickness anduniformity. A schematic diagram of a typical setup for electroplating is shown in thefigure below.

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When do I want to use electrodeposition?

The electrodeposition process is well suited to make films of metals such as copper, goldand nickel. The films can be made in any thickness from ~1m to >100m. Thedeposition is best controlled when used with an external electrical potential, however, itrequires electrical contact to the substrate when immersed in the liquid bath. In any

process, the surface of the substrate must have an electrically conducting coating beforethe deposition can be done.

Figure 2:Typical setup for electrodeposition.

Epitaxy

This technology is quite similar to what happens in CVD processes, however, if the

substrate is an ordered semiconductor crystal (i.e. silicon, gallium arsenide), it is possiblewith this process to continue building on the substrate with the same crystallographicorientation with the substrate acting as a seed for the deposition. If anamorphous/polycrystalline substrate surface is used, the film will also be amorphous orpolycrystalline.There are several technologies for creating the conditions inside a reactor needed tosupport epitaxial growth, of which the most important isVapor PhaseEpitaxy (VPE). Inthis process, a number of gases are introduced in an induction heated reactor where onlythe substrate is heated. The temperature of the substrate typically must be at least 50% ofthe melting point of the material to be deposited.An advantage of epitaxy is the high growth rate of material, which allows the formation

of films with considerable thickness (>100m). Epitaxy is a widely used technology forproducing silicon on insulator (SOI) substrates. The technology is primarily used fordeposition of silicon. A schematic diagram of a typical vapor phase epitaxial reactor isshown in the figure below.

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When do I want to use epitaxy?

This has been and continues to be an emerging process technology in MEMS. Theprocess can be used to form films of silicon with thicknesses of ~1m to >100m. Someprocesses require high temperature exposure of the substrate, whereas others do notrequire significant heating of the substrate. Some processes can even be used to perform

selective deposition, depending on the surface of the substrate.

Figure 3:Typical cold-wall vapor phase epitaxial reactor.

Thermal oxidation

This is one of the most basic deposition technologies. It is simply oxidation of thesubstrate surface in an oxygen rich atmosphere. The temperature is raised to 800 C-1100 C to speed up the process. This is also the only deposition technology whichactually consumes some of the substrate as it proceeds. The growth of the film is spurnedby diffusion of oxygen into the substrate, which means the film growth is actuallydownwards into the substrate. As the thickness of the oxidized layer increases, thediffusion of oxygen to the substrate becomes more difficult leading to a parabolicrelationship between film thickness and oxidation time for films thicker than ~100nm.This process is naturally limited to materials that can be oxidized, and it can only formfilms that are oxides of that material. This is the classical process used to form silicondioxide on a silicon substrate. A schematic diagram of a typical wafer oxidation furnaceis shown in the figure below.

When do I want to use thermal oxidation?

Whenever you can! This is a simple process, which unfortunately produces films withsomewhat limited use in MEMS components. It is typically used to form films that are

used for electrical insulation or that are used for other process purposes later in a processsequence.

Physical Vapor Deposition (PVD)

PVD covers a number of deposition technologies in which material is released from asource and transferred to the substrate. The two most important technologies areevaporation and sputtering.

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When do I want to use PVD?

PVD comprises the standard technologies for deposition of metals. It is far more commonthan CVD for metals since it can be performed at lower process risk and cheaper inregards to materials cost. The quality of the films are inferior to CVD, which for metalsmeans higher resistivity and for insulators more defects and traps. The step coverage is

also not as good as CVD.The choice of deposition method (i.e. evaporation vs. sputtering) may in many cases bearbitrary, and may depend more on what technology is available for the specific materialat the time.

Figure 4:Typical wafer oxidation furnace.

EvaporationIn evaporation the substrate is placed inside a vacuum chamber, in which a block (source)of the material to be deposited is also located. The source material is then heated to thepoint where it starts to boil and evaporate. The vacuum is required to allow the moleculesto evaporate freely in the chamber, and they subsequently condense on all surfaces. Thisprinciple is the same for all evaporation technologies, only the method used to the heat(evaporate) the source material differs. There are two popular evaporation technologies,which are e-beam evaporation and resistive evaporation each referring to the heatingmethod. In e-beam evaporation, an electron beam is aimed at the source material causinglocal heating and evaporation. In resistive evaporation, a tungsten boat, containing thesource material, is heated electrically with a high current to make the material evaporate.

Many materials are restrictive in terms of what evaporation method can be used (i.e.aluminum is quite difficult to evaporate using resistive heating), which typically relates tothe phase transition properties of that material. A schematic diagram of a typical systemfor e-beam evaporation is shown in the figure below.

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Figure 5:Typical system for e-beam evaporation of materials.

Sputtering

Sputtering is a technology in which the material is released from the source at muchlower temperature than evaporation. The substrate is placed in a vacuum chamber withthe source material, named a target, and an inert gas (such as argon) is introduced at lowpressure. A gas plasma is struck using an RF power source, causing the gas to becomeionized. The ions are accelerated towards the surface of the target, causing atoms of thesource material to break off from the target in vapor form and condense on all surfacesincluding the substrate. As for evaporation, the basic principle of sputtering is the samefor all sputtering technologies. The differences typically relate to the manor in which theion bombardment of the target is realized. A schematic diagram of a typical RF sputtering

system is shown in the figure below.

Figure 6:Typical RF sputtering system.

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Casting

In this process the material to be deposited is dissolved in liquid form in a solvent. Thematerial can be applied to the substrate by spraying or spinning. Once the solvent isevaporated, a thin film of the material remains on the substrate. This is particularly usefulfor polymer materials, which may be easily dissolved in organic solvents, and it is the

common method used to apply photoresist to substrates (in photolithography). Thethicknesses that can be cast on a substrate range all the way from a single monolayer ofmolecules (adhesion promotion) to tens of micrometers. In recent years, the castingtechnology has also been applied to form films of glass materials on substrates. The spincasting process is illustrated in the figure below.

When do I want to use casting?

Casting is a simple technology which can be used for a variety of materials (mostlypolymers). The control on film thickness depends on exact conditions, but can besustained within +/-10% in a wide range. If you are planning to use photolithography youwill be using casting, which is an integral part of that technology. There are also other

interesting materials such as polyimide and spin-on glass which can be applied bycasting.

Figure 7:The spin casting process as used for photoresist in photolithography.

Etching ProcessesIn order to form a functional MEMS structure on a substrate, it is necessary to etch thethin films previously deposited and/or the substrate itself. In general, there are twoclasses of etching processes:

3. Wet etching where the material is dissolved when immersed in a chemicalsolution4. Dry etching where the material is sputtered or dissolved using reactive ions or avapor phase etchant

In the following, we will briefly discuss the most popular technologies for wet and dryetching.

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Lithography

Pattern Transfer

Lithography in the MEMS context is typically the transfer of a pattern to a photosensitivematerial by selective exposure to a radiation source such as light. A photosensitive

material is a material that experiences a change in its physical properties when exposed toa radiation source. If we selectively expose a photosensitive material to radiation (e.g. bymasking some of the radiation) the pattern of the radiation on the material is transferredto the material exposed, as the properties of the exposed and unexposed regions differs(as shown in figure 1).

Figure 1:Transfer of a pattern to a photosensitive material.This discussion will focus on optical lithography, which is simply lithography using aradiation source with wavelength(s) in the visible spectrum.In lithography for micromachining, the photosensitive material used is typically aphotoresist (also called resist, other photosensitive polymers are also used). When resistis exposed to a radiation source of a specific a wavelength, the chemical resistance of theresist to developer solution changes. If the resist is placed in a developer solution afterselective exposure to a light source, it will etch away one of the two regions (exposed orunexposed). If the exposed material is etched away by the developer and the unexposedregion is resilient, the material is considered to be a positive resist (shown in figure 2a). Ifthe exposed material is resilient to the developer and the unexposed region is etchedaway, it is considered to be a negative resist (shown in figure 2b).

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Figure 2: a) Pattern definition in positive resist, b) Pattern definition in negative resist.

Lithography is the principal mechanism for pattern definition in micromachining.Photosensitive compounds are primarily organic, and do not encompass the spectrum ofmaterials properties of interest to micro-machinists. However, as the technique is capableof producing fine features in an economic fashion, a photosensitive layer is often used asa temporary mask when etching an underlying layer, so that the pattern may betransferred to the underlying layer (shown in figure 3a). Photoresist may also be used as a

template for patterning material deposited after lithography (shown in figure 3b). Theresist is subsequently etched away, and the material deposited on the resist is "lifted off".The deposition template (lift-off) approach for transferring a pattern from resist toanother layer is less common than using the resist pattern as an etch mask. The reason forthis is that resist is incompatible with most MEMS deposition processes, usually becauseit cannot withstand high temperatures and may act as a source of contamination.

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Figure 3: a) Pattern transfer from patterned photoresist to underlying layer by etching,

b) Pattern transfer from patterned photoresist to overlying layer by lift-off.Once the pattern has been transferred to another layer, the resist is usually stripped. Thisis often necessary as the resist may be incompatible with further micromachining steps. Italso makes the topography more dramatic, which may hamper further lithography steps.

Alignment

In order to make useful devices the patterns for different lithography steps that belong toa single structure must be aligned to one another. The first pattern transferred to a waferusually includes a set of alignment marks, which are high precision features that are usedas the reference when positioning subsequent patterns, to the first pattern (as shown infigure 4). Often alignment marks are included in other patterns, as the original alignment

marks may be obliterated as processing progresses. It is important for each alignmentmark on the wafer to be labeled so it may be identified, and for each pattern to specify thealignment mark (and the location thereof) to which it should be aligned. By providing thelocation of the alignment mark it is easy for the operator to locate the correct feature in ashort time. Each pattern layer should have an alignment feature so that it may beregistered to the rest of the layers.

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Figure 4:Use of alignment marks to register subsequent layers

Depending on the lithography equipment used, the feature on the mask used for

registration of the mask may be transferred to the wafer (as shown in figure 5). In thiscase, it may be important to locate the alignment marks such that they don't effectsubsequent wafer processing or device performance. For example, the alignment markshown in figure 6 will cease to exist after a through the wafer DRIE etch. Pattern transferof the mask alignment features to the wafer may obliterate the alignment features on thewafer. In this case the alignment marks should be designed to minimize this effect, oralternately there should be multiple copies of the alignment marks on the wafer, so therewill be alignment marks remaining for other masks to be registered to.

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Figure 5:Transfer of mask registration feature to substrate during lithography (contact

aligner)

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Figure 6:Poor alignment mark design for a DRIE through the wafer etch (cross hair is

released and lost).Alignment marks may not necessarily be arbitrarily located on the wafer, as theequipment used to perform alignment may have limited travel and therefore only be ableto align to features located within a certain region on the wafer (as shown in figure 7).

The region location geometry and size may also vary with the type of alignment, so thelithographic equipment and type of alignment to be used should be considered beforelocating alignment marks. Typically two alignment marks are used to align the mask andwafer, one alignment mark is sufficient to align the mask and wafer in x and y, but itrequires two marks (preferably spaced far apart) to correct for fine offset in rotation.

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Figure 7:Restriction of location of alignment marks based on equipment used.

As there is no pattern on the wafer for the first pattern to align to, the first pattern istypically aligned to the primary wafer flat (as shown in figure 8). Depending on thelithography equipment used, this may be done automatically, or by manual alignment toan explicit wafer registration feature on the mask.

Exposure

The exposure parameters required in order to achieve accurate pattern transfer from themask to the photosensitive layer depend primarily on the wavelength of the radiationsource and the dose required to achieve the desired properties change of the photoresist.Different photoresists exhibit different sensitivities to different wavelengths. The doserequired per unit volume of photoresist for good pattern transfer is somewhat constant;

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however, the physics of the exposure process may affect the dose actually received. Forexample a highly reflective layer under the photoresist may result in the materialexperiencing a higher dose than if the underlying layer is absorptive, as the photoresist isexposed both by the incident radiation as well as the reflected radiation. The dose willalso vary with resist thickness.

Figure 8:Mask alignment to the wafer flat.There are also higher order effects, such as interference patterns in thick resist films onreflective substrates, which may affect the pattern transfer quality and sidewallproperties.At the edges of pattern light is scattered and diffracted, so if an image is overexposed, thedose received by photoresist at the edge that shouldn't be exposed may becomesignificant. If we are using positive photoresist, this will result in the photoresist imagebeing eroded along the edges, resulting in a decrease in feature size and a loss of

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sharpness or corners (as shown in figure 9). If we are using a negative resist, the

Figure 9:Over and under-exposure of positive resist.

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photoresist image is dilated, causing the features to be larger than desired, againaccompanied by a loss of sharpness of corners. If an image is severely underexposed, thepattern may not be transferred at all, and in less sever cases the results will be similar tothose for overexposure with the results reversed for the different polarities of resist. If thesurface being exposed is not flat, the high-resolution image of the mask on the wafer may

be distorted by the loss of focus of the image across the varying topography. This is oneof the limiting factors of MEMS lithography when high aspect ratio features are present.High aspect ratio features also experience problems with obtaining even resist thicknesscoating, which further degrades pattern transfer and complicates the associatedprocessing.

The Lithography Module

Typically lithography is performed as part of a well-characterized module, whichincludes the wafer surface preparation, photoresist deposition, alignment of the mask andwafer, exposure, develop and appropriate resist conditioning. The lithography processsteps need to be characterized as a sequence in order to ensure that the remaining resist atthe end of the modules is an optimal image of the mask, and has the desired sidewallprofile.The standard steps found in a lithography module are (in sequence): dehydration bake,HMDS prime, resist spin/spray, soft bake, alignment, exposure, post exposure bake,develop hard bake and descum. Not all lithography modules will contain all the processsteps. A brief explanation of the process steps is included for completeness.

Dehydration bake - dehydrate the wafer to aid resist adhesion. HMDS prime - coating of wafer surface with adhesion promoter. Not necessary

for all surfaces.

Resist spin/spray - coating of the wafer with resist either by spinning or spraying.Typically desire a uniform coat.

Soft bake - drive off some of the solvent in the resist, may result in a significantloss of mass of resist (and thickness). Makes resist more viscous.

Alignment - align pattern on mask to features on wafers. Exposure - projection of mask image on resist to cause selective chemical

property change.

Post exposure bake - baking of resist to drive off further solvent content. Makesresist more resistant to etchants (other than developer).

Develop - selective removal of resist after exposure (exposed resist if resist ispositive, unexposed resist if resist is positive). Usually a wet process (althoughdry processes exist).

Hard bake - drive off most of the remaining solvent from the resist. Descum - removal of thin layer of resist scum that may occlude open regions inpattern, helps to open up corners.

We make a few assumptions about photolithography. Firstly, we assume that a wellcharacterized module exists that: prepares the wafer surface, deposits the requisite resistthickness, aligns the mask perfectly, exposes the wafer with the optimal dosage, developsthe resist under the optimal conditions, and bakes the resist for the appropriate times atthe appropriate locations in the sequence. Unfortunately, even if the module is executedperfectly, the properties of lithography are very feature and topography dependent. It is

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therefore necessary for the designer to be aware of certain limitations of lithography, aswell as the information they should provide to the technician performing the lithography.The designer influences the lithographic process through their selections of materials,topography and geometry. The material(s) upon which the resist is to be deposited isimportant, as it affects the resist adhesion. The reflectivity and roughness of the layer

beneath the photoresist determines the amount of reflected and dispersed light presentduring exposure. It is difficult to obtain a nice uniform resist coat across a surface withhigh topography, which complicates exposure and development as the resist has differentthickness in different locations. If the surface of the wafer has many different heightfeatures, the limited depth of focus of most lithographic exposure tools will become anissue (as shown in figure 10).

Figure 10:Lithography tool depth of focus and surface topology.The designer should keep all these limitations in mind, and design accordingly. Forexample, it is judicious, when possible, to perform very high aspect patterning step(lithography and subsequent etch/deposition) last, as the topography generated oftenhampers any further lithography steps. It is also necessary for the designer to make itclear which focal plane is most important to them (keeping in mind that features furtheraway in Z from the focal plane will experience the worst focus). The resolution teststructures should be located at this level (as they will be used by the fab to check the

quality of a photo step).

Wet etching

This is the simplest etching technology. All it requires is a container with a liquidsolution that will dissolve the material in question. Unfortunately, there are complicationssince usually a mask is desired to selectively etch the material. One must find a mask thatwill not dissolve or at least etches much slower than the material to be patterned.

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Secondly, some single crystal materials, such as silicon, exhibit anisotropic etching incertain chemicals. Anisotropic etching in contrast to isotropic etching means differentetch rates in different directions in the material. The classic example of this is the crystal plane sidewalls that appear when etching a hole in a silicon wafer in achemical such as potassium hydroxide (KOH). The result is a pyramid shaped hole

instead of a hole with rounded sidewalls with a isotropic etchant. The principle ofanisotropic and isotropic wet etching is illustrated in the figure below.

Figure 1:Difference between anisotropic and isotropic wet etching.

When do I want to use wet etching?

This is a simple technology, which will give good results if you can find the combinationof etchant and mask material to suit your application. Wet etching works very well foretching thin films on substrates, and can also be used to etch the substrate itself. Theproblem with substrate etching is that isotropic processes will cause undercutting of themask layer by the same distance as the etch depth. Anisotropic processes allow theetching to stop on certain crystal planes in the substrate, but still results in a loss of space,since these planes cannot be vertical to the surface when etching holes or cavities. If thisis a limitation for you, you should consider dry etching of the substrate instead. However,keep in mind that the cost per wafer will be 1-2 orders of magnitude higher to performthe dry etchingIf you are making very small features in thin films (comparable to the film thickness),you may also encounter problems with isotropic wet etching, since the undercutting willbe at least equal to the film thickness. With dry etching it is possible etch almost straightdown without undercutting, which provides much higher resolution.

Dry etching

The dry etching technology can split in three separate classes called reactive ion etching(RIE), sputter etching, and vapor phase etching.In RIE, the substrate is placed inside a reactor in which several gases are introduced. Aplasma is struck in the gas mixture using an RF power source, breaking the gas moleculesinto ions. The ions are accelerated towards, and reacts at, the surface of the material beingetched, forming another gaseous material. This is known as the chemical part of reactive

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ion etching. There is also a physical part which is similar in nature to the sputteringdeposition process. If the ions have high enough energy, they can knock atoms out of thematerial to be etched without a chemical reaction. It is a very complex task to developdry etch processes that balance chemical and physical etching, since there are manyparameters to adjust. By changing the balance it is possible to influence the anisotropy of

the etching, since the chemical part is isotropic and the physical part highly anisotropicthe combination can form sidewalls that have shapes from rounded to vertical. Aschematic of a typical reactive ion etching system is shown in the figure below.A special subclass of RIE which continues to grow rapidly in popularity is deep RIE(DRIE). In this process, etch depths of hundreds of microns can be achieved with almostvertical sidewalls. The primary technology is based on the so-called "Bosch process",named after the German company Robert Bosch which filed the original patent, wheretwo different gas compositions are alternated in the reactor. The first gas compositioncreates a polymer on the surface of the substrate, and the second gas composition etchesthe substrate. The polymer is immediately sputtered away by the physical part of theetching, but only on the horizontal surfaces and not the sidewalls. Since the polymer only

dissolves very slowly in the chemical part of the etching, it builds up on the sidewalls andprotects them from etching. As a result, etching aspect ratios of 50 to 1 can be achieved.The process can easily be used to etch completely through a silicon substrate, and etchrates are 3-4 times higher than wet etching.Sputter etching is essentially RIE without reactive ions. The systems used are verysimilar in principle to sputtering deposition systems. The big difference is that substrate isnow subjected to the ion bombardment instead of the material target used in sputterdeposition.Vapor phase etching is another dry etching method, which can be done with simplerequipment than what RIE requires. In this process the wafer to be etched is placed insidea chamber, in which one or more gases are introduced. The material to be etched isdissolved at the surface in a chemical reaction with the gas molecules. The two mostcommon vapor phase etching technologies are silicon dioxide etching using hydrogenfluoride (HF) and silicon etching using xenon diflouride (XeF2), both of which areisotropic in nature. Usually, care must be taken in the design of a vapor phase process tonot have bi-products form in the chemical reaction that condense on the surface andinterfere with the etching process.

When do I want to use dry etching?

The first thing you should note about this technology is that it is expensive to runcompared to wet etching. If you are concerned with feature resolution in thin filmstructures or you need vertical sidewalls for deep etchings in the substrate, you have toconsider dry etching. If you are concerned about the price of your process and device,

you may want to minimize the use of dry etching. The IC industry has long since adopteddry etching to achieve small features, but in many cases feature size is not as critical inMEMS. Dry etching is an enabling technology, which comes at a sometimes high cost.

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Figure 2:Typical parallel-plate reactive ion etching system.in MEMS. Dry etching is an enabling technology, which comes at asometimes high cost.

There are numerous possible applications for MEMS and Nanotechnology. As a

breakthrough technology, allowing unparalleled synergy between previously unrelatedfields such as biology and microelectronics, many new MEMS and Nanotechnologyapplications will emerge, expanding beyond that which is currently identified or known.Here are a few applications of current interest:

Biotechnology

MEMS and Nanotechnology is enabling new discoveries in science and engineering suchas the Polymerase (polimeraza) Chain Reaction (PCR) microsystems for DNA

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amplification and identification, micromachined Scanning Tunneling Microscopes(STMs), biochips for detection of hazardous chemical and biological agents, andmicrosystems for high-throughput drug screening and selection.

Communications

High frequency circuits will benefit considerably from the advent of the RF-MEMStechnology. Electrical components such as inductors and tunable capacitors can beimproved significantly compared to their integrated counterparts if they are made usingMEMS and Nanotechnology. With the integration of such components, the performanceof communication circuits will improve, while the total circuit area, power consumptionand cost will be reduced. In addition, the mechanical switch, as developed by severalresearch groups, is a key component with huge potential in various microwave circuits.The demonstrated samples of mechanical switches have quality factors much higher thananything previously available.Reliability and packaging of RF-MEMS components seem to be the two critical issuesthat need to be solved before they receive wider acceptance by the market.

AccelerometersMEMS accelerometers are quickly replacing conventional accelerometers for crash air-bag deployment systems in automobiles. The conventional approach uses several bulkyaccelerometers made of discrete components mounted in the front of the car with separateelectronics near the air-bag; this approach costs over $50 per automobile. MEMS andNanotechnology has made it possible to integrate the accelerometer and electronics ontoa single silicon chip at a cost between $5 to $10. These MEMS accelerometers are muchsmaller, more functional, lighter, more reliable, and are produced for a fraction of the costof the conventional macroscale accelerometer elements.

This is only a very brief overview of the MEMS and Nanotechnology field. MEMS and

Nanotechnology are still the subject of broad and diverse research efforts, and the field isconstantly changing.

The image is a colorized Scanning Electron Micrograph (SEM) of a high-aspect ratioMEMS device fabricated out of single-crystal silicon by the MEMS and NanotechnologyExchange fabrication network. The device itself is made from a Silicon-On-Insulator(SOI) wafer where a relatively thick single-crystal silicon device layer (shown in yellowand blue in the image) has been etched into a complex micromechanical element that canmove under force. The underlying area, shown in red in the image, is the SOI handlewafer which also has been etched to form a circular hole completely through thesubstrate. This image demonstrates the complexity of micromechanical devices that canbe realized using the MEMS and Nanotechnology Exchange.

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This whimsical image is a colorized Scanning Electron Micrograph (SEM) of mechanical

gear which is smaller than a human hair. The gear was made polycrystalline silicon usingsurface micromachining techniques and is no longer attached to the substrate. However,the gear did eventually lodge onto an electrical bond pad (shown in green) due to surfaceforces. This image illustrates the extraordinary capability of MEMS technology to enablethe realization of extremely small mechanical elements. This device was made throughthe MEMS and Nanotechnology Exchange fabrication network.

The image is a colorized Scanning Electron Micrograph (SEM) of a salient-poleelectrostatically actuated micromotor made from polycrystalline silicon using surfacemicromachining techniques. The central rotating element of the motor (e.g., the rotor) isthe circular structure in the middle (shown in blue) held to the substrate by the centralbearing (which is shown in red). Properly phased voltage potentials are placed on themotor stators (typically 120 degrees advanced in phase sequentially around the stators),which are equally spaced around the perimeter of the rotor (also shown in blue) and theseapplied voltages on the stators cause the central rotor to turn around the bearing at

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extremely high angular velocities. This device was made through the MEMS andNanotechnology Exchange fabrication network.

"The image is a colorized Scanning Electron Micrograph (SEM) of microstructure madeusing extremely short wavelength exposure techniques of a thick radiation sensitivepolymer layer which was spun onto the substrate and developed after exposure to revealan extraordinarily high aspect ratio microstructure. The central post (shown in orange) ishundreds of microns tall and only a few microns in diameter. The surrounding angularshaped structures are also a few microns wide, separated from one another by a fewmicrons, and are also hundreds of microns tall. This structure was made through theMEMS and Nanotechnology Exchange fabrication network.

Deep reactive ion etching is a process used to etch substrates to form deep cavitieswith relatively high aspect ratio (10-20). Most Deep RIE systems use the so-called"Bosch process" in which a fluor polymer is used to passivate the etching of thesidewalls.

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LIGA stands for X-ray LIthography, Electroforming (German: Galvanoformung), andmolding (German: Abformung). This technology allows us to define high aspect ratiostructures in nickel. The process consists of exposing a sheet of PMMA bonded to awafer using X-ray lithography. The PMMA is then developed and the exposed material isremoved. Nickel is then electroplated up in the open areas of the PMMA. The nickelover-plate is removed by polishing, leaving high aspect ratio nickel parts. The PMMA isremoved, and the nickel parts may remain anchored to the substrate or be released.

We offer a range of options for mask design and fabrication. Our engineers can make thelayout design for you or use your layout files. Our mask fabrication capabilities rangefrom pattern generation, to E-beam, to X-ray.

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