Memristor Memory With Crossbar Architecture

© Copyright 2013 Hewlett-Packard Development Company, L.P. The information contained herein is subject to change without notice.

Memristor Memory With Crossbar Architecture Naveen MurlimanoharHP LabsJune 14th 2014

© Copyright 2013 Hewlett-Packard Development Company, L.P. The information contained herein is subject to change without notice.2

Why New Technology?

• Explosion of data – faster than Moore’s law− Memory is the focal point

− Strong demand for cheap memory

• In memory computation is gaining popularity− Volt DB, SAP HANA, Memcached

• DRAM cost/bit is high and its scaling is slowing− DRAM is also volatile

• Other technologies such as PCM and STT-RAM are facing challenges


Technology Trend – Memory Scaling Problem

• DRAM capacity increase 4X / 3years for decades, but now is scaling much slower

Source: Horst Simon


Memory Capacity

• Requirement 1B/FLOPRef: DARPA’sexascale report

By 2020 we could be well below <0.1B/FLOP!More number crunching with less data


Outline

• Need for a new technology• Why Memristor is different?• Crossbar Architecture• Tradeoffs in Crossbar Architecture• Opportunities


The memristor: 4th fundamental two terminal circuit element

Predicted 1971Leon ChuaU.C. Berkeley

Reduced to practice 2008R. Stanley Williams

HP Laboratories

MEMRISTORdφ = M dq

1971Chua

Ohm1827

1831Faraday

Von Kleist1745RESISTOR

dv = R diCAPACITORdq = C dv

INDUCTORdφ = L di

i

v

q

φ


Memristor - First Glance

HP Confidential

• The memristor is built on a Metal-Insulator-Metal (MIM) structure.

• Memristor can be switched between High Resistance State (HRS) and Low Resistance State (LRS) by applying an external voltage across the cell.

• Current, voltage relationship is non-linear


Memristor Cell

HP Confidential

Memristor switching device with low non-linearity

Selector with high non-linearity

Combination of a selector in series with memristor device

Ideally we want the memristor IV curve to be highly non-linear

Memristor

Selector

Memristor Cell

© Copyright 2013 Hewlett-Packard Development Company, L.P. The information contained herein is subject to change without notice.9HP Confidential

Accessing Traditional Memory

• 2D grid of cells with a dedicated access switch in each cell

• Easier to read/write to a cell

• Low density but high read margin


Traditional Memory vs. Memristor Crossbar

Cells being read or written

Row select signal to read or write a row


Traditional Memory vs. Memristor Crossbar

Access transistor isolates

unnecessary signal- But it increases

cost

Cells being read or written


Crossbar Memristor array

HP Confidential

• No access transistor a dense crossbar array with a cell size of 4F2

• You can lay transistors and circuits below the array• Maximum use of silicon area

Selected Cell

Half Selected Cell


Outline


HP Confidential

Memristor Operation

Row select signal to read or write a row

Vdd/2 Vdd/2 Vdd/2 Vdd/2 Vdd/2 Vdd/2 Vdd/2

Vdd

Vdd/2

Vdd/2

Vdd/2

Vdd/2

0

HP Confidential

Memristor Operation

Half Selected Cells Leak Current


Vdd

Vdd/2

Vdd/2

Vdd/2

Vdd/2

0

Non-linearity (Kr) helps reduce leakage currentKr = ILSR(@VSET) / ILSR(@VSET/2)

HP Confidential

Memristor OperationUnselected cells shown in light blue will also get impacted


Vdd

Vdd/2

Vdd/2

Vdd/2

Vdd/2

0


HP Confidential

Complex Tradeoffs in Crossbar

Enough voltage drop (for switching)

Avoid write disturbance

Enough ∆I (noise margin)

Write

Read V/2?V/3?Floating?

?

I?V

Array sizeselected cell

>1 bit?

HP Confidential

Complex Tradeoffs in Designing Memristor Crossbar

Enough voltage drop (for switching)

Avoid write disturbance

Enough ∆I (noise margin)

V/2?V/3?Floating?

?

I?V

selected cell

• Design decisions are not obvious

• What is the optimal array

dimensions?

• What is the right driving voltage?

• What is the biasing voltage?

• Tradeoff in writing/reading single

bit vs. multiple bits per arrayDepending upon the delay/energy/area constraints, we can tune the array accordingly

Outline• Need for a new technology• Why Memristor is different?• Crossbar Architecture• Tradeoffs in Crossbar Architecture• Opportunities


Operating Voltage vs. Array Size

Big array requires large voltage

HP Confidential


Choice of Material


HP Confidential

• Non-linearity increases the density

Max

imum

Num

ber

of W

ordl

ines

&

Bitl

ines


Read Operation

• The read voltage/current is lower than that of the write operation

• The read reliability is determined by the voltage swing for reading HRS and LRS cells

• However, sneak path and data pattern can reduce the voltage swing


Operating Speed vs. Density vs. Bandwidth

Larger array More sneak paths Lower read margin

Challenging with process variation

HP Confidential


Two-Step Read Operation

• Two-step sensing: senses the background current first, then the overall current is sensed

• Increased sensing overhead low bandwidth or poor density

HP Confidential

One-step Reading Two-step Reading


Outline



More Challenges

• Reliability of crossbar • Process variation • Fault tolerance• Data encoding

HP Confidential

Effect of Data on Sneak Current

Half Selected Cells Leak Current


Vdd

Vdd/2

0

1 1Cells in low resistance state More sneak current

0 0 0 0


Impact of data patternWrite the furthest cell in a 8x8 cross-point array# of “1”s (LRS) in the selected wordline mattersgap between worst-case and best case?

2 3 4 5 6 7 8610

620

630

640

650

660

worst-case best-case# of "1"s in selected wordlines

Votla

ge d

rop

(mV)

2 3 4 5 6 7 81E-08

1E-07

1E-06

1E-05

worst-case best-case# of "1"s in selected wordlines

switc

hing

tim

e (s

)HP Confidential


Impact of data patternWrite the furthest cell in a 8x8 cross-point arraypositions of “1”s (LRS) in the selected wordline also mattermoving “1”s closer to the write driver helpshints: mirror coding

0000

0011

0000

0101

0000

1001

0001

0001

0010

0001

0100

0001

1000

0001

648

652

656

660

Data in selected wordline

volta

ge d

rop

(mV)

0000

0011

0000

0101

0000

1001

0001

0001

0010

0001

0100

0001

1000

0001

4.0E-08

6.0E-08

8.0E-08

1.0E-07

1.2E-07

Data in selected wordline

switc

hing

tim

e (s

)HP Confidential


Summary

HP Confidential

• Opportunity to change the memory technology do not come along everyday• More aggressive micro architecture that can provide better density than existing

technologies is critical • Memristor characteristics are well suited for future memory systems• Crossbar architecture is an interesting way to leverage resistive

memories such as Memristor• Its high density along with architectural enhancements can make it a compelling

option for future systems


Resources – Learn more…Memristor . . . More Info . . .

Memristor Basic Info:The Memristor – Incredible: https://www.youtube.com/watch?v=wZAHG3COYYAWikipedia on Memristor: http://en.wikipedia.org/wiki/Memristor

Technical papers:• Niu et al., Design of Cross-point Metal-oxide ReRAM Emphasizing Reliability and Cost.", (ICCAD),

2013.• Xu et al., Understanding the Tradeoffs in MLC ReRAM Memory Design, DAC, 2013.• Niu et al., Design Tradeoffs for High Density Cross-Point Resistive Memory.", ISLPED, 2012.

https://www.google.com/url?q=http://www.dailytech.com/HP+to+Deploy+Memristor+Powered+SSD+Replacement+Within+18+Months/article22963.htm&sa=U&ei=hS0eU_qnDqO42gXblYGABA&ved=0CD4Q9QEwBw&usg=AFQjCNEg8_nDGtEhYndhnd6xgGl-hrX_Ag

https://www.google.com/url?q=http://en.wikipedia.org/wiki/Memristor&sa=U&ei=hS0eU_qnDqO42gXblYGABA&ved=0CDgQ9QEwBA&usg=AFQjCNGyGxBxiR2DljFpbd63LJJltCYhPA


The basic model of crossbar array

• Vw/ V’w : Voltage at the edge of wordline• VB / V’B : Voltage at the edge of bitline• Rl : Interconnection wire resistance• Ri,j : Resistance of the memristor at the intersection of the ith wordline

and the jth bitline• Vi,j / V’i,j : Top/bottom voltage of the memristor with Ri,j• Array simulation is done through HSPICE

Memristor

Selector

Voltage controlled current source

Current controlled voltage source

Memristor Memory With Crossbar Architecture

Documents

Transcript of Memristor Memory With Crossbar Architecture