Memory Unit Design 01

7/30/2019 Memory Unit Design 01

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Abdu Rahiman VLecturer in ECE

Govt. College of Engineering,

Kannur, Kerala, India

Abdu Rahiman V. Govt. College of Engg. Kannur.


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Memory Store instruction and data

Memory requirements

Should be as fast as processor Large size

Low cost

Essential in any processing unit



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Processor and memory interface


Memory

Upto2k addressable

locations

Word length n bits

MAR

MDR

Control bus

n bit Data bus

kBit address bus


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Memory Units used with memory

Byte, KB, MB, GB, TB

Memory access time- time between giving read signal andreceiving MFC

Memory cycle time minimum time required between twosuccessive read signals

Random access memory any location can be read or written ina fixed time

Serial access memory memory access time depends on the

position of data Types of memory

Main memory or primary memory Secondary memory Cache memory



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Organization of memory cells in a

memory unit - Example


Sense/Write

Sense/Write

Sense/Write

b7 b7 b1 b1 b0 b0

. . .

. . .

. . .

FF

W0

W1

W15

A0

A1

A2

A3Addressdecoder

RD/WR

RD/WR RD/WR

b0b7 b1


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Bipolar Memory Cell T1 OFF & T2 ON Logic 1 T1 ON & T2 OFF Logic 0 Read operation

Make word line zero volt A voltage is applied on bit

lines Diode near the transistor in

ON state will draw a current

Write Operation

Set voltages on the bits linesand make word line low Respective transistor will

turn ON and the other willbecome OFF


Vcc

Bit Line Bit Line

Word

Line

T1 T2

D1

R1

D2

R2


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CMOS Memory Cell T1 OFF & T2 ON Logic 1

T1 ON & T2 OFF Logic 0

Read operation

Make word line high

T5 & T6 ON, voltages atthe points are availableon bit lines

Write Operation Set voltages on the bit

lines and make word linehigh


Vcc

Ground

Bit Line Bit Line

Word

Line

T1 T2

T4

T6T5

T3


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Dynamic Memory Minimum number of

transistors required

High density memoryfabrication is possible

Volatile

Refresh circuitry is

required Low cost per bit


Bit Line

Word

Line


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Addressing multiple module

memory system


ABR DBR ABR DBR ABR DBR

Module Address in Module

. . . . . .

DataBus

ABR- Address Buffer RegisterDBR- Data Buffer Register

Consecutive memory locations

are stored in same module


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Addressing multiple module

memory system


ABR DBR ABR DBR ABR DBR

ModuleAddress in Module

. . . . . .

DataBus

ABR- Address Buffer RegisterDBR- Data Buffer Register

Consecutive memory locations are stored in same consecutivemodule

Memory interleaving


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Memory interleaving

It is possible to access multiple words in one cycle

Reduces the total time to read the required data



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Cache Memory


ProcessorCache

memoryMain

MemorySecondaryMemory

Small sizeHigh speedHigh cost

Medium sizeMedium speedMedium cost

Large sizelow speedLow cost


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Cache Memory Locality of reference

Spatial:-the instructions stored in nearby locations arelikely to be executed repeatedly

Temporal:- the instructions executed recently are

likely to be executed repeatedly



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Cache Memory High speed memory to store small portion of main

memory

Cache and main memories are divide in to smallblocks

Block containing the data referenced is brought in tothe cache memory



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Cache memory

Main memory

Block 0

Block 1

.

.

Block m-1Block m

Block m+1

.

.

Block 2m-1

Block 2m

Block 2m+1

.

.

Block pm-1

Block 0

Block 1

.

.

Block m-1


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Cache MemoryAny modification made in cache has to be made in

main memory also

Write through : write to main memory along with thewrite to cache

Write back : write to cache, if it is modified, beforediscarding the cache content

Dirty/modified bit: set to 1 if the content of cache ismodified

Valid bit:- to indicate cache contain valid data



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Cache memory mapping functions Direct Mapping

Searching is easy

Tag field used to identifythe block


Block 0

Block 1

.

.

Block m-1

Block m

Block m+1

.

.

Block 2m-1

Block 2m

Block 2m+1

.

.

Block pm-1

Block 0

Block 1

.

.

Block m-1

TagCacheblock

Word Address

Main Memory Address


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Direct mapping - Example Block size 16 bytes

Total main memory 16

KB

Number of blocks in

main memory 1024

Cache size 1 KB, 64

blocks


Block 0

Block 1

.

.

Block 63

Block 64

Block 65

.

.

Block 127

Block 128

Block 129

.

.

Block 1023

Block 0

Block 1

.

.

Block 63

Tag4 bits

Cacheblock6 bits

Word Address4 bits

Main Memory Address


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Associative mappingAny block can be loaded

to any available block incache


Block 0

Block 1

.

.

Block m-1

Block m

Block m+1

.

.

Block 2m-1

Block 2m

Block 2m+1

.

.

Block pm-1

Block 0

Block 1

.

.

Block m-1

Tag Word Address

Main Memory Address


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Associative mapping - Example Block size 16 bytes


KB

Number of blocks in

main memory 1024

Cache size 1 KB, 64

blocks


Block 0

Block 1

.

.

Block 63

Block 64

Block 65

.

.

Block 127

Block 128

Block 129

.

.

Block 1023

Block 0

Block 1

.

.

Block 63

Tag10 bits

Word Address4 bits

Main Memory Address


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Set Associative mapping Blocks can be moved

to free blocks in theset


Tag Set Number Word Address

Main Memory Address

Block 0

Block 1

.

.

Block m-1

Block m

Block m+1

.

.

Block 2m-1

Block 2m

Block 2m+1

.

.

Block pm-1

Block 0

Block 1

.

.

Block m-2

Block m-1

Block 2

Block 3

Set 1

Set 2

Set p


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Set Associative mapping - Example

Block size 16 bytes


KB

Number of blocks in

main memory 1024

Cache size 1 KB, 64

blocks and 32 sets Two way set associative

mapping


Tag5 bits

Set No.5 bits

Word Address4 bits

Main Memory Address

Block 0

Block 1

.

.

Block 63

Block 64

Block 65

.

.

Block 127

Block 128

Block 129

.

.

Block 1023

Block 0

Block 1

.

.

Block m-2

Block 63

Block 2

Block 3

Set 0

Set 2

Set 31


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Cache memory Cache hit - accessed data is present in cache

Cache miss accessed data is not present in cache

Hit rate Number of hits / total access attemps In case of cache miss, new data block has to be moved

to cache memory

Miss penaltyThe delay to fetch the block after cache

miss



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Cache Replacement Schemes Least Recently Used :- Remove the LRU block and

replace with the new one

Oldest block:- Remove the oldest block and copy thenew one

Performance of this method is very poor

Random replacement:- Randomly select the block to

be replace. This method has relatively good performance



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Thank You

Abdu Rahiman V Govt College of Engg Kannur

Memory Unit Design 01

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