***.param th=0.9.param thh=0.7.param tl=0.1.param tll=0.3.param tm=0.5*************** 3*tp == Read Write (Addr11- RD0 WR1)** 4*tp == Only read (Addr11 - RD1)** 6*tp == only write ( Addr11- WR0)************************* Pulse latch related margins *************************************1/ ck should be high enough to latch csn value.meas tran f_a_setup_2_aclk_1_fall_rw+ trig V(xsram.xi0.xictrl.xiclkgen.aclk_1) val = 'tl*supply_mem' vlg='0.5*supply_mem' fall=1 td='3*tp'+ targ V(xsram.xi0.xictrl.xiclkgen.a_setup) val = 'th*supply' vlg='0.5*supply' fall=1 td='3*tp'.meas tran f_a_setup_2_aclk_rise_rw+ trig V(xsram.xi0.xictrl.xiclkgen.aclk) val = 'th*supply_mem' vhg='0.5*supply_mem' rise=1 td='3*tp'+ targ V(xsram.xi0.xictrl.xiclkgen.a_setup) val = 'th*supply' vlg='0.5*supply' fall=1 td='3*tp'.meas tran f_a_setup_2_aclk_1_fall_r+ trig V(xsram.xi0.xictrl.xiclkgen.aclk_1) val = 'tl*supply_mem' vlg='0.5*supply_mem' fall=1 td='4*tp'+ targ V(xsram.xi0.xictrl.xiclkgen.a_setup) val = 'th*supply' vlg='0.5*supply' fall=1 td='4*tp'.meas tran f_a_setup_2_aclk_rise_r+ trig V(xsram.xi0.xictrl.xiclkgen.aclk) val = 'th*supply_mem' vhg='0.5*supply_mem' rise=1 td='4*tp'+ targ V(xsram.xi0.xictrl.xiclkgen.a_setup) val = 'th*supply' vlg='0.5*supply' fall=1 td='4*tp'.meas tran f_b_setup_2_bclk_1_rise_rw+ trig V(xsram.xi0.xictrl.xiclkgen.bclk_1) val = 'tl*supply_mem' vlg='0.5*supply_mem' fall=1 td='3*tp'+ targ V(xsram.xi0.xictrl.xiclkgen.b_setup) val = 'th*supply' vlg='0.5*supply' fall=1 td='3*tp'.meas tran f_b_setup_2_bclk_rise_rw+ trig V(xsram.xi0.xictrl.xiclkgen.bclk) val = 'th*supply_mem' vhg='0.5*supply_mem' rise=1 td='3*tp'+ targ V(xsram.xi0.xictrl.xiclkgen.b_setup) val = 'th*supply' vlg='0.5*supply' fall=1 td='3*tp'.meas tran f_b_setup_2_bclk_1_fall_w+ trig V(xsram.xi0.xictrl.xiclkgen.bclk_1) val = 'tl*supply_mem' vlg='0.5*supply_mem' fall=1 td='6*tp'+ targ V(xsram.xi0.xictrl.xiclkgen.b_setup) val = 'th*supply' vlg='0.5*supply' fall=1 td='6*tp'.meas tran f_b_setup_2_bclk_rise_w+ trig V(xsram.xi0.xictrl.xiclkgen.bclk) val = 'th*supply_mem' vhg='0.5*supply_mem' rise=1 td='6*tp'+ targ V(xsram.xi0.xictrl.xiclkgen.b_setup) val = 'th*supply' vlg='0.5*supply' fall=1 td='6*tp*2/ reset pw high enough to latch -> readyb_rd, readbyb_wr, readyb_wrscan.meas tran f_readyb_rd_rise_2_aclk_1_rise_rw+ trig V(xsram.xi0.xictrl.xiclkgen.aclk_1) val = 'th*supply_mem' rise=1 td='3*tp'+ targ V(xsram.xi0.xictrl.xiclkgen.readyb_rd) val='tl*supply_mem' rise=1 td='3*tp'.meas tran f_readyb_rd_rise_2_aclk_fall_rw+ trig V(xsram.xi0.xictrl.xiclkgen.aclk) val = 'tl*supply_mem' fall=1 td='3*tp'+ targ V(xsram.xi0.xictrl.xiclkgen.readyb_rd) val='tl*supply_mem' rise=1 td='3*tp'.meas tran f_readyb_rd_rise_2_aclk_1_rise_r+ trig V(xsram.xi0.xictrl.xiclkgen.aclk_1) val = 'th*supply_mem' rise=1 td='4*tp'+ targ V(xsram.xi0.xictrl.xiclkgen.readyb_rd) val='tl*supply_mem' rise=1 td='4*tp'.meas tran f_readyb_rd_rise_2_aclk_fall_r+ trig V(xsram.xi0.xictrl.xiclkgen.aclk) val = 'tl*supply_mem' fall=1 td='4*tp'+ targ V(xsram.xi0.xictrl.xiclkgen.readyb_rd) val='tl*supply_mem' rise=1 td='4*tp'.meas tran f_readyb_wr_rise_2_bclk_1_rise_rw+ trig V(xsram.xi0.xictrl.xiclkgen.bclk_1) val = 'th*supply_mem' rise=1 td='3*tp'+ targ V(xsram.xi0.xictrl.xiclkgen.readyb_wr) val='tl*supply_mem' rise=1 td='3*tp'.meas tran f_readyb_wr_rise_2_bclk_fall_rw+ trig V(xsram.xi0.xictrl.xiclkgen.bclk) val = 'tl*supply_mem' fall=1 td='3*tp'+ targ V(xsram.xi0.xictrl.xiclkgen.readyb_wr) val='tl*supply_mem' rise=1 td='3*tp'.meas tran f_readyb_wr_rise_2_bclk_1_rise_w+ trig V(xsram.xi0.xictrl.xiclkgen.bclk_1) val = 'th*supply_mem' rise=1 td='6*tp'+ targ V(xsram.xi0.xictrl.xiclkgen.readyb_wr) val='tl*supply_mem' rise=1 td='6*tp'.meas tran f_readyb_wr_rise_2_bclk_fall_w+ trig V(xsram.xi0.xictrl.xiclkgen.bclk) val = 'tl*supply_mem' fall=1 td='6*tp'+ targ V(xsram.xi0.xictrl.xiclkgen.readyb_wr) val='tl*supply_mem' rise=1 td='6*tp'.meas tran f_readyb_wrscan_rise_2_bclk_1_rise_scan+ trig V(xsram.xi0.xictrl.xiclkgen.bclk_1) val = 'th*supply_mem' rise=1 td='14*tp'+ targ V(xsram.xi0.xictrl.xiclkgen.readyb_wrscanb) val='tl*supply_mem' rise=1 td='14*tp'.meas tran f_readyb_wrscan_rise_2_bclk_fall_scan+ trig V(xsram.xi0.xictrl.xiclkgen.bclk) val = 'tl*supply_mem' fall=1 td='14*tp'+ targ V(xsram.xi0.xictrl.xiclkgen.readyb_wrscanb) val='tl*supply_mem' rise=1 td='14*tp'*3/ No glitch at Falling edge of ck.meas tran f_a_setup_fall_2_vssg_rise_rw+ trig V(xsram.xi0.xictrl.xiclkgen.vssg) val = 'th*supply' vhg='0.5*supply' rise=1 td='3*tp'+ targ V(xsram.xi0.xictrl.xiclkgen.a_setup) val = 'tl*supply' vhg='0.5*supply' rise=1 td='3*tp'.meas tran f_a_setup_fall_2_vssg_rise_r+ trig V(xsram.xi0.xictrl.xiclkgen.vssg) val = 'th*supply' vhg='0.5*supply' rise=1 td='4*tp'+ targ V(xsram.xi0.xictrl.xiclkgen.a_setup) val = 'tl*supply' vhg='0.5*supply' rise=1 td='4*tp'.meas tran f_b_setup_fall_2_vssg_rise_rw+ trig V(xsram.xi0.xictrl.xiclkgen.vssg) val = 'th*supply' vhg='0.5*supply' rise=1 td='3*tp'+ targ V(xsram.xi0.xictrl.xiclkgen.b_setup) val = 'tl*supply' vhg='0.5*supply' rise=1 td='3*tp'.meas tran f_b_setup_fall_2_vssg_rise_w+ trig V(xsram.xi0.xictrl.xiclkgen.vssg) val = 'th*supply' vhg='0.5*supply' rise=1 td='6*tp'+ targ V(xsram.xi0.xictrl.xiclkgen.b_setup) val = 'tl*supply' vhg='0.5*supply' rise=1 td='6*tp'*4/ reset should come after set gone.meas tran f_scc_a_setup_fall_2_readyb_rd_fall_rw+ trig V(xsram.xi0.xictrl.xiclkgen.a_setup) val = 'tl*supply' vlg='0.5*supply' fall=1 td='3.3*tp'+ targ V(xsram.xi0.xictrl.xiclkgen.readyb_rd) val = 'th*supply_mem' fall=1 td='3.3*tp'.meas tran f_scc_a_setup_fall_2_readyb_rd_fall_r+ trig V(xsram.xi0.xictrl.xiclkgen.a_setup) val = 'tl*supply' vlg='0.5*supply' fall=1 td='4.3*tp'+ targ V(xsram.xi0.xictrl.xiclkgen.readyb_rd) val = 'th*supply_mem' fall=1 td='4.3*tp'.meas tran f_scc_b_setup_fall_2_readyb_wr_fall_rw+ trig V(xsram.xi0.xictrl.xiclkgen.b_setup) val = 'tl*supply' vlg='0.5*supply' fall=1 td='3.3*tp'+ targ V(xsram.xi0.xictrl.xiclkgen.readyb_wr) val = 'th*supply_mem' fall=1 td='3.3*tp'.meas tran f_scc_b_setup_fall_2_readyb_wr_fall_w+ trig V(xsram.xi0.xictrl.xiclkgen.b_setup) val = 'tl*supply' vlg='0.5*supply' fall=1 td='6.3*tp'+ targ V(xsram.xi0.xictrl.xiclkgen.readyb_wr) val = 'th*supply_mem' fall=1 td='6.3*tp'.meas tran f_scc_b_setup_fall_2_readyb_wr_fall_scan+ trig V(xsram.xi0.xictrl.xiclkgen.b_setup) val = 'tl*supply' vlg='0.5*supply' fall=1 td='14.3*tp'+ targ V(xsram.xi0.xictrl.xiclkgen.readyb_wrscanb) val = 'th*supply_mem' fall=1 td='14.3*tp'****************************************************************************************