Measurement Solution for new Radar Microcontroller yyy: RadarRaw Data protocol . CPU0 . CPU1 . 1or2...

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V1.01 | 2015-12-03 Measurement Solution for new Radar Microcontroller

Transcript of Measurement Solution for new Radar Microcontroller yyy: RadarRaw Data protocol . CPU0 . CPU1 . 1or2...

Page 1: Measurement Solution for new Radar Microcontroller yyy: RadarRaw Data protocol . CPU0 . CPU1 . 1or2 x 1 GBit Eth. High speed ECU (RAM) measurement . 11 ... HDD Storage . Docking Station

V1.01 | 2015-12-03

Measurement Solution for new Radar Microcontroller

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Technology Change New Vehicle Architecture

„Some ECU“ age „ECU less“ age „ECU Network“ age

Autonomous driving

E-Drive

Connectivity

Cloud computing

Security

„Near Future“

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ECU Technology Prognose New Vehicle Architecture

(Source: INTEL Automotive Division)

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Micro Controller

Impact on: DCU Micro Controller / OS / Bus Interfaces New Vehicle Architecture

Adaptive ECU OS

Bus Interfaces

+

+

+

ECU MC-Interfaces:

PCIe

Aurora with up to 25 GBit/s

XCP standard update necessary:

No fixed mapping: Signal<> RAM address

Eth. => Tap Mode

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XCP- ECU Access Datarate

Factor 50.000

JTAG

XCPonEth.

XCPonFR.

XCPonCAN

DAP2

ECU RAM Access

Aurora

0,5 MBit/s

25 GBit/s

PCIe

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XCP Dataflow via Serial Bus Interfaces or Debug-Interface

ECU RAM for Measurement

ECU RAM for Application

Possible Datarate: Network Interfaces; > XCPonCAN ~10 kB/s > Private CAN for MC ~50 kB/s > XCPonFlexRay ~ 100 kB/s > XCPonEth. ~ 2000 kB/s

Debug Interfaces: > JTAG ~1000 kB/s > DAP/LFast ~3000 kB/s > DAP2/LFast max. ~10000 kB/s DAQ Adress

Plug On

Device max. 8,5 m

XCP on Ethernet

CANape

High speed ECU (RAM) measurement

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Data Trace Approach High speed ECU (RAM) measurement

25 GB/s AURORA

5 GB/s HSSL2 Cable

1 x 50 MB/s XCPonEth VX145x

POD

VX113x Base Module

MC Tool

ECU

Requires special Aurora µC connector

6,25 GB/s AURORA

1,8 GB/s HSSL Cable

2 x 100 MB/s

New Requirement:

Next. Gen µC: i.e 4 x 6,25 GBit/s

Radar Raw Data : 100 MByte/s + XCP Data : 70 MByte/s

VX1132

VX1135

CANape

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High speed ECU (RAM) measurement

Aurora Lanes:

4 x 1,25 GBit NXP RaceRunner 4 x 1,2 GBit NXP RaceRunner Ultra 2 x 3,125 GBit Renesas RH850 V1

Vector approach for Radar µC from NXP and Renesas

Radar raw data must share the Aurora interface with RAM data

CPU (RAM data) can be stalled in case of overload, radar raw data not

» Aurora Interface overload must be avoided in any situation

Radar Front-End

Radar µC

NXP / Renesas Radar Setup: XCP-Data + Radar-Raw Data

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Renesas/ NXP Timing Diagram : Radar Raw Data / FFT / Object List Timing

40 µs

Chirp1 Chirp 256

40 µs

37,2 ms = ( 50-12,8) ms

No Chirps received

(50µs * 256 ) = 12,8 ms

……..

Pause:

10 µs

CHIRP Datarate 80 MByte/s (4 kByte/50 us) over 12,8 ms Average Chirp rate = 20 MByte/s

Objectlist 100 kByte

FFT Buffer=1 MByte/50 ms

time

2.nd FFT, Classification, Detection , Tracking Calcuation

Objectlist 100 kByte Copy Object list via Mem-Sync

Objectlist = 100 kByte / 50 ms = 2 MByte/s

Chirp2 Chirp3

Objectlist 100 kByte

……..

Chirps Buffer in VX1000 BaseModule

Mem-Sync function „Copy over Trace“ for Objectlist

High speed ECU (RAM) measurement

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2,5 GBit AURORA

2 x 2,5 GBit HSSL Cable VX1438

POD

VX1135 Base Module

MC Tool

Radar ECU

8 x 400 MBit Raw Data

Infineon Aurix Radar Setup: XCP-Data + Radar-Raw Data

CANape

Port xxx: XCPonEth.

Port yyy: RadarRaw Data protocol

CPU0

CPU1

CPU2

1or2 x 1 GBit Eth.

High speed ECU (RAM) measurement

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For some Aurix µC there are too less CPU Master Trace units

» In consequence 1 Core must be measured via RAM Copy ( CPU load + additional RAM)

Example setup for Aurix TC29x ( 3 Core): M1,M2 => Master Trace Units ( Data Trace measurement ) S1,S2 => Slave Trace Units ( Data Trace measurement ) O = OLDA ( RAM Copy measurement => This creates CPU load )

Infineon Aurix Core Trace Limitation

CPU0 CPU1 CPU2D/PSPR0 D/PSPR1 D/PSPR2

LMU SRAM,EMEM

M1

S2

M2 O

O

S1

M1 M1 M2 O

VX1000 MEM Sync function to save RAM for measurement

High speed ECU (RAM) measurement

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Radar Raw Data Replay

Every traffic situation is unique, i.e depends also on other vehicle position

Modified algorithm must be validate with exact the same traffic situation

Existing Algorithm in C/C++/C# could be re-used / wrapped in a vADAS developer component

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ADAS Logging Setup: 500 MByte/s => ~16 TByte/Day

CANape XCP Recorder Visualisierung

Time Sync Trigger Handling

PC1

Video Recorder 1

XCP Recorder 4

XCP Recorder 3

USB

XCPonEth.

2 x 1GBit/s Eth. Front Radar

Stereo-Camara

ESP-ECU

ADAS Logging

XCP + Raw Data Recorder 2

Sensor- Fusion ECU

XCP Recorder 7 4 x Corner Radar

50 MB/s

150 MB/s

100 MB/s

4 x 40 MB/s

100 MB/s

PC2

Ethernet

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ADAS Logging

Storage Server

Shock Proof Logging on SSD

Li-Ion UPS i.e. EV/HEV

Transfer via WLAN: ~2 weeks

Data Recording and Data Transport i.e 16 TByte Data

10 GBit/Eth USB.30

Thunderbolt

Thunderbolt/USB HDD Storage

Docking Station

Transport Storage Bay

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ADAS Logging

Flexible and easy to use Object Editor

Fast camera calibration

Via Chessboard and Image processing

Operational Concept: “ADAS visualization”

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Visual feedback and performing actions Displaying information like Status of the system, few signal values, … Doing actions on the touch screen like fire a trigger, execute scripts, …

Operational Concept: “Taxi Driver” Mode ADAS Logging

USB bus powered

User-defined GUI

USB LCD Touch Screen

High End Logging System

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Example: ADAS Test-Setup with several Radar + Vehicle-Cam

ADAS Logging

675 MByte/s

PC CPU Load: ~50 %

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18 © 2015. Vector Informatik GmbH. All rights reserved. Any distribution or copying is subject to prior written approval by Vector. V1.01 | 2015-12-03

For more information about Vector and our products please visit www.vector.com

Author: Alfred Kless Vector Germany