MCP 6566 6R 6U 7 9 1.8V Low Power Open Drain Output Comparator
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Transcript of MCP 6566 6R 6U 7 9 1.8V Low Power Open Drain Output Comparator
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2011 Microchip Technology Inc. DS22143C-page 1
MCP6566/6R/6U/7/9
Features:
Propagation Delay at 1.8VDD:
- 56 ns (typical) High-to-Low
Low Quiescent Current: 100 A (typical)
Input Offset Voltage: 3 mV (typical)
Rail-to-Rail Input: VSS- 0.3V to VDD+ 0.3V
Open-Drain Output
Wide Supply Voltage Range: 1.8V to 5.5V
Available in Single, Dual and Quad
Packages: SC70, SOT-23-5, SOIC, MSOP,
TSSOP
Typical Applications:
Laptop Computers
Mobile Phones
Hand-held Electronics
RC Timers
Alarm and Monitoring Circuits
Window Comparators
Multi-vibrators
Design Aids:
Microchip Advanced Part Selector (MAPS)
Analog Demonstration and Evaluation Boards
Application Notes
Related Device:
Push-Pull Output: MCP6561/1R/1U/2/4
Typical Application
Description:
The Microchip Technology, Inc. MCP6566/6R/6U/7/9
families of open-drain output comparators are offered
in single, dual and quad configurations.
These comparators are optimized for low-power 1.8V,
single-supply applications with greater than rail-to-rail
input operation. The internal input hysteresis eliminates
output switching due to internal input noise voltage,
reducing current draw. The open-drain output of the
MCP6566/6R/6U/7/9 family requires a pull-up resistor
and it supports pull-up voltages above and below VDD,which can be used to level shift. The output toggle
frequency can reach a typical of 4 MHz (typical) while
limiting supply current surges and dynamic power
consumption during switching.
This family operates with single supply voltage of 1.8V
to 5.5V while drawing less than 100 A/comparator of
quiescent current (typical).
Package Types
VIN
VOUT
+5VDD
R2
RFR3
VDD
+3VPU
MCP656X
MCP6567
+INA
-INA
VSS
1
2
3
4
8
7
6
5
-
OUTA
+ -
+
VDD
OUTB
-INB
+INB
MCP6569
+INA
-INA
VSS
1
2
3
4
14
13
12
11
-
OUTA
+ -+
VDD
OUTD
-IND
+IND
10
9
8
5
6
7OUTB
-INB
+INB +INC
-INC
OUTC
+- -+
5
4
MCP6566
1
2
3
-+
5
4
MCP6566R
1
2
3
-+
+IN
VSS
OUT
-IN
VDD
+IN
VDD
OUT
-IN
VSS
SOT-23-5, SC70-5 SOIC, MSOP
SOT-23-5 SOIC, TSSOP
4
1
2
3
5
SOT-23-5
VSS
VIN+
VIN
VDD
OUT
MCP6566U
-
+
1.8V Low-Power Open-Drain Output Comparator
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MCP6566/6R/6U/7/9
DS22143C-page 2 2011 Microchip Technology Inc.
NOTES:
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2011 Microchip Technology Inc. DS22143C-page 3
MCP6566/6R/6U/7/9
1.0 ELECTRICALCHARACTERISTICS
1.1 Maximum Ratings*
VDD- VSS ................ ............... ............... ................ ......... 6.5V
Open-Drain Output.............................................VSS+ 10.5V
All other inputs and outputs.......... .VSS 0.3V to VDD+ 0.3V
Difference Input voltage ........ ............... ............... |VDD- VSS|
Output Short Circuit Current ....................................25 mA
Current at Input Pins ..................................................2 mA
Current at Output and Supply Pins ..........................50 mA
Storage temperature ................................... -65C to +150C
Ambient temp. with power applied .............. -40C to +125C
Junction temp............................................................ +150C
ESD protection on all pins (HBM/MM) 4 kV/300V
*Notice: Stresses above those listed under Maximum
Ratings may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
operational listings of this specification is not implied. Expo-
sure to maximum rating conditions for extended periods may
affect device reliability.
DC CHARACTERISTICS
Electrical Characteristics:Unless otherwise indicated: VDD= +1.8V to +5.5V, VSS= GND, TA= +25C, VIN+ = VDD/2, VIN- = VSS,and RPull-Up= 20 kto VPU= VDD(see Figure 1-1).
Parameters Symbol Min Typ Max Units Conditions
Power Supply
Supply Voltage VDD 1.8 5.5 V
Quiescent Current per comparator IQ 60 100 130 A IOUT= 0
Power Supply Rejection Ratio PSRR 63 70 dB VCM = VSS
Input
Input Offset Voltage VOS -10 3 +10 mV VCM = VSS (Note 1)
Input Offset Drift VOS/T 2 V/C VCM = VSSInput Offset Current IOS 1 pA VCM = VSSInput Bias Current IB 1 pA TA= +25C, VIN- = VDD/2
60 pA TA= +85C, VIN- = VDD/2
1500 5000 pA TA= +125C, VIN- = VDD/2
Input Hysteresis Voltage VHYST 1.0 5.0 mV VCM = VSS (Notes 1, 2)
Input Hysteresis Linear Temp. Co. TC1 10 V/C
Input Hysteresis Quadratic Temp. Co. TC2 0.3 V/C2
Common-Mode Input Voltage Range VCMR VSS0.2 VDD+0.2 V VDD= 1.8V
VSS0.3 VDD+0.3 V VDD= 5.5V
Common-Mode Rejection Ratio CMRR 54 66 dB VCM= -0.3V to VDD+0.3V, VDD= 5.5V
50 63 dB VCM= VDD/2 to VDD+0.3V, VDD= 5.5V
54 65 dB VCM= -0.3V to VDD/2, VDD= 5.5V
Common Mode Input Impedance ZCM 1013||4 ||pF
Differential Input Impedance ZDIFF 1013||2 ||pF
Note 1: The input offset voltage is the center of the input-referred trip points. The input hysteresis is the difference between the
input-referred trip points.
2: VHYSTat different temperatures is estimated using VHYST(TA) = VHYST @ +25C+ (TA- 25C) TC1+ (TA- 25C)2TC2.
3: Limit the output current to Absolute Maximum Rating of 50 mA.
4: The pull-up voltage for the open drain output VPULL_UPcan be as high as the absolute maximum rating of 10.5V. In this
case, IOH_leakcan be higher than 1 A (see Figure 2-30).
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MCP6566/6R/6U/7/9
DS22143C-page 4 2011 Microchip Technology Inc.
Push-Pull Output
Pull-up Voltage VPULL_UP 1.6 5.5 V
High Level Output Voltage VOH VPULL_UP V (see Figure 1-1) (Notes 3, 4)
High Level Output Current leakage IOH_leak 1 A Note 4
Low Level Output Voltage VOL 0.6 V IOUT= 3 mA/8 mA @ VDD= 1.8V/5.5V
Short Circuit Current (Notes 3) ISC 30 mA Not to exceed Absolute Max. Rating
Output Pin Capacitance COUT 8 pF
DC CHARACTERISTICS (CONTINUED)
Electrical Characteristics:Unless otherwise indicated: VDD= +1.8V to +5.5V, VSS= GND, TA= +25C, VIN+ = VDD/2, VIN- = VSS,
and RPull-Up= 20 kto VPU= VDD(see Figure 1-1).
Parameters Symbol Min Typ Max Units Conditions
Note 1: The input offset voltage is the center of the input-referred trip points. The input hysteresis is the difference between the
input-referred trip points.
2: VHYSTat different temperatures is estimated using VHYST(TA) = VHYST @ +25C+ (TA- 25C) TC1+ (TA- 25C)2TC2.
3: Limit the output current to Absolute Maximum Rating of 50 mA.
4: The pull-up voltage for the open drain output VPULL_UPcan be as high as the absolute maximum rating of 10.5V. In this
case, IOH_leakcan be higher than 1 A (see Figure 2-30).
AC CHARACTERISTICSElectrical Characteristics:Unless otherwise indicated,: Unless otherwise indicated,: VDD= +1.8V to +5.5V, VSS= GND,
TA= +25C, VIN+ = VDD/2, VIN-= VSS, RPull-Up= 20 kto VPU= VDD, and CL= 25 pf (see Figure 1-1).
Parameters Symbol Min Typ Max Units Conditions
Propagation Delay
High-to-Low,100 mV Overdrive tPHL 56 80 ns VCM= VDD/2, VDD= 1.8V
34 80 ns VCM= VDD/2, VDD= 5.5V
Output
Fall Time tF 20 ns
Maximum Toggle Frequency f TG 4 MHz VDD= 5.5V
2 MHz VDD= 1.8V
Input Voltage Noise ENI 350 VP-P 10 Hz to 10 MHz (Note 1)
Note 1: ENI is based on SPICE simulation.
2: Rise time tRand tPLHdepend on the load (RLand CL). These specification are valid for the specified load only.
TEMPERATURE SPECIFICATIONS
Electrical Characteristics:Unless otherwise indicated: VDD= +1.8V to +5.5V and VSS= GND.
Parameters Symbol Min Typ Max Units Conditions
Temperature Ranges
Specified Temperature Range TA -40 +125 C
Operating Temperature Range TA -40 +125 C
Storage Temperature Range TA -65 +150 C
Thermal Package ResistancesThermal Resistance, SC70-5 JA 331 C/W
Thermal Resistance, SOT-23-5 JA 220.7 C/W
Thermal Resistance, 8L-MSOP JA 211 C/W
Thermal Resistance, 8L-SOIC JA 149.5 C/W
Thermal Resistance, 14L-SOIC JA 95.3 C/W
Thermal Resistance, 14L-TSSOP JA 100 C/W
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2011 Microchip Technology Inc. DS22143C-page 5
MCP6566/6R/6U/7/9
1.2 Test Circuit Configuration
This test circuit configuration is used to determine the
AC and DC specifications.
FIGURE 1-1: AC and DC Test Circuit for
the Open-Drain Output Comparators.
VDD
VSS= 0V
200 k
200 k
RPU
VOUT
VIN= VSS
25 pF
VPU= VDD
20 kIOUT
MCP656X
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MCP6566/6R/6U/7/9
DS22143C-page 6 2011 Microchip Technology Inc.
NOTES:
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2011 Microchip Technology Inc. DS22143C-page 7
MCP6566/6R/6U/7/9
2.0 TYPICAL PERFORMANCE CURVES
Note:Unless otherwise indicated, VDD
= +1.8V to +5.5V, VSS
= GND, TA
= +25C, VIN
+ = VDD
/2, VIN
= GND,
RL= 20 kto VPU= VDD, and CL = 25 pF.
FIGURE 2-1: Input Offset Voltage.
FIGURE 2-2: Input Offset Voltage Drift.
FIGURE 2-3: Input vs. Output Signal, No
Phase Reversal.
FIGURE 2-4: Input Hysteresis Voltage.
FIGURE 2-5: Input Hysteresis Voltage
Drift - Linear Temp. Co. (TC1).
FIGURE 2-6: Input Hysteresis Voltage
Drift - Quadratic Temp. Co. (TC2).
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
0%
10%
20%
30%
40%
50%
-10 -8 -6 -4 -2 0 2 4 6 8 10
VOS(mV)
Occurrences(%)
VDD= 1.8V
VCM= VSSAvg. = -0.1 mV
StDev = 2.1 mV
3588 units
VDD= 5.5V
VCM= VSSAvg. = -0.9 mV
StDev = 2.1 mV
3588 units
0%
10%
20%
30%
40%
50%
60%
-60 -48 -36 -24 -12 0 12 24 36 48 60
VOSDrift (V/C)
Occurrences(%)
VCM= VSS
Avg. = 0.9 V/C
StDev = 6.6 V/C
1380 Units
TA= -40C to +125C
-1.0
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
Time (3 s/div)
VOUT
(V)
VIN- VOUT
VDD = 5.5V VIN+ = VDD/2
0%
5%
10%
15%
20%
25%
30%
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VHYST(mV)
Occurrences(%)
VDD = 1.8V
Avg. = 3.4 mV
StDev = 0.2 mV
3588 units
VDD = 5.5V
Avg. = 3.6 mV
StDev = 0.1 mV
3588 units
0%
10%
20%
30%
40%
50%
60%
0 2 4 6 8 10 12 14 16 18 20
VHYSTDrift, TC1 (V/C)
Occurrences(%)
1380 Units
TA= -40C to 125C
VCM= VSS
VDD= 5.5V
Avg. = 10.4 V/C
StDev = 0.6 V/C
VDD= 1.8V
Avg. = 12 V/C
StDev = 0.6 V/C
0%
10%
20%
30%
-0.50 -0.25 0.00 0.25 0.50 0.75 1.00
VHYSTDrift, TC2 (V/C2)
O
ccurrences(%) VDD= 5.5V
Avg. = 0.25 V/C2
StDev = 0.1 V/C2
VDD= 1.8V
Avg. = 0.3 V/C2
StDev = 0.2 V/C2
1380 Units
TA= -40C to +125C
VCM= VSS
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MCP6566/6R/6U/7/9
DS22143C-page 8 2011 Microchip Technology Inc.
Note:Unless otherwise indicated, VDD= +1.8V to +5.5V, VSS= GND, TA= +25C, VIN+ = VDD/2, VIN= GND,
RL= 20 kto VPU= VDD, and CL = 25 pF.
FIGURE 2-7: Input Offset Voltage vs.
Temperature.
FIGURE 2-8: Input Offset Voltage vs.
Common-mode Input Voltage.
FIGURE 2-9: Input Offset Voltage vs.Common-mode Input Voltage.
FIGURE 2-10: Input Hysteresis Voltage vs.
Temperature.
FIGURE 2-11: Input Hysteresis Voltage vs.
Common-mode Input Voltage.
FIGURE 2-12: Input Hysteresis Voltage vs.Common-mode Input Voltage.
-3.0
-2.0
-1.0
0.0
1.0
2.0
3.0
-50 -25 0 25 50 75 100 125
Temperature(C)
VOS(mV)
VDD= 1.8V
VDD= 5.5V
VCM = VSS
-4.0
-2.0
0.0
2.0
4.0
-0.3 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1
VCM(V)
VOS
(mV)
VDD = 1.8V
TA= +25C
TA= +125C
TA= +85C
TA= -40C
-3.0
-2.0
-1.0
0.0
1.0
2.0
3.0
-1.0 0.0 1.0 2.0 3.0 4.0 5.0 6.0
VCM(V)
VOS
(mV)
VDD = 5.5V
TA= -40C
TA= +25C
TA= +125C
TA= +85C
1.0
2.0
3.0
4.0
5.0
-50 -25 0 25 50 75 100 125
Temperature(C)
VHYST(mV
)VDD= 5.0V
VDD= 1.8V
VCM = VSS
1.0
2.0
3.0
4.0
5.0
-0.3 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1
VCM(V)
VHYST(mV)
VDD = 1.8V
TA= +25C
TA= +125C
TA= +85C
TA= -40C
1.0
2.0
3.0
4.0
5.0
-0.5 0.5 1.5 2.5 3.5 4.5 5.5
VCM(V)
VHYST(mV)
VDD = 5.5V
TA= -40C
TA= +85C
TA= +25C
TA= +125C
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MCP6566/6R/6U/7/9
Note:Unless otherwise indicated, VDD= +1.8V to +5.5V, VSS= GND, TA= +25C, VIN+ = VDD/2, VIN= GND,
RL= 20 kto VPU= VDD, and CL = 25 pF.
FIGURE 2-13: Input Offset Voltage vs.
Supply Voltage vs. Temperature.
FIGURE 2-14: Quiescent Current.
FIGURE 2-15: Quiescent Current vs.Common-mode Input Voltage.
FIGURE 2-16: Input Hysteresis Voltage vs.
Supply Voltage vs. Temperature.
FIGURE 2-17: Quiescent Current vs.
Supply Voltage vs Temperature.
FIGURE 2-18: Quiescent Current vs.Common-mode Input Voltage.
-3.0
-2.0
-1.0
0.0
1.0
2.0
3.0
1.5 2.5 3.5 4.5 5.5
VDD(V)
VOS
(mV)
TA= -40C
TA= +85C
TA= +25C
TA= +125C
0%
10%
20%
30%
40%
50%
60 70 80 90 100 110 120 130
IQ(A)
Occurrences(%)
VDD= 5.5V
Avg. = 97 A
StDev= 4 A
1794 units
VDD= 1.8V
Avg. = 88 A
StDev= 4 A
1794 units
60
70
80
90
100
110
120
130
-0.5 0.0 0.5 1.0 1.5 2.0 2.5
VCM(V)
IQ(A)
VDD = 1.8V
Sweep VIN+ ,VIN- = VDD/2
Sweep VIN- ,VIN+=
Sweep VIN+ ,VIN- = VDD/2
Sweep VIN- ,VIN+= VDD/2
1.0
2.0
3.0
4.0
5.0
1.5 2.5 3.5 4.5 5.5
VDD(V)
VHYST(mV)
TA= +85C
TA= +125C
TA= +25C
TA= -40C
0.0
20.0
40.0
60.0
80.0
100.0
120.0
140.0
0.0 1.0 2.0 3.0 4.0 5.0 6.0
VDD(V)
IQ(A)
TA= -40C
TA= +85C
TA= +125C
TA= +25C
60
70
80
90
100
110
120
130
-1.0 0.0 1.0 2.0 3.0 4.0 5.0 6.0
VCM(V)
IQ(A)
VDD = 5.5V
Sweep VIN+ ,VIN- = VDD/2
Sweep VIN- ,VIN+= VDD/2
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DS22143C-page 10 2011 Microchip Technology Inc.
Note:Unless otherwise indicated, VDD= +1.8V to +5.5V, VSS= GND, TA= +25C, VIN+ = VDD/2, VIN= GND,
RL= 20 kto VPU= VDD, and CL = 25 pF.
FIGURE 2-19: Quiescent Current vs.
Pull-up Voltage.
FIGURE 2-20: Quiescent Current vs.
Toggle Frequency.
FIGURE 2-21: Output Headroom vs OutputCurrent.
FIGURE 2-22: Quiescent Current vs.
Pull-up to Supply Voltage Difference.
FIGURE 2-23: Output Leakage Current vs.
Pull-up Voltage.
FIGURE 2-24: Output Headroom Vs OutputCurrent.
50
75
100
125
150
0.5 1.5 2.5 3.5 4.5 5.5 6.5 7.5 8.5 9.5 10.5VPU(V)
IQ(A)
IDDSpike near VPU= 0.9V
VDD = 5.5V
VDD= 4.5V
VDD= 3.5V
VDD= 2.5V
VDD= 2.0V
VDD= 1.8V
50
100
150
200
250
300
350
400
10 100 1000 10000 100000 100000
0
1E+07Toggle Frequency (Hz)
IQ(A)
VDD = 1.8V
VDD = 5.5V
10 100 1k 10k 100k 1M 10M
100 mV Over-Drive
VCM= VDD/2
RL= Open
0dB Output Attenuation
0
200
400
600
800
1000
0.0 3.0 6.0 9.0 12.0 15.0
IOUT (mA)
VOL(mV)
VDD= 1.8V
TA = +125C
TA= +85C
TA = +25C
TA= -40C
50
75
100
125
150
-4.5 -2.5 -0.5 1.5 3.5 5.5 7.5 9.5
VPU- VDD (V)
IQ(A)
VDD = 3.5 V
VDD = 1.8 V
VDD = 2.5 V
VDD = 2.0 V
VDD = 4.5 V
VDD = 5.5 V
1
10
100
1,000
10,000
100,000
1.5 2.5 3.5 4.5 5.5 6.5 7.5 8.5 9.5 10.5
VPU (V)
IOH_
leak(pA)
TA = +25C
TA = +85C
TA =
0
200
400
600
800
1000
0 5 10 15 20 25
IOUT (mA)
VOL(mV)
VDD= 5.5V
TA = 125CTA = 125C
TA= +85C
TA= -40C
TA = +25C
TA = +125C
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MCP6566/6R/6U/7/9
Note:Unless otherwise indicated, VDD= +1.8V to +5.5V, VSS= GND, TA= +25C, VIN+ = VDD/2, VIN= GND,
RL= 20 kto VPU= VDD, and CL = 25 pF.
FIGURE 2-25: High-to-Low Propagation
Delays.
FIGURE 2-26: Propagation Delay vs. Input
Over-Drive.
FIGURE 2-27: Propagation Delay vs.Supply Voltage.
FIGURE 2-28: High-to-Low Propagation
Delays.
FIGURE 2-29: Propagation Delay vs.
Temperature.
FIGURE 2-30: Short Circuit Current vs.Supply Voltage vs. Temperature.
0%
10%
20%
30%
40%
50%
30 35 40 45 50 55 60 65 70 75 80
Prop. Delay (ns)
Occurrences(%)
VDD= 1.8V
100 mV Over-Drive
VCM= VDD/2
tPHLAvg. = 54.4 ns
StDev= 2 ns
198 units
10
60
110
160
210
260
1 10 100 1000
Over-Drive (mV)
Prop.Delay(ns)
tPHL, VDD= 1.8V
tPHL, VDD= 5.5V
VCM= VDD/2
20
40
60
80
100
120
140
1.5 2.5 3.5 4.5 5.5
VDD(V)
Prop.Delay(ns)
tPHL , 10 mV Over-Drive
tPHL , 100 mV Over-Drive
VCM= VDD/2
0%
10%
20%
30%
40%
50%
30 35 40 45 50 55 60 65 70 75 80
Prop. Delay (ns)
Occurrences(%)
VDD= 5.5V
100mV Over-DriveVCM= VDD/2
tPHL
Avg. = 33 nsStDev= 1 ns
198 units
20
30
40
50
60
70
80
-50 -25 0 25 50 75 100 125
Temperature(C)
Prop.Delay(ns)
tPHL, VDD= 1.8V
100 mV Over-DriveVCM= VDD/2
tPHL, VDD= 5.5V
-120
-80
-40
0
40
80
120
0.0 1.0 2.0 3.0 4.0 5.0 6.0
VDD (V)
ISC
(mA)
TA= -40C
TA= +85C
TA= +125C
TA= +25C
TA= -40C
TA= +85C
TA= +25C
TA= +125C
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Note:Unless otherwise indicated, VDD= +1.8V to +5.5V, VSS= GND, TA= +25C, VIN+ = VDD/2, VIN= GND,
RL= 20 kto VPU= VDD, and CL = 25 pF.
FIGURE 2-31: Propagation Delay vs.
Common-mode Input Voltage.
FIGURE 2-32: Propagation Delay vs.
Capacitive Load.
FIGURE 2-33: Input Bias Current vs. InputVoltage vs Temperature.
FIGURE 2-34: Propagation Delay vs.
Common-mode Input Voltage.
FIGURE 2-35: Propagation Delay vs.
Pull-up Resistor.
FIGURE 2-36: Propagation Delay vs.Pull-up Voltage.
20
30
40
50
60
70
80
0.00 0.50 1.00 1.50 2.00
VCM(V)
Prop.
Delay
(ns)
tPHL
VDD= 1.8V
100 mV Over-Drive
0.01
0.1
1
10
100
1000
1 10 100 1000 10000 100000 1E+06
Capacitive Load (nf)
Prop.Delay(s)
0.001 0.01 0.1 1 10 100 1000
VDD= 5.5V, tPHL
100mV Over-Drive
VCM= VDD/2
VDD= 1.8V, tPHL
1E-01
1E+01
1E+03
1E+05
1E+07
1E+09
1E+11
-0.8 -0.6 -0.4 -0.2 0
Input Voltage(V)
InputCurrent(A)
TA= -40C
TA= +85C
TA= +125C
TA= +25C
0.1p
10p
1n
100n
10
1m
10m
20
30
40
50
60
70
80
0.0 1.0 2.0 3.0 4.0 5.0 6.0
VCM(V)
Prop.
Delay
(ns)
tPHL
VDD= 5.5V
100 mV Over-Drive
10
100
1000
10000
0.1 1.0 10.0 100.0
RPU(k)
Prop.Delay(ns)
tPLH
tPHL
100 mV Over-Drive
VCM= VDD/2
10
100
1000
10000
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VPU(V)
Prop.Delay(ns)
tPLH, VDD= 5.5V
100 mV Over-Drive
VCM= VDD/2
tPLH, VDD= 1.8V
tPHL, VDD= 1.8V
tPLH, VDD= 5.5V
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Note:Unless otherwise indicated, VDD= +1.8V to +5.5V, VSS= GND, TA= +25C, VIN+ = VDD/2, VIN= GND,
RL= 20 kto VPU= VDD, and CL = 25 pF.
FIGURE 2-37: Common-mode Rejection
Ratio and Power Supply Rejection Ratio vs.
Temperature.
FIGURE 2-38: Power Supply Rejection
Ratio (PSRR).
FIGURE 2-39: Input Offset Current and
Input Bias Current vs. Temperature.
FIGURE 2-40: Common-mode Rejection
Ratio (CMRR).
FIGURE 2-41: Common-mode Rejection
Ratio (CMRR).
FIGURE 2-42: Input Offset Current and
Input Bias Current vs. Common-mode Input
Voltage vs. Temperature.
70
72
74
76
78
80
-50 -25 0 25 50 75 100 125
Temperature(C)
CMRR/PSRR
(dB)
VCM = -0.3V to VDD + 0.3V
VDD= 5.5V
CMRR
VCM = VSSVDD= 1.8V to 5.5V
PSRR
Input Referred
0%
5%
10%
15%
20%
25%
30%
-600 -400 -200 0 200 400 600
PSRR (V/V)
Occurrences(%)
VCM = VSS
Avg. = 200 V/V
StDev= 94 V/V
3588 units
0.1
1
10
100
1000
25 50 75 100 125
Temperature(C)
IOS
andIB(pA)
IB
|IOS|
0%
10%
20%
30%
-5 -4 -3 -2 -1 0 1 2 3 4 5
CMRR (mV/V)
Occurrences
(%)
VDD= 1.8V
3588 units
VCM= -0.2V to VDD/2
Avg. = 0.5 mV
StDev= 0.1 mV
VCM= VDD/2 to VDD+ 0.2V
Avg. = 0.7 mV
StDev= 1 mV
VCM= -0.2V to VDD + 0.2V
Avg. = 0.6 mV
StDev= 0.1 mV
0%
10%
20%
30%
-2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5
CMRR (mV/V)
Occurrences(%)
VDD= 5.5V
3588 units
VCM= -0.3V to VDD/2
Avg. = 0.2 mV
StDev= 0.4 mV
VCM= VDD/2 to VDD+ 0.3V
Avg. = 0.03 mV
StDev= 0.7 mV
VCM= -0.3V to VDD + 0.3V
Avg. = 0.1 mV
StDev= 0.4 mV
0.001
0.01
0.1
1
10
100
1000
10000
0 1 2 3 4 5 6
VCM (V)
IOS
andIB(pA)
IB@ TA= +125C
IB@ TA= +85C
|IOS|@ TA= +125C
|IOS|@ TA= +85C
VDD = 5.5V
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Note:Unless otherwise indicated, VDD= +1.8V to +5.5V, VSS= GND, TA= +25C, VIN+ = VDD/2, VIN= GND,
RL= 20 kto VPU= VDD, and CL = 25 pF.
FIGURE 2-43: Output Jitter vs. Input
Frequency.
0.1
1
10
100
1000
10000
100 1000 10000 100000 100000
0
1E+07Input Frequency (Hz)
OutputJitterpk-pk(ns) VDD = 5.5V
100 1k 10k 100k 1M 10M
VIN+ = 2Vpp (sine)
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3.0 PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1.
TABLE 3-1: PIN FUNCTION TABLE
3.1 Analog Inputs
The comparator non-inverting and inverting inputs are
high-impedance CMOS inputs with low bias currents.
3.2 Digital Outputs
The comparator outputs are CMOS, open-drain digital
outputs. They are designed to make level shifting andwired-OR easy to implement.
3.3 Power Supply (VSSand VDD)
The positive power supply pin (VDD) is 1.8V to 5.5V
higher than the negative power supply pin (VSS). For
normal operation, the other pins are at voltages
between VSSand VDD.
Typically, these parts are used in a single (positive)
supply configuration. In this case, VSSis connected toground and VDD is connected to the supply. VDDwill
need a local bypass capacitor (typically 0.01 F to
0.1 F) within 2 mm of the VDDpin. These can share a
bulk capacitor with nearby analog parts (within
100 mm), but it is not required.
MCP6566 MCP6566R MCP6566U MCP6567 MCP6569
Symbol DescriptionSC70-5,
SOT-23-5 SOT-23-5 SOT-23-5
MSOP,
SOIC
SOIC,
TSSOP
1 1 5 1 1 OUT, OUTA Digital Output (comparator A)
4 4 3 2 2 VIN, VINA Inverting Input (comparator A)
3 3 1 3 3 VIN+, VINA+ Non-inverting Input (comparator A)
5 2 4 8 4 VDD Positive Power Supply
5 5 VINB+ Non-inverting Input (comparator B)
6 6 VINB Inverting Input (comparator B)
7 7 OUTB Digital Output (comparator B)
8 OUTC Digital Output (comparator C)
9 VINC Inverting Input (comparator C)
10 VINC+ Non-inverting Input (comparator C)
2 5 2 4 11 VSS Negative Power Supply
12 VIND+ Non-inverting Input (comparator D)
13 VIND Inverting Input (comparator D)
14 OUTD Digital Output (comparator D)
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4.0 APPLICATIONS INFORMATION
The MCP6566/6R/6U/7/9 family of open-drain output
comparators are fabricated on Microchips
state-of-the-art CMOS process. They are suitable for a
wide range of high speed applications requiring low-
power consumption.
4.1 Comparator Inputs
4.1.1 NORMAL OPERATION
The input stage of this family of devices uses two
differential input stages in parallel. This configuration
provides three regions of operation, one operates at
low input voltages, one at high input voltages, and one
at mid input voltage. With this topology, the input
voltage range is 0.3V above VDDand 0.3V below VSS,
while providing low offset voltage throughout the
common mode range. The input offset voltage is
measured at both VSS- 0.3V and VDD+ 0.3V to ensure
proper operation.
The MCP6566/6R/6U/7/9 family has internally-set
hysteresis VHYST that is small enough to maintain input
offset accuracy and large enough to eliminate output
chattering caused by the comparators own input noise
voltage ENI. Figure 4-1 depicts this behavior. Input
offset voltage (VOS) is the center (average) of the
(input-referred) low-high and high-low trip points. Input
hysteresis voltage (VHYST) is the difference between
the same trip points.
FIGURE 4-1: The MCP6566/6R/6U/7/9
comparators internal hysteresis eliminates
output chatter caused by input noise voltage.
4.1.2 INPUT VOLTAGE AND CURRENT
LIMITS
The ESD protection on the inputs can be depicted as
shown in Figure 4-2. This structure was chosen to
protect the input transistors, and to minimize input bias
current (IB). The input ESD diodes clamp the inputs
when they try to go more than one diode drop below
VSS. They also clamp any voltages that go too far
above VDD; their breakdown voltage is high enough to
allow normal operation, and low enough to bypass ESD
events within the specified limits.
FIGURE 4-2: Simplified Analog Input ESD
Structures.
In order to prevent damage and/or improper operation
of these amplifiers, the circuits they are in must limit the
currents (and voltages) at the VIN+ and VIN pins (see
Section 1.1 Maximum Ratings*at the beginning of
Section 1.0 Electrical Characteristics). Figure 4-3
shows the recommended approach to protecting these
inputs. The internal ESD diodes prevent the input pins
(VIN
+ and VIN) from going too far below ground, and
the resistors R1and R2limit the possible current drawn
out of the input pin. Diodes D1and D2prevent the input
pin (VIN+ and VIN) from going too far above VDD.
When implemented as shown, resistors R1and R2also
limit the current through D1and D2.
FIGURE 4-3: Protecting the Analog
Inputs.
-3
-2
-1
0
1
2
3
4
5
6
7
8
Time (100 ms/div)
OutputVoltage(V)
-30
-25
-20
-15
-10
-5
0
5
10
15
20
25
InputVoltage(10mV/
div)
VOUT
VIN
VDD= 5.0V
Hysteresis
Bond
Pad
Bond
Pad
Bond
Pad
VDD
VIN+
VSS
InputStage
Bond
PadVIN
V1R1
VDD
D1
R2VSS (minimum expected V2)
2 mA
VOUT
V2R2 R3
D2
+
R1 VSS (minimum expected V1)
2 mA
VPU
R4
MCP656X
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It is also possible to connect the diodes to the left of the
resistors R1and R2. In this case, the currents through
the diodes D1and D2need to be limited by some other
mechanism. The resistor then serves as in-rush current
limiter; the DC current into the input pins (V IN+ and
VIN) should be very small.
A significant amount of current can flow out of the
inputs when the common mode voltage (VCM) is below
ground (VSS); see Figure 4-3. Applications that are
high-impedance may need to limit the usable voltage
range.
4.1.3 PHASE REVERSAL
The MCP6566/6R/6U/7/9 comparator family uses
CMOS transistors at the input. They are designed to
prevent phase inversion when the input pins exceed
the supply voltages. Figure 2-3shows an input voltage
exceeding both supplies with no resulting phase
inversion.
4.2 Open-Drain OutputThe open-drain output is designed to make
level-shifting and wired-OR logic easy to implement.
The output stage minimizes switching current
(shoot-through current from supply-to-supply) when
the output changes state. See Figures 2-15, 2-18,
2-35and 2-36, for more information.
4.3 Externally Set Hysteresis
Greater flexibility in selecting hysteresis (or input trip
points) is achieved by using external resistors.
Hysteresis reduces output chattering when one input is
slowly moving past the other. It also helps in systems
where it is best not to cycle between high and low
states too frequently (e.g., air conditioner thermostatic
control). Output chatter also increases the dynamic
supply current.
4.3.1 NON-INVERTING CIRCUIT
Figure 4-4 shows a non-inverting circuit for
single-supply applications using just two resistors. The
resulting hysteresis diagram is shown in Figure 4-5.
FIGURE 4-4: Non-Inverting Circuit with
Hysteresis for Single-Supply.
FIGURE 4-5: Hysteresis Diagram for the
Non-Inverting Circuit.
The trip points for Figures 4-4and 4-5are:
EQUATION 4-1:
VREF
VIN
VOUT
VDD
R1 RF
+
-
VPU
RPU
MCP656X
VOUT
High-to-Low Low-to-High
VDDVOH
VOLVSS
VSS VDDVTHL VTLH
VIN
VTL H
VRE F
1
R1
RF
-------+
VOL
R1
RF
-------
=
VTH L
VRE F
1
R1
RF
-------+
VOH
R1
RF
-------
=
Where:
VTLH = trip voltage from low-to-high
VTHL = trip voltage from high-to-low
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4.3.2 INVERTING CIRCUIT
Figure 4-6shows an inverting circuit for single-supply
using three resistors. The resulting hysteresis diagram
is shown in Figure 4-7.
FIGURE 4-6: Inverting Circuit with
Hysteresis.
FIGURE 4-7: Hysteresis Diagram for the
Inverting Circuit.
In order to determine the trip voltages (VTHLand VTLH)for the circuit shown in Figure 4-6, R2and R3can be
simplified to the Thevenin equivalent circuit with
respect to VDD, as shown in Figure 4-8.
FIGURE 4-8: Thevenin Equivalent Circuit.
Where:
Using this simplified circuit, the trip voltage can be
calculated using the following equation:
EQUATION 4-2:
Figure 2-21and Figure 2-24can be used to determine
typical values for VOHand VOL.
4.4 Bypass Capacitors
With this family of comparators, the power supply pin
(VDD for single supply) should have a local bypass
capacitor (i.e., 0.01 F to 0.1 F) within 2 mm for good
edge rate performance.
4.5 Capacitive Loads
Reasonable capacitive loads (e.g., logic gates) havelittle impact on propagation delay (see Figure 2-32).
The supply current increases with increasing toggle
frequency (Figure 2-20), especially with higher
capacitive loads. The output slew rate and propagation
delay performance will be reduced with higher
capacitive loads.
VIN
VOUT
VDD
R2
RFR3
VDD
VPU
RPU
MCP656X
VOUT
High-to-LowLow-to-High
VDDVOH
VOLVSS
VSS VDDVTLH VTHL
VIN
V23
VOUT
VDD
R23 RF
+
-
VSS
VPU
RPU
MCP656X
R23
R2
R3
R2
R3
+-------------------=
V23
R3
R2
R3
+------------------- V
DD=
VTH L
VOH
R23
R23
RF
+-----------------------
V23
RF
R23
RF
+----------------------
+=
VTL H
VOL
R23
R23
RF
+-----------------------
V23
RF
R23
RF
+----------------------
+=
Where:
VTLH = trip voltage from low-to-high
VTHL = trip voltage from high-to-low
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4.6 PCB Surface Leakage
In applications where low input bias current is critical,
PCB (Printed Circuit Board) surface leakage effects
need to be considered. Surface leakage is caused by
humidity, dust or other contamination on the board.
Under low humidity conditions, a typical resistance
between nearby traces is 10
12. A 5V difference wouldcause 5 pA of current to flow. This is greater than the
MCP6566/6R/6U/7/9 familys bias current at +25C
(1 pA, typical).
The easiest way to reduce surface leakage is to use a
guard ring around sensitive pins (or traces). The guard
ring is biased at the same voltage as the sensitive pin.
An example of this type of layout is shown in
Figure 4-9.
FIGURE 4-9: Example Guard Ring Layout
for Inverting Circuit.
1. Inverting Configuration (Figures 4-6and 4-9):
a) Connect the guard ring to the non-inverting
input pin (VIN+). This biases the guard ring
to the same reference voltage as the
comparator (e.g., VDD/2 or ground).b) Connect the inverting pin (VIN) to the input
pad without touching the guard ring.
2. Non-inverting Configuration (Figure 4-4):
a) Connect the non-inverting pin (VIN+) to the
input pad without touching the guard ring.
b) Connect the guard ring to the inverting input
pin (VIN).
4.7 PCB Layout Technique
When designing the PCB layout it is critical to note that
analog and digital signal traces are adequately
separated to prevent signal coupling. If the comparator
output trace is at close proximity to the input traces
then large output voltage changes from, VSSto VDDor
visa versa, may couple to the inputs and cause thedevice output to oscillate. To prevent such oscillation,
the output traces must be routed away from the input
pins. The SC70-5 and SOT-23-5 are relatively immune
because the output pin OUT (pin 1) is separated by the
power pin VDD/VSS(pin 2) from the input pin +IN (as
long as the analog and digital traces remain separated
throughout the PCB). However, the pinouts for the dual
and quad packages (SOIC, MSOP, TSSOP) have OUT
and -IN pins (pin 1 and 2) close to each other. The
recommended layout for these packages is shown in
Figure 4-10.
FIGURE 4-10: Recommended Layout.
4.8 Unused Comparators
An unused amplifier in a quad package (MCP6569)
should be configured as shown in Figure 4-11. This
circuit prevents the output from toggling and causingcrosstalk. It uses the minimum number of components
and draws minimal current (see Figure 2-15 and
Figure 2-15).
FIGURE 4-11: Unused Comparators.
Guard Ring
VSSIN- IN+
-INA
+INA -INB
+INB
OUTB
OUTA
VSS
VDD
VDD
+
MCP6569
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5.0 DESIGN AIDS
5.1 Microchip Advanced Part Selector
(MAPS)
MAPS is a software tool that helps semiconductor
professionals efficiently identify Microchip devices that
fit a particular design requirement. Available at no costfrom the Microchip web site at www.microchip.com/
maps, the MAPS is an overall selection tool for
Microchips product portfolio that includes Analog,
Memory, MCUs and DSCs. Using this tool you can
define a filter to sort features for a parametric search of
devices and export side-by-side technical comparison
reports. Helpful links are also provided for Data Sheets,
Purchase, and Sampling of Microchip parts.
5.2 Analog Demonstration and
Evaluation Boards
Microchip offers a broad spectrum of Analog
Demonstration and Evaluation Boards that are
designed to help you achieve faster time to market. For
a complete listing of these boards and their
corresponding users guides and technical information,
visit the Microchip web site at www.microchip.com/
analogtools. Three of our boards that are especially
useful are:
8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board,
P/N SOIC8EV
14-Pin SOIC/TSSOP/DIP Evaluation Board, P/N
SOIC14EV
5/6-Pin SOT23 Evaluation Board, P/N VSUPEV2
5.3 Application Notes
The following Microchip Application Notes are
available on the Microchip web site at
www.microchip.com and are recommended as
supplemental reference resources:
AN895, Oscillator Circuit For RTD Temperature
Sensors, DS00895.
http://www.microchip.com/%20mapshttp://www.microchip.com/%20mapshttp://www.microchip.com/%20mapshttp://www.microchip.com/%20mapshttp://www.microchip.com/%20mapshttp://www.microchip.com/%20mapshttp://www.microchip.com/%20mapshttp://www.microchip.com/%20mapshttp://www.microchip.com/%20mapshttp://www.microchip.com/%20mapshttp://www.microchip.com/%20mapshttp://www.microchip.com/analogtoolshttp://www.microchip.com/analogtoolshttp://www.microchip.com/analogtoolshttp://www.microchip.com/analogtoolshttp://www.microchip.com/analogtoolshttp://www.microchip.com/analogtoolshttp://www.microchip.com/analogtoolshttp://www.microchip.com/analogtoolshttp://www.microchip.com/http://www.microchip.com/http://www.microchip.com/http://www.microchip.com/http://www.microchip.com/http://www.microchip.com/analogtoolshttp://www.microchip.com/%20maps -
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6.0 PACKAGING INFORMATION
6.1 Package Marking Information
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week 01)
NNN Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn)
* This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3e
3e
5-Lead SC70 (MCP6566) Example:
XXNN
5-Lead SOT-23 (MCP6566, MCP6566R) Example:
XXNN JY25
BJ25
8-Lead SOIC (150 mil) (MCP6567) Example:
XXXXXXXX
XXXXYYWW
NNN
MCP6567ESN^^1040
256
3e
8-Lead MSOP (MCP6567) Example:
XXXXXX
YWWNNN
6567E
040256
Device Code
MCP6566T JYNN
MCP6566RT JZNN
MCP6566UT WLNN
Note: Applies to 5-Lead SOT-23.
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Package Marking Information (Continued)
14-Lead TSSOP (MCP6569)
XXXXXXXX
YYWWNNN
Example:
MCP6569E
1040256
14-Lead SOIC (150 mil) (MCP6569) Example:
XXXXXXXXXX
YYWWNNN
XXXXXXXXXXMCP6569
1040256E/SL^ 3e
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D
b
123
E1
E
4 5
e e
c
LA1
A A2
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Nb
E
E1
D
1 2 3
e
e1
A
A1
A2 c
L
L1
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Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
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D
N
E
E1
NOTE 1
1 2
e
b
A
A1
A2c
L1 L
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MCP6566/6R/6U/7/9
DS22143C-page 32 2011 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
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2011 Microchip Technology Inc. DS22143C-page 33
MCP6566/6R/6U/7/9
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
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MCP6566/6R/6U/7/9
DS22143C-page 34 2011 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
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2011 Microchip Technology Inc. DS22143C-page 35
MCP6566/6R/6U/7/9
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MCP6566/6R/6U/7/9
DS22143C-page 36 2011 Microchip Technology Inc.
NOTE 1
N
D
E
E1
1 2 3
b
e
A
A1
A2
L
L1
c
h
h
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2011 Microchip Technology Inc. DS22143C-page 37
MCP6566/6R/6U/7/9
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MCP6566/6R/6U/7/9
DS22143C-page 38 2011 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
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2011 Microchip Technology Inc. DS22143C-page 39
MCP6566/6R/6U/7/9
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
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MCP6566/6R/6U/7/9
DS22143C-page 40 2011 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
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2011 Microchip Technology Inc. DS22143C-page 41
MCP6566/6R/6U/7/9
APPENDIX A: REVISION HISTORY
Revision C (February 2011)
The following is the list of modifications:
1. Replaced the MCP5468 package name with the
correct MCP6567 package name on page 1 and
in Table 3-1.
Revision B (August 2009)
The following is the list of modifications:
1. Added MCP6566U throughout the document.
2. Updated package outline drawings.
Revision A (March 2009)
Original Release of this Document.
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MCP6566/6R/6U/7/9
DS22143C-page 42 2011 Microchip Technology Inc.
NOTES:
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2011 Microchip Technology Inc. DS22143C-page 43
MCP6566/6R/6U/7/9
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Device: MCP6566T: Single Comparator (Tape and Reel)(SC70, SOT-23)
MCP6566RT: Single Comparator (Tape and Reel)(SOT-23 only)
MCP6566UT: Single Comparator (Tape and Reel)(SOT-23 only)
MCP6567: Dual ComparatorMCP6567T: Dual Comparator (Tape and Reel)MCP6569: Quad ComparatorMCP6569T: Quad Comparator (Tape and Reel)
TemperatureRange:
E = -40C to +125C
Package: LT = Plastic Small Outline Transistor (SC70), 5-leadOT = Plastic Small Outline Transistor (SOT-23), 5-leadMS = Plastic Micro Small Outline Transistor, 8-leadSN = Plastic Small Outline Transistor, 8-leadST = Plastic Thin Shrink Small Outline Transistor, 14-leadSL = Plastic Small Outline Transistor, 14-lead
Examples:
a) MCP6566T-E/LT: Tape and Reel,Extended Temperature,5LD SC70 package.
b) MCP6566T-E/OT: Tape and ReelExtended Temperature,5LD SOT-23 package.
a) MCP6566RT-E/OT: Tape and ReelExtended Temperature,5LD SOT-23 package.
a) MCP6566UT-E/OT: Tape and ReelExtended Temperature,5LD SOT-23 package.
a) MCP6567-E/MS: Extended Temperature8LD MSOP package.
b) MCP6567-E/SN: Extended Temperature8LD SOIC package.
a) MCP6569T-E/SL: Tape and ReelExtended Temperature14LD SOIC package.
b) MCP6569T-E/ST: Tape and ReelExtended Temperature14LD TSSOP package.
PART NO. X /XX
PackageTemperatureRange
Device
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MCP6566/6R/6U/7/9
DS22143C-page 44 2011 Microchip Technology Inc.
NOTES:
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2011 Microchip Technology Inc. DS22143C-page 45
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyers risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQlogo, MPLAB, PIC, PICmicro, PICSTART,
PIC32logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit SerialProgramming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,
TSHARC, UniWinDriver, WiperLock and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
2011, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-60932-892-4
Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchips DataSheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as unbreakable.
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchips code protect ion feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2002 certification for its worldwideheadquarters, design and wafer fabrication facilities in Chandler andTempe, Arizona; Gresham, Oregon and design centers in Californiaand India. The Companys quality system processes and proceduresare for its PICMCUs and dsPICDSCs, KEELOQcode hoppingdevices, Serial EEPROMs, microperipherals, nonvolatile memory andanalog products. In addition, Microchips quality system for the designand manufacture of development systems is ISO 9001:2000 certified.
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