MC68020 32-Bit Microprocessor User's Manual

Introduction • Data Organization and • Addressing Capabilities

Instruction Set Summary • Signal Description •

Bus Operation • Processing States •

On·Chlp Cache Memory • Coprocessor Interface Description •

Instruction Execution Timing • Electrical Specifications •

Ordering Information and Mechanical Data • Condition Codes Computation •

Instruction Set • Instruction Format Survey •

Advanced Topics • MC68020 Extensions to M68000 Family •

® MOTOROLA

MC68020 32-BIT MICROPROCESSOR

USER'S MAN UAL

Second Edition

PRENTICE-HALL, Inc., Englewood Cliffs, N.J. 07632

© 1 985, 1 984 by Motorola Inc.

All rights reserved. No part of this book may be reproduced, in any form or by any means, without permission in writing from the publisher.

ISBN: 0-1 3-566860-3 (Prentice-Hall ed ition)

ISBN: 0-1 3-566878-6 (Motorola edition)

Thi s document contains information on a new product. S pec if icat ions and information herein are subject to change w ithout not ice. Motorol a reserves the right to m ake changes to any products herein to i m prove functioning or design. Although the informat ion in th i s document has been carefu l ly reviewed and i s bel ieved to be rel i able, Motorol a does not assume any l i ab i l ity ari sing out of the a p p l icat ion or use of any product or c ircuit described herein; neither does it convey any l icense under i ts patent rights nor the rights of others.

Motorola, Inc. general policy does not recommend the use of its components in life support applications where in a failure or malfunction of the component may directly threaten life or injury. Per Motorola Terms and Conditions of Sale, the user of Motorola components in li fe support applications assumes all risk of such use and indemnifies Motorola against all damages.

Printed in the United States of America

1 0 9 8 7

ISBN 0-13-566860-3 01 {PRENTICE-HALL ED.}

ISBN 0-13-566878-6 01 {MOTOROLA ED.}

Prentice-Hall International (UK) Limited, London Prentice-Hall of Australia Pty. Limited, Sydney Prentice-Hall Canada Inc., Toronto Prentice-Hall Hispanoamericana, SA, Mexico Prentice-Hall of India Private Limited, New Delhi Prentice-Hall of Japan, Inc., Tokyo Prentice-Hall Southeast Asia Pte. Ltd., Singapore Editora Prentice-Hall do Brasil, Ltda., Rio de Janeiro Whitehall Books Limited, Wellington, New Zealand

Paragraph Number

1 . 1 1 .2 1 .3 1 .3 . 1 1 .3.2 1 .4

2.1 2.2 2.2 . 1 2.2.2 2.2.3 2.3 2.4 2.5 2.6 2.7 2.8 2.8. 1 2.8. 1 . 1 2.8. 1 .2 2.8.2 2.8.2.1 2.8.2.2 2.8.2.3 2.8.2.4 2.8.3 2.8.3. 1 2.8.3.2 2.8.4 2.8.4. 1 2.8.4.2 2.8.5 2.8.6 2.8.6. 1

TABLE OF CONTENTS

Title

Section 1 Introduction

Data Types and Address ing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . I nstruct ion Set Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V i rtual Memory/Mach i ne Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . .

V i rtual Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V i rtual Mach i ne . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

P ipe l i ned Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Section 2 Data Organization and Addressing Capabil ities

Operand Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Organ izat ion i n Reg isters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address Reg isters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Data Organizat ion in Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I nstruction Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ProgramlData References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Registers: Notation Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Effective Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reg ister Di rect M odes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Register D i rect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address Register D i rect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Register I nd i rect Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address Register I nd i rect . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address Register Ind i rect with Post increment . . . . . . . . . . . Address Register I nd i rect with Predecrement . . . . . . . . . . . . Address Register Ind i rect with Displacement . . . . . . . . . . . .

Reg ister Ind i rect with I ndex M odes . . . . . . . . . . . . . . . . . . . . . . . . Address Register Ind i rect with I ndex (8-Bit Disp lacement) . Address Reg ister I nd i rect with I ndex (Base Disp lacement) .

Memory Ind i rect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Ind i rect Post-I ndexed . . . . . . . . . . . . . . . . . . . . . . . . . Memory I nd i rect Pre- I ndexed . . . . . . . . . . . . . . . . . . . . . . . . . .

Program Counter I nd i rect with Displacement Mode . . . . . . . . . . . Program Counter I nd i rect with I ndex Modes . . . . . . . . . . . . . . . . .

PC I ndirect with I ndex (8-Bit Displacement) . . . . . . . . . . . . . .

v

Page Number

1 -4 1 -5 1 -7 1 -7 1 -7 1 -8

2-1 2-1 2-1 2-2 2-2 2-2 2-4 2-5 2-5 2-5 2-6 2-6 2-6 2-7 2-7 2-7 2-7 2-8 2-8 2-8 2-9 2-9

2-1 0 2-1 1 2-1 2 2-1 3 2-1 3 2-1 4

Paragraph Number

2.8.6.2 2.8.7 2.8.7.1 2.8.7.2 2.8.8 2.8.8.1 2.8.8.2 2.8.9 2.9 2. 1 0 2 . 1 1 2 . 1 2

3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3 . 10

4 . 1 4.2 4.3 4.4 4.5 4.5. 1 4.5.2 4.5.3 4.5.4 4.5.5 4.5.6 4.5.7 4.5.8 4.6

TABLE OF CONTENTS (Continued)

Title

PC I nd i rect with I ndex (Base D isplacement) . . . . . . . . . . . . .

Program Counter Memory I nd i rect Modes . . . . . . . . . . . . . . . . . . .

Program Counter Memory I nd i rect Post· l ndexed . . . . . . . . .

Program Counter Memory I nd i rect Pre· l ndexed . . . . . . . . . . Absolute Address Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Absolute Short Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Absolute Long Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I mmediate Data: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Effective Address Encod i ng Summary . . . . . . . . . . . . . . . . . . . . . . . . . . System Stack . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .

User Program Stacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Section 3 Instruction Set Summary

Data Movement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I nteger Ar ithmetic Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Log ical Operat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Shift and Rotate Operat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Bit Man ipu lation Operat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Bit Field Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Binary Coded Decimal Operat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Program Control Operat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

System Control Operat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

M u lt i processor Operat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Section 4 Signal Description

Fu nction Code S ignals (FCO through FC2) . . . . . . . . . . . . . . . . . . . . . . .

Address Bus (AO through A31 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Data Bus (DO through 031 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Transfer Size (SilO, SIl1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Asynchronous Bus Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Cyc le Start (ECS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operand Cycle Start (OCS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Read·Mod i fy·Write Cyc le (RMC) . . . . . . . . . . . . . . . . . . . . . . . . . . .

Address Strobe (AS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Data Strobe (OS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Read/Write (RIW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Data Buffer Enable (DB EN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Data Transfer and Size Acknowledge (DSACKO, DSACK1) . . . . . .

Cache Disable (CDIS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

vi

Page Number

2·1 4 2·1 5 2·1 6 2·1 7 2·1 8 2·1 8 2·1 8 2·1 9 2·1 9 2·20 2·21 2·22

3·2 3·2 3·4 3·4 3·5 3·6 3·6 3·7 3·8 3·9

4·2 4·2 4·2 4·2 4·2 4·2 4·3 4·3 4·3 4·3 4·3 4·3 4·3 4·4

Paragraph Number

4.7 4.7. 1 4.7.2 4.7.3 4.8 4.8.1 4.8.2 4.8.3 4.9 4.9. 1 4.9.2 4.9.3 4 . 10 4.1 1

5 .1 5 .1 . 1 5 . 1 .2 5. 1 .3 5 . 1 .4 5.2 5.2. 1 5.2.2 5.2.3 5.2.4 5.2.4. 1 5.2.4. 1 . 1 5.2.4. 1 .2 5.2.4. 1 .3 5.2.4. 1 .4 5.2.4. 1 .5 5.2.4.2 5.2.4.3 5.2.5 5.2.5. 1 5.2.5.2 5.2.5.3 5.2.5.4 5.2.6 5.2.7


Title

I nterru pt Control S ignals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I nterru pt Priority level (I PlO, I Pl1 , I Pl2) . . . . . . . . . . . . . . . . . . . . I nterru pt Pending (I PEN D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Autovector (AVEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Bus Arbitration Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Request (BR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Grant (BG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus G rant Acknowledge (BGACK) . . . . . . . . . . . . . . . . . . . . . . . . . .

Bus Except ion Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset (RESET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Halt (HALT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Error (BERR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Clock (ClK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Section 5 Bus Operation

Operand Transfer Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dynamic Bus Siz ing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . M isa l ignment of Bus Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . Effects of Dynamic Bus Sizing and Operand M isal ignment . . . . . Address, Size, and Data Bus Relationships . . . . . . . . . . . . . . . . . .

Bus Operat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write Cyc le . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read-Modify-Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CPU Space Cyc les . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I nterrupt Operat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I nterrupt levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recognit ion of I nterrupts . . . . . . . . . .. . . . . . . . . . . . . . . I nterrupt Acknowledge Sequence (lACK) . . . . . . . . . . . . Spu rious I nterrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . lACK Generat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Breakpoint Acknowledge Cyc le . . . . . . . . . . . . . . . . . . . . . . . Coprocessor Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Bus Error and Halt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Error Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Retry Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . H alt Operat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Double Bus Fau lts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reset Operat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Arbitrat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

vii

Page Number

4-4 4-4 4-4 4-4 4-4 4-4 4-4 4-5 4-5 4-5 4-5 4-5 4-6 4-6

5-2 5-2

5-1 0 5-1 4 5-1 6 5-1 8 5-1 8 5-22 5-22 5-26 5-26 5-26 5-27 5-27 5-31 5-31 5-31 5-34 5-34 5-34 5-35 5-39 5-39 5-41 5-42

Paragraph Number

5.2.7.1 5.2.7.2 5.2.7.3 5.2.7.4 5.2.8 5.2.9 5.2.9.1 5.2.9.2

6.1 6. 1 . 1 6. 1 .2 6. 1 .3 6. 1 .4 6. 1 .5 6. 1 .6 6.2 6.2. 1 6.2.2 6.2.3 6.2.4 6.2.5 6.3 6.3. 1 6.3.2 6.3.3 6.3.4 6.3.5 6.3.6 6.3.7 6.3.8 6.3.9 6.3. 1 0 6.3. 1 1 6.4 6.4.1 6.4.2 6.4.2 . 1 6.4.2.2 6.5


Title

Request ing the Bus ........ . . . .. ........ . ..... ..... . . Receivi ng the Bus G rant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Acknowledgement of Mastership . . . . . . . . . . . . . . . . . . . . . . Bus Arbitrat ion Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

The Relat ionsh ip of DSACK, BERR, and HALT . . . . . . . . . . . . . . . Asynchronous versus Synchronous Operation . . . . . . . . . . . . . . .

Asynchronous Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronous Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Section 6 Processing States

Privi lege States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Use of Priv i lege States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Supervisor States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . User State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Change of Priv i lege State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address Space Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CPU Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Exception Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Except ion Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Exception Stack Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Exception Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Exception Processing Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . M u lt i ple Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Exception Process i ng: Deta i l . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I nstruction Traps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Format Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I l legal or Un implemented I nstructions . . . . . . . . . . . . . . . . . . . . . . Privi lege V iolat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Trac ing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I nterrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Return From Exception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Bus Fau l t Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Special Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Complet ing the Bus Cyc le(s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Complet ing the Bus Cycle(s) via Software . . . . . . . . . . . . . . . Complet ing the Bus Cycle(s) via RTE . . . . . . . . . . . . . . . . . . .

MC68020 Exception Stack Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

viii

Page Number

5-46 5-46 5-46 5-47 5-49 5-50 5-50 5-51

6-1 6-2 6-2 6-3 6-3 6-4 6-4 6-4 6-5 6-6 6-6 6-7 6-7 6-8 6-8 6-9 6-9

6-1 0 6-1 0 6-1 1 6-1 1 6-1 2 6-1 3 6-1 4 6-1 5 6-1 6 6-1 7 6-1 8 6-1 8 6-1 9 6- 1 9

Paragraph Number

6.5.1 6.5.2 6.5.3 6.5.4 6.5.5 6.5.6 6.5.7

7 . 1 7. 1 . 1 7. 1 .2 7 . 1 .2.1 7 . 1 .2.2 7.1 .2.3 7 . 1 .2.4 7.1 .2.5 7.2 7.3 7.4

8 . 1 8 .2 8.2. 1 8.2.2 8.2.3 8.2.4 8.2.4. 1 8.2.4.2 8.2.4.3 8.3 8.3.1 8.3. 1 . 1 8.3. 1 .2 8.3.2 8.3 .2 .1 8.3.2. 1 . 1 8.3.2. 1 .2


Title

Normal Four Word Stack Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . Throwaway Four Word Stack Frame . . . . . . . . . . . . . . . . . . . . . . . . N ormal S ix Word Stack Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . Coprocessor M id-I nstruction Except ion Stack Frame . . . . . . . . . Short Bus Cyc le Fault Stack Frame . . . . . . . . . . . . . . . . . . . . . . . . Long Bus Cyc le Fault Stack Frame . . . . . . . . . . . . . . . . . . . . . . . . . Stack Frame Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Section 7 On-Chip Cache Memory

Cache Des ign and Operat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-Ch ip Cache Organ izat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cache Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Cache Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E - Enable Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F - Freeze Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CE - Clear Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C - Clear Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Cache Address Reg ister . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cache D isable I nput . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cache I n it ia l ization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Section 8 Coprocessor Interface Description

I ntroduct ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC68000 Fami ly Coprocessor I nterface Overview . . . . . . . . . . . . . . . .

I nterface Featu res . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Concu rrent Coprocessor Operat ion Support . . . . . . . . . . . . . . . . . Coprocessor I nstruct ion Format . . . . . . . . . . . . . . . . . . . . . . . . . . . M68000 Coprocessor System I nterface . . . . . . . . . . . . . . . . . . . . .

M68000 Coprocessor Bus I nterface . . . . . . . . . . . . . . . . . . . . CPU Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Coprocessor I nterface Register (CI R) Select ion . . . . . . . . . .

Coprocessor I nstruct ion Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Coprocessor General I nstructions . . . . . . . . . . . . . . . . . . . . . . . . .

Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Cond it ional Coprocessor I nstructions . . . . . . . . . . . . . . . . . . . . . . Branch On Coprocessor Cond it ion I nstructions . . . . . . . . . .

Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ix

Page Number

6-20 6-20 6-20 6-21 6-22 6-23 6-24

7-1 7-1 7-2 7-2 7-3 7-3 7-3 7-3 7-3 7-4 7-4

8-1 8-2 8-2 8-3 8-3 8-4 8-4 8-4 8-5 8-7 8-8 8-8 8-9

8-1 0 8-1 0 8-1 0 8-12

Paragraph Number

8.3.2.2 8.3.2.2 . 1 8.3.2.2.2 8.3.2.3 8.3.2.3 .1 8.3.2.3.2 8.3.2.4 8.3.2.4. 1 8.3.2.4.2 8.3.3 8.3.3. 1 8.3.3. 1 . 1 8.3.3. 1 .2 8.3.3.2 8.3.3.2 . 1 8.3.3.2.2 8.3.3.3 8.3.3.4 8.3.3.4 . 1 8.3.3.4.2 8.3.3.4.3 8.3.3.4.4 8.4 8.4. 1 8.4.2 8.4.3 8.4.4 8.4.5 8.4.6 8.4.7 8.4.8 8.4.9 8.4. 1 0 8.4. 1 1 8.5 8.5. 1 8.5.2 8.6 8.6. 1 8.6. 1 . 1 8.6. 1 .2


Title

Set On Coprocessor Condit ion . . . . . . . . . . . . . . . . . . . . . . . . Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Test Coprocessor Condit ion, Decrement and Branch . . . . . Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Trap On Coprocessor Cond it ion . . . . . . . . . . . . . . . . . . . . . . . Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Coprocessor Context Save and Context Restore . . . . . . . . . . . . . Coprocessor Context Save . . . . . . . . . . . . . . . . . . . . . . . . . . .

Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Coprocessor Context Restore . . . . . . . . . . . . . . . . . . . . . . . . . Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Coprocessor I nternal State Frames . . . . . . . . . . . . . . . . . . . . Coprocessor Format Words . . . . . . . . . . . . . . . . . . . . . . . . . . .

Empty/Reset Format Word . . . . . . . . . . . . . . . . . . . . . . . .

Not Ready Format Word . . . . . . . . . . . . . . . . . . . . . . . . . . I nva l id Format Words . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Val id Format Words . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Coprocessor I nterface Reg ister (CI R) Set . . . . . . . . . . . . . . . . . . . . . . .

Response CIR ($00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control ($02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control C IR ($04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Restore C IR ($06) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operation Word C IR ($08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command CIR ($OA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cond it ion CIR ($OE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operand C IR ($1 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Register Select C IR ($1 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I nstruction Address C IR ($1 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operand Address C IR ($1 C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Coprocessor Response Pr imit ives I nt roduction . . . . . . . . . . . . . . . . . . Coprocessor Response Prim it ive Format . . . . . . . . . . . . . . . . . . . ScanPC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Coprocessor Response Prim i t ive Set Description . . . . . . . . . . . . . . . . Busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

x

Page Number

8·1 2 8·1 2 8·1 3 8·1 3 8·1 3 8·1 4 8·1 4 8·1 4 8·1 5 8·1 6 8·1 6 8· 1 6 8·1 7 8·1 8 8·1 8 8·1 9 8·20 8·21 8·21 8·22 8·22 8·23 8·23 8·23 8·23 8·24 8·24 8·24 8·24 8·24 8·24 8·25 8·25 8·25 8·25 8·26 8·27 8·27 8·28 8·28 8·28

Paragraph N umber

8.6.2 8.6.2. 1 8.6.2.2 8.6.3 8.6.3. 1 8.6.3.2 8.6.4 8.6.4. 1 8.6.4.2 8.6.5 8.6.5. 1 8.6.5.2 8.6.6 8.6.6. 1 8.6.6.2 8.6.7 8.6.7 . 1 8.6.7.2 8.6.8 8.6.8. 1 8.6.8.2 8.6.9 8.6.9. 1 8.6.9.2 8.6. 1 0 8.6. 1 0. 1 8.6. 1 0.2 8.6. 1 1 8.6. 1 1 . 1 8.6. 1 1 .2 8.6. 1 2 8.6. 1 2. 1 8.6. 1 2.2 8.6. 1 3 8.6. 1 3. 1 8.6. 1 3.2 8.6. 1 4 8.6. 1 4 . 1 8.6. 1 4.2 8.6. 1 5 8.6. 1 5. 1 8.6. 1 5.2


Title

N u l l (No Operands) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Supervisor Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Transfer Operat ion Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Transfer from I nstruction Stream . . . . . . . . . . . . . . . . . . . . . . . . . . Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Eval uate and Transfer Effective Address . . . . . . . . . . . . . . . . . . . . Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Eval uate Effective Address and Transfer Data . . . . . . . . . . . . . . . Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Write to Previously Eva luated Effective Address . . . . . . . . . . . . . Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Take Address and Transfer Data . . . . . . . . . . . . . . . . . . . . . . . . . . . Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Transfer To/From Top of Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Transfer S ing le Ma in Processor Reg ister . . . . . . . . . . . . . . . . . . . . Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Transfer Ma in Processor Control Reg ister . . . . . . . . . . . . . . . . . . . Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Transfer M u lt ip le Ma in Processor Reg isters . . . . . . . . . . . . . . . ' . . Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Transfer M u lt ip le Coprocessor Registers . . . . . . . . . . . . . . . . . . . Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Transfer Status Register and ScanPC . . . . . . . . . . . . . . . . . . . . . . Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

x i

Page N umber

8·29 8·29 8-29 8-30 8-30 8·31 8·31 8-31 8·31 8-31 8·31

. 8-32 8·32 8-32 8-32 8-33 8-33 8-34 8-35 8-35 8-35 8-36 8-36 8-37 8·37 8-37 8-37 8-38 8-38 8-38 8·38 8-38 8-39 8-39 8-39 8-39 8-40 8-40 8-40 8-41 8-42 8·42

Paragraph Number

8.6. 1 6 8.6. 1 6. 1 8.6. 1 6. 1 . 1 8.6. 1 6. 1 .2 8.6. 1 6.2 8.6. 1 6.2.1 8.6. 1 6.2.2 8.6. 1 6.3 8.6. 1 6.3 .1 8.6. 1 6.3.2 8.7 8.8 8.8 . 1 8.8. 1 . 1 8.8. 1 .2

8.8 .1 .3 8.8. 1 .4 8.8. 1 .5 8.8.2 8.8.2 . 1 8.8.2.2 8.8.2.3 8.8.2.4 8.8.2.5 8.8.2.6 8.8.2.7 8.8.2.8 8.8.3 8.9 8. 1 0

9.1 9.1 . 1 9. 1 .2 9. 1 .3 9. 1 .4 9. 1 .5 9.2 9.2.1


Title Page

Number

Ex cept ion Processing Request Pr imit ives . . . . . . . . . . . . . . . . . . . Take Pre-I nstruct ion Except ion . . . . . . . . . . . . . . . . . . . . . . . .

Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Take M id-I nstruct ion Ex cept ion . . . . . . . . . . . . . . . . . . . . . . . Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Take Post- I nstruct ion Ex cept ion . . . . . . . . . . . . . . . . . . . . . . . Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Coprocessor Classif icatons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Except ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Coprocessor Detected Ex cept ions . . . . . . . . . . . . . . . . . . . . . . . . . Coprocessor Detected Protocol Violations . . . . . . . . . . . . . . Coprocessor Detected I l legal Command or Cond it ion

Words . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . Coprocessor Data Processing Ex cept ions . . . . . . . . . . . . . . Coprocessor System Related Ex cept ions . . . . . . . . . . . . . . . Format Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Ma in Processor Detected Ex cept ions . . . . . . . . . . . . . . . . . . . . . . Protocol Vio lat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F-Li ne Emu lator Except ions . . . . . . . . . . . . . . . . . . . . . . . . . . Privi lege Violat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . cpTRAPcc I nstruction Traps . . . . . . . . . . . . . . . . . . . . . . . . . . Trace Except ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I nterru pts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address and Bus Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Ma in Processor Detected Format Errors . . . . . . . . . . . . . . . . . . . . Coprocessor Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Coprocessor I nstruction Format Summary . . . . . . . . . . . . . . . . . . . . . . Coprocessor Response Pr imit ive Format Summary . . . . . . . . . . .

Section 9 Instruction Execution Timing

Timing Estimation Factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I n struction Cache and Prefetch . . . . . . . . . . . . . . . . . . . . . . . . . . . Operand M isal ignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Concu rrency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overlap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I nstruction Stream Timing Exam ples . . . . . . . . . . . . . . . . . . . . . . .

I nstruction T iming Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fetch Effective Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

x i i

8-43 8-43 8-43 8-43 8-45 8-45 8-45 8-46 8-46 8-46 8-47 8-48 8-48 8-48

8-49 8-50 8-50 8-50 8-50 8-51 8-51 8-52 8-53 8-53 8-54 8-54 8-55 8-55 8-56 8-56

9-1 9-1 9-2 9-2 9-2 9-3 9-8

9-1 1

Paragraph Number

9.2.2 9.2.3 9.2.4 9.2.5 9.2.6 9.2.7 9.2.8 9.2.9 9.2. 1 0 9.2. 1 1 9.2. 1 2 9.2. 1 3 9.2. 1 4 9.2. 1 5 9.2. 1 6 9.2 . 1 7 9.2 . 1 8

1 0. 1 1 0.2 1 0.3 1 0.4 1 0.5 1 0.6 1 0.7

1 1 . 1 1 1 .2

TABLE OF CONTENTS (Concluded)

Title

Fetch I mmediate Effective Address . . . . . . . . . . ... . . ... . . . . . . Calcu late Effective Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Calcu late I mmediate Effective Address . . . . . . . . . . . . . . . . . . . . . Jump Effective Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MOVE I nstruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Special Pu rpose MOVE I nstruction . . . . . . . . . . . . . . . . . . . . . . . . . Ar ithmet ic/Log ical Operat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . I m mediate Arithmetic/Logical Operations . . . . . . . . . . . . . . . . . . . B i nary Coded Dec imal Operations . . . . . . . . . . . . . . . . . . . . . . . . . S ingle Operand I nstructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Shift/Rotate I nstruct ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bit Manipu lation I nstructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bit Field Manipu lation I nstructions . . . . . . . . . . . . . . . . . . . . . . . . Condit ional Branch I nstructions . . . . . . . . . . . . . . . . . . . . . . . . . . . Control I nstructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Except ion Related I nstructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . Save and Restore Operat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Section 10 Electrical Specifications

Max i mum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Characterist ics - PGA Package . . . . . . . . . . . . . . . . . . . . . . . Power Considerat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Electr ical Characteristics - Clock I nput . . . . . . . . . . . . . . . . . . . . . AC E lectrical Characterist ics - Read and Write Cyc les . . . . . . . . . . . AC E lectrical Characteristics - Typical Capacitance

Derat ing Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Section 1 1 Ordering Information and Mechanical Data

Standard MC68020 Ordering I nformat ion . . . . . . . . . . . . . . . . . . . . . . . Package Dimensions and P in Ass ignment . . . . . . . . . . . . . . . . . . . . . .

APPEN DICES

Page Number

9-1 1 9-1 3 9-1 3 9-1 5 9-1 5 9-21 9-22 9-22 9-23 9-24 9-24 9-25 9-26 9-26 9-27 9-28 9-28

1 0-1 1 0-1 1 0-1 1 0-2 1 0-3 1 0-4

1 0-6

1 1 -1 1 1 -2

A Condition Codes Computat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 B I nstruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1 C I nstruction Format Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-1 D Advanced Topics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-1 E M C68020 Extensions to M68000 Fami ly . . . . . . . . . . . . . . . . . . . . . . . . . E-1

x i i i

LIST OF ILLUSTRATIONS

Figure Page Number Title Number

1 -1 MC68020 B lock Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 -2 1 -2 User Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 -3 1 -3 Supervisor Programming Model Supplement . . . . . . . . . . . . . . . . . . . . 1 -3 1 -4 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 -4 1 -5 MC68020 Pipe l i ne . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 -9

2-1 Memory Operand Address ing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2-2 Memory Data Organizat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2-3 I nstruction Word General Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2-4 Sing le-Effect ive-Address I nstruction Operat ion Word . . . . . . . . . . . . . 2-6

4-1 Fu nctional Signal G roups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

5-1 Relationship Between External and I nternal Signals . . . . . . . . . . . . . . 5-1 5-2 Sample Wi ndow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5-3 MC68020 I nterface to Various Port Sizes . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5-4 I nternal Operand Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 5-5 Example of Long Word Transfer to Word Bus . . . . . . . . . . . . . . . . . . . . 5-6 5-6 Long Word Operand Write Timing ( 16- B it Data Port) . . . . . . . . . . . . . . . 5-7 5-7 Example of Long Word Transfer to Byte Bus . . . . . . . . . . . . . . . . . . . . . 5-8 5-8 Long Word Operand Write Timing (8-Bit Data Port) . . . . . . . . . . . . . . . . 5-9 5-9 M isal igned Long Word Transfer to Word Bus Example . . . . . . . . . . . . 5-1 0 5-1 0 M isal igned Long Word Transfer t o Word Bus . . . . . . . . . . . . . . . . . . . . 5-1 1 5-1 1 Example of M isal igned Word Transfer to Word Bus . . . . . . . . . . . . . . . 5-1 2 5-1 2 M isal igned Word Transfer t o Word Bus . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 3 5-1 3 M isal igned Long Word Transfer t o Long Word Bus . . . . . . . . . . . . . . . . 5-1 4 5-1 4 M isal igned Write Cycles to 32-Bit Data Port . . . . . . . . . . . . . . . . . . . . . 5-1 5 5-1 5 Byte Data Select Generat ion for 1 6- and 32-Bit Ports . . . . . . . . . . . . . . 5-1 7 5-1 6 Long Word Read Cycle Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 8 5-1 7 Long-Word Read Cycle Timing (32-Bit Data Port) . . . . . . . . . . . . . . . . . 5-1 9 5-1 8 Byte Read Cyc le Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20 5-1 9 Byte and Word Read Cycle Timing (32-Bit Data Port) . . . . . . . . . . . . . . 5-21 5-20 Write Cyc le Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22 5-21 Byte and Word Write Cycle Timing (32-Bit Data Port) . . . . . . . . . . . . . . 5-23 5-22 Read-Modify-Write Cyc le Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24 5-23 Read-Modify-Write Cyc le Timing (32-Bit Port, CAS I nstruction) . . . . . . 5-25 5-24 MC68020 CPU-Space Address Encoding . . . . . . . . . . . . . . . . . . . . . . . . 5-26 5-25 I nterrupt Acknowledge Sequence Flowchart . . . . . . . . . . . . . . . . . . . . . 5-28

xiv

LIST OF ILLUSTRATIONS (Continued)

Figure Page Number Title Number

5-26 I nterrupt Acknowledge Cyc le Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29 5-27 Autovector Operat ion Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-30 5-28 M C68020 Breakpoint Operat ion Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-31 5-29 Breakpo int Acknowledge Cyc le T iming (Opcode Returned) . . . . . . . . . 5-32 5-30 Breakpo int Acknowledge Cyc le T iming (Exception S ignal led) . . . . . . 5-33 5-31 Bus Error Timing (Exception Taken) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-35 5-32 Delayed Bus Error (Ex ception Taken) . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-36 5-33 Delayed Bus Cyc le Retry T im ing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-37 5-34 Retry Operat ion Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-38 5-35 H alt Operation T iming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-40 5-36 External Reset Operat ion T iming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-41 5-37 Processor Generated Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . 5-43 5-38 Bus Arbitration F lowchart for S ing le Request . . . . . . . . . . . . . . . . . . . . 5-44 5-39 Bus Arbitration Operat ion T iming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-45 5-40 Bus Arbitrat ion State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-47 5-41 Bus Arbitrat ion (Bus I nactive) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-48

6-1 Exception Stack Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6 6-2 Spec ial Status Word (SSW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 7 6-3 Format $0 - Four Word Stack Frame . . . . . . . . . . . . . . . . . . . . . . . . . . 6-20 6-4 Format $1 - Throwaway Four Word Stack Frame . . . . . . . . . . . . . . . . 6-20 6-5 Format $2 - Six Word Stack Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21 6-6 Format $9 - Coprocessor M id-Instruction Except ion

Stack Frame (1 0 Words) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21 6-7 Format $A - Short Bus Cyc le Fau lt Stack Frame (1 6 Words) . . . . . . . 6-22 6-8 Format $B - Long Bus Cyc le Fau l t Stack Frame (46 Words) . . . . . . . 6-23 6-9 Stack Frame Format Def in it ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24

7-1 MC68020 On-Ch ip Cache Organ izat ion . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 7-2 Cache Control Reg ister . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 7-3 Cache Address Reg ister . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3

8-1 F-L ine Coprocessor I nstruction Operation Word . . . . . . . . . . . . . . . . . 8-3 8-2 MC68020 CPU Space Address Encodi ngs . . . . . . . 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8-5 8-3 Coprocessor I nterface Reg ister Set Map 0 0 0 0 0 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 0 0 8-6 8-4 Coprocessor Address Map i n MC68020 CPU Space 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 8-6 8-5 M68000 Coprocessor I nterface Signal Usage 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8-7 8-6 Coprocessor General I nstruction Format (cpG EN) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8-8 8-7 Coprocessor I nterface Protocol for General Category I nstructions 0 0 8-9 8-8 Coprocessor I nterface Protocol for Condit ional Category

I nstruct ions 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 • 0 0 0 0 8-1 1 8-9 Branch on Coprocessor Cond it ion I nstruct ion (cpBccoW) 0 0 0 0 0 0 0 0 • 0 8-1 1 8-1 0 Branch on Coprocessor Condit ion I nstruction (cpBccoL) 0 0 0 0 0 0 0 0 0 0 0 8-1 1

xv

Figure Number

8-1 1 8- 1 2

8- 1 3 8- 1 4 8- 1 5 8-1 6 8- 1 7 8-1 8 8- 1 9 8-20 8-21 8-22 8-23 8-24 8-25 8-26 8-27 8-28 8-29 8-30 8-31 8-32 8-33 8-34 8-35 8-36 8-37 8-38 8-39 8-40 8-41 8-42 8-43 8-44 8-45 8-46

9-1 9-2 9-3

LIST OF ILLUSTRATIONS (Continued)

Page Title Number

Set on Coprocessor Cond it ion (cpScc) . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12 Test Coprocessor Condit ion, Decrement and Branch I nstruct ion

Format (cpDBcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 3 Trap o n Coprocessor Condit ion (cpTRAPcc) . . . . . . . . . . . . . . . . . . . . . 8-1 5 Coprocessor Context Save Instruction Format (cpSAVE) . . . . . . . . . . 8-1 6 Coprocessor Context Save I nstruct ion Protocol . . . . . . . . . . . . . . . . . . 8-1 7 Coprocessor Context Restore I nstruct ion Format (cpRESTORE) . . . . 8-1 8 Coprocessor Context Restore I nstruct ion Protocol . . . . . . . . . . . . . . . 8-1 9 Coprocessor State Frame Format in Memory . . . . . . . . . . . . . . . . . . . . 8-20 Control C IR Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . _ . . . . . . 8-23 Cond it ion C IR Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-24 Operand A l ignment for Operand CIR Accesses . . . . . . . . . . . . . . . . . . 8-25 Coprocessor Response Pr imit ive Format . . . . . . . . . . . . . . . . _ . . . . . . 8-26 Busy Pri mit ive Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . _ . . . . . . 8-28 N u l l Pri mit ive Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-29 Supervisor Check Pr imit ive Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-30 Transfer Operat ion Word Pr imit ive Format . . . . . . . . . . . . . . . . . . . . . . 8-31 Transfer From I nstruct ion Stream Prim it ive Format . . . . . . . . . . . . . . . 8-32 Eval uate and Transfer Effective Address Pr imit ive Format . . . . . . . . . 8-32 Eval uate Effect ive Add ress and Transfer Data Prim it ive Format . . . . 8-33 Write to Previously Eva luated Effect ive Address Pr imit ive Format . . . 8-35 Take Address and Transfer Data Pr imit ive Format . . . . . . . . . . . . . . . . 8-36 Transfer S ing le Top of Stack Pr imit ive Format . . . . . . . . . . . . . . . . . . . 8-37 Transfer Main Processor Reg ister Pr imit ive Format . . . . . . . . . . . . . . . 8-38 Transfer Main Processor Control Reg ister Pr imit ive Format . . . . . . . . 8-38 Transfer M u lt i ple Ma in Processor Reg isters Pr imit ive Format . . . . . . 8-39 Reg ister Select Mask Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-40 Transfer M u lt iple Coprocessor Reg isters Primit ive Format . . . . . . . . . 8-40 Operand Format Transfer M u lt iple Coprocessor Reg isters to - (An) . 8-41 Transfer Status Reg ister and Scan PC Pr imit ive Format . . . . . . . . . . . 8-42 Pre-I nstruct ion Except ion Primit ive Format . . . . . . . . . . . . . . . . . . . . . . 8-43 MC68020 Pre-I nstruction Stack Frame . . . . . . . . . . . . . . . . . . . . . . . . . . 8-44 Take M id-I nstruction Except ion Pr imit ive Format . . . . . . . . . . . . . . . . . 8-45 MC68020 M id-I nstruction Stack Frame . . . . . . . . . . . . . . . . . . . . . . . . . 8-45 Take Post-I nstruct ion Ex cept ion Pr imit ive Format . . . . . . . . . _ . . . . . . 8-46 MC68020 Post- I nstruction Stack Frame . . . . . . . . . . . . . . . . . . _ . . . . . . 8-46 Coprocessor I nstruct ion Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-56

S imu ltaneous I nstruction Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 I nstruction Execut ion for I nstruct ion Timing Purposes . . . . . . . . . . . . 9-3 Processor Activity for Example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4

xvi

Figure Number

9-4 9-5 9-6

LIST OF ILLUSTRATIONS (Concluded)

Title

Processor Activity for Example 2 Processor Activity for Example 3 Processor Activity for Example 4

Page Number

9-6 9-6 9-7

1 0- 1 RESET Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0-2 1 0-2 HALT Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0-2 1 0-3 Test Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0-3 1 0-4 Clock I nput T im ing D iagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0-3 1 0-5 Read Cyc le T iming Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Foldout

1 1 0-6 Write Cyc le T iming Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Foldout

2 1 0-7 Bus Arbitrat ion T iming Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Foldout

3 1 0-8 Address Capac itance Derat ing Curve . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0-6 1 0-9 OS, AS, I PE N D, and BG Capac i tance Derat ing Curve . . . . . . . . . . . . . . 1 0-6 1 0-1 0 DBEN Capacitance Derat ing Cu rve . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0-7 1 0-1 1 ECS and OCS Capacitance Derat ing Curve . . . . . . . . . . . . . . . . . . . . . . 1 0-7 1 0- 12 R/W, FC, SIZO-SIZ1 , and RMC Capac itance Derat ing Curve . . . . . . . . . 1 0-8 1 0-1 3 Data Capacitance Derat ing Curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0-8

xvii

LIST OF TABLES

Table Page Number Title Number

1 -1 Addressing M odes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 -5 1 -2 I nstruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 -6

2-1 Effective Address Specif ication Formats . . . . . . . . . . . . . . . . . . . . . . . 2-1 9 2-2 I S- Il lS Memory I nd i rection Encodings . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 2-3 Effective Address Encoding Summary . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20

3-1 Data M ovement Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3-2 I nteger Arithmetic Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3-3 Logical Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3-4 Shift and Rotate Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3-5 Bit Manipulation Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3-6 Bit Field Operat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3-7 B inary Coded Decimal Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3-8 Program Control Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3-9 System Control Operat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3-1 0 M ultiprocessor Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9

4-1 Fu nction Code Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4-2 Signal Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6

5-1 SIZE Output Encod ings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 5-2 Address Offset Encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 5-3 MC68020 I nternal to External Data Bus M u lt ip lexor . . . . . . . . . . . . . . . 5-5 5-4 DSACK Codes and Resu lts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 5-5 Memory Al ignment and Port Size Inf luence on Bus Cyc les . . . . . . . . . 5-1 4 5-6 Data Bus Activity for Byte, Word, and Long Word Ports . . . . . . . . . . . . 5-1 6 5-7 I nterrupt Control Line Status for Each Requested I nterrupt Level

=�a� nd Corresponding I nterru pt Mask Levels . . . . . . . . . . . . . . . . . . . 5-27 5-8 DSACK, BERR, and HALT Assertion Resu lts . . . . . . . . . . . . . . . . . . . . . 5-49

6-1 Address Space Encod ings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 6-2 Exception Vector Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 6-3 Exception Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8 6-4 Privi leged I nstructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 2 6-5 Tracing Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 3

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LIST OF TABLES (Concluded)

Table Page Number Title Number

8-1 cpTRAPcc Opmode Encod ings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 5 8-2 Coprocessor Format Word Encodings . . . . . . . . . . . . . . . . . . . . . . . . . . 8-21 8-3 N u l l Coprocessor Response Primitive Encod i ngs . . . . . . . . . . . . . . . . . 8-30 8-4 Valid Effective Address Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-33 8-5 Main Processor Control Reg ister Selector Codes . . . . . . . . . . . . . . . . . 8-39 8-6 Exceptions Related to Primitive Processing . . . . . . . . . . . . . . . . . . . . . 8-52

9-1 Example I nstruction Stream Execution Comparison . . . . . . . . . . . . . . 9-8 9-2 I nstruction Timings for Timing Tables . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 0 9-3 Observed Instruction Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 0

xix/xx

SECTION 1 I NTRODUCTION

The MC68020 is the first fu l l 32-bit implementation of the M68000 Family of microprocessors from Motorola. Using VLSI technology, the MC68020 is implemented with 32-bit registers and data paths, 32-bit addresses, a rich instruction set, and versatile addressing modes.

The MC68020 is object code compatible with the earlier members of the M68000 Family and has the added featu res of new addressing modes in su pport of h igh level languages, an on-chip instruction cache, and a flexible coprocessor i nterface with fu l l I EEE f loatingpoint support (the MC68881) . A lso, the internal operations of this microprocessor are designed to operate in paral le l , a l lowing mult iple instructions to be executed concurrent ly. The execution time of an instruction can be completely absorbed by the execution time of surrounding instructions for a net execution time of zero c lock periods.

The asynchronous bus structure of the MC68020 utilizes a non-mult ip lexed bus with 32 bits of address and 32 bits of data. The processor supports a dynamic bus sizing mechanism that a l lows the processor to transfer operands to or from external devices while automatical ly determin ing device port size on a cyc le-by-cycle basis. The dynamic bus interface al lows for s imple, high ly effic ient access to devices of differing data bus widths, in addition to eliminating all data al ig nment restrictions.

The resources available to the MC68020 user consist of the fol lowing: • Virtual Memory/Machine Su pport • Sixteen 32-Bit General-Purpose Data and Address Registers • Two 32-Bit Supervisor Stack Pointers • 32-Bit Program Counter • Five Special Pu rpose Control Registers • 4 Gigabyte Direct Addressing Range • Two Processor Speeds: 12 and 16 M Hz • 1 8 Addressing Modes • Memory Mapped I/O • Coprocessor I nterface • H igh Performance On-Chip I nstruction Cache • 32-Bit Upgraded and New I nstructions • Operations on Seven Data Types • Complete Floating-Point Su pport via the MC68881 Coprocessor

A block diagram of the MC68020 is shown in Figure 1 - 1 . The major blocks depicted operate in a high ly i ndependent fashion that maximizes concu rrency of operation while managing the essential synchronizat ion of instruction execution and bus operation.

1 -1

•

Address Bus

Sequencer

Control Unit

Execution Unit

Instruction Prefetch and

Decode

Controller

I nstruction Cache

Figure 1 · 1 . MC68020 Block Diagram

Bus Control

Data Bus

The bus contro l ler loads instructions from the data bus into the decode unit and the onchip cache. The sequencer and control unit provide overal l chip control, managing the internal buses, registers, and functions of the execution unit.

As shown in the programming models (Figures 1 -2 and 1 -3), the MC68020 has 16 32·bit general-purpose registers, a 32-bit program counter, a 1 6·bit status register, a 32-bit vector base register, two 3·bit a lternate function code registers, and two 32·bit cache handling (address and control) registers. Registers 00-07 are used as data registers for bit and bit field (1 to 32 bits), byte (8-bit), word (1 6-bit), long word (32-bit), and quad word (64-bit) operations. Registers AO-A6 and the user, interru pt, and master stack pOinters are address registers that may be used as software stack pointers or base address registers. I n addition, the address registers may be used for word and long word operations. A l l of the 16 (00-07, AO·A7) registers may be used as index registers.

The vector base register is used to determine the location of the exception vector table in memory to support multiple vector tables. The alternate function code registers al low the supervisor to access any address space.

The cache registers (control - CACR; address - CAAR) al low software manipulation of the on-chip instruction cache. Control and status accesses to the instruction cache are provided by the cache control register (CACR), while the cache address register (CAAR) holds the address for cache control functions when required.

The status register (Figure 1 ·4) contains the interru pt priority mask (three bits) as wel l as the condition codes: extend (X), negative (N), zero (Z), overflow (V), and carry (C). Additional control bits indicate that the processor is in the trace mode (T1 and TO), supervisor/user state (8), and master/interrupt state (M).

1 -2

31 16 15 8 7 0 DO D1 D2 D3

Data Registers D4

D5 D6

D7

31 16 15 0 AO A1 A2 A3 Address Registers

A4 A5 A6

31 16 15 0 I A7 IUSP) User Stack Pointer

31 0

I PC 0

I CCR 15 7

� = ��>_ = _'r" ----..:, Figure 1 ·2. User Programming Model

31 1 6 1 5 0

Program Counter

Condition Code Register

LI ____________ ---II ____________ ---.JI A7' liSP) Interrupt Stack Pointer

31 16 15 0

LI ____________ ---I ____________ ---.JI A7" IMSP) Master Stack Pointer

31

31 r I- - - -

L. _

31

31

15 87 0

I ICCR) I SR Status Register

0 I VBR Vector Base Register

2 0 = a SFC Alternate Function

DFC Code Registers

0

I CACR Cache Control Register

0 I CAAR Cache Address Register

Figure 1 ·3. Supervisor Programming Model Supplement

1 ·3

•

• System Byte

User Byte (Condition Code Register)

��----------�--------��---�---------------------�-15 14 13 1 2 1 1 10 9 8 6 5 4 3 2

Supervisor/User State

Masterllnterrupt State

Figure 1 ·4. Status Register

1 .1 DATA TYPES AND ADDRESSING MODES

Seven basic data types are su pported. These data types are: • Bits • Bit Fields (Field of consecutive bits, 1 ·32 bits long) • BCD Digits (Packed: 2 dig its/byte, Unpacked: 1 digit/byte) • Byte I ntegers (8 bits) • Word I ntegers (1 6 bits) • Long Word Integers (32 bits) • Quad Word Integers (64 bits)

Zero

Overflow

o

Carry

In addition, operations on other data types such as memory addresses, status word data, etc., are supported in the instruction set. The coprocessor mechanism a l lows direct support of f loating-point operat ions with the MC68881 f loating-point coprocessor, as wel l as specia l ized user-defined data types and functions.

The 18 addressing modes, shown in Table 1 · 1 , inc lude nine basic types: • Register Di rect • Register I ndirect • Register I nd i rect with I ndex • Memory I nd i rect • Program Counter I ndirect with Disp lacement • Program Counter I ndirect with I ndex • Program Counter Memory I ndirect • Absolute • Immediate

I ncl uded in the register indirect addressing modes are the capabilities to postincrement, predecrement, offset, and index. The program counter re lative mode also has index and offset capabi l it ies. Both modes are extended in the MC68020 to provide indirect reference through memory. I n addition to these addressing modes, many instructions impl icit ly specify the use of the condition code register, stack pointer, and/or program counter.

1 -4

Table 1 -1 . Addressing Modes

Addressing Modes Syntax Register Direct Data Register Direct Dn Address Register Direct An

Register Indi rect Address Register I ndirect IAnl Address Register Indirect with Postincrement IAnl + Address Register Indirect with Predecrement - IAnl Address Register I ndirect with Displacement Id 16,Anl

Register Indirect with Index Address Register Indirect with I ndex IS-Bit Displacementl Ids,An,Xnl Address Register Indirect with Index I Base Displacement! I bd,An,Xnl

Memory Indirect Memory Indirect Post-Indexed II bd,Anl.Xn,odl Memory Indi rect Pre-Indexed I lbd,An,Xnl.odl

Program Counter Indirect with Displacement Id16, PCI Program Counter Indirect with Index PC Indirect with Index IS-Bit Displacementl Ids, PC,Xnl PC I ndirect with Index I Base Displacement! Ibd,PC,Xnl

Program Counter Memory Indirect PC Memory Indirect Post-Indexed I lbd, PCI .Xn,odl PC Memory Indirect Pre-I ndexed I lbd ,PC,Xnl .odl

Absolute Absolute Short Ixxxl .W Absolute Long Ixxxi . L

Immediate #< data > NOTES:

Dn = Data Register, DO-D7 An = Address Register, AO-A7

dS, d16 = A twos-complement. or sign-extended displacement; added as part of the effective address calculation; size is S or 16 bits Id16 and dS are 1 6- and S-bit displacementsl; when omitted, assemblers use a value of zero.

Xn = Address or data register used as an index register; form is Xn .S IZE* SCALE, where SIZE is .W or . L lindicates index register sizel and SCALE is 1 , 2, 4, or S l index register is multiplied by SCALEI ; use of SIZE and/or SCALE is optional.

bd = A twos-complement base displacement; when present, size can be 16 or 32 bits., ad = Outer displacement, added as part of effective address calculation after any memory indirection; use is optional with a size

of 16 or 32 bits. PC = Program Counter

< data> = Immediate value of 8, 16, or 32 bits I I = Effective address I I = Use as indirect address to long word address.

1 .2 INSTRUCTION SET OVERVIEW

The MC68020 instruction set is shown i n Table 1 -2. Special emphasis has been placed on the instruction support of structured h igh-leve l languages and sophisticated operating systems, Each instruction, with few exceptions, operates on bytes, words, and long words and most instructions can use any of the 18 addressing modes.

1 -5

•

• Table 1 ·2. Instruction Set Summary

Mnemonic Description Mnemonic Description

ABCD Add Decimal with Extend MULS Signed Multiply ADD Add MULU Unsigned Multiply ADDA Add Address NBCD Negate Decimal with Extend ADDI Add Immediate NEG Negate ADDQ Add Quick NEGX Negate with Extend ADDX Add with Extend NOP No Operation AND Logical AND NOT Logical Complement ANDI Logical AND Immediate ASL, ASR Arithmetic Sh i f t Left and Right OR Logical Inclusive OR

Bcc Branch Conditionally ORI Logical Inclusive OR Immediate

BCHG Test Bit and Change PACK Pack BCD BClR Test Bit and Clear PEA Push Effective Address BFCHG Test Bit Field and Change RESET Reset External Devices B FCLR Test Bit Field and Clear ROL, ROR Rotate Left and Right BFEXTS Signed Bit Field Extract ROXL, ROXR Rotate with Extend Left and Right B FEXTU Unsigned Bit Field Extract RTD Return and Deallocate BFFFO Bit Field Find First One RTE Return from Exception BF INS Bit Field Insert RTM Return from Module BFSET Test Bit Field and Set RTR Return and Restore Codes BFTST Test Bit Field RTS Return from Subroutine BKPT Breakpoint SBCD Subtract Decimal with Extend BRA Branch Scc Set Conditionally BSET Test Bit and Set STOP Stop BSR Branch to Subroutine SUB Subtract BTST Test Bit SUBA Subtract Address CALLM Cal l Module SUB I Subtract Immediate CAS Compare and Swap Operands SUBQ Subtract Quick CAS2 Compare and Swap Dual Operands SUBX Subtract with Extend CHK Check Register Against Bound SWAP Swap Register Words CHK2 Check Register Against Upper and TAS Test Operand and Set

Lower Bounds TRAP Trap CLR Clear TRAPcc Trap Conditionally CMP Compare TRAPV Trap on Overflow CMPA Compare Address TST Test Operand CMPI Compare Immediate UNLK Unlink CMPM Compare Memory to Memory UNPK Unpack BCD CMP2 Compare Register Against Upper and

Lower Bounds COPROCESSOR INSTRUCTIONS

DBcc Test Condition, Decrement and Branch cpBcc Branch Conditionally DIVS, DIVSL Signed Divide cpDBcc Test Coprocessor Condition, DIVU, DIVUL Unsigned Divide Decrement, and Branch EOR Logical Exclusive OR cpGEN Coprocessor General Instruction EORI logical Exclusive OR Immediate cpRESTORE Restore Internal State of Coprocessor EXG Exchange Registers cpS AVE Save Internal State of Coprocessor EXT,EXTB Sign Extend cpScc Set Conditionally

cpTRAPcc Trap Conditionally I LLEGAL Take I l legal Instruction Trap JMP Jump JSR Jump to Subroutine LEA Load Effective Address LINK Link and Allocate LSL, LSR Logical Shift Left and Right MOVE Move MOVEA Move Address MOVE CCR Move Condition Code Register MOVE SR Move Status Register MOVE USP Move User S tack Pointer MOVEC Move Control Register MOVEM Move Mu ltiple Registers MOVEP Move Peripheral MOVEO Move Qui«k MOVES Move Alternate Address Space

1 ·6

1 .3 VI RTUAL M EMORY/MACHINE CONCEPTS

The fu l l addressing range of the MC68020 is 4 gigabytes (4,294,967,296). However, most MC68020 systems implement a smaller physical memory. Nonetheless, by using virtual memory techniques, the system can be made to appear to have a fu l l 4 g igabytes of physical memory avai lable to each user program. These techniques have been used for many years in large mainframe computers and more recently in min icomputers. With the M C68020 (as with the MC6801 0 and MC6801 2), virtual memory can be fu l ly supported in microprocessor·based systems.

In a virtual memory system, a user program can be written as though it has a large amount of memory avai lable to it when actual ly, on ly a smal ler amount of memory is physical ly present i n the system. In a s imi lar fashion, a system can be designed i n such a manner as to al low user programs to access other types of devices that are not physi· cally present in the system such as tape drives, d isk drives, printers, or term inals. With proper software emu lation, a physical system can be made to appear to a user program as any other M68000 computer system and the program may be g iven fu l l access to a l l of the resources of that emulated system. Such an emu lated system is cal led a virtual machine.

1 .3.1 Virtual Memory

The basic mechanism for support ing virtual memory is to provide a l imited amount of h igh·speed physical memory that can be accessed d i rect ly by the processor whi le main· tain ing an image of a much larger "virtual" memory on secondary storage devices such as large capacity disk drives. When the processor attempts to access a location in the virtual memory map that is not res ident in physical memory (referred to as a page fau lt), the access to that location is temporari ly suspended whi le the necessary data is fetched from secondary storage and placed in physical memory; the suspended access is then either restarted or continued.

The MC68020 uses i nstruction cont inuation to support virtual memory. In order for the MC68020 to use instruction cont inuation, it stores its internal state on the su pervisor stack when a bus cycle is terminated with a bus error s ignal . It then loads the program counter with the address of the virtual memory bus error hand ler from the except ion vec· tor table (entry number two) and resumes program execution at that new address. When the bus error exception handler rout ine has completed execution, an RTE instruction is executed which reloads the MC68020 with the internal state stored on the stack, re·ru ns the fau lted bus cycle (when requ i red), and cont inues the suspended instruction.

I nstruction cont inuation is crucial to the support of virtual I/O devices in memory· mapped input/output systems. Si nce virtual reg isters may be s imu lated in the memory map, an access to such a reg ister w i l l cause a fault and the fu nction of the register can be emulated by software.

1 .3.2 Virtual Machine

A typical use for a virtual mach ine system is the development of software, such as an operat ing system, for a new mach ine also under development and not yet avai lable for programming use. In such a system, a govern ing operating system emulates the hard· ware of the prototyped system and al lows the new operating system to be executed and

1 ·7

•

debugged as though it were running on the new hardware. Since the new operating system is control led by the governing operating system, it is executed at a lower privilege level than the governing operating system. Thus, any attempts by the new operating system to use virtual resources that are not physical ly present (and should be emulated) are t rapped to the governing operating system and hand led by its software. I n the MC68020, a virtual machine is fu l ly supported by ru nning the new operating system in the user mode. The governing operating system executes in the supervisor mode and any attempt by the new operating system to access supervisor resources or execute privileged instructions wil l cause a t rap to the governing operating system.

In order to fu l ly support a virtual machine, the MC68020 must protect the supervisor resources from access by user programs. The on ly supervisor resource that is not fu l ly protected on the MC68000 and MC68008 is the system byte of the status register. On the MC68000 and MC68008, the MOVE from SR instruction al lows user programs to test the S bit in the status register (in addition to the T bits and interru pt mask) and thus determine that they are ru nning in the user mode. For fu l l virtual machine su pport, an operating system must not be aware of the fact that it is running in the less privileged user mode and thus should not be al lowed direct access to the S bit. For this reason, the MOVE from SR instruction on the MC68010, MC6801 2, and MC68020 is a privileged instruction and the MOVE from CCR (condition code register) instruction is available to a l low user prog rams direct access to the condition codes. By making the MOVE from SR instruction privileged, when the new operating system attempts to access the system byte of the status register, a t rap to the governing operating system wi l l occur, where the operation can be emu lated.

1 _4 PIPELINED ARCHITECTU RE

The MC68020 uses a three stage instruction pipe, as shown in Figure 1 -5, to implement a pipelined internal architecture. The pipeline is completely internal to the microprocessor. The benefit of the pipeline is to al low concurrent operations to occur for up to three words of a single instruction or for up to three consecutive instructions.

I nstructions are loaded from the on-chip cache or f rom external memory du ring instruction prefetch into stage B. The instructions are sequenced from stage B through stage C to D. Stage 0 presents a fu l ly decoded and val idated instruction to the control unit for execution. I nstructions with immediate data and extension words find these words a l ready loaded in stage C and ready for use by the control and execution units.

1 -8

Sequencer

Control Unit

Execution Unit

I I Stage

I D

I L - - -

Instruction Fetch and Decode

-

Stage

- - -

C

- - -

Figure 1 ·5. MC68020 Pipeline

1 ·9/1 · 10

- - - .., I I

Stage B I

I - 1- - J

Instru Flow f

ction rom and ory

Cache Mem

SECTION 2 DATA ORGAN IZATION AND ADDRESSING CAPABIL ITI ES

This section contains a description of the registers and the data organization of the MC68020.

2.1 OPERAN D SIZE

Operand sizes are defined as fol lows: a byte equals 8 bits, a word equals 16 bits, a long word equals 32 bits, and a quad word equals 64 bits. The operand size for each instruc· tion is either explicitly encoded in the instruction or implicit ly defined by the instruction operation. The coprocessor interface a l lows the su pport of any operand size from a bit to 256 bytes.

2.2 DATA ORGAN IZATION IN REG ISTERS

The eight data registers support data operands of 1 , 8, 1 6, 32, and 64 bits, addresses of 1 6 o r 3 2 bits, and bit f ields o f 1 t o 3 2 bits. The seven address registers and the stack pointers su pport add ress operands of 1 6 or 32 bits. The six control registers (SR, VBR, SFC, DFC, CACR, and CAAR) support various data sizes depending on the register specified. Coprocessors may define u n ique operand sizes, and support them with on-chip registers according ly.

2.2.1 Data Registers

Each data register is 32 bits wide. Byte operands occu py the low order 8 bits, word operands the low order 16 bits, and the long word operands the entire 32 bits. The least sign ificant bit of an integer is addressed as bit zero and the most significant bit is addressed as bit 31 . For bit fields, the most sign ificant bit is addressed as bit zero and the least significant bit is addressed as the width of the field minus one.

The quad word data type is two long words and is used on ly for 32-bit mul tiply and divide (signed and unsigned) instructions. Quad words may be organ ized in any two data registers without restrictions on order or pairing. There are no explicit instructions for the management of this data type, although the MOVEM instruction can be used to move a quad word into or out of the reg isters.

When a data reg ister is used as either a source or destination operand, on ly the appropriate low order byte or word (in byte or word operations, respective ly) is used or changed; the remain ing high order portion is neither used nor changed.

2-1

•

• 2.2.2 Address Registers

Each address register and stack pointer is 32 bits wide and holds a fu l l 32·bit address. Address registers can not be used for byte-sized operands. Therefore, when an address register is used as a source operand, either the low order word or the entire long word operand is used, depending upon the operation size. When an address register is used as the destination operand, the entire register is affected regardless of the operation size. If the operation size is word, operands are sign extended to 32 bits before the operation is performed. Address registers may a lso be used to support some simple data operations.

2.2.3 Control Registers

The status register (SR) is 1 6 bits wide with the lower byte accessed as the condition code register (GGR). Not a l 1 1 6 bits of the status register are defined, and u ndefined bits are read as zeros and ignored when written. Operations to the condition code register are word operations; however, the upper byte is read as a l l zeroes and ignored when written.

The cache control register (GAGR) provides control and status access to the on-chip instruction cache. The cache address register (GAAR) holds the necessary address for those cache control functions that req uire one. The vector base register (VBR) provides the starting address of the exception vector table. A l l operations involving the GAGR, GAAR, and VBR are long word operations regard less of whether these registers are used as the sou rce or destination operand.

The alternate function code registers (SFG and DFC) are three bits wide and contain the address space values p laced on FGO-FG2 during the operand read or write of a MOVES instruction. Transfers to and from the alternate function code registers are accomplished using the MOVEG instruction and are long word, although the upper 29 bits are read as zeroes and ignored when written.

Accesses to the control registers are privileged operations and are available only in the supervisor mode.

2.3 DATA ORGANIZATION IN M EMORY

Memory is organized on a byte-addressable basis where lower addresses correspond to higher-order bytes. The address, N , of a long word datum corresponds to the address of the most significant byte of the higher-order word. The lower-order word is located at address N + 2, leaving the least significant byte at address N + 3 (see Figure 2- 1 ). Notice that the MG68020 does not require data to be al igned on even byte boundaries (see Figure 2-22) but the most efficient data transfers occur when data is a l igned on the same byte boundary as its operand size. However, instruction words must be al igned on even byte boundaries.

The data types su pported in memory by the MG68020 are: bit and bit field data; i nteger data of 8, 1 6, or 32 bits; 32-bit addresses; and binary coded decimal data (packed and unpacked). These data types are organized in memory as shown in F igure 2-2. (The quad word is only an operand when located in the data registers.) Note that a l l of these data types can be accessed at any byte address.

2-2

31

1

23 15

Long Word $00000000 Word $00000000 1 Word $00000002

B yle $00000000 1 B yl e $()()()()OO() 1 Byte $()()()()oo()2 I Byte $00000003

Long Word $00000004 Word $00000004 Word $00000006

B Yle $00000004 1 Byte $()()()()oo()5 Byte $<XXXlOOO6 I Byte $()()()()OO() 7

• •

• '1 • t

• •

Long Word $FFFFFFFC Word $FFFFFFFC I Word $FFFFFFFE

Byte $FFFFFFFC I Byte $FFFFFFFD Byte $FFFFFFFE I

Figure 2·1 . Memory Operand Addressing

Byte n - 1

Byte n - 1

o 7 7 6 5 4

Base Address

o 7

Bit Number

Byte n

Bit Data o 7

Byte n + 1

Bit Field Data Base Bit

Byte $FFFFFFFF

Byte n+ 2

I+- - -O;fset. - 3 - 2 - 1 0 2

-Offset- -+ - - Width - - �

7 Byte n - 1

Byte n - 1

Base Address

MSB

Address

o 7

Address

Byte n

Byte Integer Data o

LSB o 7

Byte n + 1

Word Integer Data o o

Word Integer Byte n+ 2

Byte n + 2

o 7 Byte n + 3

Figure 2·2. Memory Data Organization (Sheet 1 of 2)

2·3

o

•

'1

o

o

o

o 7 Byte n - l

Address

o 7 Byte n - l

Address

o 7 Byte n - l

Address

xx = User-Defined Value

MSD

xx

Long Word Integer Data o 7

Packed Binary-Coded Data

Byte n+ 1

Unpacked B inary-Coded Data

o 7 Byte n + 2

Byte n + 2

Figure 2·2. Memory Data Organization (Sheet 2 of 2)

o

o

Coprocessors may implement any data types and lengths. For example, the MC68881 Floating·Point Coprocessor supports memory accesses for quad·word sized items (double·precision f loating·point val ues).

A bit datum is specified by a base address that selects one byte in memory (base byte) and a bit number that selects the one bit in this byte. The most sign ificant bit of the byte is bit number seven.

A bit f ield datum is specified by: 1) a base address that selects one byte in memory, 2) a bit f ield offset that indicates the leftmost (base) bit of the bit field in relation to the

most significant bit of the base byte, and 3) a bit field width that determines how many bits to the right of the base bit are in the

bit field. The most sign ificant bit of the base byte is bit offset 0, the least significant bit of the base byte is bit offset 7, and the least significant bit of the previous byte in memory is bit offset - 1 . Bit field offsets may have va lues in the range of - 231 to 231 - 1 and bit field widths may range between 1 and 32.

2.4 I NSTRUCTION FORMAT

Al l instructions are at least one word and up to 1 1 words in length as shown in Figure 2·3. The length of the instruction and the operat ion to be performed is determined by the first word of the i nstruction, the operation word. The remaining words, cal led extension words, further specify the instruction and operands. These words may be immediate operands, extensions to the effective address mode specified in the operation word, branch displacements, bit number or bit field specifications, special register specifica· t ions, trap operands, pack/unpack constants, argument counts, or coprocessor condition codes.

2·4

1 5 o Operation Word

lOne Word, Specifies Operation and Modes)

Special Operand Specifiers I If Any, One or Two Words)

Immediate Operand or Source Effective Address Extension I l f Any, One to Five Words)

Destination Effective Address Extension I I f Any, One to Five Words)

Figure 2·3. Instruction Word General Format

2.5 PROG RAM/DATA REFERENCES

The MC68020 separates memory references i nto two c lasses: program references and data references. Program references, as the name impl ies, are references to that section of memory that contains the program i nstructions. Data references refer to that section of memory that contains the program data. General ly, operand reads are from the data space. A l l operand writes are to the data space, except when caused by the MOVES instruction.

2.6 ADDRESSI NG

I nstructions for the MC68020 contai n two kinds of i nformation: the funct ion to be per· formed and the location of the operand(s) on which that function is performed. The methods used to locate (or address) the operand(s) are explained in the fol lowing paragraphs.

I nstruct ions specify an operand location in one of three ways: Reg ister Spec if icat ion - The number of the reg ister is g iven i n the reg ister f ield of , the instruct ion. Effective Address - Use of the various effective addressing modes. I mpl icit Reference - The def in it ion of certain i nstructions impl ies the use of

specif ic registers.

2.7 REGISTERS: NOTATION CONVENTIONS

Registers are ident i f ied by the fol lowing mnemonic descript ion: An - Address reg ister n (e.g . , A3 is address reg ister 3) On - Data reg ister n (e.g . , 05 is data reg ister 5) Rn - Address or Data Register n Xn - Denotes index reg ister n (data or address) PC - The program counter SR - The status reg ister

CCR - The condit ion code register; part of the status reg ister SP - The act ive stack pointer; SP and A7 are equ ivalent names.

USP - The user stack poi nter (A7) ISP - The i nterru pt stack pOinter (A7')

2·5

•

• MSP - The master stack poi nter (A7 ") SSP - The supervisor stack poi nter, either the master (MSP) or i nterrupt ( ISP)

stack poi nter SFC - The source function code reg ister DFC - The dest i nation function code reg ister VBR - The vector base reg ister

CACR - The cache control reg ister CAAR - The cache address reg ister

The reg ister f ield w i th in an i nstruct ion spec if ies the reg ister to be used. Other f ields w i th in the i nstruct ion specify whether the reg ister selected is an address or data reg ister and how the reg ister is to be used.

2.8 EFFECTIVE ADDRESS

M ost i nstructions specify the locat ion of an operand by us ing the effective address f ield (EA) i n the operat ion word. For example, F igure 2·4 shows the general format of the s ing le effective address i nstruction operat ion word. The effective address is composed of two 3·bit f ields; the mode f ie ld and the reg ister f ield. The val ue in the mode f ield selects one of the addressing modes. The reg ister f ield contains the number of a reg ister. The i n· struct ion operand word for each i nstruction is located i n APPENDIX C.

1 5 14 13 1 2 1 1 10 9 7 5 4 3 2 Effective Address

Mode Register

Figure 2·4. Slngle·Effectlve·Address Instruction Operation Word

o

The effective address f ield may requ i re add it ional i nformat ion to fu l ly specify the operand address. This add i t ional i nformat ion, cal led the effective address extension, is contained i n fol lowing word or words and is considered part of the i nstruct ion, as shown in F igure 2·3. Detai ls describ ing the format of the extension words can be found in 2.9 EF· FECTIVE ADDRESS ENCODING SUMMARY.

2.8.1 Register Direct Modes

These effective addressing (EA) modes specify that the operand is in one of s ixteen general purpose reg isters or one of six control reg isters (SR, VBR, SFC, DFC, CACR, and CAAR).

2.8.1 .1 DATA REGISTER DIRECT. The operand is in the data reg ister specif ied by the effective address reg ister f ield.

Generation: EA = Dn Assembler Syntax: On Mode: 000 31 0 Register: n ·1 Data Register: On Operand

2·6

I

2.8.1 .2 ADDRESS REGISTER DIRECT. The operand is i n the address reg ister specif ied by the effective address reg ister f ield.

Generation: Assembler Syntax: Mode: Register: Address Register:

EA = An An 001

31 0 n ,-________________________ --, An ----------�.�I ________ o_p_e_ra_n_d

________ �1 2.8.2 Register Indirect Modes

These effective address ing modes specify that the operand is in memory and the contents of a reg ister is used to calcu late the address of the operand.

2.8.2.1 ADDRESS REGISTER I N DI RECT. The address of the operand is in the address reg ister spec if ied by the reg ister f ield.

Generat ion: Assembler Syntax: Mode: Reg ister: Address Register:

Memory Address:

EA = (An) (An) 010 n An ------------+1

31 o Memory Address

31 o Operand

2_8.2.2 ADDRESS REGISTER I N DI RECT WITH POSTINCREMENT. The address of the operand is in the address reg ister specified by the reg ister f ield. After the operand address is used, i t is i ncremented by one, two, or four depend ing upon whether the s ize of the operand is byte, word, or long word. Coprocessors may support increment ing for any s ize, up to 256 bytes, of operand. If the address reg ister is the stack pointer and the operand size is byte, the address is i ncremented by two rather than one to keep the stack po inter on a word bou ndary.

Generat ion:

Assembler Syntax: Mode: Reg ister: Address Reg ister:

EA = (An) An = An + SIZE (An) + 01 1 n 31 o An -------.1 Memory Address

� ________ �� ____ � ______ --J

Operand Length (1 , 2, or 4): --------------------�

31 o

Memory Address: Operand

2-7

•

• 2.8.2.3 ADDRESS REGISTER I N DIRECT WITH P REDECREMENT. The address of the operand is in the address reg ister specif ied by the reg ister field. Before the operand ad· d ress is used, it is decremented by one, two, or four depending upon whether the operand s ize is byte, word, or long word. Coprocessors may support decrement ing for any s ize, up to 256 bytes, of operand. If the address reg ister is the stack pointer and the operand s ize is byte, the address is decremented by two rather than one to keep the stack pointer on a word bounary.

Generation:

Assembler Syntax: Mode: Register: Address Register:

An = An - SIZE EA = (An) - (An) 1 00

31 n An ------+-t Memory Address

Operand Length (1 , 2, or 4): -----------.{

31 Memory Address: Operand

o

o

2.8.2.4 ADDRESS REGISTER I N DI RECT WITH DISPLACEMENT. This addressing mode requ i res one word of extension. The address of the operand is the sum of the address i n the address reg ister and t h e s ign·extended 1 6·bit d isplacement i nteger i n the extension word. Displacements are always sign extended to 32 bits prior to being used i n effective address calcu lations.

Generation: Assembler Syntax: Mode: Register: Address Register:

D isplacement:

Memory Address:

EA = (An) + d1 6 (d1 6,An) 1 01 n 31 o An ------� Memory Address L-_____ �._-----�

31 1 5 r - - - - - - - -,-----------,

L � i�n �x�e�d�d_ -,-__ I n_t_e_ge_r_--,

31 o Operand

2.8.3 Register Indirect with Index Modes

These effective address ing modes specify that the contents of an address reg ister are used in calculat ing the f inal effective address of the operand. I n addit ion, an i ndex reg ister and a d isplacement are also used in calculat ing the f inal address (the val ues are both s ign extended to 32 bits before the calcu lation). The variat ions avai lable for adj ust ing the i ndex reg ister cause the i ndex to be considered an " index operand".

2-8

The format of the i ndex operand is "Xn.S IZE*SCALE". "Xn" selects any data or address reg i ster as the i ndex reg ister. "SIZE" specif ies the i ndex s ize and may be "W" for word s ize or "L" for long word s ize. "SCALE" al lows the i ndex reg ister value to be mu lt ipl ied by a value of one (no sca l ing), two., four, or eight.

D isp lacements and i ndex operands are always sign extended to 32 bits prior to being used i n effective address calculations.

2.8.3.1 ADDRESS REGISTER I N DI RECT WITH IN DEX (8·BIT DISPLACEM ENT). This addressing mode requ i res one word of extension that conta ins the i ndex reg ister i nd icator (with its s ize selector and sca l ing mode), and an a-bit d isplacement. In th is mode, the address of the operand is the sum of the address reg ister, the s ign extended d isplacement val ue in the low order e ight bits of the extension word, and the s ign extended contents of the i ndex reg ister (possibly scaled). The user must specify the displacement, the address reg ister, and the i ndex reg ister i n th is mode.

Generat ion: Assembler Syntax: Mode: Reg ister:

EA = (An) + (Xn) + da (da,An,Xn.S IZE * SCALE) 1 1 0 n 31 o

Address Register: An ------+1 Memory Address L-_____ � _____ ,-__ � 31 7 0

D isplacement: [ = = � i� �x�e�d�d= = = -'--_-'--..,;------------� I ndex Reg ister:

Scale:

31

Memory Address:

S ign Extended Value

Scale Value

31 Operand

2.8.3.2 ADDRESS REGISTER I N DI RECT WITH IN DEX (BASE DISPLACEM ENT). This form of address reg ister ind i rect with i ndex requ i res one, two, or three extens ion words that conta in i ndex reg ister i nd ication and an optional 1 6- or 32-bit base d isplacement (wh ich is s ign extended before i t is used in the effective address calcu lation). The address of the operand is the sum of the contents of the address reg ister, the scaled contents of the s ign-extended i ndex reg ister and the base d isp lacement.

In th is mode, specif icat ion of all three addends is optional. If none are spec if ied, the processor creates an effective address of zero.

2-9

•

• Note that if an i ndex reg ister is specif ied, but not the address reg ister, and a data reg ister (On) is used as the i ndex reg ister, then a "data reg ister ind i rect" access can be generated.

Generat ion: Assembler Syntax: M ode: Reg ister: Address Register:

31

EA = (An) + (Xn) + bd (bd,An,Xn.SIZE*SCALE) 1 1 0 n An ------+t

31

o Base Displacement: '"--___ S_i

g_n_E_x_t_e_nd_e_d_V_a_l u_e __ --'

I ndex Reg ister:

Scale:

31

Memory Address:

2.8.4 Memory Indirect

o Sign Extended Value

Scale Value

31

o Memory Address

Operand

This addressing mode requ i res one to five words of extension, as deta i led in 2.9 EFFEC· TIVE ADDRESS ENCODING SUMMARY. Memory ind i rect is d ist ingu ished from address reg ister ind i rect by use of square brackets ([ ]) in the assembler notat ion. The assembler generates the appropriate i nd icators in the extension words when this addressing mode is selected.

In th is case, four user·spec if ied values are used in the generat ion of the fi nal address of the operand. An address reg ister is used as a base reg ister and its va lue can be adj usted by add ing an optional base d isplacement. An i ndex reg ister specifies an i ndex operand and f inal ly, an outer d isplacement can be added to the address operand, y ie ld ing the effective address.

The locat ion of the square brackets determi nes the user·spec if ied values to be used i n calculat ing an i ntermediate memory address. An address operand is then fetched from that i ntermed iate memory address and i t is used in calculat ing the effective address. The i ndex operand may be added in after the i ntermediate memory access (post·i ndexed) or before the i ntermed iate memory access (pre· i ndexed).

A l l four user·spec if ied va lues are optional. Both the base and outer d isp lacements may be nu l l , word, or long word. When a d isplacement is nu l l , or an element is suppressed, its value is taken as zero in the effective address calcu lat ion.

2·1 0

2.8.4.1 M EMORY I N DI RECT POST·IN DEXED. I n th is case, an i ntermediate i nd i rect memory address is calcu lated us ing the base reg ister (An) and base displacement (bd). • This address is used for an ind i rect memory access of a long word, fol lowed by add ing the i ndex operand (Xn.SIZE* SCALE) to the fetched address. Final ly, the opt ional outer displacement (od) is added to yield the effective address.

Generation: EA = (bd + An) + Xn.SIZE*SCALE + od Assembler Syntax: ([bd,An),Xn.SIZE*SCALE,od) Mode: 1 1 0 31 �------------------------� Address Register: An Memory Address

Base Displacement:

I ndex Register:

Scale:

Outer D isplacement:

Effective Address:

31 0 Sign Extended Value

31 Ind i rect Memory Address

Points To 31

Value at I nd i rect Memory Address

31 Sign Extended Value

Scale Value

31

Sign Extended Value

31 Operand

2-1 1

• 2.8.4.2 M EM O RY I N DI RECT P RE· I N DEXED. I n th is case, the i ndex operand (Xn.SIZE*SCALE) is added to the base reg ister (An) and base d isplacement (bd). This i ntermediate sum i s then used as an ind i rect address i nto the data space. Fol lowing the long word fetch of the operand address, the opt ional outer d isplacement (od) may be added to yield the effective address.

Generat ion: EA = (bd + An + Xn.SIZE*SCALE) + od Assembler Syntax: ([bd,An,Xn.SIZE*SCALE],od) M ode: 1 1 0 31

�-------------------------; An _________ � Address Register: Memory Address

31 Base Displacement: Sign Extended Value

31 o I ndex Register: S ign Extended Value

Scale: Scale Value

31 Ind i rect Memory Address

Points To 31

Value at I nd i rect Memory Address

31 o Outer D isplacement: S ign Extended Value

31 Effective Address: Operand

2-1 2

2.8.5 Program Counter Indirect With Displacement Mode

This address ing mode requ i res one word of extension. The address of the operand is the sum of the address in the program counter and the s ign extended 1 6·bit d isp lacement integer in the extension word. The val ue i n the program counter is the address of the ex· tension word. The reference is c lassified as a program reference.

Generat ion: Assembler Syntax: Mode: Register: Program Counter:

Displacement:

Memory Address:

EA = (PC) + d1 6 (d1 6,PC) 1 1 1 010 31

31 1 5 o [ �g� �� .... ---

I n-

t-e-g-e-r ---'I---�

31 Operand

2.8.6 Program Counter Indirect with Index Modes

o

These addressing modes are analogous to the reg ister i nd i rect with i ndex modes described in 2.8.3, but the PC is used as the base reg ister. As before, the i ndex operand (sized and scaled) and a displacement are used in the calcu lation of the effective address also. Displacements and i ndex operands are always s ign extended to 32 bits prior to be· ing used in effective address calculations.

PC relat ive accesses are always c lassif ied as program space references.

2·1 3

•

• 2.8.6.1 PC I N DIRECT WITH IN DEX (8·BIT DISPLACEMENT). The address of the operand is the sum of the address in the program cou nter, the s ign extended displacement i nteger in the lower e ight bits of the extension word, and the sized and scaled s ign· extended i ndex operand. The value i n the PC is the address of the extension word. This reference is c lassif ied as a program space reference. The user must inc lude the displacement, the PC, and the i ndex reg ister when specifying th is address mode.

Generat ion: Assembler Syntax: Mode: Reg ister:

EA = (PC) + (Xn) + da (da, PC,Xn.SIZE * SCALE) 1 1 1 01 1 31 o

Program Cou nter: ---------� �---------------�--�

Address of Extension Word

Displacement:

I ndex Reg ister:

Scale:

Memory Address:

31 7 0 r - - - - - - - - - - -L _ _

� i�n�� _

_ I nteger f-----_+{

31 0 Sign Extended Value

Scale Value

31 Operand

2.8.6.2 PC I N DI RECT WITH IN DEX (BASE DISPLACEM ENT). This address mode requ i res add it ional extension words that conta in the i ndex reg ister i nd ication and an optional 1 6-or 32-bit base d isplacement (which is sign extended to 32 bits before being used). The address of the operand is the sum of the contents of the PC, the scaled contents of the s ign·extended i ndex reg ister, and the base d isp lacement.

In this mode, specif ication of all three addends is opt ional . However, in order to d ist ingu ish th is mode from address reg ister ind i rect with i ndex (base d isplacement), when the user w ishes to specify no PC, the assembler notation "ZPC" (zero value is taken for the PC) must be used. This al lows the user to access the program space, without necessarily using the PC i n calculat ing the effective address. Note that i f ZPC and an i n· dex reg ister are spec if ied, and a data reg ister (On) is used, then a "data reg ister ind i rect" access can be made to the program space, without us ing the PC.

2·1 4

Generation: Assembler Syntax: Mode: Reg ister:

EA = (PC) + (Xn) + bd (bd,PC,Xn.SIZE*SCALE) 1 1 1 01 1 31

Program Counter: ---------� o

Address of Extension Word �-------------------.--� 31

Base Displacement: S ign Extended Va l ue

31 o I ndex Reg ister: S ign Extended Value

Scale: Scale Value

31 Memory Address: Operand

2.8.7 Program Counter Memory Indirect Modes

As in the memory ind i rect modes (refer to 2.8.4 Memory Indirect) the square brackets ([ ]) ind icate that an i ntermediate access to memory is made as part of the f inal effective address calculation.

In this case, the PC is used as a base reg ister and its value can be adjusted by add ing an optional base d isplacement. An i ndex reg ister specif ies an i ndex operand and f i nal ly, an outer d isp lacement can be added to the address operand, y ie ld ing the effective address.

The locat ion of the square brackets determ i nes the user-specif ied val ues to be used i n calcu lat ing an i ntermediate memory address. An address operand is then fetched from that i ntermediate address and i t is used in the f inal calcu lat ion. The i ndex operand may be added in after the i ntermed iate memory access (post-i ndexed) or before that access (pre-i ndexed).

A l l four user-spec if ied values are optional. Both the base and outer d isp lacements may be nu l l , word, or long word. When us ing n u l l d isp lacements, the value of zero is used i n the effective address calcu lation. I n order t o specify no P C but st i l l make program space references, the notat ion "ZPC" should be used in its p lace.

2-1 5

•

• 2.8.7.1 P ROG RAM COUNTER M EMORY I N DIRECT POST· IN DEXED. An i ntermediate i nd i rect memory address is calcu lated by add ing the PC, used as a base reg ister, and a base d isplacement (bd). This address is used for an ind i rect memory access i nto program space of a long word, fol lowed by add ing the i ndex operand (Xn.SIZE *SCALE) with the fetched address. F inal ly, the opt ional outer d isplacement (od) is added to yield the effect ive address.

Generat ion: Assembler Syntax: Mode: Reg ister Fie ld:

EA = (bd + PC) + Xn.SIZE*SCALE + od ([bd,PGJ,Xn.SIZE*SCALE,od) 1 1 1 01 1 31 o

Program Counter: ---------+1 �----------.--�

31 Base Displacement:

31 I ndex Register:

31 Outer Displacement:

Effective Address:


31

31

I nd i rect Memory Address

Value at I nd i rect Memory Address in Program Space


Scale Value

Sign Extended Value

31 Operand

2-1 6

2.8.7.2 PROG RAM COUNTER M EMORY I N DI RECT PRE· IN DEXED. I n th is case, the i ndex operand (Xn .SIZE* SCALE) is added to the program counter and base displacement (bd) . This i ntermediate sum is then used as an ind i rect address i nto the program space. Fol lowing the long word fetch of the new effective address, the optional outer d isplace· ment may be added to yield the effective address.

Generat ion: . Assembler Syntax: Mode: Reg ister F ie ld:

EA = (bd + PC + Xn.SIZE*SCALE) + od ([bd, PC,Xn.SIZE * SCALE],od) 1 1 1 01 1 31 o

Program Counter: ---------� L-__________ -._�

31 Base Displacement:

31 I ndex Reg ister:

31 Outer Displacement:

Effect ive Address:

S ign Extended Value

Sign Extended Value

Scale Value

31

31 Value at I nd i rect Memory

Address i n Program Space


31 Operand

2·1 7

•

2.8.8 Absolute Address Modes

• Absolute address modes have the address of the operand i n the extension word(s).

2.8.8.1 ABSOLUTE SHORT ADDRESS. This addressing mode requ i res one word of exten· s ion. The address of the operand is in the extension word. The 1 6·bit address is s ign ex· tended to 32 bits before i t is used.

Generat ion: Assembler Syntax: Mode: Register:

EA g iven (xxx).w 1 1 1 000 31 o , - - - - - - -r------------�

Extension Word: -------------------l.�1 Si g n Exte nded L _ _ _ _ _ _ Memory Address

o 31 Memory Address: Operand

2.8.8.2 ABSOLUTE LONG ADDRESS. This address ing mode requ i res two words of exten· s ion. The address of the operand is developed by the concatenat ion of the extension words. The high order part of the address is the f i rst extension word; the low order part of the address is the second extension word.

Generat ion: Assembler Syntax: Mode: Register:

EA g iven (xxx). L 1 1 1 001

F i rst Extension Word: -------------�

Second Extension Word:

Memory Address:

2·1 8

1 5 o Address H igh

1 5 o

31

Concatenat ion

31 o Operand

2.8.9 Immediate Data

This addressing mode req u i res one or two words of extension, depending on the size of the operat ion.

Byte Operat ion Word Operat ion Long Word Operat ion

Generation: Assembler Syntax: Mode: Register:

- Operand is in the low order byte of the extension word - Operand is in the extension word - Operand is in two extension words; h igh order 16 bits are

in the f i rst extension word; low order 16 bits are in the se· cond extension word. Coprocessors may provide support for i mmediate data of any s ize with the instruct ion port ion taking at least one word.

Operand g iven #xxx 1 1 1 1 00

2.9 EFFECTIVE ADDRESS ENCODING SUM MARY

Table 2-1 deta i ls effective address word formats. The i nstruct ion operand extension words fal l i nto three categories: s i ng le·effective·address i nstruction, i ndexed/ ind i rect (brief format), and i ndexedl ind i rect (fu l l format). The longest i nstruction for the MC68020 contains ten extension words. They consist of both source and dest i nation effective ad· dresses us ing the fu l l format extension word, with both base d isplacements and outer d isplacements being 32 bits.

Field

Register D/A

W/L

Scale

15 I D/A I 1 5

D/A I

Table 2·1. Effective Address Specification Formats

Single Effective Address Instruction Format 1 1 10 9 8 7 6 5 4 3 2 o

Effective Address Mode Register

MC68020. Brief Format Extension Word

14 13 12 1 1 10 9 8 7 6 5 4 3 2 a Register IW/L I Scale I a I Displacement

MC68020. Full Format Extension Word(s)

14 13 12 1 1 10 9 8 7 6 5 4 3 2 0 Register IW/L I Scale I 1 I BS I IS I BD SIZE I a I I / IS

Definition

Index Register Number Index Register Type: O = Dn l = An

Base Displacement 10. 1 , or 2 Wordsl Outer Displacement la, 1 , or 2 Wordsl

Field

BS

I S Word/Long Word Index Size:

a = Sign Extended Word 1 = Long Word

Scale Factor: 00= 1 01 = 2 10=4 1 1 = 8

B D S IZE

I l l S

2-1 9

Definition

Base Suppress: 0= Base Register Added 1 = Base Register Suppressed

Index Suppress: a = Evaluate and Add Index Operand 1 = Suppress Index Operand

Base Displacement Size: 00 = Reserved 01 = Null Displacement 10= Word Displacement 1 1 = Long Displacement

Index/ Indirect Selection: Indirect and Indexing Operand Determined in Conjunction with Bit 6, Index Suppress

•

• The i ndex suppress (IS) and i ndex/ind i rect select ion (I/IS) f ields are combi ned to determine the type of ind i rect ion to be performed us ing the i ndexli ndirect fu l l format addressi ng mode_ The encodings and subsequent operat ions are described in Table 2-2.

Table 2-2_ IS-IllS Memory Indirection Encodlngs

Index/ IS Indirect Operation 0 ()()() No Memory Indirection 0 001 Indi rect Pre-Indexed with Nul l Displacement 0 010 Indirect Pre-Indexed with Word Displacement 0 01 1 Indirect Pre-Indexed with Long Displacement 0 1 00 Reserved 0 101 I ndirect Post-Indexed with Nul l Displacement 0 1 1 0 Indirect Post-Indexed with Word Displacement 0 1 1 1 Indirect Post-Indexed with Long Displacement 1 ()()() No Memory Indirection 1 001 Memory Indirect with Null Displacement 1 010 Memory Indirect with Word Displacement 1 01 1 Memory Indirect with Long Displacement 1 100- 1 1 1 Reserved

Table 2-3 is the encoding of the effective addressing modes d iscussed in the previous paragraphs.

Table 2-3. Effective Address Encoding Summary

Addressing Mode Mode Register

Data Register Direct ()()() Reg # Address Register Direct 001 Reg # Address Register Indirect 010 Reg # Address Register Indirect with Postincrement 01 1 Reg # Address Register Indirect with Predecrement 1 00 Reg # Address Register Indirect with Displacement 101 Reg # Address Register and Memory I ndirect with Index 1 1 0 Reg # Absolute Short 1 1 1 ()()() Absolute Long 1 1 1 001 Program Counter Indirect with Displacement 1 1 1 010 Program Counter and Memory Indirect with Index 1 1 1 01 1 Immediate Data 1 1 1 1 00 Reserved for Future Motorola Use 1 1 1 101 Reserved for Future Motorola Use 1 1 1 1 1 0 Reserved for Future Motorola Use 1 1 1 1 1 1

2.10 SYSTEM STACK

Address reg ister seven (A7) is used as the system stack pOinter (SP) where any one of three system stack reg isters is active at any one t i me. The M and S bits of the status reg ister determine which stack poi nter is used. I f S = 0, the user stack poi nter (USP) is the active system stack poi nter and the master and i nterrupt stack pointers cannot be referenced. If S = 1 and M = 1 , the master stack pOinter (MSP) is the active system stack poi nter and the user and interrupt stack pOi nters cannot be referenced as address reg isters. If S = 1 and M = 0, the i nterrupt stack pointer (ISP) is the active system stack pointer and the user and master stack pOinters cannot be referenced as address reg isters. (Th i s corresponds to the MC68000, MC68008, MC68010, and MC68012 supervisor mode.) The term supervisor stack poi nter (SSP) refers to the master or i nterru pt stack poi nters, depend ing on the state of the M bit. Each system stack f i l ls from h igh to low memory.

2·20

The act ive system stack po inter is impl ic i t ly referenced by a l l i nstructions that use the system stack for l i nkage or storage al locat ion.

The program counter is saved on the active system stack on subrout i ne cal ls and restored from the active system stack on returns. During the processing of traps and i nterru pts, both the program counter and the status reg ister are saved on the supervisor stack (either master or interrupt). Thus, the execution of supervisor state code is not dependent on the behavior of user code or cond it ion of the user stack, and user programs may use the user stack pai nter independent of supervisor stack requ i rements.

In order to keep data on the system stack a l igned for maximum eff ic iency when byte data is pushed on to or pul led from the system stack, the stack poi nter is decremented or i ncremented by two as appropriate.

The eff ic iency of the MC68020 system stacking operat ions (e.g. , stacking of except ion f rames, subrout ine cal ls, etc.) is S ign if icantly i ncreased i n long word organ ized memory when the stack poi nter is long word a l igned.

2_1 1 USER PROG RAM STACKS

Addit ional user program stacks can be i mplemented by employing the address reg ister ind i rect with post i ncrement and predecrement addressing modes. Using an address reg ister (AO through A6), the user may imp lement stacks which are f i l led e ither from h igh memory to low memory, or vice versa. The i mportant considerat ions are:

• using predecrement, the reg ister is decremented before its contents are used as the pointer to the stack;

• using post i ncrement, the reg ister is i ncremented after its contents are used as the pai nter to the stack.

Care must be exercised when mix ing byte, word, and long word items in these stacks.

Stack g rowth from h igh to low memory is i mplemented with - (An) to push data on the stack, (An) + to pu l l data from the stack.

After either a push or a pu l l operat ion, reg ister An paints to the top item on the stack. This is i l l ustrated as:

Low Memory (Free)

An --+ Top of Stack • 7 7 • •

Bottom of Stack H igh Memory

2-21

•

• Stack g rowth from low to h igh memory is implemented with

(An) + to push data on the stack, - (An) to pu l l data from the stack.

After e ither a push or pu l l operat ion, reg ister An pOints to the next avai lable space on the stack. This is i l l ustrated as:

Low Memory Bottom of Stack

• 7 • L •

Top of Stack An -+ (Free)

H igh Memory

2.1 2 QUEUES

User queues can also be implemented with the address reg ister ind i rect with post increment or predecrement addressing modes. Using a pai r of address registers (two of AD through A6), the user may i mplement queues which are f i l led either from h igh memory to low memory, or vice versa. Because queues are pushed from one end and pul led from the other, tiNo reg isters are used: the 'put' and 'get' pointers.

Queue growth from low to h igh memory is implemented with (An) + to put data i nto the queue, (Am) + to get data from the queue.

After a put operat ion, the 'put' address reg ister pOints to the next avai lable space in the queue and the u nchanged 'get' address reg ister points to the next item to be removed from the queue. After a 'get' operat ion, the 'get' address reg ister points to the next item to be removed from the queue and the u nchanged 'put' address reg ister points to the next avai lable space in the queue. This is i l l ustrated as:

Low Memory Last Get (Free)

Get (Am) + -+ Next Get •

7 7 L

• •

Last Put Put (An) + -+ (Free)

H igh Memory

2-22

If the queue is to be imp lemented as a c i rcu lar buffer, the relevant address reg ister should be checked and, i f necessary, adjusted before the 'put' or 'get' operat ion is performed. The add ress reg ister is adj usted by subtract ing the buffer length ( in bytes), produc ing a "wrap-around."

Queue growth from high to low memory is implemented with - (An) to put data into the queue, - (Am) to get data from the queue.

After a 'put' operat ion, the 'put' address reg ister poi nts to the last item put in the queue and the unchanged get address reg ister poi nts to the last item removed from the queue. After a 'get' operat ion, the 'get' address reg ister points to the last item removed from the queue and the u nchanged 'put' address reg ister pOints to the last item put in the queue. This is i l l ustrated as:

Put - (An)

Get - (Am)

-+

L

-+

Low Memory (Free)

Last Put • • •

Next Get Last Get (Free) H igh Memory

If the queue is to be implemented as a c i rcu lar buffer, the 'get' or 'put ' operation should be performed f i rst, and then the relevant address reg ister should be checked and, if necessary, adjusted. The address reg ister is adjusted by add ing the buffer length ( in bytes).

2-23/2-24

•

SECTION 3 I NSTRUCTION SET SUM MARY

This section contai ns an overview of the MC68020 i nstruction set. The i nstructions form a set of tools to perform the fol lowi ng operations:

Data Movement B i t Field Manipu lat ion I nteger Arithmet ic B i nary Coded Deci mal Arithmetic Logical Program Control Shift and Rotate System Control Bit Manipulation M u lt iprocessor Communicat ions

The complete range of i nstruct ion capab i l it ies combi ned with the flex ible addressing modes described previously provide a very f lexible base for program development.

The fol lowing notations w i l l be used throughout this sect ion. An = any address reg ister, AO-A7 Dn = any data reg ister, DO-D7 Rn = any address or data reg ister

CCR = cond it ion code reg ister ( lower byte of status reg ister) cc = cond it ion codes from CCR SP = active stack poi nter

USP = user stack poi nter SSP = supervisor stack pointer DFC = dest i nation fu nction code reg ister SFC = source fu nct ion code reg ister

Rc = control reg ister (VBR, SFC, DFC, CACR, CAAR, USP, MSP, ISP) d = displacement; d1 6 is a 1 6-bit d isplacement

< ea > = effective address l i st = l i st of reg isters, e.g. , DO-D3

# < data> = i mmediate data; a l iteral i nteger (offsetwidth] = bit f ield select ion

label = assembly program label [7] = bit 7 of respective operand

[31 :24] = bits 31 through 24 of operand; i .e . , h igh order byte of a reg ister X = extend (X) bit in CCR N = negative (N) bit in CCR Z = zero (Z) bit in CCR

- = i nvert; operand is log ica l ly complemented A = log ical A N D V = log ical O R

e = logical exclus ive O R

3-1

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•

Dc = data reg ister, 00-07 used dur ing compare Ou = data reg ister, 00-07 used dur ing update

Dr, Oq = data reg ister, remainder or quotient of d ivide Oh,OI = data reg ister, h igh or low order 32 bits of mu lt iply resu l t

3.1 DATA MOVEMENT

The bas ic means of address and data manipu lation (transfer and storage) is accompl ish· ed by the move (MOVE) i nstruct ion and its associated effective address ing modes. Data movement i nstructions al low byte, word, and long word operands to be transferred from memory to memory, memory to reg ister, reg ister to memory, and reg ister to register. Address movement instructions (MOVE or MOVEA) a l low word and long word operand t ransfers to ensure that only legal address manipu lat ions are executed. In add it ion to the general MOVE instruction there are several special data movement instruct ions: move mult ip le reg isters (MOVEM), move peripheral data (MOVEP), move qu ick (MOVEO), exchange reg isters (EXG), load effective address (lEA), push effective address (PEA), l i nk stack (LI N K), u n l i nk stack (UN lK). Table 3-1 is a summary of the data movement operations.

Table 3·1 . Data Movement Operations

Operand Operand Instruction Syntax Size Operation

EXG Rn, Rn 32 Rn - Rn LEA < ea > ,An 32 < ea > - An LINK An,# < d > 1 6, 32 SP - 4 - SP ; An - ISP I ; SP - An; SP + d - SP MOVE < ea > , < ea > 8 , 1 6, 32 source - destination MOVEA < ea > , An 16, 32 - 32 MOVEM l ist , < ea > 1 6, 32 listed registers - destination

< ea > , list 16, 32 - 32 source - listed registers MOVEP Dn, (d1 6.Anl 16 , 32 Dn[31 : 24] - (An + dl ; Dn[23: 1 6] - (An + d + 21 ;

Dn[ 15:8] - (An + d + 41 ; Dn[7 0] - (An + d + 61 (d 16,Anl ,Dn (An + dl - Dn[31 :24] ; (An + d + 21 - Dn[23: 16] ;

(An + d + 41 - Dn[ 1 5:8]; IAn + d + 61 - Dn[7:0] MOVEO # < data > ,Dn 8 - 32 immediate data - destination PEA < ea > 32 S P - 4 - SP; < ea > - (SP I UNLK An 32 An - SP; (SPI - An; S P + 4 - SP

3.2 INTEG ER ARITHMETIC OPERATIONS

The arithmet ic operat ions i nc lude the four bas ic operat ions of add (ADD), subtract (SUB), mu lt i ply (MUl), and d ivide (OIV) as wel l as arithmetic compare (CM P, CMPM, CM P2), c lear (ClR), and negate (N EG). The ADD, CMP, and SUB i nstructions are avai lable for both ad· dress and data operat ions, with data operat ions accept ing a l l operand s izes. Address operat ions are l i m ited to legal address s ize operands (16 or 32 bits). The c lear and negate i nstructions may be used on a l l s izes of data operands,

3-2

The MUL and DIV operat ions are avai lable for s igned and uns igned operands us ing word mult iply to produce a long word product, long word mult iply to produce a long word or quad word product; a long word d ividend with word d ivisor to produce a word quotient with a word remainder; and a long word or quad word d ividend with long word d iv isor to produce long word q uotient and ' Iong word remainder.

M u l t iprec ision and mixed s ize arithmet ic can be accompl ished us ing a set of extended i nstructions. These instruct ions are: add extended (ADDX), su btract extended (SU BX), s ign extend (EXT), and negate binary with extend (N EGX).

Refer to Table 3-2 for a summary of the i nteger arithmetic operat ions.

Table 3-2. Integer Arithmetic Operations


ADD Dn, <ea> 8, 16, 32 source + destination - destination <ea > , Dn 8, 16, 32

ADDA <ea> , An 16, 32 ADDI # < data > , <ea> 8, 16, 32 immediate data + destination - destination ADDO #< data > , <ea> 8, 1 6, 32 ADDX Dn, Dn 8, 16, 32 source + destination + X - destination

- IAnl , - IAnl 8, 16, 32 CLR <ea> 8, 16, 32 o - destination CMP <ea> , Dn 8, 16, 32 destination - source CMPA <ea > , An 16, 32 CMPI # < data > , < ea> 8, 16, 32 destination - immediate data CMPM IAnl + , IAnl + 8, 16, 32 destination - source CMP2 <ea > , Rn 8, 16, 32 lower bound < = Rn < = upper bound DIVS/ DIVU < ea > , Dn 321 16- 16 : 16 destination/source - destination Isigned or unsignedl

< ea > , Dr: Dq 64/32 -32:32 <ea > , Dq 32/32-32

DIVSLlDIVUL <ea > , Dr:Dq 32/32 -32:32 EXT Dn 8- 16 sign extended destination - destination

Dn 1 6-32 EXTB Dn 8-32 MULS/MULU <ea > , Dn 1 6x 16-32 source" destination - destination Isigned or unsignedl

< ea > , DI 32 x 32-32 <ea> , Dh :DI 32 x 32-64

NEG <ea> 8, 16, 32 o - destination - destination NEGX <ea> 8, 16, 32 o - destination - X - destination SUB <ea> , Dn 8, 16, 32 destination - source - destination

Dn, <ea> 8, 16, 32 SUBA <ea > , An 16, 32 SUB I # < data> , < ea > 8, 16, 32 destination - immediate data - destination SUBO # < data > , < ea > 8, 16, 32 SUBX Dn, Dn 8, 16, 32 destination - source - X - destination

- IAnl, - IAnl 8, 16, 32

3-3

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3.3 LOGICAL OPERATIONS

Log ical operat ion instructions A N D, OR, EOR, and NOT are avai lable for al l s izes of i n· teger data operands. A s imi lar set of immediate i nstructions (AN DI , ORI , and EORI) pro· vide these logical operat ions with a l l s izes of immediate data. TST is an arithmetic com· parison of the operand with zero which is then reflected in the condit ion codes. Table 3·3 is a summary of the log ical operat ions.

Table 3·3. Logical Operations


AND < ea > , Dn 8, 16, 32 source A destination - destination Dn, < ea > 8, 16, 32

ANDI # < data > , < ea > 8, 16 , 32 immediate data A destination - destination EOR Dn, < ea > 8 , 16, 32 source Ell destination - destination EORI # < data > , < ea > 8, 16, 32 immediate data Ell destination - destination NOT < ea > 8 , 16, 32 - destination - destination OR < ea > , Dn 8, 16, 32 source V destination - destination

Dn, < ea > 8 , 16 , 32 ORI # < data > , < ea > 8 , 16, 32 immediate data V destination - destination TST < ea > 8 , 16 , 32 source - 0 to set condition codes

3.4 SHIFT AND ROTATE OPERATIONS

Shift operat ions i n both d i rect ions are provided by the arithmetic sh ift i nstruct ions ASR and ASL, and logical sh ift instructions LSR and LSL. The rotate i nstructions (with and without extend) avai lable are ROR, ROL, ROXR, and ROXL.

A l l sh ift and rotate operat ions can be performed on either reg isters or memory.

Reg ister sh ifts and rotates su pport a l l operand s izes and a l low a sh ift count (from one to e ight) to be specif ied i n the i nstruct ion operation word or a sh ift count (modulo 64) to be specified in a register.

Memory sh ifts and rotates are for word operands only and al low only s ing le·bit shifts or rotates. The SWAP i nstruct ion exchanges the 1 6·bit halves of a register. Performance of sh i ft/rotate i nstructions is enhanced so that use of the ROR or ROL instructions with a sh ift count of e ight a l lows fast byte swapping.

Table 3·4 is a su mmary of the sh ift and rotate operat ions.

3·4

Table 3·4. Shift and Rotate Operations


ASL On, On 8, 1 6, 32 # < data > , On 8, 1 6, 32 � .. r--O

< ea > 1 6 ASR O n , O n 8, 16 , 32 r--l - � # < data > , On 8, 1 6, 32

< ea > 1 6 I LSL On , On 8, 16 , 32

# < data > , On 8, 16 , 32 �. r-- O < ea > 1 6

LSR O n , O n 8, 1 6, 32 # < data > , On 8, 16, 32 o --I � � < ea > 1 6

ROL On, On 8, 16 , 32 I � # < data > , On 8, 16 , 32 [0 .. I .. < ea > 1 6 ROR On, On 8, 1 6, 32 Y I # < data > , On 8, 1 6, 32 � I -[0 < ea > 1 6 ROXL On, On 8, 16 , 32 I � # < data > , On 8, 16 , 32 [0 .. I" < ea > 1 6 ROXR On, On 8, 16 , 32 C{±H I # < data > , On 8, 16 , 32

- I -W < ea > 1 6 SWAP On 32

M�W L�W I I I

3.5 BIT MANIPULATION OPERATIONS

Bit manipu lat ion operat ions are accompl ished us ing the fol lowing i nstruct ions: b it test (BTST), bit test and set (BSET), bit test and c lear (BClR), and bit test and change (BCHG). A l l bit manipu lation operat ions can be performed on either reg isters or memory, with the bit nu mber specif ied as immediate data or by the contents of a data reg ister. Register operands are always 32 bits, wh i le memory operands are always 8 bits. Table 3·5 is a summary of the bit manipu lation operat ions, (Z is bit 2, the "zero" bit , of the status reg ister.)

Table 3·5. Bit Manipulation Operations


BCHG On, < ea > 8, 32 - « bit number> of destination) - Z - bit of # < data > , < ea > 8, 32 destination

BCLR On, < ea > 8, 32 « bit number> of destination) Z· # < data > , < ea > 8, 32 o - bit of destination

BSET On, < ea > 8, 32 - « bit number> of destination) - Z; # < data > , < ea > 8, 32 1 - bit of destination

BTST On, < ea > 8, 32 - « bit number> of destination) - Z # < data > , < ea > 8, 32

3·5

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3.6 BIT FIELD OPERATIONS

The MC68020 su pports variable length bit f ield operations on f ields of up to 32 bits. The bit field insert (BFI NS) i nserts a va lue i nto a bit f ield. Bit field extract uns igned (BFEXTU) and bit f ield extract s igned (BFEXTS) extracts a val ue from the f ield. B it f ield f ind f i rst one (BFFFO) f inds the f i rst bit that is set in a bit f ield. Also i ncl uded are i nstruct ions that are analagous to the bit manipu lation operations; bit f ield test (BFTST), bit field test and set (BFSET), bit f ield test and clear (BFCLR), and bit f ield test and change (BFCHG).

Table 3·6 is a summary of the bit f ield operat ions.

Table 3·6. Bit Field Operations


BFCHG < ea > ! offset width I 1 ·32 - Field - Field BFCLR < ea > !offsetwidthl 1 ·32 O's - Field BFEXTS < ea > !offsetwidthLDn 1 -32 Field - Dn; Sign Extended BFEXTU < ea > !offsetwidthLDn 1 -32 Field - Dn; Zero Extended BFFFO < ea > !offsetwidthLDn 1 ·32 Scan for first bit set in Field; offset - Dn BF INS Dn, < ea > !offsetwidthl 1 -32 Dn - Field BFSET < ea > loffsetwidthl 1 ·32 l 's - Field BFTST < ea > I offset width I 1·32 Field MSB - N; - lOR of al l bits in fieldl - Z

NOTE: All bit field instructions set the N and Z bits as shown for BFTST before performing the specified operallon .

3.7 BI NARY CODED DECIMAL OPERATIONS

Mult iprec is ion arithmetic operat ions on binary coded decimal nu mbers are accompl ished us ing the fol lowing i nstructions: add decimal with extend (ABCD), subtract decimal with extend (SBCD), and negate decimal with extend (N BCD). PACK and UN PACK al low conversion of byte encoded numeric data, such as ASCI I or EBCDIC strings, to BCD data and vice versa. Table 3·7 is a summary of the b inary coded dec imal operat ions.

Table 3·7. Binary Coded Decimal Operations


ABCD Dn, Dn 8 sourcelO + destinationlO + X - destination - IAni, - IAni 8

NBCD < ea > 8 o - destinationlO - X - destination PACK - IAni, - IAni , 1 6-8 unpacked source + immediate data - packed destination

# < data > Dn, Dn, # < data > 1 6-8

SBCD Dn, Dn 8 destinationl O - sourcel O - X - destination - IAni , - IAni 8

UNPK - IAni , - IAni, 8- 16 packed source - unpacked source # < data > unpacked source + immediate data -

Dn, Dn,# < data > 8-1 6 unpacked destination

3-6

3.8 PROG RAM CONTROL OPERATIONS

Program control operations are accomplished us ing a set of conditional and uncondi· t ional branch i nstructions and return i nstruct ions. These instructions are summarized in Table 3·8.

Table 3·8. Program Control Operations

Instruction Operand Syntax Operation

Conditional Bee < label> 8, 16, 32 if condition true, then PC + d - PC OBcc On, < label > 16 if condition false, then On - 1 - On

if On 7- - 1 , then PC + d - PC Sec < ea > 8 if condition true, then 1 ' s - destination; else O's - destination

Unconditional BRA < label > 8, 16 , 32 PC + d - PC BSR < label > 8, 16 , 32 SP - 4 - SP ; PC - ISP I ; PC + d - PC CALLM # < data > , < ea > none Save module state in stack frame; load new module state from

destination JMP < ea > none destination - PC JSR < ea > none SP - 4 - SP; PC fSP I ; destination PC NOP none none PC + 2 PC

Returns RTO # < d > 16 ISP I - PC; S P + 4 + d - SP RTM Rn none Reload saved module state from stack frame: place module data

area pointer in Rn RTR none none I SPI - CCR; SP + 2 - SP; ISP I - PC; SP + 4 - SP RTS none none I SPI - PC; SP + 4 - SP

The cond it ional i nstruct ions provide test ing and branch ing for the fol lowing cond it ions: CC - carry clear LS - low or same CS - carry set L T - less than EO - equal MI - minus F - never true· NE - not equal GE - g reater or equal PL - plus GT - g reater than T - always true· HI - high VC - overflow clear LE - less or equal VS - overflow set

• Not avai lable for the Bcc or cpBcc i nstructions.

3-7

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3.9 SYSTEM CONTROL OPERATIONS

System control operat ions are accompl ished by us ing privi leged instructions, trap generating i nstruct ions, and i nstructions that use or modify the condit ion code reg ister. These i nstruct ions are summarized in Table 3-9 .

Instruction

ANDI EORI MOVE

MOVE

MOVEC

MOVES

ORI R ES ET RTE

STOP

B KPT

CHK CHK2 I LLEGAL

TRAP

TRAPcc

TRAPV

ANDI EORI MOVE

ORI

Table 3·9. System Control Operations

Operand Syntax

# < data > . SR # < data > . S R

< ea > , S R SR , < ea > USP , An An, USP Rc , Rn Rn, Rc

Rn , < ea > < ea > , Rn

# < data > , S R none none

# < data >

# < data >

< ea > , Dn < ea > , Rn

none

# < data >

none # < data >

none

# < data > , CCR # < data > , CCR

< ea > , CCR CCR, < ea >

# < data > , CCR

Operation

Privileged 1 6 immediate data 1\ S R - S R 16 immediate data e SR - SR 16 source - S R 1 6 S R - destination 32 USP - An 32 An - USP 32 Rc - Rn 32 Rn - Rc

8, 1 6, 32 Rn - destination using DFC source using S FC - Rn

16 immediate data V S R - SR none assert R ESET line none ( SP) - SR; SP + 2 - SP; ( SP) - PC; S P + 4 - SP;

Restore stack according to format 16 immediate data - SR ; STOP

Trap Generating none i f breakpoint cycle acknowledged, then execute returned

operation word, else trap as illegal instruction 16, 32 if Dn<O or Dn> (ea ) , then CHK exception

8, 16 , 32 if Rn< lower bound or Rn> upper bound, then CHK exception none SSP - 2 - SSP ; Vector Offset - ISSP) ;

SSP - 4 - SSP; PC - ISSP) ; SSP - 2 - SSP ; SR - (SSP) ; I l legal Instruction Vector Address - PC

none SSP - 2 - SSP; Format and Vector Offset - (SSP) ; SSP - 4 - SSP; PC - (SSP) ; SSP - 2 - SSP ; SR - I SSP) ; Vector Address - PC

none if cc true, then TRAP exception 16 , 32 none if V then take overflow TRAP exception

Condition Code Register 8 immediate data 1\ CCR - CCR 8 immediate data e CCR - CCR

16 source CCR 1 6 CCR - destination 8 immediate data V CCR - CCR

3-8

3.1 0 M U LTIPROCESSOR OPERATIONS

Commun icat ion between the MC68020 and other processors i n the system is ac· compl ished by us ing the TAS, CAS, CAS2 instructions (which execute i ndivisible read· mod ify·write bus cyc les), and coprocessor instructions. These i nstructions are sum· marized i n Table 3·1 0.

Instruction

CAS

CAS2

TAS

cpBcc cpDBcc

cpGEN cpRESTORE cpSAVE cpScc cpTRAPcc

Table 3·10. Multiprocessor Operations

Operand Syntax

Dc, Du, < ea>

Dcl : Dc2, Dul : Du2, IRn ) : I Rn) < ea>

< label > < label > , On

User Defined < ea> < ea> < ea> none

# < data>

Operation

Read-Modify-Write 8, 16, 32 destination - Dc - CC; if Z then Du - destination

else destination - Dc 16, 32 dual operand CAS

8 destination - 0; set condition codes; 1 - destination (7J

Coprocessor 16, 32 if cpcc true then PC + d - PC 16 if cpcc false then On - 1 - On

if On '" - " then PC + d - PC User Defined operand - coprocessor

none restore coprocessor state from < ea > none save coprocessor state at < ea > 8 if cpcc true, then l's - destination; elseO's - destination

none if cpcc true then TRAPcc exception 16, 32

3-9/3·1 0

•

SECTION 4 SIGNAL DESCRIPTION

This section contains a brief desciption of the i nput and output s ignals by their fu nct ional g roups, as shown in Figure 4-1 . Each s ignal is explained in a brief paragraph with reference (if appl icable) to other sect ions that conta in more detai l about the funct ion being performed.

NOTE The terms assertion and negation are used extensively. Th is is done to avoid confusion when deal ing with a mixture of "act ive-low" and "active-h igh" s ignals. The term assert or assertion i s used to indicate that a s ignal is active or true, i ndependent of whether that level is represented by a h igh or low voltage. The term negate or negation i s used to ind icate that a s ignal is i nactive or false.

FCO-FC2

AO-A3

DO·D3

Transfer Size

Asynchronous Bus

Control

1

1

{

/1 <Junct ion Codes E5iS

Address Bus �terruPt Priority

Data BUS:) irnm MC68020 AVIT

Microprocessor

SIZO ID1" SIZl BG

BGACK m OCS RESET RMC HALT

AS BERR 55

R/W ClK DBEN

DSACKO VCC ( 10) DSACK l G ND ( 15)

Figure 4-1 _ Functional Signal Groups

4-1

Cache Control

} Bus Arbitration Control

} Bus Exception Control

Interrupt Control

4.1 FUNCTION CODE SIG NALS (FCO through FC2)

These three·state outputs ident ify the processor state (supervisor or user) and the ad· dress space of the bus cycle currently being executed as def i ned in Table 4. 1 .

Table 4·1 . Function Code Assignments

FC2 FC1 FCD Cycle Type 0 0 0 I Undefined, Reservedl *

0 0 1 User Data Space 0 1 0 User Program Space 0 1 1 I Undefined, Reservedl *

1 0 0 I Undefined, Reservedl *

1 0 1 Supervisor Data Space 1 1 0 Supervisor Program Space 1 1 1 CPU Space

* Address space 3 IS reserved for user definition, while 0 and 4 are reserved for future use by Motorola.

By decod ing the function codes, a memory system can ut i l ize the fu l l 4 g igabyte address range for several address spaces,

4.2 ADDRESS BUS (AO through A31)

These three-state outputs provide the address for a bus t ransfer dur ing all currently def i ned cycles except CPU-space references. Dur ing CPU-space references the add ress bus provides CPU related i nformation. The address bus is capable of addressing 4 g igabytes (232) of data.

4.3 DATA BUS (DO through 031)

These three-state, b id i rectional signals provide the general purpose data path between the MC68020 and all other devices. The data bus can transmit and accept data us ing the dynamic bus sizing capabi l i t ies of the MC68020. Refer to 4.4 TRANSFER SIZE (SIZO, SIZ1) for add it ional i nformation,

4.4 TRANSFER SIZE (SIZO, SIZ1)

These three·state outputs are used in conju nction with the dynamic bus S IZ ing capabi l i t ies of the MC68020. The SIZO and SIZ1 outputs i nd icate the number of bytes of an operand remain ing to be t ransferred dur ing a g iven bus cycle,

4.5 ASYNCH RONOUS BUS CONTROL SIGNALS

The asynchronous bus control s ignals for the MC68020 are descri bed in the following paragraphs.

4.5.1 External Cycle Start (ECS)

This output is asserted dur ing the fi rst one-half clock of every bus cycle to provide the earliest i nd icat ion that the MC68020 may be start ing a bus cyc le. The use of this s ig nal

4·2

must be val idated later with address strobe, since the MC6S020 may start an i nstruct ion fetch cycle and then abort i t if the instruction word is found in the cache. The MC6S020 drives only the address, s ize, and function code outputs (not address strobe) when it aborts a bus cyc le due to cache h i t.

4.5.2 Operand Cycle Start (OCS)

This output s ignal has the same t iming as ECS, except that it is asserted only dur ing the f i rst bus cyc le of an operand transfer or instruction prefetch.

4.5.3 Read-Modlfy-Wrlte Cycle (RMC)

This three-state output s ignal provides an ind ication that the current bus operat ion is an i nd ivisible read-modify-write cycle. This s ignal is asserted for the duration of the readmodify-write sequence. RMC should be used as a bus lock to insure integrity of i nstruct ions which use the read-modify-write operat ion.

4.5.4 Address Strobe (AS)

This three-state output s ig nal ind icates that valid function code, address, s ize, and RIW state i nformation is on the bus.

4.5.5 Data Strobe (OS)

I n a read cycle, th is three-state output i nd icates that the s lave device should drive the data bus. In a write cycle, it i nd icates that the MC6S020 has placed val id data on the data bus.

4.5.6 ReadlWrlte (RIW)

This three-state output s ignal defi nes the d i rect ion of a data transfer. A h igh level ind icates a read f rom an external device, a low level i nd icates a write to an external device.

4.5.7 Data Buffer Enable (DB EN)

This three-state output provides an enable to external data buffers. This signal al lows the RIW signal to change without possible external buffer content ion.

This pin is not necessary i n al l systems.

4.5.8 Data Transfer and Size Acknowledge (DSACKO, DSACK1)

These i n puts i nd icate that a data t ransfer is complete and the port size of the external device (S-, 1 6-, or 32-bits). Dur ing a read cyc le, when the processor recogn izes DSACKx, it latches the data and then terminates the bus cycle; dur ing a write cyc le, when the pro· cessor recogn izes DSACKx, the bus cycle is terminated. See 5.1 .1 Dynamic, Bus Sizing for further i nformation on DSACKx encodi ngs.

The processor w i l l synchron ize the DSACKx i nputs and al low skew between the two i nputs. See 10.6 AC ELECTRICAL SPECI FICATIONS- READ AND WRITE CYCLES for further i nformation.

4-3

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4.6 CACHE DISABLE (CDIS)

This i nput s ignal dynamically d isables the on·ch ip cache. The cache is d isabled i nternally after the cache d isable i nput is asserted and synchron ized i nternal ly. The cache w i l l be reenabled i nternally after the i nput negat ion has been synchron ized i nternally. See SEC· TION 7 ON·CHIP CACHE M EMORY for further i nformat ion.

4.7 INTERRUPT CONTROL SIG NALS

The following paragraphs descr ibe the i nterrupt control s ignals for the MC68020. Refer to 5.2.4.1 INTERRUPT OPERATION for add it ional i nformation.

4.7.1 Interrupt Priority Level ( IPLO, IPL 1, IPL2)

These i nputs i nd icate the encoded priority level of the device request ing an i nterrupt. Level seven is the h ighest priority and cannot be masked; level zero i nd icates that no i nterru pts are requested. The least s ign i f icant bit is IPLO and the most s ign i f icant bit is I P L2.

4.7.2 Interrupt Pending (IPEND)

This output i nd icates that the encoded i nterrupt priority level act ive on the I PLO-I PL2 inputs is h igher than the current level of the i nterrupt mask i n the status reg ister or that a non-maskable i nterru pt has been recogn ized.

4.7.3 Autovector (AVEC)

The AVEC i nput is used to request i nternal generat ion of the vector number dur ing an i nterrupt acknowledge cycle.

4.8 BUS ARBITRATION SIGNALS

The following paragraphs describe the three-wi re bus arbitration pins used to determ i ne which device i n a system wi l l be the bus master. Refer to 5.2.7 BUS ARBITRATION for add it ional i nformat ion.

4.8.1 Bus Request (BR)

This i nput is w i re-ORed with al l request s ig nals from al l potential bus masters and i nd icates that some device other than the MC68020 requ i res bus mastership .

4.8.2 Bus Grant (BG)

This output s ig nal i nd icates to potential bus masters that the MC68020 w i l l release ownership of the bus when the current bus cyc le is completed .

4-4

4.8.3 Bus Grant Acknowledge (BGACK)

This i nput i nd icates that some other device has become the bus master. Th is s ignal should not be asserted unt i l the following cond i t ions are met:

1) BG (bus g rant) has been received through the bus arbitration process, 2) AS is negated, i ndicat ing that the MC68020 is not us ing the bus, 3) DSACKO and DSACK1 are negated i nd icat ing that the previous external device is

not us ing the bus, and 4) BGACK is negated, wh ich i nd icates that no other device is st i l l c la iming bus

mastersh ip.

BGACK must remain asserted as long as any other device is bus master.

4.9 BUS EXCEPTION CONTROL SIG NALS

The fol lowing paragraphs describe the bus exception control s ignals for the MC68020.

4.9.1 Reset (RESEn

This b id i rect ional open·dra in s ignal is used as the systems reset s ignal . If RESET is asserted as an i n put, the processor w i l l enter reset exception process i ng . As an output, the processor asserts RESET to reset external devices, but is not affected i nternally. Refer to 6.3.1 Reset for more i nformation.

4.9.2 Halt (HAL n

The assert ion of th is b id i rect ional , open·dra in s ignal stops all processor bus act ivity at the completion of the cu rrent bus cycle. When the processor has been halted us ing th is i nput, al l control s ignals wi l l be placed i n the ir i nactive state, the R/w, fu nction code, and s ize S ignals, and the add ress bus remain dr iven with the previous bus cycle information. The RMC s ig nal wi l l be driven i nact ive, if asserted. The data bus is three·stated.

When the processor has stopped execut ing i nstruct ions, due to a double bus fault condi· t ion, the HALT l i ne is dr iven by the processor to ind icate to external devices that the processor has stopped.

4.9.3 Bus Error (BERR)

This i nput s ignal i nforms the processor that there has been a problem with the bus cyc le currently being executed. These problems may be the result of:

1) Non·respond ing devices, 2) I nterrupt vector number acqu is i t ion fai lure, 3) I l legal accesses as determined by a memory management u n it, or 4) Various other appl ication dependent errors.

The bus error s ig nal i nteracts with the halt S ignal to determi ne i f the cu rrent bus cycle should be re-run or aborted with a bus error. Refer to SECTION 5 BUS OPERATION for add it ional i nformat ion.

4-5

•

•

4.1 0 CLOCK (ClK)

The MC68020 clock i nput is a TTL·compat ible s ignal that is i nternally buffered to develop i nternal clocks needed by the processor. The clock should not be gated off at any t ime and must conform to min imum and maximum period and pulse width t imes.

4.1 1 SIG NAL SUMMARY

Table 4·2 provides a summary of the electrical characteristics of the signals d iscussed i n t h e previous paragraphs.

Table 4·2. Signal Summary

Signal Function Signal Name Input/Output Active State Three-State Function Codes FCO-FC2 Output High Yes Address Bus AO-A31 Output High Yes Data Bus DO-D31 I nput/Output High Yes Size S IZO-S lll Output H igh Yes External Cycle Start ECS Output Low No Operand Cycle Start OCS Output Low No Read-Modify-Write Cycle RMC Output Low Yes Address Strobe AS Output Low Yes Data Strobe DS Output Low Yes Read/Write R/W Output High/Low Yes Data Buffer Enable DBEN Output Low Yes Data Transfer and Size Acknowledge DSACKO-DSACK 1 Input Low -

Cache Disable CDIS Input Low -

Interrupt Priority Level IPLO-IPL2 Input Low -

Interrupt Pending IPEND Output Low No Autovector AVEC Input Low -

Bus Request BR Input Low -

Bus Grant BG Output Low No Bus Grant Acknowledge BGACK Input Low -

Reset RESET Input/Output Low No* Halt HALT Input/Output Low No* Bus Error BERR Input Low -

Clock CLK Input - -

Power Supply VCC Input - -

Ground GND Input - -

*Open Drain

4-6

SECTION 5 BUS OPERATION

Th is section describes the control s ignal and bus operation dur ing data t ransfer operat ions, bus arbitrat ion, bus error and halt condit ions, and reset operat ion.

NOTE I n the paragraphs dea l i ng with bus transfers, a "port" refers to the external data bus width at the s lave device (memory, peripheral , etc.).

Dur ing a write cycle, the MC68020 always drives all sections of the data bus.

The term "synchron izat ion" is used repeated ly when d iscussing bus operat ion. This delay is the t ime period requ i red for the MC68020 to sample an external asynchronous i nput S ignal , determine whether it is h igh or low, and synchron ize the i nput to the i nternal c locks of the processor. F igure 5-1 shows the relat ionship between the c lock signal , an external i nput, and its associated i nternal S ignal that is typical for all of the asynchronous i nputs.

Fu rthermore, for all i nputs, there is a sample w i ndow dur ing which the processor latches the level of the input. This w i ndow is i l l ustrated in F igure 5-2. In order to guarantee the recognit ion of a certai n level on a spec if ic fal l i ng edge of the c lock, that level must be held stable on the input through the sample w indow. I f an input makes a transit ion dur ing the sample w i ndow, the level recognized by the processor is not pred ictable; however, the processor w i l l always resolve the latched level to a logic h igh or low before tak ing act ion on it. One except ion to th is rule is for the late assert ion of BERR (see 5.2.5.1 BUS ERROR OPERATION), where the signal must be stable through the w indow or the processor may exh ibit errat ic behavior. I n add it ion to meet ing input setup and hold t imes, a l l i nput S ignals must obey the protocols described later in th is section (e.g. , when DSACKx is asserted, it must remain asserted unt i l AS is negated).

elK

EXT

INT

��! ----�----�---

I \�--

I+-- Sync Delay -!

Figure 5·1 . Relationship Between External and Internal Signals

5-1

•

•

tsu -.j I-

elK

�

I- th

I I I I

------------�:'{��: ------------I I I I EXT � � Sample

Window

Figure 5·2. Sample Window

5.1 OPERAN D TRANSFER M ECHANISM

The MC68020 arch itecture supports byte, word, and long word operands al lowing access to 8·, 1 6·, and 32·bit data ports through the use of the data transfer and s ize acknowledge i n puts (DSACKO and DSACK1). The DSACKx i nputs are control led by the s lave device cur· rently being accessed and are discussed further i n 5.1 .1 Dynamic Bus Sizing.

The MC68020 places no restrictions on the a l ignment of operands in memory, that is, word and long word operands may be located at any byte bou ndary. However, i nstruction a l ignment on word (even byte) boundaries is enforced for max imum eff ic iency and i n order t o maintain compatib i l ity with earl ier members o f the M68000 Fam i ly. The user should be aware that misa l ignment of word or long word operands may cause the MC68020 to perform mu lt ip le bus cyc les for the operand transfer and therefore, pro· cessor performance is opt im ized if word and long word memory operands are a l igned on word or long word bou ndaries, respect ively. Refer to 5.1 .3 Effects of Dynamic Bus Sizing and Operand Misalignment for a d iscussion of the impact of dynam ic bus sizing and operand a l ignment.

5.1 .1 Dynamic Bus Sizing

The MC68020 a l lows operand t ransfers to or from 8·, 16·, and 32·bit ports by dynam ica l ly determi n i ng the port s ize dur ing each bus cyc le. During an operand transfer cyc le, the slave device s ignals its port s ize (byte, word, or long·word) and transfer status (complete or not complete) to the processor through the use of the DSACKx i nputs. The DSACKx i n· puts perform the same transfer acknowledge function as does the DTACK i nput of other processors in the M68000 Fami ly as well as informing the MC68020 of the cu rrent port width. See Table 5·4 for DSACKx encodi ngs and assert ion resu lts.

For example, if the processor is execut ing an i nstruct ion that requ i res a read of a long word operand it w i l l attempt to read 32 bits during the fi rst bus cycle (refer to 5.1 .2 Mis· al ignment of Bus Transfers). If the port responds that it is 32 bits w ide, the MC68020 latches a l l 32 bits of data and cont i nues with the next operat ion. If the port responds that it is 1 6 bits wide, the MC68020 latches the 1 6 bits of val id data and runs another cyc le to obtain the other 1 6 bits. An B·bit port is hand led s im i larly, but with fou r read cyc les.

5·2

I t is important to realize that the assert ion of OSACK, in add it ion to signal l ing complet ion of the bus cyc le, indicates the device port s ize not the transfer size. For example, a 32·b it device always returns OSACK for a 32-bit port regard less of whether the bus cycle is a byte, word, or long word operat ion.

Each port is f ixed i n ass ignment to part icu lar sect ions of the data bus. A 32-bit port is located on data bus bits 31 through 0, a 1 6-bit port is located on data bus bits 31 through 1 6, and an 8-bit port is located on data bus b i ts 31 through 24. The MC68020 makes these assumptions in order to locate va l id data. This scheme min im izes the nu mber of bus cycles needed to t ransfer data to the 8- and 1 6-bit ports. The MC68020 wil l always attem pt to t ransfer the max imum amount of data on al l bus cycles; i .e. for a long word operat ion, it always assumes that the port is 32 bits wide when beg inn ing the bus cycle .

F igure 5-3 shows the requ i red organ izat ion of data ports on the MC68020 bus for 8-, 1 6-, and 32-bit devices. The "OPn" labels in F igure 5-3 define the various operand bytes, with OPO being the most s ign i f icant. F igure 5-4 shows the i nternal organ ization of byte, word, and long word operands. The four bytes shown in F igure 5-3 are routed to the external data bus via the data mult iplex and dupl icat ion hardware which is also shown. Th is hardware provides the basic mechanism through which the MC68020 supports dynam ic bus sizing and operand misal ignment.

The mult iplexor operation, as detai led in F igure 5-3, shows the mult ip lexor connect ions for d i fferent combinations of address and data s izes. The mult ip lexor takes the four bytes of the 32-bit bus and routes them to their requ i red posit ions. For example, OPO can be routed to 031 -024, as would be the normal case, or i t can be routed to any other byte posit ion in order to su pport a m isal igned transfer. The same is t rue for any of the operand bytes. The posit ioning of bytes is determ i ned by the s ize (SIZ1 and SIZO) and address (AO and A1 ) outputs.

I nternal Source/Destination

I ncreasing Memory

Addresses

t

Multiplexor

External Data Bus

Address xxxxxxxO

xxxxxxxO 2

xxxxxxxO

2 3

a

OPO 0

\ I / D31-D24

Byte 0

Byte 0 Byte 2

.. b Byte 0 Byte 1 Byte 2 Byte 3

MC68020 OP1 OP2 OP3 1 I 2 I 3 I \ j 1

Routing and Duplication I I \ \ D23-D16 D 1 5-D8 D7-DO I

Byte 1 I Byte 2 I Byte 3 I 32-Bit Port

Byte 1 : 1 6-Bit Port Byte 3

8-Bit Port

Figure 5-3. MC68020 Interface to Various Port Sizes

5·3

•

•

Long Word Operand I oPo OP1 OP2 OP3 I 31 0

Word Operand I OP2 OP3 I 1 5 0

Byte Operand I OP3 I 7 0

Figure 5·4. Internal Operand Representation

The mult i plexor routes and/or dupl icates the bytes of the bus to al low for any combina· t ion of al igned or misal igned transfers to take place. The SIZO and SIZ1 outputs i ndicate the remaining number of bytes to be transferred during the next bus cycle .

The number of bytes transferred during a bus cyc le w i l l be equal to or less than the operand s ize i nd icated by the SIZO and SIZ1 outputs, depending on port width and operand a l ignment. For example, during the f i rst bus cyc le of a long word transfer to a word port, the size outputs wi l l i nd icate four bytes are to be transferred although only two bytes w i l l be moved on that cyc le. Table 5·1 shows the encod ings of SIZ1 and SIZO.

Table 5·1 . SIZE Output Encodlngs

SIZI SIZO Size 0 1 Byte 1 0 Word 1 1 3 Byte 0 0 Long Word

The address l i nes AO and A 1 also effect operation of the data mult ip lexor. Ouring an operand transfer ( instruction or data), A2·A31 i ndicate the long word base address of that portion of the operand to be accessed, whi le AO and A 1 g ive the byte offset from the base. For example, consider a word write to a long word address with an offset of one byte (A1 /AO = 01) . The MC68020 will in it iate the transfer (SIZ1 /SIZO = 1 0, A1 /AO = 01 ) and the data mult iplexor w i l l place OP2 and OP3 (see Figure 5·3 and 5·4) on 01 6·023 and 08·01 5 respectively. Table 5·2 shows the encodi ngs of A 1 and AO and the corresponding byte offsets from the long word base.

Table 5·2. Address Offset Encodings

A1 AO 0 0 0 1 1 0 1 1

5·4

Offset + 0 Bytes + 1 Byte + 2 Bytes + 3 Bytes

Table 5-3 describes the use of SIZ1 , SIZO, A 1 , and AO i n def in ing the transfer pattern from the MC68020's i nternal mu l t ip lexor to the external data bus.

Table 5-3_ MC68020 Internal to External Data Bus Multiplexor

Transfer Size Address Size SIZ1 SIZO A1 AO 031: 024 Byte 0 1 x x

1 0 x 0 Word

1 0 x 1

1 1 0 0

1 1 0 1 3 Byte

1 1 1 0

1 1 1 1

0 0 0 0

0 0 0 1 Long Word

0 0 1 0

0 0 1 1

* On write cycles this byte is output, on read cycles this byte is ignored. x ; don' t care.

OP3

OP2

OP2

OP1

OP1

OP1

OP1

OPO

OPO

OPO

OPO

Source/ Destination External Data Bus Connection

023:016 015:08 OP3 OP3

OP3 OP2

OP2 OP3

OP2 OP3

OP1 OP2

OP2 OP1

OP1 OP2

OP1 OP2

OPO OP1

OP1 OPO

OPO OP1 *

07:00 OP3

OP3

OP2

OPO

OP3

OP2

OP1

OP3

OP2

OP1

OPO

NOTE: The OP labels on the external data bus refer to a particular byte of the operand that will be read or written on that section of the data bus (see Figure 5-4).

Table 5-4 describes the encod i ngs of the DSACKx pins to s ignal current port s ize.

Table 5-4. DSACK Codes and Results

DSACKl DSACKO Result H H Insert Wait S tates in Current Bus Cycle H L Complete Cycle - Data Bus Port Size is 8 Bits L H Complete Cycle - Data Bus Port S ize is 16 Bits L L Complete Cycle - Data Bus Port Size is 32 Bits

5-5

•

•

Figure 5·5 shows the basic control f low assoc iated with an a l igned long word transfer to a 1 6·bit port. Refer to F igure 5·6 for t i m i ng relat ionships. The high order word of the long word (OPO and OP1) w i l l be t ransferred to the port located on 016·031 dur ing the f i rst bus operat ion. The s ize outputs w i l l i nd icate a long word operand and the lower address bits w i l l show a zero offset from the long word base (SIZ1/SIZO/A 1 IAO = 0000). The port responds to the processor by assert ing the OSACK i nputs to i nd icate complet ion of a 1 6-bit transfer (OSACK1/0SACKO = LH). The MC68020 terminates th is cyc le and beg ins a second cyc le to complete the t ransfer. For the second cycle, the s ize and address out· puts w i l l i nd icate that a word t ransfer is to occur on the upper data bus 016·031 (SIZ1 /SIZO/A 1 /AO = 1 01 0). The base offset has been i ncremented by two in order to access the next h ighest word locat ion. The processor a lso mult ip lexes the lower word of the operand to 031 -016 and the port agai n responds by assert ing the OSACKx inputs (OSACK1 IDSACKO = LH).

31

031

Long Word Operand

OPO 1 OP1

Data Bus

l Word Memory MSB LSB

OP2

016

SIZ1 o

OP3 I o

MC68020 SIZO

o o

A1 o

AO o o

Memory Control OSACKI OSACKO -- --

L H H

Figure 5-5. Example of Long Word Transfer to Word Bus

5·6

so S2 S4 so S2 S4 ClK

A2-A31 =X� _______ �X'-________ _

A1 ""\ AO ""\

/

FCO-FC2 =x ________ __'X'-_______ _

S IZ1 :00\ / -�--'---------'

S ilO _\-'-________________ _

R/W _\____'_ ________________ _

ECS � OCS �

\'-------.J/

\'--__ ---.J/

\'-------.Jr

\'-----DBEN ___ \� _____ �� __ ____'_ ____ ___

D24-D31 )>----«'-___ OP_O __ ...J) ('-___ O_P2 __ _

D16-D23 )>--�(,---__ OP_1 __ ...J)>-----«,---__ O_P3 __ _ !.---word Write .1... word Write--l f.------ long Word Operand Write to 16-Bit port-----l Figure 5·6. Long Word Operand Write Timing (1 6·Bit Data Port)

5-7

•

•

The control f low for an a l igned long word transfer to an 8-bit port is shown i n F igure 5-7. Four bus cyc les w i l l be requ i red to t ransfer th is operand, moving one byte per cycle. Simi lar to the previous example, the s ize outputs indicate a long word transfer dur ing the f i rst cycle, three byte dur ing the second, word during the th i rd, and byte dur ing the f i nal cycle. See Table 5-3 for processor mult i plexor operat ion during this t ransfer. F igure 5-8 shows t im ing relationsh ips for these t ransfers.

Long Word Operand

OPO OP1 OP2 OP3 31 • 0

Data Bus

� Byte Memory MC68020 Memory Control

SIZl S IZO Al AO DSACKl DSACKO OPO 0 0 0 0 H OP1 0 H L OP2 1 0 0 H OP3 0 H

Figure 5-7_ Example of Long Word Transfer to Byte Bus

5-8

SO S2 S4 SO S2 S4 SO S2 S4 SO S2 S4

CLK

A2-A31 =x x x X A1 � / AD � / \ /

FCO-FC2 =x X X X S IZ1 � / \ / • S IZO � / \ / \ R/W \ ECS \J V V V \ OCS \J \

AS

OS

OSACKO

5SAOO J OBEN \ 1\ 1\ 1\

024-031 =>----< OPO >---< OP1 >---< OP2 >---< OP3 >-I:- Byte Write ·1"" Byte Write ·1"" Byte Write ·1"" Byte Write=-:! Long Word Operand Write to 8-Bit Port

Figure 5·8. Long Word Operand Write Timing (8·Bit Data Port)

5-9

•

5.1 .2 Misalignment of Bus Transfers

I n the 32·bit arch itecture of the M C68020, it is poss ible to execute an operand transfer on a memory address bou ndary that may not fal l on an equ ivalent operand size bou ndary. Examples are words t ransferred to odd addresses and long words transferred to addresses other than long word boundaries. The MC68000, MC68008, and MC6801 0 implementat ions a l low long word transfers on odd word boundaries but force an except ion i f word or long word operand t ransfers are attempted at odd byte addresses.

The MC68020 does not enforce any data a l ignment restrictions. Some performance degradat ion can occur due to the mu lt ip le bus accesses that the MC68020 must make when long word (word) operand accesses do not fal l on long word (word) boundaries .

Note that i nstructions, and the i r associated ( i f any) extension words, are req u i red to fal l on word address boundaries, but th is is not requ i red for program space operand references. The MC68020 forces an address error except ion i f an i nstruct ion prefetch is attempted at an odd address. This occu rs when an i nstruct ion (e.g . , a branch with an odd offset) leaves the program counter set to an odd address.

Dynam ic bus sizi ng also affects the t ransfer posit ion of misal ignment operands.

NOTE In the fol lowing examples for misal igned transfers, xxx in a byte denotes that the val ue is left u nchanged.

F igure 5-9 shows the control associated with transferri ng a long word operand to an odd address in word organ ized memory. F igure 5-1 0 shows the t im ing relat ionship for th is operat ion. Th is t ransfer requ i res that the MC68020 place a long word in memory start ing at the least s ign i f icant byte of long word O. This transfer crosses two word boundaries and requ i res three bus cyc les to complete. The f i rst cyc le executes with A2/A 1 /AO = 001 ) and the s ize outputs ind icat ing a long word t ransfer (SIZ1/SIZO = 00). The word addressed dur ing th is t ransfer conta ins on ly one byte of the dest i nation and w i l l respond w i th DSACK1/DSACKO = LH (port width = 1 6 bits). The system designer must ensure that the unused byte of the word accessed dur ing this cyc le does not receive an enable (refer to 5.1 _4 Address, Size, and Data Bus Relationships). The processor executes

31

D31

Long Word Operand OPO i OP1 OP2

Data Bus

Word Memory

MSB LSB

xxx OPO OP1 OP2 OP3 XXX

D16

� 0 1 0

OP3 o

MC68020 Memory Control

SilO A2 A1 AO DSACK1 DSACKO

0 0 0 1 L H 0 1 0 H

0 0 H

Figure 5-9. Misaligned Long Word Transfer to Word Bus Example

5-1 0

SO S2 S4 SO S2 S4 SO S2 S4 ClK

A2-A31 � X X Al � / \ AO J \

FCO-FC2 � X X S IZl � / \ • SIZO � / Riw � ECS V V V OCS V AS

OS

OSACKO

l5Si'\CK'1 \ / � � OBEN T\ r\ 1\

024-031 ( OPO ) ( OPl ) ( OP3

016-023 ( OPO ) ( OP2 ) ( OP3

08-0 15 ( OPl ) ( OPl ) ( OP3

00-07 ( OP2 ) ( OP2 ) ( OP3

r

BYteWrite -I- Word Write -I- Byte Write

----:l long Word Operand Write

Figure 5·1 0. Misal igned Long Word Transfer to Word Bus

5-1 1

•

the next transfer with A2/A 1 /AO = 010 and SIZ1 /SIZO = 1 1 (three bytes remaini ng). The memory accepts two bytes on this transfer and again asserts DSACK1 /DSACKO = LH. The f inal cycle is executed with the t ransfer of a s ing le byte (SIZ1 /SIZO = 01) to address A2tA1 /AO = 1 00.

F igure 5-1 1 shows an example of a word transfer to an odd address in word organ ized memory. This example is s imi lar to the one shown in F igure 5-9 except that the operand is of word size and requ i res on ly two bus cyc les. F igure 5-1 2 shows the s ignal t iming associated with th is example.

15

031

Word Operand OP2 l OP3

0

Data Bus

� 016

Word Memory

SIZl

o

SIZO

o

MC68020

A2 -o o

Al

o AO

o

Memory Control

OSACKl DSACKO

L H L H

Figure 5-1 1 . Example of Misaligned Word Transfer to Word Bus

5-1 2

SO S2 S4 SO S2 S4 ClK

A2-A31 � X A1 \ / AO J \

FCO-FC2 � X SIZ1 J \ • SIZO \ / R/W \ ECS � U OCS �

AS \ / \ I OS

OSACKO

OSACK1 \ / \ r OBEN 1\ /\

024-031 ( OP2 ) ( OP3

016-023 ( OP2 ) ( OP3

08-0 15 ( OP3 ) ( OP3

00-07 ( OP2 ) ( OP3

I: Word Operand Write to A l l AO = 01 :1 Word Write -I· Byte Write

Figure 5·1 2. Misaligned Word Transfer to Word Bus

5-1 3

Figure 5·1 3 shows an example of a long word transfer to an odd address i n long·word· organ ized memory. I n th is example, a long word access is attempted beg inn ing at the least s ign i f icant byte of a long·word·organ ized memory. Thus, only one byte is transfer· red in the f i rst bus cyc le. The second bus cyc le then consists of a three byte access to a long word boundary. Si nce the memory is long word organ ized, no further bus cyc les are necessary. F igure 5·1 4 shows the s ignal t im ing associated with th is example.

Long Word Operand OPO OP1 l · OP2 OP3

31 o Data Bus

D31 DO

Long Word Memory MC68020 Memory Control

SIZl SIZO E .E. � DSACKl DSACKO

0 0 0 1 L 0 0 L

Figure 5·1 3. Misaligned Long Word Transfer to Long Word Bus

5.1 .3 Effects of Dynamic Bus Sizing and Operand Misalignment

The combi nat ion of operand s ize, operand a l ignment, and port s ize affect the operat ion of the MC68020 operand transfer mechan ism by d ictat ing the number of bus cyc les reo q u i red to perform a part icu lar memory access. Table 5·5 shows the number of bus cyc les that are requ i red for d i fferent operand s izes through d i fferent port s izes based on the a l ignment of that operand.

Table 5·5. Memory Alignment and Port Size Influence on Bus Cycles

Number of Bus Cycles I Al /AO 00 01 1 0 1 1

I nstruction* 1 : 2 :4 N/A N/A N/A

Byte Operand 1 : 1 : 1 1 : 1 : 1 1 : 1 : 1 1 : 1 : 1 Word Operand 1 : 1 : 2 1 : 2 : 2 1 : 1 :2 2 : 2 : 2 Long-Word Operand 1 :2 :4 2:3 :4 2:2:4 2:3 :4 Data Port Size 32-8Its: 16- 8Its: 8-Blts * I nstruction prefetches are always two words from a long word boundary.

As can be seen in th is table, the MC68020 bus throughput can be s ign i f icantly affected by port s ize and a l ignment. The MC68020 system des ig ner should be aware of and ac· count for these effects, part icu larly in t ime crit ical appl ications.

Table 5·5 shows that the processor always prefetches i nstructions by read ing two words from a long word boundary. When the MC68020 prefetches from the i nstruct ion stream, it a lways reads a long word f rom an even word address (A 1 /AO = 00), regard less of port s ize or a l ignment.

5·1 4

SO S2 S4 SO S2 S4 ClK

A2-A31 -y., X A 1 J \ AO J \

FCO-FC2 -y., X S IZl :\ / • SIZO \ / R/W "), m '-J LI ocs '-J

AS \ / \ I os "---/ \ r

OSACKO ..J \ / \ OSACKl ..J \ / \

OBEN J\ r\ 024-31 ) ( OPO ) ( OPl

0 16-023 ) ( OPO ) ( OP2

08-0 15 ) ( OPl ) ( OP3

00-07 ) ( OPO ) ( OPl

I: Byte Write -I· 3-Bytes Write :1 long Word Operand Write

Figure 5·1 4. Misaligned Write Cycles to 32·Bit Data Port

5-1 5

•

5.1 .4 Address, Size, and Data Bus Relationships

The dynam ic bus capabi l it ies of the MC68020, coup led with the al lowance for m isal ig ned operands, create an extremely powerfu l and f lexible bus structure. Correct external interpretat ion of bus control s ignals is crit ical to ensure valid data transfer operat ion.

The MC68020 system des igner should ensure that data ports are a l igned as d iscussed in 5.1 .1 Dynamic Bus Sizing such that the MC68020 is able to route data to the correct locations. It is also requ i red that the correct byte data strobes (four, for a long word memory) be generated which enable only those section of the data port(s) which are active dur ing the current bus cyc le. The MC68020 always drives a l l sections of the data bus dur ing a write cycle, so this necess itates carefu l control of the enable s ignals for independent bytes of a data port.

For example, consider the bus transfer operat ion i l l ustrated in F igure 5-9. The transfer described is a long word write to an odd address in word-organ ized memory, requ i ring three bus cyc les to complete. Both the f i rst and the last transfers requ i re writ ing a s ing le byte to a word address. I n order not to overwrite those bytes which are not i nvolved i n these transfers, no byte data strobe should be asserted for those bytes.

The requ i red act ive bytes of the data bus for any g iven bus transfer are a fu nction of the s ize (SIZ1 /SIZO) and lower address (A1 /AO) outputs of the MC68020 and are shown i n Table 5-6. I ndiv idual data strobes for each byte o f t h e bus can b e generated by qual ifying the above enables with data strobe (OS). Devices resid ing on 8-bit ports can ut i l ize OS alone s i nce there is on ly one valid byte for any transfer.

F igure 5-1 5 shows a logic d iagram of one method of generat ing byte data selects for 1 6 and 32-bit ports from the s ize and address encodi ngs.

Table 5·6. Data Bus Activity for Byte, Word, and Long Word Ports

Oata Bus Active Sections

Transfer Byte (B) - Word (W) - Long Word ( L) Ports

Size SIZl SIZO Al AD 031-024 023-016 015-08 07-00

0 1 0 0 B W L - - -

Byte 0 1 0 1 B W L - -

0 1 1 0 B W - L -

0 1 1 1 B W - L 1 0 0 0 B W L W L - -

Word 1 0 0 1 B W L L -

1 0 1 0 B W W L L 1 0 1 1 B W - L 1 1 0 0 B W L W L L -

Three- 1 1 0 1 B W L L L Byte 1 1 1 0 B W W L L

1 1 1 1 B W - L 0 0 0 0 B W L W L L L

Long 0 0 0 1 B W L L L Word 0 0 1 0 B W W L L

0 0 1 1 B W - L

5-1 6

AO

Al

S IZO

SIZl

� � � Lc

� I r--. I I "\ -../

I

I J -r-

J � -../ � I -

I --""""-J J -

" ./

UUD Upper Upper Data 132-Bit Port! UMD Upper Middle Data 132-Bit Port) LMD Lower Middle Data 132-Bit Port) LLD Lower Lower Data 132-Bit Port) UD Upper Data 1 16-Bit Port) LD Lower Data 1 16-B i t Port)

, " -...../

l " ./

I l '"

I ./

Figure 5·1 5. Byte Data Select Generation for 1 6· and 32·Bit Ports

5·1 7

UUD

UMD

LMD •

LLD

UD

LD

•

5.2 BUS OPERATION

Transfer of data between the processor and other devices i nvolves the fol lowing s ignals: 1 . Address Bus AO through A31 , 2. Data Bus DO through 031 , and 3. Control S ignals.

The address and data buses are paral lel , non-mult ip lexed buses used to transfer data with an asynchronous bus protocol. I n a l l bus cycles, the bus master is responsible for deskewing a l l s ignals issued at both the start and the end of the cyc le. I n add it ion, the

, bus master is responsible for deskewing the acknowledge and data S ignals from the s lave devices .

The fol lowing sections explain the data t ransfer operat ions, bus arbitration fu nctions, and except ion processing.

5.2.1 Read Cycles

During a read cycle, the processor receives data from a memory or peripheral device. The processor reads bytes in a l l cases. The MC68020 w i l l read a byte, or bytes, as determi ned by the operand s ize and a l ignment. See 5.1 OPERAN D TRANSFER MECHANISM. If the DSACKx i n puts or BERR are not asserted during the sample w indow of the fal l ing edge of S2, wait cycles w i l l be inserted in the bus cycle unt i l either DSACK1 /DSACKO or BERR is recogn ized as being asserted.

A f lowchart of a long word read cycle is shown in F igure 5-1 6 with posit ional s ignal i nformation shown in F igure 5-1 7. A flowchart of a byte read cyc le is shown i n F igure 5-1 8 with byte and word read cycle t im ing shown i n F igure 5·19. Actual read cycle t iming diagrams specif ied in terms of c lock periods are shown in SECTION 10 ELECTRICAL SPECIFICATIONS.

BUS MASTER Address Device SLAVE

11 Set R/W to Read 21 Drive Function Code on FCO-FC2 31 Drive Address on AO-A31 41 Drive S ilO-Sill I Four Bytesl 51 Assert ECS/OCS for One-Half Clock 61 Assert Address Strobe IASI 71 Assert Data Strobe IDS I 81 Assert Data Buffer Enable I DBENI r-----. Present Data

1 1 Decode Address 21 Place Data on 00-031

Acquire Data t-- 31 Assert Data Transfer and Size Acknowledge IDSACKxl 1 1 Latch Data 21 Negate OS 31 Negate AS 41 Negate DBEN � Terminate Cycle I

, 1 1 Remove Data from 00-031 Start Next Cycle 21 Negate DSACK

Figure 5·1 6. Long Word Read Cycle Flowchart

5·1 8

SO S2 S4

ClK

A2-A31 Y Al \ AO ""\

FCO-FC2 Y S IZl ""\ .. S IZO ""\ R/W J ECS � OCS �

AS \ r OS \ r

OSACKO \ r OSACKl \ r

OBEN \ r 00-031 <

I· Read ·1 Figure 5·1 7. Long·Word Read Cycle Timing (32·Bit Data Port)

5·1 9

BUS MASTER S LAVE

Address Device

1 1 Set R/W to Read 21 Drive Function Code on FCO-FC2 31 Drive Address on AO-A31 41 Drive S IZO-SIZl lOne By tel 51 Assert ECS/OCS for One-Half Clock 51 Assert Address S trobe lAS I 71 Assert Data Strobe IDS I BI Assert Data Buffer Enable IDBENI r--- Present Data

1 1 Decode Address 21 Place Data on DO-D31 ,

D15-D23, D8-D15 , or 00-07

• I Based on AO, A 1 , and Bus Widthl Acquire Data � 31 Assert Data Transfer and Size Acknowledge I�)

1 1 Latch Data 21 Negate OS 31 Negate AS 41 Negate DBEN f-----+I Terminate Cycle I 'f 1 1 Remove Data from 00-031 I Start Next Cycle 2) Negate DSACK

Figure 5·1 8. Byte Read Cycle Flowchart

5·20

SO S2 S4 SO S2 S4 CLK

A2-A31 =::x x A1 ---:\ ! AO ---:\

FCO-FC2 =::x x SIZ1 � \ -SIZO ---:\ I R/W � ECS -U U ocs -U U AS \ ! \ r OS \ / \ r

OSACKO \ / \ DsAffi \ / \

08EN � \ / \ r 024-031 ( OP2 ) 016-023 ( OP3 ) 08-0 15 ( OP3

I· Word Read �I· Byte Read �I Figure 5·19. Byte and Word Read Cycle Timing (32·Blt Data Port)

5-21

•

5.2.2 Write Cycle

Dur ing a write cyc le, the processor sends data to memory or a peripheral device. The fu nct ion of the operand transfer mechanism dur ing a write cycle is identical to that duri ng a read cyc le. See 5.1 OPERAN D TRANSFER M ECHANISM.

A f lowchart of write cyc le operat ion for words is shown i n F igure 5-20. Byte and word write cycle t im ing is shown in F igure 5·21 . The actual write cycle t iming diagrams specif ied in terms of c lock periods and detai ls of both word and byte write cyc le operat ions are g iven in SECTION 10 ELECTRICAL SPECIFICATIONS.

BUS MASTER S LAVE

Address Device

1 1 Set R/W to Write 21 Drive Function Code on FCO·FC2 31 Drive Address on AO-A31 41 Drive Size on S IZO-S IZ1 ( Four Bytesl 51 Assert ECS/OCS for One-Half Clock 61 Assert Address Strobe (ASI 71 Assert Data Buffer Enable (oBENI 81 Place Data on Data Bus 91 Assert Data Strobes (oSI Present Data

1 1 Decode Address 21 Latch Data

Terminate Output Transfer 31 Assert Data and Size Acknowledge ( oSACKI 1 1 Negate OS 21 Negate AS 31 Remove Data from 00·031 41 Negate DBEN Terminate Cycle I • 1 1 Negate DSACK

Start Next Cycle

Figure 5·20. Write Cycle Flowchart

5.2.3 Read·Modify·Write Cycle

The read-modify-write cyc le performs a read(s), modif ies the data in the arithmet ic-log ic unit and writes the data back to the same address(es). I n the M68000 arch itectu re this process is i ndiv is ible. During the ent i re read·mod i fy·write sequence the MC68020 asserts the RMC s ignal to i nd icate that an i nd iv is ib le operation is occurr ing. The MC68020 w i l l not issue a b u s g rant (BG) i n response t o a b u s request (BR) dur ing t h i s operation.

The read-mod ify-write sequence is implemented to provide a means for secure intertask and/or i nter-processor commun ication.

The test and set (TAS) and compare and swap (CAS and CAS2) i nstructions are the only MC68020 i nstructions which ut i l ize this featu re.

5·22


A2-A31 X X Al } AD \

FCO-FC2 X X SIZl 7 \ • SIZO � ! R/W \ ECS \.J V OCS \.J U AS � ! \ r os \ ! \ r

OSACKO J \ / \ OSACKl J \ / \

OBEN \ 1\ 024-031 ) ( OP2 ) ( OP3

016-023 ) ( OP3 ) ( OP3

08-01 5 ) ( OP2 ) ( OP3

00-07 ) ( OP3 ) ( OP3

I- Word Write -I- Byte Write ·1 Figure 5·21 . Byte and Word Write Cycle Timing (32·Bit Data Port)

5-23

•

A f lowchart of the read-mod ify-write cyc le operat ion is shown i n F igure 5-22. For the CAS and CAS2 i nstruct ions, the operand read(s) and optional operand write(s) w i l l use the dynamic bus sizing and operand misal ignment capab i l it ies of the processor to transfer up to two or four long word operands respectively. Thus, w i th in both the read and write phases of the i ndiv is ib le cycle, there may be up to e ight bus cycles to different addresses. Note that th is can impact bus arbitrat ion latency if CAS or CAS2 operands are not long word a l igned in a 32-bit port. F igure 5-23 depicts posit ional c lock information for the read-modi fy-write operat ion. Actual t im ing d iagrams specif ied in terms of c lock periods are g iven in SECTION 10 ELECTRICAL SPECI FICATIONS_

BUS MASTER SLAVE

Lock Bus

11 Assert RMC

t Start Input Transfer

1 1 Drive R/W to Read 2 1 Drive Function Code on FCO-FC2 31 Drive Address on AO-A31 41 Drive S ilO-Sill 51 Assert ECS/OCS for One-Half Clock 61 Assert Address Strobe IASI 71 Assert Data Strobe IDSI 81 Assert DB EN - Present Data

1 1 Decode Address 21 Place Data on DO-D31

Terminate Input Transfer r.--- 31 Assert Data and Size Acknowledge

1 1 Latch Data IDSACKxl

2 1 Negate AS ® 31 Negate DS I f CAS2 Instruction and 41 Negate DBEN On ly One Operand Read, 51 Start Data Modification Then Go to ®; If f----. Terminate Cycle Operands Do Not Match

1 1 Remove Data from DO-D31 r- Then go to ©; Else Start Output Transfer � 21 Negate DSACK Go to ®

1 1 Set R/W to Write ® © 21 Assert ECS/OCS for One-Half Clock 31 Assert AS 41 Assert DBEN 51 Place Data on DO-D31 61 Assert Data Strobe IDS I r--- Accept Data

1 1 Store Data on DO-D31 Terminate Output Transfer � 21 Assert Data and Size Acknowlege

1 1 Negate DS IDSACKxl 21 Negate AS 31 Remove Data from DO-D31 41 Negate DBEN

--l Terminate Cycle @ 1 1 Negate DSACKx r-. If CAS2 I nstruction and

Only One Operand Written Unlock Bus The Go to @ Else

1 1 Negate RMC Go to CD .. CD I Start Next Cycle I t

Figure 5-22. Read·Modify-Write Cycle Flowchart

5-24


AO-A31 =x x FCO-FC2 =x

S llO-SIZ1 =x x R/W J \ RMC " I ECS V V AS � I \ / O S � / "--I

OSACKO "----J \ / \ OSACK1 "----J \ / \

OBEN "----J \ / \ 00-031 J---< ) (

BG

lot Indivisible Cycle

Figure 5·23. Read·Modify·Write Cycle Timing (32·Bit Port, CAS Instruction)

5·25

·1

•

•

5.2.4 CPU Space Cycles

Normal processor bus operat ions fal l i nto two d ist inct classes: those which reference program areas and those which access data areas, as defined by the function code outputs. See 4.1 FUNCTION CODE SIG NALS (FCO·FC2). A th i rd c lass of operat ion incorporates those processor fu nct ions which do not properly fal l i nto one of the above categories. These cyc les are c lass if ied as CPU space cycles (FCO-FC2 = 1 1 1 ) and i nc lude i nterrupt acknowledge, breakpo int , module operations, and coprocessor commun ications. The CPU space type is encoded on A16-A1 9 dur ing a CPU space operat ion and i nd icates the fu nct ion that the processor is performi ng. On the MC68020, four of the encod ings are i mplemented as shown in F igure 5-24.

A l l unused encod ings are reserved by Motorola for future extension of CPU space fu nctions.

5_2.4.1 I NTERRUPT OPERATION. The fol lowing paragraphs describe the recognit ion and acknowledgement of i nterrupts for the MC68020. See 6.3.1 0 Interrupts for i nterrupt process ing deta i ls.

5.2.4. 1 .1 Interrupt Levels. The M68000 arch itectu re su pports seven levels of priorit ized i nterrupts ( level seven being the h ighest priority). Devices may be chai ned external ly with in i nterrupt priority levels, al lowing an un l im ited number of devices to i nterru pt the processor. I nterrupt recogn it ion and subsequent processing is based on the encoded state of the I PLO-I PL2 control i nputs and the cu rrent processor priority set in the i nterrupt priority mask (12, 1 1 , 10) of MC68020 status reg ister. I nterrupt request leve l zero (I PLO/i15'ITII PL2 = H H H) i nd icates that no i nterru pt service is requested. When an i nterrupt level one through s ix is requested via I PLO-I PL2, the processor compares the interrupt request leve l to the i nterru pt mask in order to determ i ne whether the i nterrupt should be processed. I nterru pt requests are ignored for al l i nterrupt request leve ls that are less than or equal to the current processor priority determined by the i nterru pt mask. Level seven i nterrupts are non-maskable and are d iscussed further in 6.3.10 Interrupts.

Function Code Address Bus

I I 2 0 31 : 23 19 1 6 : 4 2 0

BreakpOint f"J11l 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 BKPT # 1 0 0 I Acknowledge� . . . . . 31

Access Level � 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 Control � . . _

31 : 15 1 3

6 o MMU REG 4 0

coprog::�r � I 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 o ! CPID 1 0 0 0 0 0 0 0 0 1 CP REG

31 : I n terruPt � 1 1 1 1 1 J 1 1 J 1 1 Acknowledge � 1 1 1 1 1 1 1 1 1

, I CPU Space Type Field

1 1 1 1 1 1 1

Figure 5·24. MC68020 CPU·Space Address Encoding

5-26

1 1 1 3 1 0

1 1 LEVEL 1 1 I

Table 5-7 shows the relat ionship between the actual requested i nterrupt leve l , the i nterrupt control l i nes ( IPLO-I PL2), and the i nterrupt mask leve ls requ i red for recogn it ion of the requested i nterrupt.

Table 5-7. Interrupt Control Line Status for Each Requested Interrupt Level and Corresponding Interrupt Mask Levels

Requested Control Line Status Interrupt Mask Level Interrupt Level I Pl2 IPLl I PLO Required for Recognition

0* High High High N/A* 1 High High Low 0 2 High Low High 0-1 3 High Low Low 0-2 4 Low High High 0-3 5 Low High Low 0-4 6 Low Low High 0-5 7 Low Low Low 0-7

* I ndicates that no interrupt is requested.

5.2.4. 1 .2 Recognition of Interrupts. To ensure that an i nterrupt w i l l be recogn ized, the fol lowing ru les should be followed:

1 ) The i ncoming i nterru pt request level must be at a h igher priority level than the mask level set in the status reg ister (except for level seven, the non-maskable i nterru Pt).

2) The I PLO-I P L2 i nterrupt control l i nes must be held at the i nterrupt request level unt i l the MC68020 acknowledges the i nterru pt . See 5.2.4.1 .3 Interrupt Acknowledge Sequence (lACK).

The above ru les guarantee that the i nterrupt w i l l be processed; however, the i nterrupt cou ld also be processed if the request is taken away before the lACK bus cyc le.

The MC68020 i nput synchron izat ion c i rcuitry for the I PLO-I PL2 control l i nes samples these i n puts on consecutive fal l i ng edges of the processor c lock in order to synchron ize and debou nce these s ig nals. An i nterrupt request that is held constant for two consecutive c lock periods is considered a val id i nput, and therefore i t is possible that an i nterrupt request that is held for as short a period as two c lock cycles cou ld be recogn ized.

I nterrupts recogn ized through the process described above do not force i mmediate except ion processing but are made pend ing . Only those i nterrupt requests which exceed the current processor priority are made pend i ng, after the synchron izat ion and debounce delay, as described previously, and w i l l cause the assert ion of I PE N D, s igna l l i ng to external devices that the MC68020 has an i nterrupt pend i ng . Exception process ing for a pendi ng i nterrupt commences at the next i nstruct ion boundary, prov id ing that a h igher priority except ion is not also val id. See 4.7.2 Interrupt Pending (I PEND).

5.2.4. 1 .3 Interrupt Acknowledge Sequence (lACK). When there is a pending i nterrupt at an i nstruct ion boundary, the MC68020 in i t iates i nterru pt process i ng , provided that no h igher priority except ions are pendi ng. See 6.2 EXCEPTION PROCESSING. I n order to correct ly service an i nterru pt request, the processor must f i rst determi ne the start ing locat ion of the i nterrupt service rout ine correspond ing to the requested service. The

5-27

•

•

M68000 Fam i ly supports acqu isit ion of th is i nformation with the i nterru pt acknowledge cyc le, dur ing which the processor acq u i res external ly, or generates i nterna l ly, the i nterrupt vector number. See 6.2.1 Exception Vectors.

The MC68020 supports acqu is it ion of the i nterrupt vector number by two methods. For those devices that have a vector reg ister, the device may pass the vector to the processor over the data bus dur ing the lACK cyc le. For those devices that cannot supply an i nterrupt vector, the MC68020 uses i nternal ly generated autovectors. The MC68020 lACK sequence is the same for both cases, but the response of the i nterrupt ing device d i ffers.

At the beg i n n i ng of the lACK cycle, the processor sets the function code and A16-A1 9 to ind icate CPU space seven , echoes the i nterrupt level being acknowledged on A1 -A3 and drives the remainder of the address bus high to i nd icate that the CPU space access is an i nterrupt acknowledge cycle. The i nterrupt ing device then either places an i nterrupt vector number on the least s ign if icant byte of its data port and asserts DSACKO/DSACK1 to i nd icate its port s ize, or it asserts AVEC to request that the processor i nternal ly generates the vector number correspond ing to the requested i nterru pt leve l . Further deta i l of the lACK cycle is provided in F igures 5-25, 5-26, and 5-27.

PROCESSOR INTERRUPTING DEVICE

Acknowledge Interrupt Request Interrupt I 1 1 Compare Interrupt Request Level with

Interrupt Mask 2) Set R/W to Read 3) Set Function Code to CPU Space 4) Place Interrupt Level on A 1, A2, and

and A3. Type Field = lACK 5) Set Size to Byte 6) Assert Address Strobe (AS) and

Data Strobe IDS ) Provide Vector Information

1 1 Place Vector Number of Least Significant Byte of Data Port ( Depends on Port Size)

2) Assert DSACKx - or -

1 1 Assert AVEC for Automatic Generation of Acquire Vector Number Vector Number

1 1 Latch Vector Number 2) Negate DS and AS Release I

, 1 ) Negate DSACKx Start Interrupt Processing I

Figure 5·25. Interrupt Acknowledge Sequence Flowchart

5-28

so S2 S4 so CLK

A4-A31 =><'--____ ---J! A1 -A3 =>< x

AO ..J.. ___ ----'y

S2 S4 so S2

\'-----Interrupt Level XI... ___ _

FCO-FC2 =>< ______ 1 \ ...... __ _

SIZ'l =>< _____ \...l....-____ L../ __ _

SIZO =>< ____ ---JI \'-__ \'---

DSACKO r---\ / \ / -.J \�___ '-__ -'

DSACK1 � / \ 1

Vector Number From 8-Bit Port

D24-D31 J------<----""-\>--< >--<= Vector Number From 16-Bit Port

D16-D23 J------<=:::::::::::::::::::::=:>--< >--<= ___ v....;e;.:.ct.;.;.,or Number From 32-Bit Port

DO-D7 )--{ >--< >--<= ru- I PL2 \ ..... ____________ y

I I Interrupt - I - . 0( • 0( Acknowledge� W"te Stack

Figure 5·26. Interrupt Acknowledge Cycle Timing

5·29

•

/

SO S2 S4 SO S2 S4 SO S2

CLK

A4-A31 -y. 7 \ Al -A3 -y. X Interrupt Level X

AO -y, 7 \ FCO-FC2 ::::x 7 \

• SIZl -y. � L SIZO -y. 7 \ R/W J \ ECS

OCS

AS

OS

OSACKO J\ / L OSACK l J\ / �

ffiiEN =-oJ \ / \ / "-00-031 -< > �

I PLO-IPL2 \ X AVEC \ /

f.---Read .. I_ Interrupt ACknOwledge� Write Stack Autovector

Figure 5·27. Autovector Operation Timing

5·30

5.2.4. 1 .4 Spurious Interrupt. I f, dur ing the i nterru pt acknowledge cycle, no device responds by assert ing OSACKO/DSACK1 or AVEC, BERR should be asserted to terminate the vector acqu is it ion. The processor separates the processing of th is error from a bus error by fetch ing the spurious i nterrupt vector instead of the bus error vector. The pro· cessor then proceeds with the usual i nterrupt exception process ing .

5.2.4. 1 .5 lACK Generation. I n order to i nform external devices that the processor is per· forming an interrupt acknowledge cycle, it is normal to generate lACK Signals for each of the seven i nterrupt leve ls. The lACK signal for a part icu lar leve l can be derived by decoding the i nterru pt level from A 1 ·A3 and qual ifying th is with the function codes h igh (CPU space), the CPU space type (A1 6·A19) high (type $F), and address strobe (AS) asserted.

5.2.4.2 BREAKPOINT ACKNOWLEDG E CYCLE. When a breakpoi nt i nstruct ion is exe· cuted, the MC68020 performs a word read from the CPU space, type 0, at an address cor· responding to the breakpoi nt number (bits [2:0] of the opcode). I f th is bus cycle is termi· nated by BERR, the processor then proceeds to perform i l legal instruct ion except ion pro· cessi ng. If the bus cyc le is term i nated by OSACKx, the processor uses the data retu rned on 016·031 (for 1 6·bit or 32·bit ports) or two reads from 024·031 (for 8·bit port) to rep lace the breakpoi nt i nstruct ion in the internal i nstruct ion p ipe l i ne, and beg ins execution of that i nstruct ion. The breakpoint operat ion f low is shown in F igure 5·28. F igures 5·29 and 5·30 show the t im ing diagrams for the breakpoint acknowledge cyc le with the instruction opcodes suppl ied on the cycle and with an exception s ignaled, respectively.

PROCESSOR EXTERNAL DEVICE

Breakpoint Acknowledge

1 ) Set R/W to Read 2) Set Function Code to CPU Space 3) Place CPU Space Type 0 on A 16-A 19 4 ) Place B reakpoint Number on A2-A4 5) Set S IZE to Word

1 1 Place Replacement Opcode on Data Bus 6) Assert AS and DS 2) Assert DSACKx

- or -1 1 Assert BERR to In itiate Exception Processing

If DSACK Asserted: 1 ) Latch Data 2) Negate AS and DS 3) Go to ®

If BERR Asserted: 1 ) Negate AS and DS 2) Go to ®

® ®

� I 1 1 1 Place Latched Data in I nstruction Pipeline Slave Negates 2) Continue Processing DSACKx or BERR

1 1 In itiate I l legal Instruction Processing

t Figure 5·28. MC68020 Breakpoint Operation Flow

5·31

-

Figure 5·29. Breakpoint Acknowledge Cycle Timing (Opcode Returned)

5·32

SO S2 S4 SO � S4

ClK SLJLJLJ1SlJLJ A20-A31 ::::x \

Breakpoint Encoding [0000] ::::x....----------\ A16-A19 '--_____ ....l_'--_____ _

Breakpoint Number

A2-A15 =><'--____ --'X'-_____ _

A1-AO \'-___________ _ FCO-FC2 ::::x y '--____ ...J

S IZ1 ::::x ____ -'7

CPU Space

Word

S IZO ::::x _____ \->--____ _

R/W J ECS V OCS V

AS

OS

v V

OSACKO r--\ / / \'--_---J

OSACK1 /\ I

1SUL I I

=x __

I := := =:J< __

\------I

� -

- --v--- - --v--

� '--

� �

- - � 016-023 --\'-___ ....J)>-------- - - � 024-031 --< ) - - �

08-015 .J----<===J)f------- - � 00-07 .J----<===})----- � BERR ] HALT ]

� Read

Breakpoint Acknowledge Bus Error _

I _I t( Asserted � I _ Exception

� Stacking

Figure 5·30. Breakpoint Acknowledge Cycle Timing (Exception Signalled)

5-33

•

•

5.2.4.3 COPROCESSOR OPERATIONS. The MC68020 coprocessor i nterface al lows for i nstruct ion·oriented com m u nicat ion between the processor and up to e ight coprocessors. The bus communicat ion requ i red to support coprocessor operations is carried out in the MC68020 CPU space.

Coprocessor accesses ut i l ize standard bus protocol except that the address bus sup· p l ies access i nformat ion rather than an address. The CPU space type f ield (A 1 6-A 1 9) for a coprocessor operat ion is 001 0. The coprocessor identif icat ion number is encoded i n A 1 3-A 1 5 and AO-A5 ind icate the coprocessor i nterface reg ister t o be accessed. The memory management un i t of an MC68020 system is always identif ied by coprocessor I D zero and has a n extended reg ister select f ie ld (AO-A?) i n CPU space 0001 for use by the CALLM and RTM access level checking mechanism .

5.2.5 Bus Error and Halt Operation

I n a bus arch itecture that req u i res a handshake from an external device to s ignal that a bus cycle is complete, the poss ib i l ity exists that the handshake might not occur. Si nce d ifferent systems requ i re different max imum response t imes, a bus error i nput is provided; see 4_9.3 Bus Error (BERR)_ External c i rcu itry must be used to determi ne the maximum duration between the assert ion of address strobe (AS) and data t ransfer and s ize acknowledge (DSACKx) before issuing a bus error s ignal . When a BERR and/or HALT s ignal is received, the processor i n it iates a bus error exception sequence or retries the bus cyc le.

In addition to a bus t imeout i nd icator, the BERR i nput is used to i nd icate an access fau lt in a protected memory scheme or a page/segment fau lt in a virtual memory system. When an external memory management unit detects an i nva l id memory access, a bus error is generated to suspend execut ion of the cu rrent i nstruction.

5.2.5_1 BUS ERRO R OPERATION. When the bus error s ignal is issued to term i nate a bus cyc le, the MC68020 may enter exception processing immediately fol lowing the bus cycle, or may defer processing the exception unt i l it needs the data that i t was attempt ing to access. Due to the h igh ly pipel i ned arch itectu re of the MC68020, the processor attempts to prefetch i nstructions ahead of the current program cou nter. If the MC68020 encounters a bus error dur ing an i nstruct ion prefetch, the processor defers bus error except ion processing unt i l the fau lted data is actual ly needed for execution. I t is poss ib le that bus error processing w i l l not take place for a fau lted access if changes in program flow (e.g . , branches) make usage of the fau lted data unnecessary.

The bus error s ignal w i l l be recognized dur ing a bus cycle in either of the fol lowing cases: 1) DSACKx and HALT are negated and BEAR" is asserted. 2) HALT and BERR are negated and DSACKx is asserted. BERR is then asserted

with in one c lock cyc le. 3) BERR and HALT asserted.

When the bus error condit ion is recogn ized, the cu rrent bus cyc le is termi nated in the normal fash ion. F igures 5-31 and 5-32 show the t im ing d iagrams for both the normal and the delayed bus error s ig nals, assuming that the except ion is taken. See 6.3.3 Bus Error for except ion processing deta i ls .

5-34

5.2.5.2 RETRY OPERATION. When, dur ing a bus cyc le, the BERR and HALT inputs are both asserted by an external device, the processor enters the retry sequence. A delayed retry may be used, s im i lar to the delayed bus error s ignal descri bed above. F igures 5-33 and 5-34 show t im ing d iagrams for both methods of retry ing the bus cycle.

DO-D31

HALT

BEAR

Sw Sw Sw S4

___________ x � � = = = )(� __ �X::: _____

_____ X = � = � = )( x::: _____ �X= = = ==y x= � ____ -----lX - - - - - )( x:::

- - - - - \ '--------

- - - - - � - - - - - �

'-----________ r - - - - - �

'---____ -----'r - - - - -

�

\ f \ f

- - - - - �'---------« ________ = = = } ---<'-------'I-/

I .. \'------/ - - - -

1 Internal I - _I Read Bus Error Detection ---i.� Processing �Stack Write �

Figure 5·31 . Bus Error Timing (Exception Taken)

5-35

•

Sw Sw S4 SO S2 S4

� ____ --'X � = = = = =:x'-___ X _____ X n - - - =:x x ____ -----'X � = = = = =x x � ____ X - - - - - =x x "-_____ ----'1- - - - - \'-___ _

- - - - - � - - - - - �

'---_______ r - - - - - � '----_---'r - - - n �

\ /- - - - - \ / \ r - - - - \ /

- - - - - � DO-D31 ----«I.-_____ ----'}_ - - u - ---«'-__ �}_

BERR I�II(-- Write Bus Error __ -.! .. I Internal Processing I- Stack Write--+l

Figure 5·32. Delayed Bus Error (Exception Taken)

5·36

SO S2 Sw S4 SO S2 S4

ClK

AO-A3l -y., x::: FCO-FC2 -y., x:::

S IZl -:x x::: S IZO =x- x::: R/W J • ECS � V \ ocs V V \

AS � / \ ! DS � / \ !

i5SACKO J \ / DSACK l J \ /

DO-D3l J--< ) < ) I PlO-IPl2 J

BERR J \ / HAlT J \ / \-Read _I· Halt _I· Rerun�

Figure 5·33. Delayed Bus Cycle Retry Timing

5·37

SO S2 Sw S4 SO S2 S4

ClK

AO-A31 :J( '£ FCO-FC2 :J( '£

S IZl :J( '£ S IZO Y '£

• R/W � ECS V V \ ocs V V \

AS � / \ I OS � / \ I

OSACKO � / \ / OSACKl � / \ /

00-031 J------< ) ( ) I PlO- IPl2 J

BERR J \ / HALT -.I \ /

I_ Read _I_ Halt _I_ Rerun ----....J Figure 5·34. Retry Operation Timing

5·38

The processor term i nates the bus cyc le, places the control s ignals i n their i nactive state and does not run another bus cyc le unt i l the BERR and HALT s ignals are negated by external logic. The processor then retries the previous cyc le us ing the same access information (address, funct ion code, s ize, etc.). The BERR s ignal should be negated before or in conj unction with the HALT s ignal .

The MC68020 imposes no restrictions on retry ing any type of bus cyc le. Spec if1cal ly, any read or write cyc le of a read-modify-write operation may be separately retried, si nce the RMC s ignal w i l l remain asserted dur ing the ent i re retry seq uence.

Systems des igners who ut i l ize the rel i nqu ish and retry operat ion (BERR, HALT, and BR asserted) must g ive spec ial cons iderat ion to the read-modify-write operat ion s i nce the MC68020 w i l l not rel i nqu ish the bus dur ing this operat ion. Any device requ i ring that the processor g ive up the bus and retry the bus operation dur ing a read-modi fy-write cycle must assert BERR and BR (HALT must not be inc l uded). The bus error handler software should exam ine the RM bit in the special status word (see 6.4.1 Special Status Word) and, i f set, the handler can take the appropriate act ion to resolve the fau lt .

5.2.5.3 HALT OPERATION. The HALT i nput s ignal to the MC68020 performs a halt/run/s ing le-step function. The halt and run modes are somewhat self explanatory i n that when the halt s ignal is constantly asserted t h e processor "halts" (does noth i ng) and when the HALT s ignal is constantly negated the processor "runs" (does someth ing). Note that the HALT s ignal on ly halts the operat ion of the external bus, not the i nternal bus and execut ion un it. Thus, a program that resides in the cache and does not req u i re use of the external bus w i l l not be affected by the HALT signal .

The s ing le-step mode is derived from correct ly t i med t ransit ions on the HALT input. I f HALT is asserted when the processor beg ins a bus cyc le and remains asserted, that bus cyc le w i l l complete, but another cyc le w i l l not be a l lowed to start. When i t is desi red to conti nue, HALT is then negated and re-asserted when the next bus cycle is started. Thus, the s ing le-cyc le mode al lows the user to proceed through (and debug) processor operat ions, one bus cyc le at a t i me.

The t im ing requ i red for correct s ing le-step operat ion is detai led in F igure 5-35. Some care must be exercised to avoid harmfu l i nteractions between the BERR and the HALT s ignals (see 5_2.5.2 RETRY OPERATION) when us ing the s ing le-cyc le mode as a debugg ing tool .

When the processor completes a bus cyc le after recogn iz ing that the HALT signal is act ive, the bus control s ignals are p laced in the i nactive state; but the address, fu nction code, s ize, and read/write l i nes remain driven.

Whi le the processor is honori ng the halt request, bus arbitration performs as usual . See 5.2.7 Bus Arbitration. That is, halt ing has no effect on bus arbitration.

The s ing le-step operat ion described above and the software trace capabi l ity a l low the system debugger to trace s ing le bus cycles, s ing le i nstructions, or changes in program f low. These processor capabi l i t ies, along with a software debugging package, g ive complete debugg ing f lex ib i l ity.

5.2.5_4 DOU BLE BUS FAU LTS_ When a bus error except ion occu rs, the processor attempts to stack several words contai n ing i nformation about the state of the mach i ne. If a

5-39

•

•

SO S2 S4 SO S2 S4 ClK JLJ1SlJl-.- I L �

AO-A31 :::x )- - ---\ x= FCO-FC2 :::x )- - ---\ x=

S ilO-S ill :::x )- - -< x= R/W � '- _ ---.I ECS V - -

�

� \J - - � AS � '- - � OS � '- - �

� - - \ I � - - \I...------JI

� - - \�--'I 00-031 J---< ____ --'>- - - ------«\.-.-____ )-

\'---- - - � \ J

\_ � \ _ J �Read ----l.�I ....... '---Halt .1 ...

(Arbitration permitted while the processor is

haltedl

Read ----.j Figure 5·35. Halt Operation Timing

bus error exception occurs dur ing the stacking operat ion, there have been two bus errors in a row. This is referred to as a double bus fault. When a double bus fau lt occurs, the pro· cessor halts and drives the HALT l ine low. Once a bus error exception has occu rred, any addit ional bus error exception occurring before the execut ion of the f i rst instruct ion of the bus error handler rout ine constitutes a double bus fau lt.

5·40

Note that a bus cyc le that is re-tried does not constitute a bus error exception and does not contribute to a double bus fault . Note also that th is means that as long as the external hardware requests it, the processor w i l l cont i nue to retry the same bus cyc le.

The occurrance of an address error, s imi lar to that of a bus error, is c lassified as an except ion that may contribute to a double bus fau lt cond it ion. See 6_3_2 Address Error_

The bus error i nput also has an effect on processor operation after the processor receives an external reset i nput. After reset, the processor reads the vector table to determine the address to start program execution and the i n it ia l value of the i nterrupt stack pointer. If a bus error or address error occurs whi le read ing the vector table (or at any time before the f i rst i nstruct ion is executed), the processor reacts as i f a double bus fau lt has occurred and halts. On ly an external reset can re-start a halted processor.

From the above conditions a double bus fau lt is defined as the occurrance of an address error or bus error during the except ion processing for an address error, bus error, or reset except ion.

5_2_6 Reset Operation

The RESET s ignal is a b id i rectional s ignal that a l lows either the processor or an external device to reset the system. Figure 5-36 is a t iming d iagram for the power-up reset operat ion.

When the RESET signal is dr iven by an external device (for a min imum of 520 c lock periods), i t is recogn ized as an ent ire system reset, i nc lud ing the processor. The processor responds by com plet ing any active bus cyc le in an orderly fash ion, and then

ClK

Plus 5 Voits -------------I===�_::;:=�'. 'rl --------VCC

�

t >520 Clocks--\ � -, t<4 Clocks ---...l Ir-------RESET IL ____________________ - I�\ � nr.'<'7rI<'7<"7r7<Cr-

-----

----r1rI1r1r7t"7'r'7'r7'<"l't'7'I�r70._x7\1 I- 4 Clocks ---...J

BUS CYC leS � � 'I C NOTES:

Bus State Unknown:

All Control Signals Inactive Data Bus In Read Mode

Figure 5-36_ External Reset Operation Timing

5-41

I S P Read Starts

•

•

read ing the reset vector table entry (vector number zero, address $00000000) and loads it i nto the interrupt stack pointer ( ISP). Vector table entry number one at address $00000004 is then read and loaded i nto the program counter. The processor i n it ia l izes the status register to a mask level of seven with the T1 /TO and M bits cleared and the S bit set. The vector base reg ister is i n it ial ized to $0000000 and the cache enable bit in the cache con· t rol register is cleared . No other reg isters are affected by the reset sequence.

When a reset i nstruction is executed, the processor drives the RESET pin for 512 clock cyc les. In this case, the processor is resett ing the rest of the system. Therefore, there is no effect on the i nternal state of the processor. A l l the internal reg isters of the processor and the status reg isters are u naffected by the execut ion of a reset i nstruct ion. A l l exter· nal devices connected to the RESET l i ne are reset at the completion of the reset i nstruc· t ion. F igure 5·37 shows the t iming i nformat ion for the i nstruction.

Note that i n order to cause an external reset in al l cases, i nc lud ing when the processor is execut ing a reset i nstruction, the RESET s ignal must be driven as an input for 520 c lock cycles. If the reset i nstruct ion w i l l not be executed, or external log ic can detect the asser· t ion of RESET by the processor and compensate for that cond it ion, the shorter assert ion of RESET of ten c lock cycles is al l that is req u i red to reset the processor.

5.2.7 Bus Arbitration

Bus arbitration is a technique used by bus master type devices to request, be g ranted, and acknowledge bus mastership. In its s implest form, the bus arbitrat ion protocol con· sists of the fol lowing:

1 . an external device asserts a bus request to the MC68020, 2. the processor asserts bus g rant to i nd icate that the bus w i l l be avai lable at the

end of the current bus cyc le, and 3. the external device acknowledges that it has assumed bus mastersh ip by assert·

ing bus g rant acknowledge.

5·42

CLK

AO-A31 Y

FCO-FC2 -y S IZl -:x

SIZO "Y. R/W J ECS 'J OCS 'J

AS i\ / oS T\. /

oSACKO �

oSACK1 �

oBEN � / 00-031 J----< ) HALf / RESET

I--Fetch--.j

/ /

.J � =x== =x== =x== =x==

� �

L "-

\ ----<C

\'--- J -l I

_ Resume Reset Interval � Normal 512 Clocks Operation

Figure 5·37. Processor Generated Reset Operation

5·43

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•

Figure 5·38 is a f lowchart showing the deta i l i nvolved i n bus arbitration for a s i ng le device. F igure 5·39 is a t im ing d iagram for the same operat ion. This techn ique al lows pro· cess ing of bus requests d ur ing data t ransfer cyc les.

PROCESSOR

I Grant Bus Arbitration

I 1 1 Assert Bus G rant (BG )

I Terminate Arbitration

I 1 1 Negate BG and Wait for BGACK to be Negated

Processor Operation I Rs-Arbitrate or Resume

I

I

I

REQUESTING DEVICE

Request the Bus

11 Assert Bus Request ( BR I

Acknowledge Bus Mastership

1 1 External Arbitration Determines Next Bus Master

21 Next Bus Master Waits for Current Cycle to Complete

31 Next Bus Master Asserts Bus Grant Acknowledge ( BGACKI to Become New Master

41 Bus Master Negates B R

Operate a s Bus Master

1 1 Perform Data Transfers ( Read and Write Cyclesl

, Release Bus Mastership

1 1 Negate BGACK

Figure 5·38. Bus Arbitration Flowchart for Single Request

I

I

I

The t i m i ng diagram shows that the bus request (BR) is negated at the t ime that bus g rant acknowledge (BGACK) is asserted. This type of operat ion is true for a system consist ing of the processor and one device capable of bus mastersh ip. I n systems having a number of devices capable of bus mastersh ip, the bus request l i ne from each device is w i re ORed to the processor. In such a system, i t is possible that there could be more than one bus request asserted s imu ltaneously.

The t im ing d iagram is F igure 5·39 shows that the bus grant (BG) s ignal is negated a few c lock cycles after the transit ion of the bus g rant acknowledge s ignal . However, if bus reo quests are sti l l pend ing after the negation of bus g rant, the processor w i l l assert another bus g rant w i th in a few c lock cycles after i t was negated. This add i t ional assert ion of bus g rant al lows external arbitrat ion c i rcu itry to select the next bus master before the current bus master has completed us ing the bus. The fol lowing paragraphs provide add it ional i n· formation about the three steps i n the arbitration process.

5·44

ClK

AO-A31 =x c= � ______ �)r--------------------� FCO-FC2 YO c= --

------�)�------------------�

SIZO/S IZl =x ) c= R/IN J r__

ECS V \.J ocs \J \.J

AS � f' � DS � /" �

DSACKO \ / DSACK1 \ /

� ______________________ �r__ /" ) DO-D31 ( '-----'

BR \ / �--------------

\'-----�/ \'-----�/

Processor 4 1 I"" .f---- DMA Device ---..J Figure 5·39. Bus Arbitration Operation Timing

5·45

I- Processor

•

•

5.2.7.1 REQUESTI NG THE BUS. External devices capable of becoming bus masters request the bus by assert ing the bus request (BR) s ignal . This is a wi re-ORed s ignal (although it need not be constructed from open-col lector devices) that i nd icates to the processor that some external device requ i res control of the bus. The processor is effect ively at a lower bus priority level than the external device and re l i nqu ishes the bus after it has completed the current bus cyc le if one has started.

I f no acknowledge is received before the bus request s ignal is negated, the processor cont i nues execut ion once i t detects that the bus request is negated. This a l lows ord i nary process ing to cont inue i f the arbitration c i rcu i t ry i nadvertently responded to noise or an external device determ i nes that it no longer req u i res use of the bus before i t has been g ranted mastersh ip .

5.2.7.2 RECEIVING TH E BUS G RANT. The processor asserts bus g rant (BG) as soon as possi ble after receipt of the bus request. Normal ly th is is immed iately fol low ing i nternal synchronization but there is one except ion to this ru le. The exception occu rs when a read-modify-write (RMW) cyc le i s i n progress. The processor w i l l not assert bus grant u nt i l the ent ire RMW cyc le i s complete. Dur ing the RMW operat ion, the RMC s ignal w i l l be asserted to ind icate that the bus is locked.

The bus g rant s ignal may be routed through a daisy-chai ned network or through a specif ic priority-encoded network. The processor is not affected by the external method of arbitration as long as the protocol is obeyed.

5.2.7.3 ACKNOWLEDG EM ENT OF MASTERSH IP. Upon receiving a bus g rant, the requesting device waits unt i l address strobe, data transfer and s ize acknowledge, and bus g rant acknowledge are negated before assert ing its own BGACK. The negation of the AS i nd icates that the previous master has completed its cyc le; the negat ion of BGACK ind icates that the previous master has released the bus. The negation of DSACKx i nd icates the previous s lave has termi nated its connect ion to the previous master. Note that i n some appl ications DSACKx m ight not enter i nto th is function. General purpose devices are then connected such that they are on ly dependent on address strobe. When bus g rant acknowledge is asserted , the device is the bus master unt i l i t negates BGACK. Bus g rant acknowledge should not be negated unt i l after a l l bus cycles requ i red by the alternate bus master are completed. Bus mastersh ip is termi nated at the negat ion of bus grant acknowledge.

The bus request from the granted device should be negated after bus g rant acknowledge is asserted . I f a bus request is st i l l pending after the assert ion of BGACK, another bus grant w i l l be asserted wi th in a few c locks of the negation of the bus grant. Refer to 5.2.7.4 BUS ARBITRATION CONTROL. Note that the processor does not perform any external bus cyc les before i t reasserts bus g rant.

5-46

5.2.7.4 BUS ARBITRATION CONTROL. The bus arbitration control un i t i n the MC68020 i s implemented with a f in ite state mach ine. As d iscussed previous ly, a l l asynchronous i n· puts to the M C68020 are i nterna l ly synchron ized i n a max imum of two cyc les of the system c lock.

As shown in F igure 5-40, i nput s ignals labeled R and A are i nterna l ly synchronized ver· s ions of the bus request and bus grant acknowledge p ins respectively. The bus grant out· put is labeled G and the i nternal three·state control s ignal T. If T is true, the address, data, and control buses are p laced in the h igh· impedance state when AS and RMC are negated. A l l S ignals are shown in pos it ive logic (active h igh) regardless of their true ac· t ive voltage leve l .

State changes occur on the next r iS ing edge of the c lock after the i nternal s igna l is va l id. Outputs change on the fal l i ng edge of the c lock after a state is reached.

A t im ing diagram of the bus arbitration sequence dur ing a processor bus cyc le is shown in F igure 5-39. The bus arbitration sequence whi le the bus is inactive (Le., execut ing i nter· nal operat ions such as a mu lt i ply i nstruction) is shown i n F igure 5-41 .

R - Bus Request A - Bus Grant Acknowledge G - Bus G rant T - Three-State Control to Bus Control Logic X - Don·t Care NOTE: The BG output will not be asserted while RMC is asserted.

5·40. Bus Arbitration State Diagram

5·47

•

�-----------4C== >--------<c==

________ r-------�c== >--------<L

----------� ____________ �r__

v v

�----------� '-------��

� __________________ __JI

�--------------------�(

'--__ -J/ '-----�/

-iI+t---Alternate Master ---+-Processor

Figure 5·41 . Bus Arbitration (Bus Inactive)

5·48

5.2.8 The Relationship of DSACK, BERR, and HALT

I n order to properly control termination of a bus cyc le for a retry or a bus error cond it ion, DSACKx, BERR, and HALT should be asserted and negated on the r ising edge of the MC68020 clock. This w i l l assure that when two signals are asserted s imu ltaneously, the requ i red setup t ime (#47) and hold t ime (#53) for both of them w i l l be met dur ing the same bus state. This, or some eq u ivalent precaution, should be designed external to the MC68020.

The preferred bus cyc le termi nations may be summarized as fol lows (case nu mbers refer to Table 5-8).

Normal Termi nation:

Halt Term i nation:

DSACKx is asserted, BERR and HALT remain negated (case 1 ). HALT is asserted at same t i me, or before DSACKx and BERR remains negated (case 2).

Bus Error Termi nation: 'B'ERR i s asserted in l ieu of, at the same t ime, or before DSACKx (case 3) or after DSACKx (case 4) and HALT remains negated; BERR is negated at the same t ime or after DSACKx.

Retry Termi nation: HALT and B'E'R'R are asserted in l ieu of, at the same t ime, or before DSACKx (case 5) or after DSACKx (case 6); BERR is negated at the same t ime or after DSACKx, HALT may be negated at the same t ime, or after BERR.

Table 5·8. DSACK, BERR, and HALT Assertion Results

Asserted on Rising

Case Control Edge of State

No. Signal N N + 2 Result

DSACKx A S Normal cycle terminate and continue. 1 BERR NA NA

HALT NA X DSACKx A S Normal cycle terminate and halt.

2 BERR NA NA Continue when FIAIT removed. HALT A/ S S

� NA/A X Terminate and take bus error trap. possibly 3 BERR A S deferred.

HAIT NA N A DSACKx A X Terminate and take bus error trap, possibly

4 BERR NA A deferred. HALT NA NA

DSACKx NA/A X Terminate and retry when HALT removed. 5 BERR A S

HALT A/ S S DSACKx A X Terminate and retry when HALT removed.

6 EiEtiR" NA A HALT NA A

LEGEND: N - the number of current even bus state (e. g . , S2, S4, etc.1 A - signal is asserted in this bus state NA - signal is not asserted in this state X - don't care S - signal was asserted in previous state and remains asserted in this state

5-49

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•

Table 5-8 deta i ls the resu l t ing bus cycle termi nation u nder various combinations of control s ignal sequences. The correct t im ing for negation of BERR and HALT should also be ut i l ized to ensure pred ictable operat ion. For the bus cyc le retry operat ion BERR must be negated prior to, or at the same t ime as HALT. DSACKx, BERR, and HALT may be negated when AS is negated. If DSACKx or BERR remain asserted i nto S2 of the next bus cyc le, this may cause i ncorrect bus operat ion.

EXAM PLE A: A system uses a watch-dog t i mer to terminate accesses to an unpopu lated address space. The t imer asserts BERR after t ime out (case 3).

EXAM PLE B: A system uses error detect ion and correct ion on RAM contents. Designer may:

a) Delay DSACKx unt i l data verif ied, and assert i3'ERR and HALT. s imu ltaneously to retry error cyc le (case 5) , or if val id assert DSACKx (case 1 ).

b) Delay DSACKx unt i l data verif ied, and assert BERR at same t ime as DSACKx if data i n error (case 3).

c) Return DSACKx prior to data veri f ication, as described in the next section. I f data is inva l id, BERR is asserted on next c lock cycle (case 4).

d) Return DSACKx prior to data veri f icat ion, if data is i nva l id assert BERR and HALT on next c lock cycle (case 6). The memory control ler may then correct the RAM prior to or dur ing the retry.

5.2.9 Asynchronous Versus Synchronous Operation

5.2.9.1 ASYNCHRONOUS OPERATION. To achieve c lock frequency i ndependence at a system level , the MC68020 can be used i n an asynchronous manner. This requ i res us ing only the bus handshake l ines (AS, DS, DSACK1 , DSACKO, BERR, and HALT) to control the data transfer. Us ing th is method, AS s ignals the start of a bus cycle and DS is used as a condit ion for val id data on a write cyc le. Decode of the size outputs and lower address l i nes A 1 and AO provide strobes which i ndicate which port ion of the data bus is active. The s lave device (memory or peri pheral) then responds by placing the requested data on the correct port ion of the data bus for a read cyc le or latch ing the data on a write cycle and assert ing data transfer and s ize acknowledge (DSACK1IDSACKO) correspond ing to the port s ize to term i nate the cycle. If no slave responds, or the access is inval id , external control logic asserts the BERR, or BERR and HALT signal(s) to abort or retry the bus cyc le.

The DSACKx s ignals are al lowed to be asserted before the data from a slave device is val id on a read cyc le. The length of t ime that DSACKx may precede data is g iven as parameter #31 , and it must be met i n any asynchronous system to insure that va l id data is latched i nto the processor. Notice that there is no max imum t ime spec if ied from the assert ion of AS to the assert ion of DSACKx. This is because the M PU w i l l i nsert wait cycles in one c lock period increments unt i l DSACKx is recogn ized as asserted.

5-50

The- BERR and/or HALT s ignals are al lowed to be asserted after the DSACKx s ignal is asserted. BERR and/or HALT must be asserted with in the t ime g iven as parameter #48 after DSACKx is asserted i n any asynchronous system to i nsure proper operat ion. If th is max imum delay t ime is violated, the processor may exh ibit errat ic behavior.

5.2.9.2 SYNCH RONOUS OPERATION. To su pport those systems which use the system clock as a S ignal to generate DSACKx and other asynchronous i nputs, the asynchronous i nput setup t ime is g iven (parameter #47), and the asynchronous i nput hold t ime is g iven (parameter #53). If th is setup and hold t ime is met for the assert ion or negat ion of an i nput, such as DSACKx, the processor is guaranteed to recognize that s ignal level on that specif ic fal l i ng edge of the system clock. However, the converse is not true - if the i nput s ignal does not meet the setup and/or hold t ime, that level is not guaranteed not to be recogn ized. In add it ion, i f the assert ion of DSACKx is recogn ized on a fal l i ng edge of the c lock, val id data w i l l be latched i nto the processor (on a read cycle) on the next fa l l i ng edge provided that the data meets the setup t ime (parameter #27). G iven th is s i tuation, parameter #31 may be ignored. Note that i f DSACKx is asserted for the requ i red wi ndow around the fa l l i ng edge of S2 (and obeys the proper bus protocol), no wait states w i l l be i ncurred and the bus cyc le w i l l run at its max imum speed of three clock periods.

In order to assure proper operat ion in a synchronous system when BERR and/or HALT is asserted after DSACKx, BERR and/or HALT must meet the setup t ime (parameter #27 A) prior to the fal l i n g edge of the clock one clock cyc le are DSACKx is recog n ized as asserted. Th is setup t ime is cr it ical for proper operat ion, and the MC68020 may exh ibit errat ic behavior if it is violated.

The ECS (early cyc le start) s ignal is provided on the MC68020 to provide the earl iest poss ible i nd ication that the processor is beg i nn ing a bus cyc le. I n a synchronous system, the ECS output can be ut i l ized to in i t iate address decode in order to provide i mproved memory access t ime. However, the ECS output i nd icates on ly that the processor may be i n it iat ing a bus cycle. The MC68020 may in i t iate a bus cyc le by dr iv ing the address, size, and function code outputs and assert ing ECS, but if the processor f inds the data in the on-ch ip i nstruction cache, the cyc le w i l l be aborted before assert ing AS.

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SECTION 6 PROCESSING STATES

This section describes the behavior of the processor dur ing i nstruction execut ion as governed by the processing state of the machi ne. The functions of the bits in the supervisor port ion of the status reg ister are explained, as wel l as the actions taken by the processor i n response to exception cond it ions.

The processor is a lways i n one of three processing states: normal, except ion, or halted . The normal process ing state occurs dur ing i nstruct ion execution, i nc lud ing the bus cyc les to fetch i nstructions and operands, and to store the results and commun icate with a coprocessor, i f necessary. The stopped cond it ion, which the processor enters when a STOP i nstruct ion is executed, is a special case of the normal state i n which no further bus cyc les are generated.

The exception processing state is assoc iated with i nterru pts, trap i nstructions, traci ng, and other except ional cond i t ions. The exception may be i nterna l ly generated by an i nstruct ion or by an u nusual cond it ion aris ing dur ing the execution of an i nstruction. Except ion processing can also be i n it iated by cond it ions external to the processor such as an i nterrupt, a bus error, a reset, or a coprocessor primit ive command. Exception processing i s designed to provide an eff icient context switch so that the processor may qu ickly and gracefu l ly hand le u nusual cond it ions.

The halted process ing state is caused by a catastrophic system fai lure. For example, i f dur ing the exception processing of a bus error another bus error occurs, the processor assumes that the system is unusable and halts. Only an external reset can restart a ha lted processor. Note, a processor i n the stopped state is not i n the halted state.

6.1 PRIVILEGE STATES

The processor operates at one of two levels of privi lege: the user level or the su pervisor level. These levels are ordered, with the supervisor level being of h igher privi lege than the user level . Not a l l processor i nstructions are permitted to execute i n the lower-privi leged user state, but all are avai lable in the supervisor state. The privi lege level can be used by external memory management devices to control and translate accesses, and i nternally by the processor in order to choose between the user stack pOi nter and the su pervisor stack poi nter dur ing operand references.

The MC68020 provides a mechanism to a l low external hardware to enforce up to 256 privi lege levels w i th in the user level of privi lege. This mechan ism is an opt ional part of the modu le cal l/return operat ions described in APPENDIX D ADVANCED TOPICS.

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6.1 .1 Use of Privilege States

The privi lege level is a mechan ism for provid ing secu rity in a computer system. User prog rams may access only their own code and data areas, and can be restricted from accessing other i nformat ion. User program behavior is more easi ly guaranteed when errors by other programs in the system cannot affect it .

The privi lege mechanism provides security by al lowing most programs to execute in user state. Here accesses are contro l led, and their effects on other parts of the system are l imited. The operat i ng system typica l ly executes in the supervisor state, has access to a l l resou rces, performs the overhead tasks for the user state programs, and coord inates their activit ies.

6.1 .2 Supervisor States

The supervisor state is the h igher privi lege state. For i nstruct ion execution, the superv isor state is determi ned by the S bit of the status register; if the S bit is set, the processor is in the supervisor state, and a l l instructions are executable. The bus cyc les generated by i nstructions that are executed in the supervisor state are normal ly classified as supervisor references, which is reflected in the va lues p laced on the function code p ins FCO·FC2.

The MC68020 al lows a m i nor d istinction of su pervisor act ivit ies, based on the M bit of the status register. The pu rpose of the M bit is to a l low separation of task related and asynchronous, I/O related su pervisor tasks, s ince in a mult i-tasking operat ing system it is more eff ic ient to have a supervisor stack space assoc iated with each user task and a separate stack space for i nterrupt assoc iated tasks. Thus, the master stack may be used to contain task control i nformation for the currently execut ing user task whi le the i nterrupt stack is used for i nterrupt task control information and temporary storage. When a user task switch is requ i red, the master stack pOinter is loaded with a new value that points to the new task context, wh i le st i l l mainta in ing a val id, i ndependent stack space for interrupts.

When the M bit is clear, the MC68020 is in the interrupt state and operat ion is the same as the MC68000, MC68008, MC68010, and MC6801 2 su pervisor state (this is the defau lt condit ion after reset). The processor uses the interrupt stack pointer ( ISP) when it references the system stack poi nter (SSP). When the M bit is set, the processor is in the master state and the processor uses the master stack poi nter (MSP) when it references the system stack pointer (SSP). Whether the M bit is set or clear does not affect execution of priv i leged i nstruct ions. The M bit may be set or c leared by an instruction that modif ies the status reg ister (MOVE to SR, ANDI to SR, EORI to SR, ORI to SR and RTE). A lso, the processor saves the M bit conf iguration and c lears it in the SR as part of the except ion processing for i nterru pts.

A l l exception processing is done in the supervisor state. The bus cyc les generated dur ing exception process ing are c lassif ied as supervisor references. A l l stacking operat ions during except ion processing use the active su pervisor stack pOi nter.

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6.1 .3 User State

The user state is the lower privi lege state. For i nstruction execution, the user state is determi ned by the S bit of the status reg ister; if the S bit is clear, the processor is ex· ecut ing i nstruct ions i n the user state.

Most i nstruct ions execute both in the user state and in the supervisor state. However, some i nstructions which have i mportant system effects are made privi leged and are restricted to use in the supervisor state. For i nstance, user programs are not permitted to execute the STOP i nstruction or the RESET i nstruct ion. To i nsure that a user program cannot enter the privi leged su pervisor state, except in a control led manner, the i nstruct ions which can mod ify the S bit in the status reg ister are privi leged. The TRAP #n i nstruction can be used to al low user program access to privi leged services performed by the operat ing system i n the supervisor state.

The bus cycles generated by an i nstruct ion executed in the user state are classif ied as user state references, as reflected by the address space val ues placed on the fu nct ion code pins (FCO-FC2). This a l lows an external memory management device to d ist ingu ish between user and supervisor activity, and to control access to protected port ions of the address map. Whi le the processor is i n the user state, those references made to either the system stack poi nter imp l ic it ly, or address reg ister seven (A7) exp l ic it ly, are always made relative to the user stack poi nter (USP).

6.1 _4 Change of Privilege State

The on ly way for the processor to change from the user to the supervisor privi lege level is through except ion process i ng, wh ich causes a change f rom the user state to one of the supervisor states and can cause a change from the master state to the i nterru pt state. Except ion processing saves the current state of the S and M bits of the status reg ister on the active supervisor stack, and the S bit is set, forc ing the processor into the su pervisor state. A lso, i f the except ion being processed is an i nterrupt and the M bit is set, it w i l l be cleared to put the processor i nto the i nterru pt state. I nstruct ion execution proceeds i n t h e su pervisor state t o hand le the exception cond it ion.

A t ransit ion from supervisor to user state can be caused by the fol lowing i nstructions: RTE, MOVE to SR, AND I to SR, and EORI to SR. The MOVE, ANDI , and EORI to SR i nstruct ions execute at the su pervisor privi lege level , and then fetch the next i nstruct ion at the next sequential program cou nter address at the new privi lege level determ i ned by the new va lue of the S bit.

The RTE i nstruct ion examines the supervisor stack contents to determine which state restorat ions are req u i red. If the frame on top of the stack was created by an i nterrupt, t rap, or i nstruction except ion, the RTE i nstruct ion fetches the saved status reg ister and program counter from the supervisor stack, and restores each i nto its respective reg ister. The processor then cont i nues execution at the restored program counter address and at the privi lege level determi ned by the S bit of the restored status reg ister.

If the frame on top of the stack was created by a fau lted bus cyc le, the RTE i nstruction restores the ent i re saved mach ine state from the stack.

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6.1 .5 Address Space Types

Address space c lassif ication is generated by the processor accord ing to the type of ac· cess requ i red dur ing each bus cycle. This a l lows external t ranslation of addresses, con· trol of access, and d ifferentiation of specia l processor states, such as i nterrupt acknowledge. Table 6·1 lists the types of accesses and their respective address space encodings.

Table 6·1 . Address Space Encodings

FC2 FC1 FCO Address Space

0 0 0 ( Undefined. Reserved) *

0 0 1 User Data Space 0 1 0 User Program Space 0 1 1 ( Undefined. Reserved) *

1 0 0 (Undefined. Reserved) *

1 0 1 Supervisor Data Space 1 1 0 Supervisor Program Space 1 1 1 CPU Space

* Address space 3 IS reserved for user definition. while 0 and 4 are reserved for future use by Motorola.

User program and data accesses have no predefi ned memory locations. The supervisor data space also has no predefi ned locat ions. Dur ing reset, the f i rst two long words at memory locat ion zero in the su pervisor program space are used for processor i n it ial iza· t ion. No other memory locat ions are expl ic it ly defined by the processor.

6.1 .6 CPU Space

The CPU space is not intended for general instruct ion execut ion, but is reserved for pro· cessor functions; that is, those bus cyc les in which the processor must communicate with external devices for reasons beyond normal data movement assoc iated with in· structions. For example, al l M68000 processors use the CPU space for i nterrupt acknowledge cyc les. The MC68020 also makes CPU space accesses for breakpoi nts, coprocessor operations, and to support the module cal l/return mechan ism.

Although the MOVES i nstruction can be used to generate CPU space bus cyc les, this may i nterfere with proper system operat ion. Thus, the use of MOVES to access the CPU space should be done with caution.

6.2 EXCEPTION PROCESSI NG

A general descript ion of exception process ing is f i rst presented to i nt roduce the con· cepts of i nterrupts, traps, and t rac ing . Exception process ing for coprocessor detected er· rors is not d iscussed i n th is sect ion; refer to SECTION 8 COPROCESSOR INTERFACE DESCRIPTION for more deta i ls on coprocessor exception hand l ing.

The process ing of an exception occurs in fou r steps, with variations for d ifferent excep· t ion causes. Dur ing the f i rst step, a temporary i nternal copy of the status reg ister is made, and the status reg ister is set for exception process i ng . In the second step, the ex· cept ion vector is determ i ned, and in the th i rd step, the cu rrent processor context is saved. I n the fou rth step a new context is obtained, and the processor then proceeds wi th i nstruction process i ng.

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6.2.1 Exception Vectors

The vector base reg ister points to the base of the 1 K byte exception vector table contain· ing the 256 exception vectors. Exception vectors are memory poi nters used by the processor to fetch the address of rout i nes which wi l l handle various except ions. A l l except ion vectors are one long word in length, except for the reset vector, which is two long words i n length.

Exception vectors are selected by 8·bit vector nu mbers generated during exception pro· cess i ng . This vector nu mber is mu l t ip l ied by four to form the vector offset, which is added to the vector base reg ister to obtai n the address of the vector. A l l except ion vectors are located in supervisor data space, except the reset vector which is located i n superv isor program space. Vector n umbers are generated i nternally or external ly, depending on the cause of the except ion. Table 6·2 provides the ass ignments of the exception vectors.

Table 6·2. Exception Vector Assignments (Sheet 1 of 2)

Vector Vector Offset

Number(s) Hex Space Assignment

a ()()() SP Reset: Init ial Interrupt Stack Pointer 1 004 S P Reset: Init ial Program Counter 2 008 S O Bus Error 3 OOC S O Address Error 4 0 10 S O Illegal Instruction 5 0 14 S O Zero Divide 6 0 18 S O C H K , C H K 2 Instruction 7 0 1 C S O cpTRAPcc, TRAPcc, TRAPV Instructions 8 020 S O Privilege Violation 9 024 S O Trace

10 028 S O Line 1 0 1 0 Emulator 1 1 02C S O Line 1 1 1 1 Emulator 1 2 030 S O (U nassigned, Reserved) 1 3 034 S O Coprocessor Protocol Violation 14 038 S O Format Error 1 5 03C S O Uninitial ized I nterrupt 1 6 040 S O } ( Unassigned, Reserved) Through 23 05C S O 24 060 S O Spurious Interrupt 25 064 S O Level l Interrupt Auto Vector 26 068 S O Level 2 Interrupt Auto Vector 27 06C S O Level 3 Interrupt Auto Vector 28 070 S O Level 4 Interrupt Auto Vector 29 074 S O Level 5 Interrupt Auto Vector 30 078 S O Level 6 Interrupt Auto Vector 31 07C S O Level 7 Interrupt Auto Vector 32 080 S O } TRAP #0- 1 5 Instruction Vectors Through 47 aBC SO 48 OCO S O FPCP Branch o r Set o n Unordered Condition 49 OC4 S O FPCP I nexact Result 50 OC8 S O F P C P Divide b y Zero 51 OCC SO FPCP Underflow 52 000 S O F P C P Operand Error 53 004 S O FPCP Overflow 54 008 S O FPCP Signaling NAN 55 OOC S O Unassigned, Reserved 56 OEO SO PMMU Configuration 57 OE4 SO PMMU I l legal Operation

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Table 6·2. Exception Vector Assignments (Sheet 2 of 2)

Vector Numberis) Hex

58 DES 59 DEC

Through 63 DFC 64 100

Through 255 3FC

S P = Supervisor Program Space SD = Supervisor Data Space

Vector Offset

Space Assignment

SD PMMU Access Level Violation S D } Unassigned, Reserved SD SD } User Defined Vectors 1 1921 SD

As shown i n Tab le 6-2, 1 92 vectors are reserved for user def i nit ion as i nterrupt vectors and 64 are defi ned by the processor. However, there is no protection on the f i rst 64 vectors, so that external devices may use vectors reserved for internal purposes at the d iscret ion of the system designer.

6.2.2. Exception Stack Frame

Except ion processing saves the most volat i le port ion of the current processor context on the top of the supervisor stack. Th is context is organized in a format cal led the exception stack frame. This i nformation always inc ludes the status reg ister, the program cou nter, and the vector offset used to fetch the vector. The processor also marks the frame with a frame format. The format f ield a l lows the RTE instruct ion to ident ify what i nformat ion is on the stack so that i t may be properly restored and the stack space deal located. The general form of the except ion stack frame is i l l ustrated in F igure 6-1 . Refer to 6.5 MC68020 EXCEPTION STACK FRAM ES for a complete l ist of except ion stack frames.

15 12 D

SP - Status Register

Program Counter

Format I Vector Offset

Additional Processor State I nformation 12, 6, 12, or 42 Words, if Needed)

Figure 6-1 . Exception Stack Frame

6.2.3 Exception Types

Exceptions can be generated by either i nternal or external causes. The external ly generated except ions are i nterru pts, bus errors, reset, and coprocessor detected errors. I nterrupts are requests from peripheral devices for processor action, whi le the bus error and reset p ins are used for access control and processor restart. The i nternal ly generated except ions are caused by instruct ions, address errors, t raci ng, or breakpoi nts. The TRAP, TRAPcc, TRAPV, cpTRAPcc, CH K, CH K2, CALLM, RTM , RTE, and DIV instruct ions a l l can generate exceptions as part of their i nstruct ion execution. I n add it ion, i llegal i nstruct ions, address error, privi lege violations, and coprocessor protocol violat ions cause exceptions.

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6.2.4 Exception Processing Sequence

Exception processing occurs in four ident if iable steps. Dur ing the f i rst step, an i nternal copy is made of the status reg ister. After the copy is made, the processor state bits in the status reg ister are changed. The S bit is set, putt ing the processor i nto the supervisor privi lege state. The T1 and TO bits are c leared, which al lows the exception handler to execute unh i ndered by trac ing . For the reset and i nterrupt exceptions, the i nterrupt priority mask is also updated.

In the second step, the vector number of the exception is determi ned. For i nterrupts, the vector nu mber is obtai ned by a processor read from CPU space $F, which is def i ned as an i nterru pt acknowledge cycle. For coprocessor detected exceptions, the vector number is inc luded in the coprocessor except ion pr imit ive response. (Refer to SECTION 8 COPROCESSOR INTERFACE DESCRIPTION for a complete d iscussion of coprocessor except ions.) For a l l other except ions, i nternal logic provides the vector number. This vector number is then used to generate the address of the except ion vector.

For a l l except ions other than reset, the th i rd step is to save the current processor context. An exception stack f rame is created and f i l led on the act ive su pervisor stack. Other i nformat ion may also be stacked, depend ing on which exception is be ing processed and the context of the processor prior to the exception. I f the exception is an i nterrupt and the M bit is set, the M bit is cleared, and a second stack frame is created on the i nterrupt stack.

The last step is the same for a l l except ions. The exception vector offset is determ i ned by mult ip ly ing the vector number by four. This offset is then added to the contents of the vector base reg ister to determine the memory address of the except ion vector. The pro· gram counter value (and ISP for the reset except ion) is loaded with the value in the except ion vector. The i nstruct ion at the address g iven in the exception vector is fetched, and normal i nstruct ion decod ing and execution is resumed.

6.2.5 Multiple Exceptions

The fol lowing paragraphs descr ibe the processing that occurs when mu lt iple exceptions arise s imu ltaneously. Exceptions can be g rou ped accord ing to their characteristics and priority, as shown in Table 6-3.

The priority relat ionship between two except ions determi nes which is processed f i rst if both exceptions occur s imu ltaneously. The term 'process' in th is context means the execut ion of the fou r steps previously defi ned:

1) change processing states i f needed, 2) determine exception vector, 3) save old context, and 4) load new context, i nc lud ing the f i rst three i nstruct ion words at the new program

counter locat ion. 'Process' i n th is context does not i nc l ude the execution of the rout ine poi nted to by the fetched vector. As soon as the MC68020 has completed processing for an exception, i t is then ready to beg i n execut ion of the except ion handler rout ine, or beg i n exception proceSS ing for other pend ing exceptions. Also, a h igher priority except ion can be processed before the completion of exception processing for lower priority except ions (for example,

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Table 6·3. Exception Groups

Groupl Exception and

Priority Relative Priority Characteristics

0 0.0- Reset Aborts all processing ! instruction or exception) and does not save old context. 1 1 .0-Address Error Suspends processing ( instruction or exception) and saves internal context.

1 . 1 - Bus Error 2 2.0- BKPT #n, CALLM, CHK , Exception processing i s part o f instruction execution.

C H K2, cp Mid-Instruction, Cp Protocol Violation, cp TRAPcc, Divide-by-Zero, RTE, RTM, TRAP #n, TRAPV

3 3.0- l I legal Instruction, Line A , Exception processing begins before instruction is executed. Unimplemented Line F, Privilege Violation, cp Pre-Instruction

4 4.0- cp Post-Instruction Exception processing begins when current instruction or previous exception 4. 1 - Trace processing is completed. 4.2 - Interrupt

0.0 is the highest priority, 4.2 is the lowest.

if a bus error occurs dur ing the processing for a t race exception, the bus error w i l l be processed and hand led before the t race exception processing is completed). However, most exceptions cannot occur dur ing except ion processing. Furthermore, very few combi nat ions of the exceptions shown in Table 6-3 can be pending s imu ltaneously.

This priority scheme is very important i n determin ing the order i n which exception handlers are executed in m u lt ip le exception situations. As a general ru le, the lower the priority of an except ion, the more qu ickly the handler routine for that except ion w i l l be ex· ecuted. For example, if s imu ltaneous trap, t race, and i nterrupt exceptions are pend ing, the t rap exception is processed f i rst, fol lowed immediately by except ion process ing for the trace and then the i nterrupt. Thus, when the processor f inal ly resumes normal i nstruction execution, it is i n the i nterrupt hand ler, which returns to the trace hand ler, which retu rns to the trap except ion handler. An exception to this ru le is the reset exception, which is the h ighest priority and also the f i rst except ion handled, s ince a l l other exceptions are c leared by the reset condition.

6.3 EXCEPTION PROCESSI NG: DETAIL

Except ions have a number of sou rces, and each exception has characteristics which are un ique to it. The fol lowing paragraphs detai l the sou rces of except ions, how each arises, and how each is processed.

6_3_1 Reset

The RESET input provides the h ighest level of exception. The RESET S ignal provides for system i n i t ia l izat ion and recovery from catastrophic fa i l u re. Any processing in progress at the t ime of the reset is aborted, and cannot be recovered. The status reg ister is i n it ial ized: t rac ing is d isabled (both trace bits are c leared), su pervisor interru pt state is entered (the supervisor bit is set and the master bit is cleared), and the processor interru pt priority mask is set to the h ighest priority level (level seven). The vector base reg ister and cache control reg ister are in it ia l ized to zero ($00000000). A vector number is i nter· nal ly generated to reference the reset exception vector at offset zero in the su pervisor

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program address space (which is two long words instead of the normal one long word). Because no assumptions can be made about the val id ity of any reg ister contents (in part icu lar the supervisor stack pointer) neither the program counter nor the status reg ister is saved. The address contained in the f i rst long word of the reset except ion vector is fetched for use as the in it ia l interrupt stack pointer, and the address i n the second long word of the reset exception vector is fetched for use as the init ial program counter. Prog ram execution then starts at the address loaded into the program counter.

The reset i nstruction does not affect any internal reg isters, but it does assert the RESET l ine, thus resetting a l l external devices. This al lows software to reset the system to a known state and then cont inue processing at the next i nstruction.

6.3_2 Address Error

Address error exceptions occur when the processor attempts to prefetch an i nstruct ion from an odd address. The affect is much l i ke an internal ly generated bus error, so that the bus cycle is not executed and the processor beg ins except ion processing. After exception processing commences, the sequence is the same as that for bus error except ions as described i n 6.3.3 Bus Error, except that the vector offset i n the stack frame refers to the address error vector. Also, i f an address error occurs dur ing the exception processing for a bus error, address error, or reset, the processor is halted.

6.3.3 Bus Error

Bus error except ions occur during a bus cyc le when external log ic aborts the cycle by assert ing the BERR input. I f the aborted bus cycle i s a data space access, the processor immediately beg ins exception processing. If the aborted bus cycle is an i nstruction prefetch, the processor delays taking the exception (the processor w i l l wait unt i l the results of the aborted bus cyc le are requ i red for further instruction execut ion, and then takes the except ion).

Except ion processing for a bus error fol lows the usual sequence of steps. The status reg ister is copied, the supervisor state is entered, and t racing is d isabled. A vector number is generated to refer to the bus error vector. The vector offset, program counter, and the copy of the status reg ister are then saved on the stack, in addition to i nformat ion describing the non-user visible i nternal reg isters of the processor. This add it ional i nformation is requ i red to recover f rom the bus fau lt, s i nce the processor may be in the m iddle of execut ing an i nstruct ion when the fau lt is detected. The saved program cou nter va lue is the address of the instruction that was executing at the t ime the fau lt was detected. This is not necessari ly the instruction that generated the bus cyc le, due to the overlapped execution al lowed by the processor. The i nternal state information included in the stack frame contains suff icient i nformat ion to determine the cause of the bus fault and recover from the error.

For improved effic iency, the MC68020 su pports two d i fferent bus error stack frame formats as shown in F igures 6-7 and 6-8. If the bus error occurs in mid-instruction, the processor saves its ent i re state in order to properly cont inue execution of the i nstruct ion after the bus error is corrected. I f the bus error is taken as the processor is beg inn ing execution of an i nstruction, the processor can save a much smal ler amount of i nformat ion

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about the fai led cyc le i n order to cont i nue execut ion of that i nstruct ion when the except ion handler returns. The two bus error stack frames are d ist ingu ished by the stack frame format code (refer to 6_5 MC68020 STACK FRAM ES for add it ional i nformat ion).

I f a bus error occurs dur ing the exception process ing for a bus error, address error, or reset, or wh i le the processor is load ing i nternal state i nformation from the stack dur ing the execut ion of an RTE i nstruction, the processor enters the halted state. Th is s impl if ies the detect ion of catastrophic system fai lu res, s i nce the processor removes itself from the system rather than modifying the current state of the stacks and memory. Only an external RESET can restart a processor halted due to a double bus fau lt .

6.3_4 Instruction Traps

Traps are exceptions caused by i nstruct ion execution. They arise e ither from processor recogn it ion of abnormal cond it ions dur ing i nstruction execut ion, or from use of the specif ic i nstructions whose normal behavior is to cause an except ion.

Except ion processing for traps fol lows the same steps out l ined previous ly. The status reg ister is copied i nternal ly, the supervisor state is entered, and the trace b i ts are c leared. Thus, if trac ing was enabled when the trap caus ing i nstruct ion began execution, a t race except ion w i l l be generated by the i nstruct ion, but the trap handler rout ine wi l l not be t raced (the trap exception w i l l be processed f i rst, then the t race except ion). A vector nu mber is i nternal ly generated; for the TRAP #n i nstruction, part of the vector number comes from the i nstruct ion itself. The t rap vector offset, the program cou nter, and the copy of the status reg ister are saved on the supervisor stack. The saved value of the prog ram counter is the address of the i nstruct ion after the i nstruction which generated the t rap. For a l l i nstruction t raps other than TRAP #n, a poi nter to the instruct ion which caused the trap is also saved. F inal ly, i nstruct ion execution commences at the address contained in the exception vector.

Certain i nstructions are used specif ical ly to generate traps. The TRAP #n i nstruct ion always forces an except ion, and is usefu l for implement ing system cal l s for user prog rams. The TRAPcc, TRAPV, cpTRAPcc, CHK, and CHK2 i nstruct ions force an except ion i f the user program detects a ru nt ime error, which may be an arithmetic overflow or a subscript value out of bou nds. The D IVS and DIVU i nstructions w i l l force an exception i f a div is ion operation is attempted with a d ivisor of zero. The CALLM and RTM i nstructions w i l l cause a format error i f an i l legal privi lege change is requested or i nval id parameters are present i n the type or opt ion f ields.

6.3_5 Breakpoints

I n order to use the MC68020 in a hardware emu lator, it must provide a means of i nsert ing breakpoi nts i nto the target code, and then g ive a c lear annou ncement of when i t has reached a breakpoint . For the MC68000 and MC68008, th is can be done by i nsert ing an i l legal i nstruct ion at the breakpoint and detect ing when the processor fetches from the i llegal i nstruction except ion vector locat ion. Since the vector base reg ister on the MC6801 0, MC6801 2, and MC68020 al lows arbitrary relocat ion of the except ion vectors, the exception vector address cannot serve as a re l iable ind icator that the processor is tak ing the breakpoint. On the MC68010, MC68012 , and MC68020, th is function is provided by extend ing the funct ional i ty of a set of the i l legal i nstructions, $4848-$484F, to serve as

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breakpoint i nstructions. The breakpoi nt fac i l ity also al lows external hardware to mon itor the execution of a program res id ing in the on-chip cache, w ithout severe performance degradation.

When a breakpoi nt i nstruction is executed, the MC68020 performs a read from CPU space $0 at an address corresponding to the breakpoint number. Refer to Figure 5-24 for the CPU space $0 encod i ng. If this bus cycle is terminated by BERR, the processor then proceeds to perform i l legal i nstruction exception processing. If the bus cycle is termi nated by DSACKx, the processor uses the data returned to replace the breakpoi nt i nstruction i n the i nternal i nstruction p ipe, and beg ins execution of that i nstruction.

6.3.6 Format Error

J ust as the processor checks that prefetched i nstructions are va l id, the processor (with the aid of a coprocessor, i f needed) also performs some checks of data values for control operat ions, i nc lud ing the type and option fields of the descr iptor for CALLM , the coprocessor save area format for cpRESTORE, and the stack format for RTE and RTM .

The RTE i nstruction checks the val id ity of the stack format code, and i n the cases of the bus cycle fau lt formats, the va l id ity of the data to be loaded i nto the various i nternal reg isters. The only data item checked for val id ity is the version number of the processor that generated the f rame. This check ensures that the processor is not making erroneous assumptions about internal state i nformation in the stack f rame.

The CALLM and RTM both check the val ues in the option and type fields in the module descriptor and modu le stack frame, respectively. I f these fields do not contain proper values, or if an i l legal access r ights change request is detected by an external memory management un it, then an i l legal ca l l or return is being requested and is not executed. Refer to APPENDIX D.1 MODULE SUPPORT for more i nformation on the module cal l/return mechanism.

The cpRESTORE i nstruction passes the format f ield of the coprocessor save area to the coprocessor for validation. If the coprocessor does not recog n ize the format va lue, it i n· d icates th is to the main processor, and the MC68020 w i l l take a format error except ion. Refer to 8.1 5 EXCEPTION PROCESSING for deta i l s of coprocessor related except ions.

I f any of these checks determine that the format of the control data is improper, the processor generates a format error except ion. This exception saves a short format excep· t ion frame, and then cont inues execution at the address contained in the format except ion vector. The stacked program counter is the address of the i nstruct ion that detected the format error.

6.3.7 I l legal or Unimplemented Instructions

An i l legal i nstruct ion is any of the word bit patterns which do not correspond to the bit pattern of the fi rst word of a legal MC68020 i nstruct ion, or a MOVEC i nstruction with an undefi ned reg ister specif icat ion field in the f i rst extension word. The word patterns with bits [1 5: 1 2] equal to 1 0 1 0 are d ist ingu ished as un implemented instruct ions, referenced to as A-l i ne opcodes. During i nstruction execution, when an attempt is made to execute an

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i l legal i nstruction, an i l legal i nstruction except ion occurs. Un implemented i nstructions ut i l ize separate except ion vectors, permitt ing more efficient emu lation of un implemented i nstruct ions.

The word patterns with bits [1 5: 1 2] equal to 1 1 1 1 (referred to as F- l i ne opcodes) are used for coprocessor i nstructions, but may generate an un implemented instruction except ion. When the processor encou nters an F- l i ne i nstruction, it f i rst ru ns a bus cyc le referencing CPU space 2 and addressing one of eight coprocessors. I f no coprocessor responds to the bus cycle and the access is term i nated with a bus error, the processor w i l l proceed with un implemented i nstruct ion except ion processing and fetch the F- l i ne emulator vector. Thus, the function of the coprocessor may be emulated. Refer to SECTION 8 COPROCESSOR INTERFACE DESCRIPTION for more detai ls.

Except ion processing for i l legal and u n i mplemented i nstructions is s im i lar to that for t raps. After the i nstruction is fetched and decoded, the processor determi nes that execution of an i l legal or un implemented i nstruction is being attempted and starts exception processing before execut ing the i nstruction. The status reg ister is copied, the supervisor state is entered, and t rac ing is d isabled. A vector number is generated to refer to the i l legal i nstruct ion vector, or i n the case of un implemented i nstruct ions, to the correspond ing emu lation vector. The i l legal or un implemented i nstruction vector offset, cu rrent program counter, and copy of the status reg ister are saved on the supervisor stack, with the saved value of the program counter being the address of the i l legal or un implemented i nstruction. Final ly, i nstruction execut ion resumes at the address contained in the except ion vector.

6_3.8 Privilege Violations

In order to provide system security, certain i nstructions are privi leged (see Table 6-4). An attempt to execute one of the privi leged instructions whi le in the user privi lege state w i l l cause a n except ion. Also, a privi lege violat ion may occur i f a coprocessor requests a privi lege check and the processor is in the user state.

Table 6-4. Privileged Instructions

ANDI to S A MOVEC EOAI to SA MOVES cpAESTOAE OA I to SA cpSAVE A ESET MOVE from SR RTE MOVE to S A STOP MOVE USP

Except ion processing for privi lege violations is s imi lar to that for i l legal i nstruct ions. After the i nstruct ion is fetched and decoded, the processor determ i nes that a privi lege violation is being attempted, and the processor starts except ion process ing before executing the i nstruct ion. The status reg ister is copied, the supervisor state is entered, and t racing is d isabled. A vector number is generated to reference the privi lege violation vector; the privi lege violation vector offset, current program counter, and the status reg ister are saved on the supervisor stack. The saved value of the program counter is the address of the f i rst word of the i nstruct ion which caused the privi lege violation. Fi nal ly, i nstruc· t ion execut ion resumes at the address conta i ned i n the privi lege violation exception vector.

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6.3.9 Tracing

To aid in program development, the M68000 processors i nclude a fac i l ity to al low i nstruct ion-by-i nstruction t rac ing . The MC68020 also al lows tracing of i nstructions that change program f low. I n the trace mode, a t race exception is generated after an i nstruct ion is executed, a l lowing a debugger program to monitor the execution of a program under test.

The trace fac i l ity uses the T1 and TO b its in the supervisor port ion of the status reg ister. If both T bits are c lear, tracing is d isabled, and i nstruction execution proceeds normal ly. I f the T1 b i t is c lear and the TO b i t is set a t the beg i nn ing of the execution of an i nstruction, and that i nstruction causes the program counter to be updated in a non-sequential manner, a t race exception w i l l be generated after its execution is completed. I nstructions that w i l l be t raced i n this mode i nc lude al l branches, j umps, i nstruct ion traps, returns, status reg ister manipulat ions (Si nce the processor must refetch any words that may have been prefetched from the supervisor program space rather than user program space), and coprocessor general i nstructions that modify the program counter flow. I f the T1 bit is set and the TO bit is c lear at the beg i nn ing of the execut ion of any i nstruction, a t race except ion w i l l be generated after the execution of that instruct ion is completed. See Table 6-5.

Table 6-5. Tracing Control

TI TO Tracing Function

0 0 No Tracing 0 1 Trace on Change of Flow (BRA, JMP, etc.1 1 0 Trace on Instruction Execution (Any I nstructionl 1 1 Undefined, Reserved

I n general terms, a t race except ion can be viewed as an extension to the function of any i nstruction. Thus, i f a trace exception is generated by an i nstruction, the execution of that i nstruct ion is not complete unt i l the trace except ion process ing associated with i t is completed. I f the i nstruction does not complete execution due to a bus error or address error exception, t race exception processing is deferred unt i l after the execution of the suspended i nstruct ion is resumed (by the associated RTE), and the instruction execut ion is completed normal ly. I f the i nstruction is executed and an i nterru pt is pend ing on com· pletion, the trace exception processing is completed before the interrupt exception processing starts. If, dur ing the execut ion of the i nstruction, an except ion is forced by that i nstruction, the forced except ion is processed before the t race except ion is processed,

I f the processor is in the trace mode when an attempt is made to execute an i l legal or u n i mplemented i nstruction, that i nstruction w i l l not cause a trace s i nce it is not executed. Th is is of part icu lar importance to an i nstruct ion emu lation rout ine that performs the i nstruction function, adjusts the stacked program counter to beyond the un implemented i nstruct ion and then returns. Before the return is executed, the status reg ister on the stack should be checked to determine if tracing is on; and if so, then the trace exception processing should also be emu lated in order for the trace except ion hand ler to accou nt for the emu lated instruction.

The except ion processing for a t race starts at the end of normal process ing for the traced i nstruction, and before the start of the next i nstruction, An i nternal copy is made of the status reg ister. The transition to supervisor state is made, and the T bits of the

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status reg ister are cleared, d isab l ing further t rac ing . A vector number is generated to reference the t race exception vector. The address of the i nstruct ion that caused the trace except ion, the trace exception vector offset, program counter, and the copy of the status reg ister are saved on the su pervisor stack. The saved value of the program counter is the address of the next i nstruction to be executed. I nstruct ion execution resumes at the address contained in the t race exception vector.

Note that there is one case where trac ing affects the normal operat ion of one instruction. I f the STOP i nstruction beg ins execut ion with T1 = 1, a trace exception w i l l be taken after the STOP i nstruction loads the status reg ister. Upon return from the trace handler rout i ne, execution w i l l cont i nue with the instruction fol lowing the STOP, and the processor w i l l never enter the stopped cond it ion.

6_3_1 0 Interrupts

Except ion processing can be caused by external devices request ing service through the i nterru pt mechan ism described i n 5_2.4.1 INTERRUPT OPERATION. I nterrupt requests arrivi ng at the processor through the IPLO-I PL2 pins do not force immed iate except ion processing, but may be made pend ing . Pending i nterru pts are serviced between i nstruction execution, at the end of exception process i ng , or when permitted during coprocessor i nstructions. If the priority of the requested i nterru pt is less than or equal to the current i nterrupt mask level , execut ion cont inues with the next instruction and the i nterru pt request is ignored. (The recognit ion of level seven is s l ight ly d i fferent, as expla i ned below.) I f the priority of the requested i nterru pt is g reater than the current i nterrupt mask level it is made pend ing and exception processing w i l l beg i n at the next i nstruct ion bou ndary.

Exception processing for i nterrupts fol lows the same steps as previously out l ined. F i rst, an i nternal copy of the status reg ister is made, the privi lege state is set to supervisor, trac ing is suppressed, and the processor i nterru pt mask level is set to the level of the i nterrupt being serviced . The processor fetches a vector number from the i nterrupt ing device, classify ing the bus cyc le as an interrupt acknowledge and d isplaying the level number of the i nterrupt being acknowledged on p ins A 1 -A3 of the address bus. I f the vector nu mber is not generated by the interrupt ing device, external logic requests automat ic vectoring and the processor internally generates a vector number which is determi ned by the i nterru pt level number. However, if external log ic ind icates a bus error, the i nterru pt is taken to be spurious, and the generated vector number refers to the spurious interrupt vector.

Once the vector number is obtai ned, the processor proceeds with the usual exception processing, saving the exception vector offset, program cou nter, and status reg ister on the su pervisor stack. The saved value of the program counter is the address of the i nstruct ion which wou ld have been executed had the i nterrupt not been present. I f the i nterrupt was recognized during the execution of a coprocessor i nstruction, further i nternal i nformat ion is saved on the stack so that the MC68020 can conti nue execut ing the coprocessor i nstruction when the i nterru pt handler completes execution. I f the M bit of the status reg ister is set, the M bit is cleared and a throwaway except ion stack frame is created on top of the interrupt stack. Th is second frame contains the same program cou nter and vector offset as the frame created on top of the master stack, but has a format number of $1 instead of $0 or $9. The status reg ister w i l l be the same as that p laced on the master stack except that the M and S bits w i l l be set. The content of the except ion

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vector correspond ing to the vector number previously obtai ned is fetched and loaded i nto the program counter, and normal i nstruct ion execution resumes i n the i nterrupt handler rout ine.

Priority level seven is a spec ial case. Level seven i nterru pts cannot be inh ibited by the i nterru pt priority mask, thus, provid i ng a non-maskable i nterru pt capabi l ity. An i nterru pt request is generated each t ime the i nterrupt request level changes from some lower level to level seven. Note that a leve l seven i nterrupt may also be caused by level comparison if the request level and mask level are at seven and the priority mask is then set to a lower level (e.g . , with the MOVE to SA or ATE i nstruct ions).

Most M68000 Fami ly peripherals provide for programmable i nterrupt vector nu mbers to be used in the i nterru pt request/acknowledge mechanism of the system. If th is vector number is not i n it ia l ized after reset and the peripheral must acknowledge an i nterrupt request, the peripheral returns the vector number for the u n i n it ial ized i nterrupt vector, $OF .

6_3_1 1 Return From Exception

After exception stacking operat ions have been completed for a l l pend ing except ions, the processor resu mes normal i nstruction execution at the address contai ned in the vector referenced by the last exception to be processed. Once the except ion handler has completed execut ion, the processor must retu rn to the system context prior to the except ion ( i f possi ble). The mechanism used to accompl ish th is retu rn for any except ion is the ATE i nstruction.

When the ATE i nstruct ion is executed, the processor exami nes the stack frame on top of the act ive su pervisor stack to determ ine i f it is a val id frame and what type of context restoration shou ld be performed. The actions taken by the processor for each of the stack frame types is descri bed below. Aefer to 6_5 MC68020 EXC EPTI ON STACK FRAMES for the format of each frame type.

For a normal four word frame, the processor updates the status reg ister and program counter with the data pu l led f rom the stack, i ncrements the stack pointer by eight, and resumes normal i nstruction execution.

For the throwaway four word stack, the processor reads the status reg ister from the frame, i ncrements the active stack poi nter by eight, loads the SA with the previously read value, and then beg ins ATE processing again . This means that the processor reads a new format word from the stack frame on top of the act ive stack (wh ich may or may not be the same stack used for the previous operat ion) and performs the proper operations correspond ing to that format. In most cases, the throwaway frame w i l l be on the i nterru pt stack and when loaded, the S and M bits w i l l be set. Then, there w i l l be a normal fourword frame or a ten-word coprocessor mid-i nstruct ion frame on the master stack.

However, the second frame may be any format ( inc lud ing another throwaway frame) and may reside on any of the three system stacks.

For the six word stack frame, the status reg ister and program cou nter are updated from the stack, the active su pervisor stack poi nter is i ncremented by twelve, and normal instruction execution resumes.

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For the coprocessor m id· i nstruction stack frame the status reg ister, program cou nter, i n· struction address, i nternal reg isters, and eva luated effective addresses are pu l led from the stack and are restored to the correspond ing i nternal reg isters, and the stack poi nter is incremented by twenty. Then the processor reads from the response reg ister of the coprocessor that generated the except ion to determ i ne the next operat ion to be perform· ed. Refer to 8.1 5 EXCEPTION PROCESSING for deta i ls of coprocessor related excep· t ions.

For both the short and long bus fau l t stack frames, the format value on the stack is f i rst checked for val id ity. In add i t ion, for the long stack frame, the version nu mber contained in the stack must match the version number of the processor that is attempting to read the stack frame. The vers ion number is located in the most s ign i f icant n ibble (bits 1 2 through 1 5) of the word at location S P + 54 i n the long stack frame. Th is val id i ty check is used to i nsure that i n a dual processor system, the data w i l l be properly i nterpreted by the RTE i nstruction. I f the frame is found to be inva l id or i naccessi ble, a format error or a bus error exception is taken, respectively. Otherw ise, the processor reads the ent i re frame i nto the proper i nternal reg isters, deal locates the proper stack, and resumes nor· mal process i ng . Once the processor beg ins to read the frame, a bus error must not occur or the processor w i l l enter the ha lted state. Refer to 6.4 BUS FAULT RECOVERY for more i nformation on the behavior of the processor after the frame is read i nto the i nternal reg isters.

If a format error or bus error occurs dur ing the execut ion of the RTE i nstruction, e ither due to any of the errors described above or due to an i l legal format code, the processor w i l l create a normal fou r word or a bus cycle fau lt stack frame above the frame that it was attempting to use. In th is way, the fau lty stack frame remains i ntact and may be examin· ed by the format error or bus error exception hand ler and repai red, or used by another processor of a d ifferent type (e.g . , an MC68010, MC68012, or a future M68000 processor) in a mu l t iprocessor system.

6.4 BUS FAU LT RECOVERY

There are two facets to recovery from a bus cyc le fau lt: recognit ion of the fau lt and sav· ing the processor state, and restori ng the state at a later t i me.

A memory fau l t is i nd icated to the MC68020 by an address error (generated i nternal ly), or by a bus error (generated by external logic, genera l ly by a memory management device or sub·system). The processor state is saved on the su pervisor stack as descri bed in 6.3.3 Bus Error, and the state may be later restored by the RTE i nstruction as descri bed i n 6.3.1 1 Return From Exception. The act ion taken by the processor after the return can be control led, to some degree, by manipulat ing the data i n the bus fault stack frame as described below.

The MC68020 can have fau lts occur on either i nstruction stream or data accesses. Fau l ts on data accesses are taken when the bus cyc le is termi nated. Faults on i nstruction stream accesses are delayed u nt i l the processor attempts to use the i nformation, if ever, which was not obtai ned due to the aborted bus cycle. Address error faults occur only on i nstruction stream accesses, and are taken before the bus cycle is attempted.

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6.4.1 Special Status Word

There are several spec ial reg isters saved as part of the bus fau lt except ion stack frame i nformation, i nc lud ing the i nternal special status word (see F igure 6-2). This word is placed i n the stack frame, at offset $A, for both the short bus cycle fau lt format and the long bus cyc le fau lt format. Refer to 6.5.5 Short Bus Cycle Fault Stack Frame and 6.5.6 Long Bus Cycle Fault Stack Frame.

15 14 13 12 1 1 10 9 I FC FB I RC I RB I 0 I 0 I 0 8 7 6 5 4 3

DF I RM I RW I SIZ I 0

FC - Fault on Stage C of the Instruction Pipe FB - Fault on Stage B of the Instruction Pipe RC - Rerun Flag for Stage C of the Instruction Pipe* RB - Rerun Flag for Stage B of the I nstruction Pipe* DF - Fault/Rerun Flag for Data Cycle* RM - Read-Modify-Write on Data Cycle RW - Read/Write for Data Cycle - 1 = Read. 0 = Write S IZ - Size Code for Data Cycle FCO-FC2 - Address Space for Data Cycle * 1 = Rerun Faulted Bus Cycle. or Run Pending Prefetch 0= Do Not Rerun Bus Cycle

Figure 6-2. Special Status Word (SSW)

o FC2-FCO

The spec ia l status word (SSW) i nformation defines whether the fau lt was on the i nstruct ion stream, data stream, or both. There are two status bits each for the S and C stages of the i nstruction p ipe. The rerun f lag bits (RS and RC) i nd icate that the processor w i l l rerun the bus cyc le for the correspond ing stage dur ing the RTE i nstruct ion. This can be due to either a prefetch that is pend ing or to a fau lt that occurred wh i le execut ing a prefetch. The fau l t bits (FS and FC) ind icate that the processor attem pted to use a stage and found it to be marked as i nva l id due to a bus error on the prefetch for that stage. The fau l t bits are outputs only that can be used by a bus error hand ler to determ ine the cause(s) of a bus error except ion; they are ig nored when the processor reads the stack frame dur ing an RTE. The rerun bits ind icate i f an element of the i nstruction p ipe is va l id, and can be used by a handler to repair the p ipe due to a fault (either an address error or a bus error). RS and RC are used by the processor dur ing an RTE to control the execution of bus cyc les for each stage; if e ither, or both, of the rerun bits are set when the RTE i nstruction reads the frame, the processor w i l l rerun the previously fau lted prefetch cyc le (or execute a pend ing prefetch for the f i rst t i me). I f a rerun b it is clear, it is assumed that there is no prefetch pending for the corresponding stage and that software has repai red or f i l led the i mage of the stage, i f necessary. When the SSW is written to the stack frame dur ing exception process i ng, the RS and/or RC bits w i l l be set if the corresponding fau l t bit is set, or if a prefetch for the stage is pending , so that the defau l t ( if the hand ler does not modi fy RS and/or RC) is to have the processor execute the bus cycle(s). The address space for i nstruction stream fau lts is not presented expl ic i t ly, but is the program space for the privi lege level i nd icated in the status reg ister of the stack frame.

If an address error except ion occurs, the fau lt bits wri tten to the stack frame w i l l not be set (S i nce they are on ly set due to a bus error, as described above), and the rerun bits must be used to determ i ne the cause of the except ion. Depending on the state of the p ipel i ne, either RS and RC w i l l both be set, or RS alone w i l l be set. I f i t is desi red to repa i r the p ipe l i ne and cont inue execut ion of the suspended i nstruction, software must place the correct i nstruct ion stream data in the stage C and/or stage S i mages (and c lear the correspond ing reru n b its), depending on the state of the rerun bits.

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I f the OF bit of the SSW is set, a data fau lt has occu rred. I f the OF bit is set when the processor reads the stack frame, it w i l l reru n the fau lted data access; otherwise, it assumes that no data fau lt occu rred, or software has corrected the fau lt . Other i nformat ion about the data access, such as read/write, read-modi fy-write, the s ize of the operand access, and the add ress space for the access are present in the SSW. Data and i nstruct ion stream fau lts may be pend ing s imu l taneously; thus, the fau lt handler should be able to hand le any combi nation of the FC, FB, RC, RB, and OF bits.

6.4.2 Completing the Bus Cyele(s)

There are two methods of complet ing fau lted bus cyc les. The f i rst is to use a software handler to emulate the cycle and the second is to a l low the processor to rerun the bus cyc le(s) after the cause for the fau lt has been repaired.

6.4.2.1 COMPLETI NG THE BUS CYClE(S) VIA SOFTWARE. Based on the i nformation saved on the stack, the fau l t handler rout ine may emulate the fau lted bus cycle in a manner that is transparent to the i nstruction that caused the fau lt . For i nstruction stream faults, there are separate images for the B and C stages of the i nstruction p ipe that may need repai r. If the fau lt ind icator for a part icu lar stage is set, the processor has fau lted because the fetch of the i nstruct ion word was aborted by an address error or a bus error. For the short format frame, the address of the stage B word is the value in the program counter p lus fou r, and the address of the stage C word is the value in the program counter p lus two. For the long format, the address of the stage B word is g iven expl ic it ly, and the address of the stage C word is the address of the stage B word minus 2. For each fau lted stage, the software handler should fetch the i nstruction word from the proper address space as ind icated by the S bit of the status reg ister in the frame, and write i t to the i mage of the stage in the stack frame. In add it ion, the handler must c lear the rerun b i t associated with the stage that i t has completed. The fau l t bits for each stage should not be changed.

For data write operat ions, the handler must transfer the properly s ized data in the image of the data output buffer (OOB) to the location i nd icated by the fau l t address in the add ress space defi ned by the SSW. For data read operat ions, the handler must transfer properly s ized data from the location ind icated by the fau lt address and address space to the image of the data i n put buffer (OI B). Byte, word, and 3-byte operands appear r ightj ust if ied wi th in the 4-byte i mage of the data buffers. I n add it ion, the software handler must c lear the OF b i t of the SSW to i nform the processor that the fau lted data bus cyc le has been completed.

In order to emulate a read-modify-write cycle, the exception handler must f i rst determi ne what i nstruction, CAS, CAS2, or TAS, caused the fau lt . This may be accomp l ished by examin ing the operation word at the address contai ned in the stack frame program counter. Then the handler must modify not on ly the SSW of the stack frame, but also the status reg ister image and the image of any data reg ister(s} requ i red for the CAS and CAS2 i nstructions (presumably, the user v is ib le reg isters were saved upon entry to the handler with a MOVEM i nstruction and are restored later). In other words, the fau lt handler must emulate the ent i re i nstruction, rather than j ust the faulted bus cycle. Th is more detai led action is requ i red due to the fact that the processor assumes that the ent i re read-modify-write operation (which may consist of up to fou r long word t ransfers), i nc lud ing condit ion code computat ions and reg ister transfers, is completed by the handler

6-1 8

if the OF bit is clear and the RM bit is set when the frame is read by an RTE i nstruction. This is true regard less of whether the fau l t occurred on the f i rst read cycle, or su bsequent read or write cyc les of the operat ion.

After the handler has completed the software emulat ion, the stack frame and the memory state represent the state of the system after the bus cyc le(s) has been successfu l ly completed. Note that the software method must be used for address error faults.

To ensure proper operation of the processor, no modif ications to a bus cyc le fau l t stack frame other than those described above should be made.

6.4.2.2 COMPLETING THE BUS CYCLE(S) VIA RTE. I f it is not necessary to complete the fau lted bus cyc le via software emulation, the RTE i nstruction, as the last instruction to be executed in the except ion handler rout i ne, is able to complete the fau l ted bus cycle(s) . This is the default case and it is assumed that whatever caused the fau lt , such as a nonresident page in a v irtual memory system, has been repa i red or the fault w i l l occur agai n. I f a fault occu rs when the RTE i nstruction attempts to rerun the bus cycle(s), a new stack frame w i l l be created on the supervisor stack after the previous f rame is deal located; and address error or bus error exception processing w i l l start in the normal manner.

The read-mod ify-write operat ions of the MC68020 provide for a special case of the bus fau l t recovery proceSSing. Whi le the bus recovery processing for a l l read and write operat ions are str ict ly on a cyc le-by-cyc le basis, that for a read-mod ify-write operat ion is on an i nstruct ion basis . This means that du ring an RTE f rom a bus error of a read-modify-write operat ion, i f the O F bit in the SSW is set, ind icat ing that the cycle should be rerun, then the processor w i l l rerun the ent i re operat ion from beg i nn i ng to completion regard less of which part of the operat ion caused the bus error. S imi larly, if the OF bit is cleared, i nd icat ing that the operation has been completed in software, the processor assumes that the ent i re operat ion has been completed and w i l l immediately proceed with the next i nstruct ion.

Systems programmers and des igners both should be aware of this facet of the processor and its imp l ications. Specif ical ly, i t is recommended that memory management mechanisms t reat any bus cyc le with RMC asserted as a wri te operation for protection check ing operat ions regardless of the state of the R/W signal . Otherwise, the potent ia l for part ia l ly destroying system pOi nters with the CAS and CAS2 instructions ex ists si nce one port ion of the write operation cou ld take place and the remai nder aborted by a bus error.

6.5 MC68020 EXCEPTION STACK FRAMES

The MC68020 generates s ix d ifferent stack f rames. These frames consist of the normal four and six word stack frames, the four word throwaway stack frame, the coprocessor m id- instruction except ion stack frame, and the short and long bus fau lt stack f rames.

Whenever the MC68020 writes or reads a stack frame, it w i l l use long word operand t ransfers whenever possible. Thus, i f the stack area res ides in a 32-bit ported memory and the stack poi nter is long word a l igned, exception processing performance w i l l be

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great ly enhanced. A lso, the order of the bus cycles used by the processor to write or read a stack frame may not fol low the order of the data in the frame.

6.5.1 Normal Four Word Stack Frame

This frame (see F igure 6·3) is created by interrupts, format errors, TRAP #n i nstruct ions, i l legal instructions, A·l i ne and F·l ine emulator traps, privi lege violations, and coprocessor pre· instruct ion exceptions. The program cou nter value is the address of the next i nstruction to be executed, or the instruction that caused the except ion, depending on the exception type.

1 5 o

SP - Status Register

+ $ 02 Program Counter

+ $ 06 0 0 0 0 I Vector Offset

Figure 6·3. Format $0 - Four Word Stack Frame

6.5.2 Throwaway Four Word Stack Frame

This stack frame (see Figure 6·4) is the throwaway frame that is created on the i nterrupt stack dur ing except ion processing for an i nterrupt when a transit ion from the master state to the i nterrupt state occurs. The program cou nter value is equal to the value on the normal four word or coprocessor mid· i nstruction exception stack frame that was created on the master stack.

15 o

SP -- Status Register

+ $0 2 Program Register


Figure 6·4. Format $1 - Throwaway Four Word Stack Frame

6.5.3 Normal Six Word Stack Frame

This stack frame (see F igure 6·5) is created by i nstruct ion related except ions which i n· c lude coprocessor post· instruction except ions, CHK, CHK2, cpTRAPcc, TRAPcc, TRAPV trace, and zero d ivide. The i nstruction address va lue is the address of the i nstruct ion that caused the except ion. The program counter value is the address of the next i nstruct ion to be executed, and the address to which the RTE i nstruct ion w i l l return.

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15 o SP -. Status Register


+ $ 06 0 0 1 0 1 Vector Offset

+ $ 06 I nstruction Address

Figure 6·5. Format $2 - Six Word Stack Frame

6.5.4 Coprocessor M id·lnstruction Exception Stack Frame

This stack frame (see F igure 6·6) is created for three d i fferent except ions, a l l related to coprocessor operations. The f i rst occurs when the "take m id·i nstruction except ion" pri mit ive is read whi le processing a coprocessor i nstruct ion . The second occurs when the main processor detects a protocol v iolat ion dur ing process ing of a coprocessor i n· struction. The th i rd occurs when a "nu l l , come agai n with i nterrupts al lowed" pr imit ive is received, and the processor detects a pend ing i nterru pt. Refer to SECTION 8 COPROCESSOR INTERFACE DESCRIPTION for further deta i ls. The program cou nter val ue is the address of the next word to be fetched from the i nstruct ion �tream. The i nstruction address va lue is the address of the f i rst word of the i nstruct ion that was execut ing when the exception occurred.

1 5

SP --

+ $0 2

+ $06 1

+ $ 08

+ $ OC

+ $ 1 2

Status Register

Program Counter

0 0 1 I Vector Offset

Instruction Address

Internal Registers, 4 Words

Figure 6·6. Format $9 - Coprocessor Mid·lnstruction Exception Stack Frame (10 Words)

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6.5.5 Short Bus Cycle Fault Stack Frame

This stack frame (see F igure 6·7) is created whenever a bus cyc le fau lt is detected, and the processor recogn izes that i t is at an i nstruct ion bou ndary and can use th is reduced version of the bus fau lt stack frame. The program cou nter value is the address of the next i nstruction to be executed.

15 o SP - Status Register


+ $ 04


+ $ 08 Internal Register

+ $ OA Special Status Word

+ $ OC Instruction Pipe Stage C

+ $ OE Instruction Pipe Stage B

+ $ 1 0 Data Cycle Fault Address

+ $ 1 2

+ $ 1 4 Internal Register

+ $ 16 Internal Register

+ $ 18 Data Output Buffer

+ $ 1 A

+ $ 1 C Internal Register

+ $ 1 E Internal Register

Figure 6·7. Format $A - Short Bus Cycle Fault Stack Frame (16 Words)

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6.5.6 Long Bus Cycle Fault Stack Frame

Th is stack frame (see F igure 6·8) is created whenever the processor detects a bus cyc le fau lt and recogn izes that i t is not on an i nstruct ion boundary. The program counter va lue is the address of the i nstruction that was execut ing when the fau lt occurred (which may not be the instruction that generated the fau lted bus cyc le).

SP ---+ + $0 2

+ $06

+ $08

+ $0 A

+ $0 C

+ $0 E

+ $ 1 0

+ $ 1 2

+ $ 14

+ $ 18

+ $ 1 C

2 + $2

+ $ 24

+ $ 28

+ $2

+ $2

A

C

+ $ 30

+ $5 A

15

1

Status Register

Program Counter

0 1 1 1 Vector Offset

Internal Register

Special Status Word

Instruction Pipe Stage C

Instruction Pipe Stage B

Data Cycle Fault Address


Data Output Buffer


Stage B Address


Data Input Buffer


Figure 6·8. Format $B - Long Bus Cycle Fault Stack Frame (46 Words)

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6.5.7 Stack Frame Summary

Figure 6·9 shows a summary of the M68000 Fam i ly defined stack frames.

Format Frame Type

0000 Short Format (4 Words) 0001 Throwaway 14 Words) 0010 Instruction Exception 16 Words!

001 1 -01 1 1 (Undefined, Reserved! 1000 MC68010 Bus Fault (29 Words) 1001 Coprocessor Mid· lnstruction ( 1 0 Words! 1010 MC68020 S hort Bus Fau l t ( 1 6 Words! 101 1 MC68020 Long Bus Fau!t 146 Words!

1 100-1 1 1 1 ( Undefined, Reserved!

Figure 6·9. Stack Frame Format Definitions

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SECTION 7 ON·CH I P CACH E M EMORY

The MC68020 incorporates an on-ch i p cache memory as a means of improving the performance of the processor. The cache is implemented as a CPU i nstruction cache and is used to store the i nstruction stream prefetch accesses from the main memory.

Studies have shown that typical programs spend most of their execut ion t ime in a few main rout ines or t ight loops. Therefore, once captured in the h igh-speed cache, these act ive code segments can execute d i rect ly from the cache. Thus, the processor does not suffer any external memory de lays, and the total execut ion t ime of the program is s ign if icantly improved. The performance is also improved by al lowing the MC68020 to make s imu ltaneous accesses to i nstructions in the i nternal cache and to data in the external memory.

Another of the major benefits of using the cache is that the processor's external bus activity is g reatly reduced. Thus, in a system with more than one bus master (such as a processor and DMA device) or a t ight ly-coup led mult i-processor system, more of the bus bandwidth is avai lable to the alternate bus masters without a major degradat ion i n the performance of the MC68020.

7_1 CACHE DESIGN AND OPERATION

The fol lowing paragraphs describe the cache design and operat ion with in the MC68020.

7.1 .1 On-Chip Cache Organ ization

The MC68020 on-ch ip instruct ion cache is a d i rect-mapped cache of 64 long word entries. Each cache entry consists of a tag field made up of the upper 24 address bits and the FC2 va lue, one va l id bit and 32 bits (two words) of i nstruct ion data.

F igure 7-1 shows a block d iagram of the on-chip cache. Whenever an i nstruct ion fetch occurs, the cache (if enabled) is f i rst checked to determi ne i f the word requ i red is in the cache. This is achieved by f i rst us ing the i ndex field (A2-A7) of the access address as an i ndex i nto the on-ch ip cache. Th is selects one of the 64 entries in the cache. Next, the access address bits A8-A31 , and FC2 are compared to the tag of the selected entry. If there is a match and the val id bit is set, a cache h i t occurs. Address bit A 1 is used to select the proper word from the cache entry and the cycle ends. I f there is no match, or the val id bit is c lear, a cache m iss occurs and the i nstruct ion is fetched from external memory. This new i nstruction is automatical ly written into the cache entry, and the va l id bit is set, u n less the freeze cache bit has been set (see 7.1 .2_3 F- FREEZE CACH E) in the cache

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A 3 1

--l 1- 1"

A A A A 2 2 2 2 3 2 1 0

MC68020 Prefetch Address A A A A A A A A A A A A A A A A A A A A 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

Tag

'� '"

d

" � I �

v

t Word Select

Word Word { Tag

� � Select

Tag Replace

Comparator

Replacement '---+----'--- Data

To I nstruction

Path Cache ::4-0--- Hit -----'-� Control

Figure 7·1 . MC68020 On·Chip Cache Organization

control reg ister. Since the processor a lways prefetches i nstructions external ly with long word, a l igned bus cycles, both words of the entry w i l l be updated, regardless of which word caused the m iss.

NOTE Data accesses are not cached, regard less of their associated address space.

7.1 .2 Cache Control

The cache itself is accessable on ly by the i nternal MC68020 control u n it. The user has no d i rect method of accessing (read/write) i nd iv idual entries (tag, data, etc.). To manipu late the cache entries, however, the user does have a set of control functions avai lable in the form of a cache control reg ister which is described below.

7.1 .2.1 CACHE CONTROL REGISTER. Access to the cache control reg ister (CACR) is pro· vided by means of the Move Control Reg ister (MOVEC) i nstruct ion. The MOVEC i nstruc· t ion is a privi leged i nstruction. The CACR is a 32·bit reg ister which is organ ized as shown i n F igure 7·2. The unused b i ts ( inc lud ing bits [31 :8] which are not shown) are always read as zeros.

7·2

31

I 0 C = Clear Cache CE = Clear Entry F = Freeze Cache E = Enable Cache

Figure 7·2. Cache Control Register

8 7 0 o I 0 I 0 I 0 I 0 I C ICE I F I E I

7.1 .2.2 E- ENABLE CACH E. The cache enable fu nction is necessary for system debug and emulat ion. This bit a l lows the des ig ner to operate the processor with the cache d isabled. C leari ng this bit w i l l d isable the cache (force cont i nuous m isses, and suppress f i l l s) and force the processor to always access external memory. The cache w i l l remain d isabled as long as th is bit i s c leared. The user must set th is bit, which is automat ical ly c leared whenever the processor is reset, to enable the cache.

7.1 .2.3 F- FREEZE CACH E. The freeze bit keeps the cache enabled, but cache misses are not a l lowed to replace val id cache data. This bit can be used by emulators to freeze the cache dur ing emu lat ion function execution.

7.1 .2.4 CE-CLEAR ENTRY. When the c lear entry bit is set, the processor takes the ad· dress ( i ndex f ie ld, bits 2·7) in the cache address reg ister (CAAR) and i nvalidates the assoc iated entry (clears the va l id b it) in the cache, regard less of whether or not i t pro· vides a h it ; i .e. , whether the tag f ield in the cache address reg ister matches the cache tag or not. This function w i l l occur only when a write to the cache control reg ister is perform· ed with the CE bit set. This bit a lways reads as a zero and the operat ion is i ndependent of the state of the E or F bits, or the external Cache D isable (CDIS) p in .

7.1 .2.5 C-CLEAR CAC H E. The cache c lear bit is used to i nva l idate a l l entries i n the cache. This function is necessary for operati ng systems and other software which must c lear old data from the cache whenever a context switch is requ i red. The setting of the c lear cache bit i n the cache control reg ister causes a l l va l id bits i n the cache to be c leared, thus i nvalidat ing a l l entries. This function occurs only when a write to the cache control reg ister is performed with the C bit set. This bit always reads as a zero.

7.2 CACHE ADDRESS REGISTER

The cache address reg ister (CAAR) is a 32·bit reg ister which provides an address for cache control functions (see F igure 7·3). The MC68020 only uses th is reg ister for the clear entry (CE) function. Access to the CAAR is provided by the Move Control Reg ister (MOVEC) i nstruction.

31

Cache Function Address

Figure 7·3. Cache Address Register

7·3

8 7

I ndex

2 1 0

I I

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7.3 CACHE DISABLE INPUT

The cache disable input is used to dynamical ly d isable the cache. The input signal on this pin is synchron ized before being used to control the internal cache. The cache is d isabled on the f i rst cache access after the synchron ized CDIS signal is recogn ized as being asserted. The cache w i l l be re·enabled on the f i rst cache access after the synchron ized CDIS signal is recogn ized as being negated. Th is pin disables the cache independent of the enable bit i n the Cache Control Register and, therefore, can be used by external emulator hardware to force the MC68020 to make a l l accesses via the external bus.

7.4 CACHE INITIALIZATION

During processor reset, the cache is cleared by resett ing a l l of the val id bits. The Cache Control Register (CACR) enable (E) and freeze (F) bits are a lso c leared.

7-4

SECTION 8 COP ROCESSOR I NTERFACE DESC RIPTION

This sect ion describes the M68000 coprocessor i nterface. I t is intended for designers who are implement ing a coprocessor to i nterface to the MC68020. Motorola coprocessors w i l l conform to the i nterface descri bed i n th is section and their use does not requ i re a detai led know ledge of the M68000 coprocessor in terface. These coprocessors w i l l execute Motorola defi ned i nstruct ions that are descri bed in the respective coprocessor user manuals.

8.1 I NTRODUCTION

The M68000 Fami ly of general pu rpose microprocessors provide a level of performance which sat isfies a w ide range of computer appl ications. Spec ial purpose hardware, however, can often provide h igher levels of performance for a spec if ic appl ication. The coprocessor concept al lows the capabi l it ies and performance of a general pu rpose pro· cessor to be enhanced for a part icu lar appl ication without unduly encu mber ing the main processor arch itectu re. A coprocessor can be des ig ned to eff ic iently hand le any number of spec if ic capabi l ity requ i rements that must typica l ly be implemented in software by a general pu rpose processor. Thus, the processing capab i l i t ies of a system can be tai lored to a spec if ic appl ication by ut i l iz ing a general purpose main processor and the appropriate coprocessor(s).

It is important to make the d ist inction between standard peri pheral hardware and a M68000 coprocessor. An M68000 coprocessor i s a device or set of devices that have the capabi l ity of commun icat ing with the main processor through the protocol def ined as the M68000 coprocessor interface. A coprocessor d iffers from a peripheral part icu larly from the perspective of the main processor programming model. This programm i ng model consists of the i nstruction set, reg ister set, and memory map avai lable to the programmer. A coprocessor adds add i t ional i nstructions, and general ly add it ional reg isters and data types which are not d i rect ly su pported by the main processor arch itecture. Dedicated coprocessor i nstructions are provided to u t i l ize the coprocessor capabi l it ies. The i nteract ions between the main processor and the coprocessor that are necessary for the coprocessor to provide a g iven service, are transparent to the prog rammer. That is, no knowledge of the commun icat ion protocol between the main processor and the coprocessor is req u i red of the programmer s i nce this protocol is implemented in hardware. Thus, the coprocessor can provide capabi l it ies to the user without appearing as hardware external to the main processor.

In contrast, standard peripheral hardware is genera l ly accessed through the use of i nterface reg isters mapped i nto the memory space of the main processor. The programmer uses standard processor i nstructions to access the peripheral i nterface reg isters and

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thus ut i l ize the services provided by the peripheral . Wh i le a peri pheral cou ld conceivably provide capab i l it ies equivalent to a coprocessor for many appl ications, the programmer must im plement the communication protocol between the main processor and the peri pheral necessary to use the peri pheral hardware.

8.2 M68000 FAMI LY COPROCESSO R INTERFACE OVERVI EW

The commun ication protocol defi ned for the M68000 coprocessor i nterface w i l l be descri bed u nder 8.3 COPROCESSOR INSTRUCTION TYPES. The algorithms necessary to imp lement the M68000 coprocessor in terface are provided in the microcode of the MC68020 and are com pletely transparent to the MC68020 programmer's model. For ex· ample, f loat i ng-point operat ions are not imp lemented in the MC68020 hardware. In a system ut i l iz ing both the MC68020 and the MC68881 F loat i ng,Po int Coprocessor, a prog rammer can use any of the i nstructions def i ned for the MC68881 without the knowledge that the actual com putat ion is performed by the MC68881 hardware.

A M68000 coprocessor may be coup led with a main processor which does not have a coprocessor interface such as an MG68000, MC68008, MC68010 , or MC68012. Th is is accompl ished by providing i nstruction seq uences that emulate the protocol of the coprocessor interface descri bed in th is sect ion. The coprocessor w i l l appear as a peri pheral in the program ming model of these processors.

8.2.1 Interface Features

The M68000 coprocessor interface des ign incorporates a number of f lexible capabi l i t ies. The phys ical coprocessor interface is based on M68000 asynchronous bus cyc les which s impl if ies the i nterface s ince there are no special purpose signals involved. Si nce standard M68000 asynchronous bus cyc les are used to transfer i nformat ion between the main processor and the coprocessor, the coprocessor can be implemented in the technology which is ava i lable to the coprocessor des igner. A coprocessor can be implemented as a VLSI device, as a separate system board, or even as a separate com puter system.

Si nce the main processor and a M68000 coprocessor communicate us ing an asynchronous bus, they are not requ i red to operate at the same c lock frequency. This feature al lows the system des igner to optim ize the speed of the various sections of the processi ng hardware for a part icu lar system appl icat ion. The deSigner is free to choose the speeds of a main processor and coprocessor which provide the opt imum performance for a g iven system.

The M68000 coprocessor i nterface also fac i l itates the des ign of coprocessors. The coprocessor des ign need only conform to the coprocessor interface and does not requ i re extensive knowledge of the arch itecture of the main processor. The coprocessor must reflect the arch itectu re of the main processor only to the extent that it must use the M68000 coprocessor i nterface protocol to communicate with the main processor. Also, the main processor can operate with a coprocessor without expl ic it provisions for the capabi l it ies of that coprocessor being made in the main processor arch itecture. Si nce the capab i l it ies of the coprocessor are not d ictated by the arch itecture of the main processor, the coprocessor des igner has a great deal of freedom in the imp lementat ion of a g iven coprocessor.

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8.2.2 Concurrent Coprocessor Operation Support

The programmers model for the M68000 Fam i ly of microprocessors is based on seq uent ia l , non-concurrent i nstruction execut ion. Th is impl ies that the i nstructions in a g iven sequence are executed i n the order which they occur and that a l l act ions performed by an i nstruction w i l l be completed by the t ime the next i nstruction in the seq uence executes. In order to maintain a un i form programmers model , any coprocessor extensions should also mainta in the model of sequential , non-concurrent i nstruct ion execut ion at the user leve l . That is, the programmer may assume that all services provided by a g iven i nstruct ion w i l l have been completed when the next i nstruct ion in the sequence executes.

The M68000 coprocessor i n terface is des igned to provide fu l l support of al l operat ions necessary for non-concu rrent operation between the main processor and its associated coprocessors. Wh i le the M68000 coprocessor interface al lows concu rrency i n coprocessor execut ion, i t is the responsib i l i ty o f the coprocessor des igner t o im plement this concu rrency whi le mainta in ing a programming model based on sequential , nonconcu rrent i nstruction execut ion.

8.2.3 Coprocessor I nstruction Format

The i nstruction set for a g iven coprocessor is defi ned by the design of that coprocessor . When a coprocessor i nstruct ion is encountered i n the main processor i nstruction stream, the MC68020 hardware i n i t iates commu nication with the coprocessor and coordi nates any interaction necessary for the i nstruction execution with the coprocessor. A prog rammer is req u i red to know on ly the i nstruct ion set and reg ister set defi ned by the coprocessor in order to ut i l ize the fu nctions provided by the coprocessor hardware.

The instruct ion set of an M68000 coprocessor is implemented by using the F-l i ne operat ion words in the M68000 i nstruction set. The operation word is the f i rst word of any M68000 Fami ly i nstruction. The F- l i ne operat ion word contains ones in bits 1 5 through 1 2 ([1 5: 1 2) = (1 1 1 1 ) ; see F igure 8-1 ) and the remain ing bits are used t o spec i fy the type of coprocessor instruct ion that w i l l be executed. The F- l i ne operation word may be fol lowed by a number of extension words which provide add it ional information necessary for the execut ion of the coprocessor i nstruction.

B its 1 1 through 9 of the F-l i ne operat ion word are used to encode the coprocessor ident i f ication code (Cp-I O). The MC68020 uses the coprocessor ident i f ication f ield to ind icate which coprocessor it is accessing for a g iven coprocessor i nstruct ion.

1 5 14 1 3 1 2 1 1 10 9 8 7 6 5 4 3 Cp- ID Type Type Dependent

Figure 8·1 . F-line Coprocessor I nstruction Operation Word

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Cp-I D codes of 000-101 are reserved for current and future Motorola coprocessors and Cp- ID codes of 1 1 0-1 1 1 are reserved for user defi ned coprocessors. The Motorola Cp- ID codes wh ich are currently defi ned are:

Cp·1D Code

000 001

Motorola Coprocessor

MC68851 Paged-Memory Management Unit MC68881 F loating-Point Coprocessor

Thus, Motorola assemblers w i l l by defau lt use the Cp- ID codes spec if ied above when generat ing the i nstruction operat ion codes for the MC68851 and MC68881 coprocessor i nstruct ions.

The encod ing of bits 8 through 0 of the coprocessor i nstruction operat ion word is dependent on the part icu lar i nstruct ion being imp lemented. These encod i ngs are d iscussed i n 8.3 COPROCESSOR INSTRUCTION TYPES.

8_2.4 M68000 Coprocessor System Interface

The commun ication protocol between the main processor and coprocessor necessary to execute a coprocessor i nstruct ion is based on a group of interface reg isters which are defi ned for the M68000 coprocessor i nterface. The MC68020 hardware in i t iates a coprocessor i nstruction by accessing one of these reg isters. The coprocessor uses a set of response pr imit ive codes and format codes def i ned for the M68000 coprocessor interface to commun icate status and service requests to the main processor. The coprocessor i nterface reg isters are also used to pass operands between the mainprocessor and the coprocessor. The coprocessor i nterface reg ister set, response prim i t ives, and format codes wi l l be d iscussed in 8.4 COPROCESSOR INTERFACE REGISTER (CI R) SET and 8_6 COPROCESSOR RESPONSE PRIMITIVE SET DESCRIPTION.

8_2.4.1 M68000 COPROCESSOR BUS INTERFACE. The MC68020 uses standard M68000 asynchronous bus cycles to access the registers i n the coprocessor i nterface reg ister set. Thus, the bus i nterface imp lemented by a coprocessor for its interface reg ister set must only satisfy the MC68020 address, data, and control s ignal t im ing to guarantee proper commun ication with the main processor. The MC68020 t iming information for read and write bus cycles is i l l ustrated in F igures 1 0-5 and 1 0-6 found on foldout pages i n the back o f t h i s manual . A detai led discussion o f the MC68020 asynchronous bus operat ion is contained in SECTION 5 BUS OPERATION.

8.2.4.2 CPU ADDRESS SPACE. Dur ing coprocessor i nstruct ion execution, the MC68020 executes bus cycles in CPU space to access the i nterface reg ister set of a coprocessor. The MC68020 ind icates that i t is acceSSing CPU space by driving the three function code outputs h igh dur ing a CPU space bus cycle (FC2-FCO = 1 1 1 ; see 5.2.4 CPU Space Cycles). Thus, the coprocessor i nterface reg ister set is mapped i nto CPU space in the same manner that a peri pheral i nterface reg ister set is genera l ly mapped into data space. The i nformation encoded on the function code l i nes and address bus of the

8-4

MC68020 dur ing a coprocessor access is used to generate the ch ip select s ignal for the coprocessor being accessed. The address l i nes of the MC68020 are also used to spec ify which reg ister i n the interface set is be ing accessed during operand transfers between the main processor and the coprocessor.

The i nformat ion that is encoded on the fu nction code and address l i nes of the MC68020 dur ing a coprocessor access is i l l ustrated in F igure 8-2.

Function Code

31

1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0

Address Bus

1 9 1 5 12 4 0 1 0 0 1 0 1 Cp-ID 1 0 0 0 0 0 0 0 0 1 CIR Register

I CPU Space Type Field

Figure 8·2. MC68020 CPU Space Address Encodings

Address s ignals A19-A1 6 specify the CPU space cycle type dur ing a CPU space bus cyc le. The types of CPU space cycles cu rrently def ined for the MC68020 are i nterru pt acknowledge, breakpoint acknowledge, modu le support operat ions, and coprocessor access cycles. CPU space type 2 (A 1 9-A 1 6 = 001 0) specif ies a coprocessor access cyc le.

A15-A1 3 of the MC68020 address bus spec ify the coprocessor ident i f icat ion code (Cp- ID) for the coprocessor being accessed. This code is extracted from bits 1 1 -9 of the coprocessor i nstruct ion operat ion word (see F igure 8-1 ) and placed on the address bus during each coprocessor access. Thus, a chip select s ignal for a g iven coprocessor can be generated by decod ing the MC68020 fu nction code s ignals and bits A19-A1 3 of the address bus. The fu nction code s ignals and A1 9-A16 i ndicate a coprocessor access in CPU space, wh i le A15-A1 3 i nd icate which of the poss ible eight coprocessors assoc iated with the main processor is being accessed.

Bits A31 -A20 and A1 2-A5 of the MC68020 address bus are always zero dur ing a coprocessor access generated in conj u nction with the execution of a coprocessor i nstruction. The MC6801 0 and MC6801 2 can emu late coprocessor access cycles i n CPU space us ing the MOVES i nstruction.

8.2.4.3 COPROCESSOR INTERFACE REGISTER (CIR) SELECTION. The MC68020 must access the reg isters defined i n the coprocessor interface reg ister (CI R) set to commun icate with the coprocessor dur ing the exeuct ion of a coprocessor i nstruction. Dur ing coprocessor access bus cycles, A4-AO of the MC68020 address bus are used to spec ify which reg ister i n the C IR set is being referenced. The reg ister map for the M68000 coprocessor i nterface is depicted i n F igure 8-3. A detai led descr ipt ion of the ind ividual reg isters i s provided in 8.4 COPROCESSOR INTERFACE REG ISTER (CIR) SET.

8-5

•

00

04

08 OC 1 0 14 18 1 C

31 15 o

Response" Control " Save* Restore*

Operation Word Command" ( Reservedl Condition*

Operand" Register Select ( Reservedl

Instruction Address Operand Address

Figure 8·3. Coprocessor Interface Register Set Map

As a resu l t of the va lues encoded on the MC68020 address bus during a coprocessor access, each coprocessor in a system is mapped i nto a un ique reg ion of the main pro· cessor's logical CPU address space. An add ress map for the coprocessor access port ion of the MC68020 CPU space is presented in F igure 8·4. A4·AO ind icate the i nterface reg ister offset from the coprocessor base address in CPU space.

2EOOO I-----------i I n terface Register Set

J 2E01 F 1-----------1 Address Space for Coprocessor with

Reserved Cp- ID = 7 �--------�

Figure 8·4. Coprocessor Address Map in MC68020 CPU Space

A block leve l d iagram of the s ignals involved in the M68000 coprocessor i nterface is provided in F igure 8·5. S ince the ch ip select for a g iven coprocessor is based in part on the Cp- ID encoded on A1 5·A13 of the MC68020 address bus, the system des igner is free to use mu lt i ple coprocessors of the same type by s imply ass ign ing a un ique Cp· ID to each one.

8·6

Main Processor FCO-FC2 ,.

CS MC68020 Coprocessor A19-A13 Decode

Logic·

AS DS Riw

DSACK x

A4-Al

D31 -DO

FC2-FCO� 1 1 1 __ CPU Space Cycle A1 9-A1 6 = OO10 __ Coprocessor Access in CPU Space A 15-A 13 = xxx __ Coprocessor Identification

Coprocessor

Ul � .S2 � 8' 0 -' c OJ o u � ro

.c -g $ > c

,;£ -

A4-A 1 = rrrr __ Coprocessor Interface Register Selector

• Chip select logic may be Integrated into the coprocessor

Address lines not specified above are "0" during coprocessor access.

Figure 8·5. M68000 Coprocessor Interface Signal Usage

The MC68851 Paged-Memory Management Un it , however, uses FC2-FCO and A31 -AO as i nputs to perform add ress t ranslations. Thus, the MC68851 decodes the i nformat ion on the MC68020 add ress bus and fu nction code l ines interna l ly to determ i ne when an access is made to one of its coprocessor interface reg isters. Si nce the MC68851 decodes the address and fu nction code p ins i nterna l ly, it req u i res no external ch ip select logic and thus must be assig ned the Cp- ID 000.

8.3 COPROCESSOR INSTRUCTION TYPES

Fou r categories of coprocessor i nstructions are defi ned for the M68000 coprocessor interface: general, cond i t ional , context save, and context restore. These fou r categories are d ist ingu ished by the type of operat ions provided by the coprocessor i nst ruct ions contai ned in each. The i nstruction category also determ ines the coprocessor interface reg ister accessed by the MC68020 to in i t iate the coprocessor i nstruction and the commun icat ion protocol between the main processor and the coprocessor necessary for instruct ion complet ion.

During the execution of i nstructions in the general or cond it ional categories, the coprocessor can req uest services from and ind icate status to the main processor using the set of coprocessor response prim i t ive codes defi ned for the M68000 coprocessor i nterface. Dur ing the execution of the i nstruct ion in the context save and context restore categories, the coprocessor ind icates its status to the main processor by ut i l iz ing the set of coprocessor format codes defi ned for the M68000 coprocessor interface.

8-7

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•

8.3.1 Coprocessor General Instructions

The general coprocessor instruction category is used to implement data processing i n· structions and other general pu rpose instructions defined for a g iven coprocessor.

8.3.1 .1 FORMAT. The format of a general type i nstruct ion is i l l ustrated in F igure 8-6.

15 14 13 1 2 1 1 10 9 8 7 6 5 4 3 o 1 I 1 I 1 I 1 I Cp-ID I 0 I 0 I 0 I Effective Address

Coprocessor Command Optional Effective Address or Coprocessor Defined Extension Words

Figure 8·6. Coprocessor General Instruction Format (cpG EN)

For the purpose of th is d iscussion, all coprocessor instructions in the general i nstruct ion category w i l l be referred to using the cpGEN mnemonic. The actual mnemon ic and syntax used to represent a coprocessor i nstruct ion is determ i ned by the syntax of the assembler or compi ler which generates the object code for the coprocessor instructions .

The coprocessor general type i nstruct ions always consists of at least two words. As i n a l l coprocessor instructions, the f i rst word o f the i nstruct ion is a n F- l ine operat ion code (bits [1 5-1 2] = 1 1 1 1 ). The Cp-I D f ield of the F-I ine operat ion code is used by the MC68020 dur ing the coprocessor access to i nd icate which of the coprocessors i n the system w i l l execute the coprocessor i nstruct ion. The Cp- ID is placed on A 1 5-A1 3 dur ing accesses to the coprocessor i nterface reg isters (see 8.2.4.2 CPU ADDRESS SPACE).

Bits [8-6] = 000 ind icate that the i nstruct ion is in the general instruct ion category. B i ts 5-0 of the F- l i ne operat ion code may be used to encode a standard M68000 effective address specif ier (see 2.8 EFFECTIVE ADDRESS). During the execution of a cpGEN i nstruction, the coprocessor can use a coprocessor response pr imit ive to request that the MC68020 perform an effective address calcu lat ion necessary for that instruction. If the MC68020 receives one of these pr imit ives, the processor w i l l then ut i l ize the effective address specif ier f ie ld of the F- l i ne operat ion code to determ ine the effective add ress ing mode being requested.

The second word of the general type i nstruct ion is the coprocessor command word. Th is command word is written to the command coprocessor interface reg ister (command CI R) to i n i t iate the coprocessor i nstruction.

An i nstruction in the coprocessor general instruct ion category may opt ional ly inc lude a nu mber of extension words which fol low the coprocessor command word in the instruct ion format. Add it ional i nformat ion requ i red for the coprocessor i nstruct ion execution can be inc luded as coprocessor def i ned extension words. I f the coprocessor requests that the MC68020 calcu late an effective address dur ing coprocessor i nstruct ion execut ion, i nformation requ i red for the calcu lat ion must be inc luded in the i nstruct ion format as effective address extension words.

8-8

8.3.1 .2 P ROTOCOL. The execution of cpGEN instructions fol lows the protocol presented in F igure 8-7. The main processor in i t iates communication with the coprocessor by writ ing the i nstruction command word to the command G IR. The coprocessor then decodes the command word to beg i n processing assoc iated with the execution of the cpG EN instruct ion. The i nterpretat ion of the coprocessor command word is spec if ied by the coprocessor des ign and the MG68020 does not attempt to decode the i nformat ion conta ined i n th is command word.

Main Processor

M 1 Recognize Coprocessor Instruction F-Line Operation Word

Coprocessor

M2 Write Coprocessor Command Word to Command C IR _ f.!. Decode Command Word and I nitiate Command Execution

M3 Read Coprocessor Response Primitive Code from Response C IR

1 1 Perform Service Requested by Response Primitive

21 If (Coprocessor Response Primitive Indicates "Come Again"l go to M3 (see Note 1 )

M4 Proceed with Execution of Next Instruction (see Note 2 1

NOTES

-

C2 While (Main Processor Service is Requiredl do Steps 1 1 and 21 below

1 1 Request Service by Placing Appropriate Response Primitive Code in Response C IR

2 1 Receive Service from Main Processor

C3 Reflect " No Come Again" in Response CI R

C4 Complete Command Execution

C5 Reflect "Processing Finished" Status in Response C IR

1 "Come Again" indicates that further service o f the main processor i s being requested by the coprocessor. 2. The next instruction should be the operation word pointed to by the ScanPC at this point. The operation of the MC68020 ScanPC

is discussed in 8.5.2 ScanPC.

Figure 8·7. Coprocessor Interface Protocol for General Category Instructions

After wr it ing to the command GIR, the main processor wi l l read the response G IR to determine its next action. Whi le the coprocessor is execut ing an instruct ion, it may req uest services from and communicate status to the main processor by plac ing the appropriate coprocessor response pr imit ive codes i n the response G IR. When the coprocessor has completed the execution of an i nstruct ion or no longer needs the services of the main processor to execute the i nstruction, it w i l l reflect th is status in the response GIR . The main processor w i l l then proceed to the next i nstruct ion in the instruct ion stream. I f a trace exception is pend ing, however, the MG68020 w i l l not termi nate commun ication with the coprocessor unt i l the coprocessor ind icates that it has completed a l l processing associated with the cpGEN i nstruction (see 8.8.2.5 TRACE EXCEp· TIONS).

8-9

•

•

The coprocessor interface protocol i l l ustrated in F igure 8-7 a l lows the operat ion of a g iven general category i nstruction to be def ined by the coprocessor. That is, the main processor s i mply in i t iates the i nstruct ion by writ ing the i nstruction command word to the command C IR and then reads the response CIR to determ i ne its next action. The execut ion of the coprocessor i nstruct ion is then defi ned by the i nternal operat ion of the coprocessor and its use of response pri mit ives to request services from the main processor. This i nstruction protocol a l lows a wide range of operat ions to be implemented i n the general instruct ion category.

8.3.2 Conditional Coprocessor Instructions

The cond it ional i nstruction category al lows program contro l , based on the operat ions of the coprocessor, to be imp lemented in a un i form manner. The execution of i nstructions i n this category is i nherently d ivided between the main processor and the coprocessor. The coprocessor is responsible for evaluat ing a condit ion and return ing a true/fa lse i nd io cator to the main processor. The completion of the instruction execution is then hand led by the main processor based on th is true/false cond it ion i nd icator.

The imp lementat ion of i nstructions in the cond it ional category promotes eff ic ient ut i l iza· t ion of the hardware provided by design in the main processor and the coprocessor. The cond it ion on which the instruction execution is based is related to the coprocessor operat ion and is therefore eva luated by the coprocessor. The i nstruct ion completion fol lowing the cond it ion evaluation is, however, d i rect ly related to the operat ion of the main processor. The port ion of the instruction involv ing change of f low, sett ing a data alterable byte, or TRAP operat ions is executed by the main processor s i nce its architec· ture inherently imp lements these operat ions to support its i nstruct ion set.

The protocol used to execute a condit ional category coprocessor instruction is i l l us· t rated in F igure 8-8. The main processor in i t iates an i nstruct ion in th is category by wr it ing a cond it ion selector to the cond it ion C IR . The cond it ion selector is decoded by the coprocessor to determ i ne what cond it ion it should eva luate. The coprocessor can use response pr imit ives to request that the main processor provide services requ i red for the cond it ion evaluat ion. Upon completion of the cond it ion evaluation, the coprocessor returns a true/fa lse ind icator to the main processor through the response CIR us ing the N u l l pr imit ive (see 8.6.2 Nul l (No Operands» . The main processor completes the coprocessor i nstruct ion execut ion when it receives the cond it ion ind icator from the coprocessor.

8.3.2.1 BRANCH ON COPROCESSOR CON DITION INSTRUCTIONS. There are two for· mats of the M68000 Fam i ly branch i nstruction provided in the cond it ional i nstruct ion category. These i nstructions al low the control of f low of instruction execution to be based on cond it ions related to the coprocessor operat ion. The execution of these i n· struct ions is based on the condit ional branch instructions provided in the M68000 Fam i ly i nstruction set.

8.3.2.1 .1 Format. The two formats of the branch on coprocessor cond it ion instructions are i l l ustrated in F igures 8-9 and 8-1 0.

8·1 0

Main Processor


M2 Write Coprocessor Condition Selector to Condition CIR

M3 Read Coprocessor Response Primit ive Code from Response CI R

1 1 Perform Service Requested by Response Primitive

21 If (Coprocessor Response Primitive I ndicates "Come Again"l go to M3 Isee Note 1 )

M4 Complete Execution of I nstruction Based on the True/ False Condition Indicator Returned in the Response CI R

NOTES

Coprocessor

_ C1 Decode Condition Selector and I nitiate Condition Evaluation

-

C2 While (Main Processor Service is Requiredl do Steps 11 and 2 1 Below

1 1 Request Service by Placing Appropriate Response Primitive Code in Response C IR

21 Receive Service from Main Processor

C3 Complete Condition Evaluation

C4 Reflect "No Come Again" Status with True/ False Condition I ndicator in Response C IR

1 . All coprocessor response primitives, except the Nul l primitive, that allow the "Come Again" primitive attribute must indicate "Come Again" when used during the execution of a conditional category instruction. If a "Come Again" attribute is not indicated in one of these primitives, the main processor will i nitiate protocol violation exception processing Isee 8.8.2. 1 PROTOCOL VIOLATIONSI .

Figure 8·8. Coprocessor Interface Protocol for Conditional Category Instructions

1 5 1 4 13 1 2 1 1 10 9 8 7 6 5 4 3 2 o 1 I 1 I 1 I 1 I Cp- ID I 0 I 1 I 0 I Condition Selector

Optional Coprocessor Defined Extension Words Displacement

Figure 8·9. Branch On Coprocessor Condition Instruction (cpBcc.W)

15 14 1 3 1 2 1 1 10 9 8 6 5 4 3 2 o 1 I 1 I 1 I 1 I Cp- ID I 0 I 1 I 1 I Condition Selector

Optional Coprocessor Defined Extension Words Displacement - High Displacement - Low

Figure 8·1 0. Branch On Coprocessor Condition Instruction (cpBcc.L)

8·1 1

•

•

The f i rst word of the branch on coprocessor cond it ion i nstruction is the F- l i ne operat ion word. As with al l coprocessor inst ruct ions, bits [1 5-1 2) = 1 1 1 1 and bits [1 1 -9) conta in the identif icat ion code of the coprocessor that w i l l evaluate the cond it ion. Bits [8-6) are used to d ist ingu ish between the word and long word d isplacement formats of the instruction, which are denoted by the cpBcc.W and cpBcc. L mnemon ics respect ively.

Bits [5-0) of the F- l i ne operation word contain the coprocessor cond it ion selector f ield. The MC68020 writes the ent i re operat ion word to the condit ion CIR to in i t iate the branch i nstruction. The coprocessor should then use bits [5-0) to determine the cond it ion which i t should evau late.

I f the coprocessor requ i res addit ional i nformat ion to eva luate the cond it ion, th is information can be inc luded in the branch i nstruction format us ing coprocessor defi ned extension words. These extension words fol low the F-l ine operation word and the nu mber requ i red for a g iven coprocessor i nstruction is determi ned by the coprocessor des ign . The f inal word(s) of the cpBcc i nstruction format contains the disp lacement used by the main processor to calcu late the dest i nation address when the branch is taken.

8.3.2. 1 .2 Protocol. The protocol used to im plement the cpBcc. L and cpBcc.W i nstruct ions is depicted in F igure 8-8. The main processor transfers the cond it ion selector to the coprocessor by wr i t ing the F- l ine operat ion word to the condit ion C IR to in i t iate the instruction. The main processor then reads the response C IR to determ i ne its next act ion . The coprocessor can use the response pr im it ive set to request services necessary to eval uate the cond it ion. I f the coprocessor returns the false condit ion i nd icator, the main processor proceeds with the execut ion of the next instruction i n the i nstruction stream. If the coprocessor returns the true condit ion i nd icator, the d isplacement is added to the MC68020 scan PC (see 8.5.2 ScanPC) to determ i ne the dest ination address at which the main processor cont i nues i nstruction execution. The scanPC must be po int ing to the locat ion of the fi rst word of the disp lacement in the i nstruction stream when the dest inat ion address is calcu lated. The disp lacement is a two's complement integer that can be either a 1 6-bit word or a 32-bit long word. The 1 6-bit d isplacement i s s ign extended to a long word va lue before the dest i nation address is calcu lated.

8.3.2.2 SET ON COPROCESSOR CONDITION. The set on coprocessor cond it ion instruct ions are used to set or reset a f lag (a data alterable byte) based on a cond it ion eva luated by the coprocessor. The operat ion of th is i nstruct ion is patterned after the operat ion of the Scc i nstruction i n the M68000 Fam i ly instruction set. Whi le the Scc i nstruct ion does not i nherently cause a change of program f low, it is often used to set f lags upon which program f low is based.

8.3.2.2.1 Format. The format for the set on coprocessor cond it ion i nstruction, denoted by the cpScc mnemonic, is i l l ustrated in F igure 8-1 1 .

1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3

1 I 1 I 1 I 1 I Cp·ID I 0 I 0 I 1 I Effective Address

I Condition Selector Optional Coprocessor Defined Extension Words

Optional Effective Address Extension Words (0·5 Words)

Figure 8·1 1 . Set On Coprocessor Condition (cpScc)

8-1 2

o

The f i rst word of the cpScc i nstruction is the F- l i ne operation word . Th is word contains the Cp- ID f ield i n bits [1 1 -9] and bits [8-6] = 001 to identify the cpScc instruct ion. The lower six bits of the F- l ine operat ion word are used to encode an M68000 Fam i ly effective address mode (see 2.8 EFFECTIVE ADDRESS).

The second word of the cpScc i nstruction format contains the coprocessor condit ion selector in bits [5-0]. Sits [1 5-6] of this word are reserved and should be zero to i nsure compat ib i l ity with future M68000 products. This word is written to the condit ion C IR to in i t iate the cpScc i nstruction.

I f the coprocessor requ i res add i t ional i nformation to eva luate the condit ion, this informat ion can be inc l uded in the cpScc i nstruction format us ing coprocessor defi ned extension words. These extension words fol low the word conta in ing the coprocessor cond it ion selector f ie ld , and the number of extension words requ i red for a g iven coprocessor instruct ion is determi ned by the coprocessor des ign .

The f i nal port ion of the cpScc i nstruction format conta ins zero to f ive effective address extension words. I f the main processor req u i res add it ional i nformation for the calcu lat ion of the effect ive address specif ied by bits [5-0] of the F- l i ne operat ion word, th is information is inc l uded i n the effect ive add ress extension words.

8_3.2.2.2 Protocol. The protocol used to implement the cpScc instruction is depicted in F igure 8-8. The MC68020 transfers the condit ion selector to the coprocessor by wr it ing the word fol lowing the operat ion word to the cond it ion CIR. The main processor then reads the response C IR to determine' its next act ion. The coprocessor can use the response pr imit ive set to request services necessary to eva luate the condit ion . The operation of the cpScc i nstruction depends on the cond it ion evaluat ion ind icator returned to the main processor by the coprocessor. I f the coprocessor returns the false condit ion i nd icator, the main processor eva luates the effective address spec if ied by bits [5-0] of the F- l ine operation word and sets the byte at that effective address to FALSE (al l bits to zero). I f the coprocessor returns the true cond it ion i nd icator, the main processor sets the byte specif ied by the effective address to TRUE (al l bits set to one).

8.3.2_3 TEST COPROCESSOR CON DITION, DECREM ENT AND BRANCH. The operation of the test coprocessor condit ion, decrement and branch i nstruction is patterned after the DScc i nstructions provided in the M68000 Fam i ly i nstruction set. This operation is based on a coprocessor eva luated condition and a loop counter provided in the main processor and is usefu l in implement ing the DO-UNTIL type constructs used i n many h igh leve l languages.

8.3.2.3.1 Format. The format of the test coprocessor cond it ion, decrement and branch i nstruction, denoted by the cpDScc mnemonic, is i l l ustrated in F igure 8-1 2.

15 14 13 12 1 1 10 9 8 7 6 5 4 3 2 0

1 I 1 I 1 I 1 I Cp- ID I 0 I 0 I 1 I 0 I 0 I 1 I Register

( Reservedl I Condition Selector Optional Coprocessor Defined Extension Words

Displacement

Figure 8-1 2. Test Coprocessor Condition, Decrement and Branch Instruction Format (cpDBcc)

8-1 3

•

•

The f i rst word of the cpOBcc instruction is the F· l i ne operat ion word. Bits [2·0] of th is operat ion word denote the main processor data reg ister that wi l l be used as the loop cou nter dur ing i nstruction execut ion.

The second word of the cpOBcc instruction format contains the coprocessor cond it ion selector in bits [5·0] and should conta in zeroes in bits [1 5·6] to maintain compat ib i l i ty with future M68000 products. This word is written to the condit ion C IR to in i t iate the cpOBcc i nstruct ion.

I f the coprocessor req u i res add it ional i nformation to eva luate the cond it ion, th is in forma· t ion can be inc luded in the cpOBcc i nstruct ion format us ing coprocessor defi ned exten· s ion words. These extension words fo l low the word conta in ing the coprocessor cond it ion selector f ie ld i n the cpOBcc i nstruct ion format.

The d isp lacement for the cpOBcc i nstruction is contained in the last word of the i nstruc· t ion format. This d isp lacement is a two's complement 1 6·bit value that is s ign extended to long word s ize when i t is used for a dest i nat ion address calculation.

8.3.2.3.2 Protocol. The protocol used to implement the cpOBcc instruct ions is depicted i n F igure 8·8. The MC68020 transfers the cond it ion selector to the coprocessor by writ ing the word fol lowing the operat ion word to the cond it ion CIR. The main processor then reads the response CIR to determ i ne its next act ion. The coprocessor can use the response pr imit ive set to request any services necessary to eval uate the cond it ion. If the coprocessor returns the true cond it ion i ndicator, the main processor proceeds with the execution of the next i nstruct ion in the i nstruct ion stream. I f the coprocessor retu rns the false condit ion i ndicator, the main processor decrements the low·order word of the reg ister specif ied by bits [2·0] of the F· l i ne operation word. If th is reg ister is equal to m inus one ( - 1 ) after being decremented, the main processor proceeds with the execu· t ion of the next i nstruction in the instruction stream. If the reg ister is not equal to m inus one (- 1 ) after be ing decremented, the ma in processor branches to the dest ination ad· dress to cont i nue i nstruction execution.

The dest i nat ion address calcu lat ion is identical to that used for the cpBcc.W i nstruct ion. That is, the d isplacement is added to the MC68020 scanPC (see 8.5.2 ScanPC) to determine the dest ination address at which the main processor conti nues i nstruct ion execut ion. The scan PC must be pOint ing to the location of the 1 6·bit d isp lacement in the i nstruct ion stream when the dest ination add ress is calcu lated.

8.3.2.4 TRAP ON COPROCESSOR CON DITION. The operat ion of the trap on coprocessor condit ion instruct ion al lows the programmer to i n it iate exception process ing based on cond it ions related to the coprocessor operat ion.

8.3.2.4.1 Format. The format for the t rap on coprocessor cond it ion i nstruction, denoted by the cpTRAPcc mnemonic, is i l l ustrated in F igure 8·1 3.

8· 1 4

15 14 13 12 1 1 10 9 8 7 6 5 4 3 o 1 I 1 I 1 I 1 I Cp� ID I 0 I 0 I 1 I 1 I 1 I 1 I Opmode

(Reservedl I Condition Selector Optional Coprocessor Defined Extension Words

Optional Word or Long Word Operand

Figure 8·1 3. Trap On Coprocessor Condition (cpTRAPcc)

Bits [2-0] of the cpTRAPcc F-l i ne operat ion word specify the number of optional operand words inc l uded in the instruction format. The i nstruct ion format can i ncl ude zero, one, or two operand words.

The second word of the cpTRAPcc i nstruct ion format contains the coprocessor condit ion selector i n bits [5-0] and should conta i n zeroes in bits [1 5-6] to maintain compat ib i l ity with future M68000 prod ucts. This word is written to the condit ion C IR to i n it iate the cpTRAPcc instruct ion.

I f the coprocessor requ i res add it ional i nformat ion to evaluate a condit ion, th is informat ion can be inc luded in coprocessor defi ned extension words. These extension words fol low the word conta in ing the coprocessor cond it ion selector f ield in the cpTRAPcc i nstruction format.

The number of operand words ind icated by bits [2-0] of the cpTRAPcc F-l i ne operat ion word fol low the coprocessor def i ned extension words. These operand words are not exp l ic i t ly used by the MC68020, but can be used to encode i nformat ion referenced by the cpTRAPcc exception hand l ing rout ines. The legal encod ings for bits [2-0] are provided i n Table 8-1 . Other encod ings of these bits map t o the encod ings o f the cpScc i nstruct ion or i f undef ined, cause an F-l ine emu lator except ion (see APPENDIX B INSTRUCTION SEn.

Table 8·1 . cpTRAPcc Opmode Encodings

Optional Words in Opmode I nstruction Format

010 One 01 1 Two 100 Zero

8.3.2.4.2 Protocol. The protocol used to im plement the cpTRAPcc i nstruct ions is depicted i n F igure 8-8. The MC68020 transfers the cond it ion selector to the coprocessor by wri t ing the word fo l lowing the operation word to the condit ion C IA. The main processor then reads the response C IR to determ ine its next action. The coprocessor can use the response prim i t ive set to req uest any services necessary to evaluate the cond i t ion. I f the coprocessor returns the true cond it ion ind icator, the ma in processor i n it iates except ion processing for the cpTRAPcc except ion (see 8.8.2.4 cpTRAPcc INSTRUCTION TRAPS). I f the coprocessor returns the false cond it ion i ndicator, the main processor proceeds wi th the exception of the next instruction in the i nstruct ion stream.

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8.3.3 Coprocessor Context Save and Context Restore

The coprocessor context save and context restore i nstruction categories are inc l uded i n the M68000 coprocessor i nterface i n order t o support mu l t itasking programming environments. In a mult itask ing environment, the context of a coprocessor may need to be changed in an asynchronous manner with respect to the operation of that coprocessor. That is, the coprocessor may be in terrupted at any po int in the execution of an instruct ion in the general or cond it ional category in order to commence context change operat ions.

In contrast to the general and cond i t ion i nstruction categories, the context save and context restore i nstruct ion categories do not use the coprocessor response pr imit ives during the i nstruct ion execution. A set of format codes is def i ned for the M68000 coprocessor i nterface to al low the coprocessor to communicate status i nformation to the main processor dur ing the execution of i nstruct ions i n the context save and context restore categories. These coprocessor format codes are d iscussed in deta i l in 8.3.3.4 COPROCESSOR FORMAT WORDS.

8.3.3.1 COPROCESSOR CONTEXT SAVE. There is one i nstruction defi ned for the M68000 coprocessor context save i nstruction category. The coprocessor context save i nstruct ion, denoted by the cpSAVE mnemonic, a l lows the context of a coprocessor to be saved in an asynchronous manner with respect to the execut ion of coprocessor i nstructions i n the general o r cond i t ional i nstruction categories. Dur ing the execution of a cpSAVE i nstruction, the coprocessor can commun icate status information to the main processor by using the coprocessor format codes.

8.3.3.1 .1 Format. The format of the cpSAVE i nstruction is i l l ustrated in F igure 8- 1 4.

15 14 13 12 1 1 10 9 8 6 5 4 3 2 o Cp· IO Effective Address

Figure 8-1 4. Coprocessor Context Save Instruction Format (cpSAVE)

The f i rst word of the i nstruction is the F-l i ne operat ion code which contains the coprocessor ident if ication spec i f ier in bits [1 1 -9] and an M68000 effective address specif ier in bits [5-0]. The effective address encoded in the cpSAVE i nstruction is used to determ ine where the state frame assoc iated with the cu rrent context of the coprocessor w i l l be saved in memory.

The control a lterable and pre-decrement addressing modes are legal w i th the cpSAVE i nstruction. Other address ing modes encoded w i th in th is i nstruction w i l l cause the MC68020 to in i t iate F-l i ne emulator except ion processing as descri bed in 8.8.2.2 F-L iNE EMULATOR EXCEPTIONS.

.

There can be up to five effective address extension words fol lowing the cpSAVE i nstruction operation word. If the main processor requ i res add i t ional i nformation for the calculat ion of the effective add ress specif ied by bits [5-0] of the operat ion word, th is i n format ion is i ncl uded in the effective address extension words.

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8.3.3. 1 .2 Protocol. The protocol for the coprocessor context save i nstruct ion i s i l l ustrated i n F igure 8·1 5. The ma in processor i n it iates the cpSAVE instruction by read ing the save CIR. Thus, the cpSAVE i nstruct ion is the on ly coprocessor instruction that is i n· i t iated by read ing from (as opposed to wr it ing to) a reg ister i n the coprocessor i nterface reg ister set. The coprocessor communicates status i nformation assoc iated with the con· text save operat ion to the main processor by placing coprocessor format codes in the save CIA .

Main Processor


M2 Read Save CIR to I nitiate the cpSAVE Instruction

M3 I f I Format = Not Readyl do Steps 1) and 21 Below 1 I Service Pending Interrupts 21 Go to M2

M3 Evaluate Effective Address Specified in F-Line Opword and Store Format Word at Effective Address

If I Format = Emptyl go to M5 Else, Transfer Number of Bytes Indicated in Format Word From Operand CI R to Effective Address

Proceed with Execution of Next Instruction

..

Coprocessor

C1 I f I Not Ready to Begin Context Save Operationl do S teps 1 1 and 21 Below

11 Place Not Ready Format Code in Save CI R 21 Suspend or Complete Current Operations

C2 Place Appropriate Format Word in Save CI R

£) Transfer Number of Bytes Indicated in Format Word Through Operand CI R

Figure 8·1 5. Coprocessor Context Save Instruction Protocol

If the coprocessor is not ready to immediately suspend its current operat ion when the main processor reads the save C IR, the coprocessor may return a format code i nd icat ing " N ot Ready" to the main processor, The main processor wi l l then service any pending i n· terrupts and return to read the save CIR and thus re· in i t iate the cpSAVE i nstruction. After plac ing the not ready format code in the save CIR, the coprocessor should proceed to either suspend or complete the operat ions assoc iated with the i nstruct ion it is currently execut ing.

Once the coprocessor has suspended or completed al l operat ions associated with the i nstruction it is execut ing, it w i l l place a format code i n the save C IR represent ing the i nternal coprocessor state. When the main processor reads the save C IR, it transfers the format word to the effective address encoded in the cpSAVE i nstruction. The lower byte of the coprocessor format word specif ies the number of bytes of state i nformat ion, not i nc lud ing the format word, which w i l l be transferred from the coprocessor to the effective address spec if ied. If the state i nformation is not a mu lt iple of four bytes in size, the MC68020 w i l l in i t iate format error exception process ing (see 8.8.1 .5 FORMAT ERRORS). The coprocessor and main processor coord i nate the transfer of the i nternal state of the coprocessor through the use of the operand CIR. The MC68020 completes the coprocessor context save by repeated ly read ing the operand CIR and writ ing the in formation obta ined into memory unt i l the nu mber of bytes specif ied in the coprocessor format word have been transferred. Fol lowing a cpSAVE i nstruct ion, the coprocessor should be in an id le state, that is, not execut ing any coprocessor i nstruct ions.

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The cpSAVE i nstruction is a privi leged i nst ruct ion. Thus, when the main processor encou nters the cpSAVE i nstruction, it checks the supervisor bit in the status reg ister to determine if it is operat ing in the supervisor state. I f the MC68020 attempts to execute a cpSAVE i nstruct ion whi le i n the user state (bit [1 3] = 0 in status reg ister), it w i l l i n it iate privi lege violation exception processing without accessing any of the coprocessor i nterface reg isters (see 8_8_2.3 PRIVI LEGE VIOLATIONS).

The MC68020 w i l l i n it iate format error exception process ing if it reads an i nval id format word of a val id format word whose length f ield is not a mu lt ip le of four bytes f rom the save CIR during the execution of a cpSAVE i nstruct ion (see 8.3.3.4.3. Invalid Format Words). The MC68020 w i l l write a $0001 to the control C IR to abort the coprocessor instruction i n th is situation prior to except ion processing. Th is case is not inc l uded i n F igure 8-1 5 s i nce a coprocessor should generally only retu rn a not ready o r a va l id format code in the context of the cpSAVE i nstruct ion. The coprocessor may return the inva l id format word, however, if a cpSAVE is in i t iated whi le the coprocessor is execut ing a cpSAVE or cpRESTORE i nstruction and the coprocessor is not able to support the suspension of these two instruct ions.

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8.3_3.2 COPROCESSOR CONTEXT RESTORE. There i s one i nst ruct ion def ined for the M68000 coprocessor context restore i nstruct ion category. The coprocessor context restore i nstruct ion, denoted by the cpRESTORE mnemoniC, provides a mechanism by which a coprocessor can be forced to terminate any cu rrent operat ions and restore a state assoc iated with a d i fferent context of execut ion. Dur ing the execut ion of a cpRESTORE instruct ion, the coprocessor can com mun icate status informat ion to the main processor by plac ing format codes in the restore CIR.

8.3.3.2.1 Format. The format of the cpRESTORE i nstruct ion is i l l ustrated i n F igure 8-1 6.

15 14 13 1 2 1 1 10 9 8 6 5 4 3 2 Effective Address

o

Figure 8-1 6. Coprocessor Context Restore Instruction Format (cpRESTORE)

The f i rst word of the i nstruction is the F-l ine operat ion code which contains the coprocessor identif ication spec if ier in bits [1 1 -9] and an M68000 effective add ress spec if ier in bits [5-0]. The effective address encoded in the cpRESTORE i nstruct ion is used to determ ine where i n memory the coprocessor context is stored. The effect ive address pOints to the coprocessor format word conta in ing i n formation related to the context that w i l l be restored to the coprocessor.

There can be up to f ive effective address extension words fol lowing the f i rst word in the cpRESTORE i nstruction format. If the main processor requ i res add it ional i nformat ion for the ca lcu lat ion of the effective address spec i f ied by bits [5-0] of the operat ion word, th is i nformat ion is inc luded i n the effective address extension words.

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A l l memory address ing modes except the pre-decrement address ing mode are legal . I l legal effective address encod i ngs cause the MC68020 to in i t iate F- l i ne emu lator except ion processing (see 8_8_2_2 F-L iNE EMU LATOR EXCEPTIONS).

8.3.3.2.2 Protocol. The protocol for the coprocessor context restore i nstruct ion is i l l ustrated in F igure 8-1 7. When the main processor encou nters a cpRESTORE instruction i t f i rst reads a coprocessor format word from the effective address spec if ied in the i nstruct ion. This format word conta ins a format code and length f ield. The main processor reta ins a copy of the length f ield to determine the number of bytes which w i l l be transferred to the coprocessor dur ing the cpRESTORE operat ion and writes the format word to the restore C IR to i n it iate the coprocessor context restore.

Main Processor

M 1 Recognize Coprocessor Instruction F-line Operation Word

M2 Read Coprocessor Format Code from Effective Address Specified in Operation Word

M3 Write Coprocessor Format Word to Restore CI R

Coprocessor

---!.� £l Terminate Current Operations and Evaluate Format Word

g If ( I nvalid Formatl Place Invalid Format Code in the M4 Read Restore CIR ...... I----I�� Restore C IR

M5 I f ( Format= Inval id Formatl Write $0001 Abort Code to Control C IR and I nitiate Format Error Exception Processing (see Note 1 )

M6 I f ( Format= Empty/Resetl go to M.? Else, Transfer Number of Bytes Specified by Format Word to Operand CI R (see Note 21

M7 Proceed with Execution of Next Instruction

NOTES: 1 See S.S. 1 .5 FORMAT ERROR .

g If (Val id Format! Receive Number of Bytes Indicated in Format Word Through Operand C IR

2 . The MC68020 uses the length field in the format word read during M2 to determine the number of bytes to read from memory and write to the operand CI R.

Figure 8-1 7. Coprocessor Context Restore Instruction Protocol

When the coprocessor receives the format word i n the restore C IR it must termi nate any cu rrent operat ions and evaluate the format word. If the format word represents a val id coprocessor context as determ ined by the coprocessor des ign, the coprocessor w i l l return the format word t o the m a i n processor through the restore C IR and prepare to receive the number of bytes specif ied in the format word through its operand CIR .

The main processor fol lows i ts write of the format word to the restore C IR by read ing that same reg ister, I f the coprocessor returns a val id format word, the main processor w i l l proceed t o transfer the number o f bytes spec if ied (by the format word read from the cpRESTORE effective address previous ly) through the operand CIR.

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If the format word written to the restore C I R does not represent a val id coprocessor state frame, the coprocessor w i l l place an i nval id format word in the restore C I R and terminate any cu rrent operat ions. Upon rece ipt of the inva l id format code, the main processor acknowledges the format error by writ ing a $0001 to the control C IR and in i t iat ing format error except ion processing (see 8.8.1 .5 FORMAT ERROR).

The cpRESTORE i nstruction is a privi leged i nstruct ion. Thus, when the main processor encounters a cpRESTORE i nstruction, it checks the supervisor bit in the status register to determ ine i f it is operat ing in the supervisor state. I f the MC68020 attempts to execute a cpRESTORE i nstruct ion wh i le in the user state (bit[1 3] = 0 in status reg ister), i t w i l l i n i t iate privi lege violat ion exception process ing without accessing any of the coprocessor interface reg isters (see 8.8.2.3 PRIVILEGE VIOLATIONS).

8.3.3.3 COPROCESSOR INTERNAL STATE FRAM ES. The cpSAVE and cpRESTORE i n· structions t ransfer an i nternal coprocessor state frame between memory and a coprocessor. This i nternal coprocessor state frame represents the state of coprocessor operat ions. Us ing the cpSAVE and cpRESTORE i nstruct ions it is poss ible to i nterru pt coprocessor operat ion, save the context assoc iated with the current operation, and i n it iate coprocessor operat ions in a new context.

A coprocessor's internal state frame is stored as a sequence of long word entries i n memory as a resu l t o f a cpSAVE i nstruct ion execution. The format of a coprocessor state frame stored in memory is i l l ustrated in F igure 8-1 8.

Save Restore Order Order 31

o 0 n

n·1 2 n·2 3

n

23 1 5 7 o Format I Length I ( U nused, Reservedl

Coprocessor· Dependent Information

·

·

·

Figure 8·18. Coprocessor State Frame Format in Memory

Dur ing the cpSAVE instruct ion, the effective address contai ned i n the operat ion word is calcu lated and the format word is stored at th is effective address. The long words that form the coprocessor state frame are then written to descending memory add resses beg inn ing with the address spec if ied by the sum of the effective address and the format word length f ield x4. Dur ing the cpRESTORE i nstruction, the format word and long words that are contai ned in the state frame are read from ascending addresses beg inn ing with the effective add ress specif ied i n the i nstruction operat ion word.

The coprocessor format word is stored at the lowest address of the state frame in memory and is the f i rst word transferred for both the cpSAVE and the cpRESTORE instruc· t ions, The word fol lowing the format word does not conta in i nformation relevant to the coprocessor state frame, but serves to keep the i nformat ion in the state frame a mu lt ip le

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of four bytes i n size. The number of entries fol lowing the format word (at h igher addresses) is determ ined by the format word length for a g iven coprocessor state.

The informat ion contai ned in a coprocessor state frame describes a context of operat ion for that coprocessor. This description of a coprocessor context inc ludes the program in· v is ib le state informat ion and, optional ly, the program vis ib le state i nformat ion. The pro· gram i nvis ib le state i nformation is any i nternal reg isters or status information which cannot be accessed by the programmer, but is st i l l necessary for the coprocessor to con· t inue its operat ion at the point of suspension. Program vis ib le state i nformat ion i ncl udes the contents of all reg isters which appear in the coprocessor programming model and which can be d i rect ly accessed us ing the coprocessor i nstruct ion set. The information saved by the cpSAVE instruct ion must i ncl ude the program invis ib le state i nformat ion. I f cpGEN i nstructions are provided to save the program vis ib le state of the coprocessor, the cpSAVE and cpRESTORE i nstructions should only transfer the program i nvis ib le state i nformation to m i n i mize i nterru pt latency dur ing a save or restore operat ion.

8.3.3.4 COPROCESSOR FORMAT WORDS. The coprocessor commun icates status infor· mation to the main processor dur ing the cpSAVE and cpRESTORE i nstructions by ut i l iz· ing coprocessor format words. The format words def ined for the M68000 coprocessor i nterface are l i sted in Table 8·2.

Table 8·2. Coprocessor Format Word Encodings

Format Code Length Meaning 00 xx Empty/Reset 01 xx Not Ready. Come Again 02 xx Invalid Format

03-0F xx Undefined, Reserved 10-FF Length Valid Format. Coprocessor Defined

The upper byte of the coprocessor format word contains the code used to commun icate coprocessor status informat ion to the main processor. The MC68020 recogn izes four types of format words: empty/reset, not ready, inval id format, and va l id format. The MC68020 i nterprets the reserved format codes ($03·$OF) as i nval id format words, The lower byte of the coprocessor format word is used to spec ify the size in bytes (which must be a mu lt ip le of fou r) of the coprocessor state frame i n conjunction with the val id format code (see 8.3.3.4.4 Valid Format Words).

8.3.3.4.1 Empty/Reset Format Word. The empty/reset format code is returned by the coprocessor dur ing a cpSAVE i nstruct ion to ind icate that the coprocessor contains no user loaded i nformat ion . That is, no coprocessor i nstruct ions have been executed si nce either the previous cpRESTORE with the empty/reset format code or the previous hard· ware reset. If the main processor reads the empty/reset format word from the save C IR dur i ng the i n it iat ion of a cpSAVE i nstruct ion, i t w i l l s imply store the format word at the ef· fective address specif ied i n the cpSAVE instruct ion, and proceed with the execution of the next i nstruction.

I f the main processor reads the empty/reset format word from memory during the execu· tion of the cpRESTORE instruction, it w i l l write the format word to the restore C IR . The main processor w i l l then read the restore C IR and if the empty/reset format word is

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returned by the coprocessor, the main processor w i l l then cont inue with the execution of the next instruct ion . The main processor can i n it ia l ize the coprocessor by writ ing the empty/reset format code to the restore C IR. When the coprocessor receives the empty/reset format code, it w i l l term inate any current operat ions and wait for the main processor to i n it iate the next coprocessor i nstruction. I n part icu lar, the cpRESTORE of the empty/reset format word should cause the coprocessor to return th is same format word if a cpSAVE i nstruct ion is executed before any other coprocessor i nstruct ions. Thus, an em pty/reset state frame consists only of the format word and the fol lowing reserved word i n memory (see F igure 8-1 8).

8.3.3.4.2 Not Ready Format Word. When the main processor i n i t iates a cpSAVE instruct ion by read ing the save C IR, the coprocessor may return a not ready format word. The main processor w i l l then service any pend ing i nterrupts and return to re-read the save C IR. The not ready format word a l lows the coprocessor to delay the save operat ion unt i l it is ready to save i ts internal state. The cpSAVE i nstruct ion may cause the suspension of a coprocessor i nstruction in the general or cond it ional category with the capabi l i ty of resuming the suspended i nstruct ion at a later t ime. If no further main processor services are requ i red to complete coprocessor i nstruct ion execution, it may be more eff icient to complete the i nstruction and thus reduce the size of the saved state. The coprocessor deSigner should consider the eff ic iency of instruction completion versus i nstruct ion suspension and resumption when a cpSAVE i nstruct ion is i n it iated by the main processor .

When the main processor i n it iates a cpRESTORE instruction by writ ing a format word to the restore C IR, the coprocessor should genera l ly term inate any cu rrent operations and restore the state frame suppl ied by the main processor. Thus, the not ready format word shou ld general ly not be retu rned by the coprocessor dur ing the execut ion of a cpRESTORE instruct ion. If the coprocessor must delay the cpRESTORE operat ion for any reason, it can return the not ready format word when the main processor reads the restore C IA . I f the main processor does read the not ready format word from the restore CIR dur ing the cpRESTORE i nstruction, it w i l l re-read the restore C IR without servic ing any pend ing interru pts.

8.3.3.4.3 Invalid Format Words. A coprocessor may place the i nval id format word in the restore C IR i n response to the main processor's i n it iation of the cpRESTORE i nstruct ion. This i nval id format ind icates that the format word written to the restore CIR does not describe a val id coprocessor state frame. If the main processor reads th is format word dur ing the cpRESTORE i nstruction, it w i l l write the abort mask ($0001 ) to the control CI R and i n i t iate format error except ion process i ng.

A coprocessor should genera l ly not p lace an i nval id format word i n the save CIR when the main processor i n it iates a cpSAVE instruction. A coprocessor, however, may not be able to support the i n it iat ion of a cpSAVE instruction whi le it is execut ing a previously i nit iated cpSAVE or cpRESTORE i nstruction. I n th is Situation, the coprocessor can return the i nval id format word when the main processor reads the save C IR to in i t iate the cpSAVE instruction w h i le either another cpSAVE or cpRESTORE instruct ion is execut i ng. If the main processor reads an inva l id format word from the save C IR it w i l l write the abort mask to the control C I R and i n i t iate format error exception process ing (see 8.8.1.5 Format Error).

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8.3.3.4.4 Valid Format Words. Val id format words are the only type of format words i n wh ich the length f ie ld, contai ned i n the lower eight bits, is re levant. When the ma in pro· cessor reads a val id format word from the save C IR during the cpSAVE i nstruct ion, it w i l l use t h e length f ie ld t o determine the size o f t h e coprocessor state frame t o save. Dur ing the cpRESTORE i nstruct ion, the main processor uses the length f ie ld i n the va l id format word read from the effect ive address spec if ied in the i nstruction to determ ine the s ize of the coprocessor state frame that w i l l be restored.

The length f ie ld of a va l id format word must be a mu l t i ple of four bytes in size. If the main processor detects a val id format length f ie ld that is not a mu l t i ple of fou r bytes i n s ize during the execut ion of a cpSAVE or cpRESTORE instruction, the main processor w i l l write t h e abort mask ($0001 ) t o t h e control C IR a n d in i t iate format error exception processing.

8.4 COPROCESSOR INTERFACE REGISTER (CI R) SET

The M68000 coprocessor in terface is im plemented us ing a protocol based on the coprocessor i nterface reg ister set. Dur ing the execut ion of a coprocessor instruct ion, the MC68020 accesses the reg isters defi ned in the CIR set to communicate with the coprocessor. It should be noted that the i nterface reg ister set is not d i rectly re lated to the reg ister set that appears i n the coprocessor's programming model.

A memory map of the coprocessor i nterface reg ister set is i l l ustrated in F igure 8-3. The reg isters denoted by an asterisk ( * ) must be inc l uded in a coprocessor i nterface in order to al low coprocessor i nstruct ions in a l l four categories to be im plemented. The complete reg ister model must be implemented if the system is to ut i l ize a l l of the coprocessor response pr imit ives defi ned for the M68000 coprocessor i nterface. A detai led descript ion of each reg ister in the CIR set is g iven i n the fol lowing paragraphs. The hex idecimal va lue i n parenthes is fol lowing each reg ister name in the fol lowing paragraph t i t les is the reg ister offset from the base address of the CIR set.

8.4.1 Response C I R ($00)

The response CIR is a 1 6-bit reg ister through which the coprocessor communicates a l l service requests to the ma in processor us ing the coprocessor response pr imit ives. The main processor reads the response CIR to receive the coprocessor response pr imit ives during the execut ion of i nstructions in the general and condit ional i nstruct ion categories.

8.4.2 Control CIR ($02)

The control C IR is a 1 6-bit reg ister which is accessed by the main processor to acknow ledge coprocessor requested exception processing or to abort the execution of a coprocessor i nstruct ion. The format of th is reg ister is i l l ustrated in F igure 8-1 9.

15 14 13 1 2 1 1 10 9 8 7 6 5 4 3 2 1 0 (Undefined, Reservedl I XA I AB I

Figure 8·19. Control C IR Format

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The MC68020 writes the hexidecimal value $0002 to the control C IR to acknowledge the receipt of one of the three "Take Except ion" coprocessor response pr imit ives. The MC68020 writes the hexidecimal va lue $0001 to the control C IR to abort any coprocessor i nstruct ion that is in progress. The MC68020 w i l l abort a coprocessor instruct ion when it detects one of three except ion cond it ions: F- l i ne emulator detected after a response pr imit ive is read, privi lege vio lat ion caused by the supervisor check prim i t ive, or a format error (see 8.8 EXCEPTIONS).

8.4.3 Save CIR ($04)

The save CIR is a 1 6-bit reg ister through which the coprocessor commun icates status and state frame format i nformat ion to the main processor dur ing the execution of a cpSAVE i nstruct ion. The main processor reads the save CIR to i n it iate the cpSAVE i nstruction.

8.4.4 Restore CIR ($06)

The restore C IR is a 1 6-bit reg ister. The main processor in i t iates the cpRESTORE i nstruct ion by wri t ing a coprocessor format word read from memory i nto th is reg ister. Dur ing the execution of the cpRESTORE i nstruction, the coprocessor communicates status and state frame format i nformation to the main processor through the use of the restore C IR.

8.4.5 Operation Word CIR ($08)

The operat ion word C IR is a 1 6-bit reg ister to which the main processor writes the F- l i ne operat ion word of the coprocessor instruct ion in progress when it is requested by the t ransfer operat ion word coprocessor response pr imit ive (8.6.4 Transfer Operation Word).

8.4.6 Command CIR ($OA)

The command CIR is a 1 6-bit reg ister. The main processor in i t iates an i nstruct ion i n the coprocessor general i nstruction category by writ ing the i nst ruct ion command word, which fol lows the i nstruction F- l i ne operat ion word, to th is reg ister.

8.4.7 Condition CIR ($OE)

The condit ion CIR is a 6-bit reg ister through which the main processor i n it iates an i nstruct ion in the coprocessor cond it ional category by writ ing the cond it ion selector assoc iated with the i nstruct ion. The format of the condit ion C IR is i l lustrated in F igure 8-20.

15 14 13 12 1 1 10 9 8 6 5 4 3 2 o Undefined Reserved Condition Selector

Figure 8-20. Condition CIR Format

8.4.8 Operand CIR ($1 0)

The operand CIR is a 32-bit reg ister. If the coprocessor requests the transfer of an operand necessary to execute an instruction, the operand transfer is performed by the main processor reading from or wr it ing to this reg ister.

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The MC68020 transfers a l l operands to and from the operand CIR a l igned with the most s ign i f icant byte of th is reg ister. Any operand larger than four bytes is read from or written to th is reg ister us ing a seq uence of long word transfers. I f the operand is not a mult ip le of fou r bytes i n size, the port ion remai n i ng after the i n it ial long word transfers wi l l be a l igned with the most S ign i f icant byte of the operand CIR. F igure 8·21 i l l ustrates the operand a l ignment used by the MC68020 when accessing the operand C IR.

31 24 23 I Byte Operand I 16 1 5

N o Transfer

Word Operand

Three Byte Operand

Long Word Operand

Ten -Byte -

Operand

8 7

No Transfer

No Transfer

No Transfer

Figure 8·21 . Operand Alignment for Operand C IR Accesses

8.4.9 Register Select CIR ($1 4)

o

The reg ister select C IR is a 1 6·bit reg ister. When the coprocessor uses a response pr imit ive to request the transfer of a main processor control reg ister, mult ip le main proc· essor reg isters, or mu lt iple coprocessor reg isters, the main processor reads th is reg ister to ident i fy the number or type of reg isters to be transferred.

8.4.10 Instruction Address CIR ($1 8)

The i nstruction address C IR is a 32·bit reg ister. I f the coprocessor uses a response pr imit ive to req uest the address of the i nstruct ion it is currently execut ing, the main proc· essor w i l l transfer th is address to the i nstruct ion address C I A. Any transfer of the scanPC is also performed through the i nstruct ion address CIR (see 8.6. 15 Transfer Status Register and ScanPC).

8.4.1 1 Operand Address CIR ($1 C)

The operand address C IR is a 32·bit reg ister. I f a coprocessor uses a response pr imit ive to request an operand address t ransfer between the main processor and the coprocessor, the address is transferred through th is reg ister.

8.5 COPROCESSOR RESPONSE PRIMITIVES INTRODUCTION

The response prim i t ives are essent ia l ly pr imit ive i nstructions that the coprocessor issues to the main processor dur ing the execut ion of a coprocessor i nstruct ion. The coprocessor can communicate status i nformation and service requests to the main proc· essor through the use of the coprocessor response pr imit ives. With in the general and cond it ional i nstruction categories, i nd ividual i nstructions are d ist ingu ished by the opera· t ion of the coprocessor hardware and the services spec if ied by coprocessor response pri mi t ives and provided by the main processor.

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8.5.1 Coprocessor Response Primitive Format

The M68000 coprocessor response pr imit ives are encoded in a 1 6·bit word which is transferred to the main processor through the use of the response C IA. The format of the coprocessor response pr imit ives is i l l ustrated in F igure 8·22.

1 5 1 4 13 1 2 I CA I PC I DR I 1 1 10 Function

9 8 7 6 5 4 3 Parameter

2

Figure 8·22. Coprocessor Response Primitive Format

o

The encod ing of bits [1 2·0] of a coprocessor response pri m i t ive is dependent on the i nd i o vidual pri mit ive being implemented. B i ts [1 5-1 3], however, are used to spec ify part icu lar att r ibutes of the response pr imit ive which can be ut i l ized i n most of the pr imit ives def i ned for the M68000 coprocessor interface.

B i t [1 5] in the coprocessor response prim i t ive format, denoted by CA, is used to specify the come again operat ion of the main processor. Whenever the main processor rece ives a response pr imit ive from the response C IR with the come again bit set to one, it w i l l perform the service i nd icated by the pr imit ive and then return to read the response CIR. This protocol al lows a coprocessor to commun icate mult ip le response pr imit ives to the main processor during the execut ion of a s ingle coprocessor i nstruction .

B i t [1 4] i n the coprocessor response pr imit ive format, denoted by PC, i s used to specify the pass program counter operat ion. If the main processor reads a pr imit ive from the response CIR that has the PC bit set, the main processor w i l l immediately pass the current va lue of its program counter to the i nstruction address C IR as the f i rst operation i n servic ing the pr imit ive request. The value o f the program cou nter passed f rom the main processor to the coprocessor is the address of the operat ion word of the coprocessor instruction execut ing when the pr imit ive is received.

The PC bit is imp lemented in a l l of the coprocessor response prim i t ives currently def ined for the M68000 coprocessor i nterface. If an undefi ned pri mit ive or a pr imit ive that reo quests an i l l egal operation is passed to the main processor, the main processor w i l l i n i · t iate exception processing for either an F- l i ne emu lator or a protocol violation (see 8.8.2 Main Processor Detected Exceptions). If the PC bit is set in one of these response pr imit ives, however, the mai n processor w i l l pass the program counter to the i nstruction address CIR before it i n i t iates except ion processing.

The PC bit w i l l genera l ly be set i n the f i rst pr imit ive returned by the coprocessor after the main processor i n it iates a cpG EN instruction that can be executed concu rrently by the coprocessor. Si nce the main processor may proceed with i nst ruct ion stream execution once the coprocessor releases it , the coprocessor must record the instruct ion address to support any poss ible except ion processing related to the i nstruction operat ion. Excep· t ion processing related to concu rrent coprocessor instruction execut ion is d iscussed i n 8.6.16.1 TAKE PRE·I NSTRUCTION EXCEPTION.

Bit [ 1 3] of the coprocessor response pr imit ive format, denoted by DR, is the d i rection bit and is used in conj unction with operand transfers between the main processor and the

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coprocessor. If DR = 0, the d i rect ion of transfer is from the main processor to the coprocessor (main processor write). If DR = 1 , the d i rect ion of transfer is from the coprocessor to the main processor (main processor read). I f the operat ion ind icated by a g iven response prim i t ive does not i nvolve an expl ic it operand transfer, the value of th is bit is dependent on the part icu lar primi t ive encod ing .

8.5.2 Scan PC

Dur ing the execution of a coprocessor i nstruct ion, the program cou nter in the MC68020 w i l l conta i n the add ress of the operat ion word of that i nstruction. A second reg ister is used to sequential ly add ress the words that compose the remain ing port ion of a g iven instruction. Th is second reg ister is referred to as the scanPC, si nce it is used to scan the i nstruction stream during the i nstruction execution.

I f the main processor requ i res extension words i n order to calcu late an effective address or dest i nation address of a branch operat ion, it uses the scanPC to address these extension words in the i nstruction stream. A lso, if a coprocessor requests the transfer of information contained i n the i nstruction stream, the scanPC is used to address coprocessor defi ned extension words (which are provided in the i nstruction format) dur ing the transfer. As each word is referenced, the scanPC is i ncremented to point to the next word in the i nstruction stream. When an i nstruct ion is com pleted, the va lue contai ned in the scanPC is transferred to the program cou nter to address the operat ion word of the next instruction to be executed.

The va lue of the scanPC at the t ime that the main processor reads the f i rst response pri mit ive after an i nstruction i n i t iation is dependent on the i nstruction being executed. For a cpGEN instruct ion, the scanPC poi nts to the word fo l lowing the coprocessor command word. For the cpBcc i nstruct ions, the scan PC poi nts to the word fol lowing the instruct ion operat ion word. For the cpScc, cpTRAPcc, or cpDBcc i nstruct ions, the scanPC poi nts to the word fol lowing the coprocessor cond it ion speci f ier word .

If a coprocessor implementation uses optional instruction extension words to define a general or condit ional i nstruction, these words must be used consistently dur ing the i nstruction execution. Specif ical ly, dur ing the execut ion of general category i nstruct ions, when the coprocessor termi nates the i nstruct ion protocol the MC68020 assu mes that the scanPC is point ing to the operat ion word of the next i nstruct ion to be executed. Dur ing the execution of cond it ional category i nstruct ions, when the coprocessor terminates the instruction protocol the MC68020 assu mes that the scanPC is po int ing to the word fol lowing the last of any coprocessor defi ned extension words in the i nstruct ion format.

8.6 COPROCESSOR RESPONSE PRIMITIVE SET DESCRIPTION

The fol lowing sect ions present a detai led descript ion of the M68000 coprocessor response pri m it ives which are supported by the MC68020. Any response pr imit ive that the MC68020 does not recogn ize w i l l cause the MC68020 to in i t iate protocol violation except ion processing (see 8.8.2.1 PROTOCOL VIOLATIONS). This method of hand l i ng undefi ned pr imit ives al lows the support of extensions to the M68000 coprocessor response pr imit ive set to be emulated by the protocol violation except ion hand ler. Exception processing related to the coprocessor i nterface is d iscussed in 8.8 EXCEPTIONS.

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8.6.1 Busy

The busy response prim i t ive causes the main processor to re· i n it iate a coprocessor instruct ion. This pr imit ive can be used with i nstructions in the general or cond i t ional category.

8.6.1 .1 FORMAT. The format of th is pr imit ive is i l l ustrated in F igure 8-23.

15 14 o I PC

1 3 1 2

1 I 0 1 1

o 1 0 9 8

o 6 5 4 o I 0 I 0

Figure 8·23. Busy Primitive Format

3 o o I 0 I 0 I 0 I

The PC bit is a l lowed and is interpreted as described i n 8.5.1 Coprocessor Response Primitive Format.

8.6.1 .2 OPERATION. The busy pri mi t ive is ut i l ized by coproCessors which can operate concu rrent ly with the main processor but cannot buffer writes to their command or cond it ion C IR. A coprocessor may execute a cpGEN instruction concurrently with i nstruct ion execut ion i n the main processor. I f the main processor attempts to in i t iate an i nstruct ion in the general or cond it ional instruction category wh i le the coprocessor is concu rrent ly execut ing a cpGEN i nstruction, the coprocessor can place the busy pr imit ive i n the response C IR. When the main processor reads th is pr imit ive, it services pending i nterru pts (us ing a pre- i nstruct ion exception stack frame, see F igure 8-41 ) and then restarts the general or cond i t ional coprocessor i nstruct ion which it had attempted to i n it iate earl ier by wr it ing to the command or cond it ion C IR respect ively.

The busy pr imit ive should only be used as the f i rst pr imit ive retu rned after the main processor attempts to in i t iate an i nstruction in the general or cond it ional category. Thus, th is prim i t ive wi l l be used on ly i n response to a write to the command or condit ion C IR . I n part icu lar, the busy pr imit ive should not be issued at a poin t i n i nstruction execution after program vis ib le resources (coprocessor or main processor program vis ib le reg isters or operands in memory) have been altered by that i nstruction operat ion. The restart of an i nstruction after it has altered program vis ib le resou rces w i l l cause those resou rces to have i nconsistent values when the i nstruct ion execution is rei n it iated. The scanPC is not considered a program vis ib le reg ister.

A spec ial case of the operat ions of the MC68020 in response to the busy pr imit ive occurs i n re lation to breakpoint cyc les (see 6.3.5 Breakpoints). This special case occurs when a coprocessor F- l i ne i nstruction is i n i t iated through a breakpoint cyc le, the busy pr imit ive is retu rned in response to the i nstruction in i t iation, and an i nterrupt is pend ing . I f these th ree cond it ions are met, the breakpo int cyc le is re-executed after the i nterru pt except ion process ing has been completed. This is of part icu lar interest to designers that i ntend to use breakpoi nts to i ncrement or decrement a cou nter i n order to monitor the number of passes through a loop, s ince this spec ial case may cause mul t i ple breakpo int acknowledge cyc les to be executed dur ing a S ing le pass through a loop.

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8.6.2 Nul l (No Operands)

The n u l l coprocessor response pri m i t ive is used to communicate coprocessor status i nformat ion to the main processor. This pr imit ive can be used in conj unction with i nstruct ions i n the general and cond it ional categories.

8.6.2.1 FORMAT. The format of the nu l l pr imit ive is i l lustrated in F igure 8-24.

1 5 1 4 13 12 I I 1 0 9 8 7 6 5 4 3 2 0 I CA I PC I 0 I 0 I 1 I 0 I 0 I IA I 0 I 0 I 0 I 0 I 0 I 0 PF I T F

Figure 8-24. Nul l Primitive Format

The CA and PC bits are implemented and are i nterpreted as described in 8.5.1 Coprocessor Response Primitive Format.

Bit [8] of the pr imit ive format, denoted by lA, is used to ind icate the i nterrupts al lowed pri m it ive attribute. This bit determ ines whether the MC68020 w i l l service pend ing

· inter

rupts prior to re-read ing the response CIR after rece iv ing a n u l l pr imit ive.

B i t [ 1 ] in the n u l l pr imit ive format, denoted by PF, is used to ind icate the process ing f i n ished status of the coprocessor. That is, PF = 1 ind icates that the coprocessor has completed a l l processing associated with an i nstruct ion.

Bit [0] of the pri m i t ive format, denoted by TF, is used to provide the true/false condit ion i nd icator to the main processor dur ing the execution of a cond it ional category instruction. TF = 1 is the true cond it ion spec i f ier and TF = 0 is the false condit ion spec if ier. The TF bit is only re levant for n u l l pri m i t ives i n which CA = 0 that are used by the coprocessor duri ng the execution of a condit ional type i nstruct ion.

8.6.2.2 OPERATION. A n u l l pr imit ive with CA = 1 is hand led i n the same man ner by the MC68020 whether execut ing a general or cond it ional type coprocessor instruction. I f the n u l l pri m it ive is issued by the coprocessor with CA = 1 and IA = 1 , the main processor w i l l service pend ing interru pts (generating a m id-i nstruct ion stack frame, see F igure 8-43) and return to read the response CIR . If the nu l l pr imit ive is issued with CA = 1 and IA = 0, the main processor wi l l s imply re-read the response C IR without serv ic ing any pend ing i nterru pts.

The main processor completes the execution of a cond it ional category coprocessor i nstruction when it receives a nu l l , CA = 0 prim i t ive. A nu l l , CA = 0 pr imit ive is used to commun icate a cond it ion eval uation ind icator to the main processor dur ing the execution of a cond it ional instruct ion and thus end the d ialogue between the main processor and coprocessor for that i nstruction. The PF bit is not re levant dur ing cond it ional i nstruct ion execution s ince there is an impl ied "coprocessor process ing f i n ish" by the nu l l , CA = 0 pr imit ive.

The d ialogue between the main processor and coprocessor for instruct ions in the general category is normal ly term inated after any pr imit ive which does not have CA = 1 . If a trace exception is pend i ng, however, the instruction d ialogue is not termi nated unt i l the main processor reads a nu l l , CA = 0, PF = 1 pr imit ive from the response CIR (see 8.8.2.5 TRACE EXCEPTIONS). Thus, the main processor w i l l cont inue to re-read the response

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CIR unt i l it receives a n u l l , CA = 0, PF = 1 prim i t ive, and w i l l then proceed with trace exception process i ng. Under these c i rcumstances, the main processor w i l l service pending interru pts before re-read ing the response CIR i f IA = 1 .

A coprocessor may be able to execute a cpGEN instruct ion concu rrently with the execution of main processor i nstructions and buffer one write to either its command or condit ion CIR. In this s i tuat ion, a n u l l pri mit ive with CA = 1 can be issued when the coprocessor is concurrent ly execut i ng a cpG EN instruction and the main processor in i t iates another general or cond it ional coprocessor i nstruct ion. This pr imit ive i nd icates that the coprocessor is currently busy and the main processor shou ld re-read the response C IR without rei n it iat ing the instruction. The IA bit of th is n u l l pr imit ive should general ly be set to m i n i mize i nterrupt latency whi le the main processor is wai t ing for the coprocessor to complete the general category i nstruct ion.

A summary of the encodings of the n u l l pr im i t ive is provided in Table 8-3.

Table 8-3_ Nul l Coprocessor Response Primitive Encodings

CA PC IA PF TF General Instructions Conditional Instructions x 1 x x x Pass Program Counter to Instruction Same as General Category

Address C IR , Clear PC Bit and Proceed with Operation Specified by CA, lA, PF, and TF Bits

1 0 0 x x Re·Read Response C IR , Do Not Service Same as General Category Pending Interrupts

1 0 1 x x Service Pending Interrupts and Re-Read Same as General Category the Response C IR

0 0 0 0 c If ITrace Pendingl Re-Read Main Processor Completes Response CI R Instruction Execution

Else, Execute Next Instruction Based on TF = c 0 0 1 0 c If (Trace Pendingl Service Pending Main Processor Completes

Interrupts and Re-Read Response C IR Instruction Execution Else, Execute Next Instruction Based on TF = c

0 0 x 1 c Coprocessor Instruction Completed; Main Processor Completes Service Pending Exceptions or Execute Instruction Execution Next Instruction Based on TF = c

x = Don' t Care c = 1 or 0 Depending on Coprocessor Condition Evaluation

8.6_3 Supervisor Check

The supervisor check pr imit ive a l lows the coprocessor to verify that the main processor is operat i ng in the su pervisor state dur ing the coprocessor i nstruct ion execution. This pr imit ive can be used in conj u nction with i nstruct ions i n the general and cond it ional coprocessor instruct ion categories.

8.6_3.1 FORMAT. The format of the supervisor check pr imit ive is i l l ustrated in F igure 8-25.

15 14 13 12 1 1

1 I PC I 0 0 0 1 0 9 1 I 0

8 o

6 5 4

o I 0 I 0 I 0 3 2

o I 0

Figure 8-25. Supervisor Check Primitive Format

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o o o I

The PC bit i s a l lowed and is i nterpreted as descri bed i n 8.5.1 Coprocessor Response Primitive Format. Whi le bit [1 5] is shown as 1 , th is bit is actual ly a "don't care" value for th is pr imit ive. That is, the pr imit ive w i l l result in the actions spec if ied below regard less of the va lue of th is bit . If th is pr imit ive is issued with bit [ 1 5] = 0 dur ing a cond it ional category i nstruction, however, the main processor w i l l i n it iate protocol violat ion excep· tion processing.

8.6.3.2 OPERATION. When the main processor reads the su pervisor check prim i t ive f rom the response CIR , it checks the va lue of the S bit in the status register. I f S = 0 (main proc· essor operat ing in user mode), the main processor aborts the coprocessor instruction ex· ecution by writ ing a $0001 mask to the control CIR. The main processor then in i t iates privi lege violation except ion processing (see 8.8.2.3 PRIVILEGE VIOLATIONS). I f the main processor is in the su pervisor mode when it receives th is pr imit ive, it w i l l s imply reo read the response CIR .

The purpose of the su pervisor check primit ive is to al low the implementat ion of privi· leged i nstructions in the coprocessor general and condit ional instruction categories. Thus, th is pr imit ive should be the f i rst one issued by the coprocessor dur ing the d ialog for an instruction which is im plemented as privi leged.

8.6.4 Transfer Operation Word

The transfer operat ion word pr imi t ive al lows the coprocessor to obta in a copy of the coprocessor i nstruct ion operation word. This pr imit ive can be used with general or condi· t ional category i nstruct ions.

8.6.4.1 FORMAT. The format of the transfer operation word prim i t ive is i l l ustrated in F igure 8·26.

15 14 13 12 1 1 10 I CA I PC I 0 0 I 0 I 1

9 8 7 6 5 4 3

Figure 8·26. Transfer Operation Word Primitive Format

1 0

o I 0

Both the CA and PC bits are al lowed and are i nterpreted as descri bed i n 8.5.1 Coprocessor Response Primitive Format. I f th is primi t ive is issued with CA = 0 dur ing a cond i t ional category instruct ion, the main processor w i l l i n i t iate protocol violat ion except ion process ing .

8.6.4.2 OPERATION. After read ing th is pr imit ive f rom the response C IR, the main proc· essor transfers the operation word of the cu rrently execut ing coprocessor i nstruct ion to the operat ion word C IR. The va lue of the scanPC is not affected by th is pr imit ive.

8.6.5 Transfer From Instruction Stream

The main processor transfers operands from the i nstruction stream to the coprocessor. This primi t ive is al lowed with general and cond it ional category instruct ions.

8.6.5.1 FORMAT. The format of the transfer from i nstruction stream pr imit ive is i l l us· trated i n F igure 8·27.

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1 5 1 4 13 12 I CA I PC I 0 0

1 1 1 0 9 8 6 5 4 3 Length

o

Figure 8·27. Transfer From Instruction Stream Primitive Format

Both the CA and PC bits are al lowed and are interpreted as described in 8.5.1 Coprocessor Response Primitive Format. If th is prim i t ive is issued with CA = 0 dur ing a cond it ional category i nstruct ion, the main processor w i l l i n i t iate protocol violation exception processing.

B its [7·0] of the pr imit ive format spec i fy the length, i n bytes, of the operand to be transferred from the i nstruction stream to the coprocessor. The length must be an even number of bytes. If an odd length is speci f ied, the main processor w i l l i n i t iate protocol violation exception processing (see 8.8.2.1 PROTOCOL VIOLATIONS).

8.6.5.2 OPERATION. When the main processor reads th is pr im i t ive from the response CIR it copies the number of bytes ind icated by the length field from the instruction stream to the operand CIR. Thus, coprocessor defi ned extension words provided in the instruction format can be transferred to the coprocessor in response to this prim i t ive. The f i rst word or long word transferred is at the locat ion poi nted to by the scanPC when the prim i t ive is read by the main processor and the scan PC is i ncremented by two after each word is transferred. Thus, the scanPC is incremented by the total nu mber of bytes transferred and poi nts to the word fol lowing the last word transferred when the pr imit ive execut ion has completed. The main processor w i l l transfer the operands from the i nstruction stream us ing a sequence of long word writes to the operand CIR. I f the length field is not an even mult i ple of four bytes, the last two bytes form the i nstruct ion stream are transferred us ing a word write to the operand CIR.

8.6.6 Evaluate and Transfer Effective Address

The effective address specif ied in the coprocessor i nstruct ion operat ion word is eva luated by the main processor and transferred to the coprocessor. This pr imit ive is a l lowed with general category i nstructions. I f this prim i t ive i s issued by the coprocessor dur ing the execut ion of a condi t ional category i nstruct ion, the main processor w i l l i n i t i ate protocol violat ion except ion processing .

8.6.6.1 FORMAT. The format of the evaluate and t ransfer effective address pri mit ive is i l l ustrated i n F igure 8-28.

1 5 1 4 1 3 I CA I PC I 0

1 2 1 1 o I 1

1 0 9 8

o I 1 I 0

7

o

6 5

o I 0

4 3

o I 0

2

o

1 0

o I 0

Figure 8·28. Evaluate and Transfer Effective Address Primitive Format

Both the CA and PC bits are al lowed and are i nterpreted as descri bed in 8.5.1 Coprocessor Response Primitive Format.

8.6.6.2 OPERATION. When the main processor receives th is pr imit ive dur ing the execution of a general category i nstruct ion, the main processor eva luates the effective address specif ied in the i nstruct ion operat ion word. If the effect ive address requ i res any

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extension words, the scanPC is assu med to be poi nt ing to the f i rst of these words when the main processor receives this pr imit ive. The scanPC is incremented by two after each of these extension words is referenced by the mai n processor. After the effective address is calcu lated, the resu l t ing 32-bit va lue is wri tten to the operand address CIA .

Only al terable control addressing modes are calcu lated by the MC68020 i n response to th is pr imit ive. I f the add ress ing mode i n the operation word is not an alterable control mode, the main processor aborts the i nstruction by writ ing a $0001 to the control C I A and in i t iates F- l i ne emulat ion exception processing (see 8.8.2.2 F·Ll N E EMULATOR EXCEPTIONS).

8.6.7 Evaluate Effective Address and Transfer Data

The main processor transfers an operand between the coprocessor and the effective address specif ied in the coprocessor i nstruction operat ion word. This pr imit ive is a l lowed with general category i nstructions. If th is pr imit ive is used by the coprocessor during the execut ion of a cond it ional category instruction, the main processor w i l l i n i t iate protocol violation exception processing.

8.6.7.1 FORMAT. The format of the eval uate effective address and transfer data prim i t ive is i l l ust rated in F igure 8-29.

15 1 4 13 12 1 1 10 9 8 7 6 5 4 3 I CA I PC I DR I 1 I a Valid EA Length a

Figure 8·29. Evaluate Effective Address and Transfer Data Primitive Format

The CA, PCr and DA bits are a l lowed and are i nterpreted as described in 8.5.1 Coprocessor Response Primitive Format.

The val id effect ive address f ie ld (bits [1 0-8]) of the pr imit ive format a l lows the coprocessor to specify the legal effective address categories for this pr imit ive. I f the effect ive add ress specif ied in the i nstruction operat ion word is not a member of the c lass specif ied by bits [1 0-8], the main processor aborts the coprocessor i nstruction by wr it ing $0001 to the control C IA , and in i t iates F- l i ne emu lation exception process ing . The val id effective address f ie ld encod i ngs are l i sted in Table 8-4.

Table 8·4. Valid Effective Address Codes

000 Control Alterable 001 Data Alterable 010 Memory Alterable al l Alterable 100 Control 101 Data 1 10 Memory 1 1 1 Any Effective Address I N o Restrictionl

Note that the control a l terable, data a lterable, and memory alterable categories are determ i ned by the i ntersect ion of the a lterable effective address ing category with the

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cont rol , data, and memory effective address ing categories respect ively (see Table C-2. Effect ive Address ing Mode Categories). If the val id effect ive address f ie lds speci f ied i n the pr imit ive and i n the i nstruction operat ion word match, the MC68020 w i l l i n i t iate protocol violat ion except ion processi ng if the pr imit ive requests a write to a non-a lterable effect ive address.

The length in bytes of the operand to be transferred is specif ied by bits [7-0) of the pr imit ive format. There are several restrict ions on the operand length field used with certain effective add ress ing modes. I f the effect ive address is a main processor reg ister (reg ister d i rect mode), only operand lengths of one, two, or four bytes are legal ; other lengths cause the mai n processor to i n it iate protocol violation exception processing. Thus, a length of zero for a reg ister d i rect effective add ress w i l l result i n a protocol violat ion. Operand lengths of zero through 255 bytes are legal i n conj unction with the memory address ing mode.

There is one exception to the length f ield for the memory effective add ress category. I f the effective address is immed iate, the operand length must be one or even and the d i rect ion of transfer must be to the coprocessor; otherwise, the mai n processor w i l l i n i t iate protocol violat ion except ion processing.

8.6.7.2 OPERATION. When the main processor receives th is pr imit ive dur ing the execut ion of a general category instruction, i t f i rst verif ies that the effective address encoded in the i nstruct ion operat ion word is in the effective address category specif ied by the pr imit ive. I f th is cond it ion is sat isf ied, the effective add ress is calcu lated us ing any necessary effect ive address extension words located at the cu rrent scanPC address and the scanPC is incremented by two for each word referenced. The main processor then t ransfers the number of bytes specif ied in the pr imit ive between the operand C I R and the effective address using long word transfers whenever possi ble. Refer to 8.4.8 Operand C IR for i nformat ion concern ing operand a l ignment for t ranfers i nvolvi ng the operand C I R.

The d i rect ion of the operand transfer is speci f ied by the DR bit. DR = 0 ind icates a transfer f rom the effect ive add ress to the operand C IR and DR = 1 ind icates a transfer from the operand CI R to the effect ive add ress.

If the effective add ress is the predecrement mode, the address reg ister used is decremented by the s ize of the operand before the transfer. The bytes wi th in the operand are then t ransferred to/from ascending add resses beg inn i ng with the locat ion spec if ied by the decremented add ress reg ister. If the effective addressing mode is predecrement, A7 is used as the address reg ister, and the operand is one byte i n length, A7 w i l l be decremented by two to mainta in a word a l igned stack.

For the post i ncrement effective add ress ing mode, the address reg ister used IS incremented by the size of the operand after the transfer. The bytes wi th in the operand are t ransferred to/from ascend ing add resses beg inn i ng with the locat ion spec if ied by the address reg ister. If the effective address ing mode is post i ncrement, A7 is used as the add ress reg ister, and the operand is one byte in length, A7 w i l l be i ncremented by two after the transfer to mainta in a word a l igned stack. It shou ld be noted that the transfer of odd length operands of lengths g reater than one us ing the - (A7) or (A7) + addreSSing modes can resu l t in a stack pOinter which is not word a l i gned.

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The effect ive address calcu lation is repeated each t ime that th is pr imit ive is issued during the execution of a g iven i nstruction. The effective address is calcu lated using the cu rrent contents of any add ress and data reg isters used in the address ing mode. The main processor locates any necessary effect ive add ress extension words at the cu rrent scanPC locat ion and increments the scanPC by two for each extension word referenced in the i nstruction stream.

The MC68020 s ign extends byte and word size operands to a long word va lue when they are transferred to an address reg ister (AO·A7) us ing th is pr imit ive and the reg ister d i rect effect ive add ress ing mode. Byte and word size operands transferred to a data reg ister (DO·D7) w i l l only overwrite the lower byte or word respectively of the data reg ister referenced.

8.6.8 Write to Previously Evaluated Effective Address

The main processor transfers an operand from the coprocessor to a previously eva luated effect ive add ress. This pr imi t ive is al lowed wi th general category i nst ruct ions. I f th is pr imit ive is used by the coprocessor during the execution of a cond i t ional category i nstruct ion, the main processor w i l l i n it iate protocol violat ion exception processing.

8.6.8.1 FORMAT. The format of the wri te to previously eva luated effective add ress pr imit ive is i l l ust rated in F igure 8-30.

15 14 13 12 1 1 10 9 8 7 6 I CA I PC I 1 I 0 I 0 I 0 I 0 I 0

5 4 3 Length

o

Figure 8·30. Write to Previously Evaluated Effective Address Primitive Format

The CA, and PC bits are a l lowed and are i nterpreted as descr ibed in 8.5.1 Coprocessor Response Primitive Format.

The length in bytes of the operand t ransferred is spec i f ied in bits [7-0] of the pr imit ive format. The MC68020 w i l l t ransfer operands between zero and 255 bytes in length.

8.6.8.2 OPERATION. When the main processor receives this pri mit ive during the execut ion of a general category i nstruction, i t t ransfers an operand from the operand CIR to an effective add ress specif ied by a temporary reg ister w i th in the MC68020. This tem porary reg ister w i l l conta in the eva luated effective address spec if ied in the coprocessor i nstruct ion operation word i f th is pr imit ive is used after either the eva luate and t ransfer effective address, eva luate effect ive address and transfer data, or transfer mul t ip le coprocessor reg isters coprocessor response pr imit ive has been executed during the coprocessor i nstruct ion. I f th is pr imit ive is used dur ing an i nstruction i n which the effective add ress specif ied in the i nstruction operat ion word has not been calculated, the effective add ress used for the write is undefi ned. Also, if the previously eva luated effective address was reg ister d i rect, the va lue written to in response to th is pri mi t ive is undefi ned.

The value on the MC68020 fu nction code s ignals during the write operat ion w i l l ind icate either su pervisor or user data space depending on whether the S bit in the MC68020 status reg ister is one or zero respectively when th is pr imit ive is received. Whi le a

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coprocessor shou ld req uest writes to only alterab le effective add ress ing modes, the MC68020 does not check the type of effective add ress used in conj unction with the execut ion of th is pr imit ive. For example, if the previously eva luated effective add ress was program counter relat ive and the MC68020 is in the user state (S = 0 in status reg ister) when th is pr imit ive is received, the MC68020 w i l l write to user data space at the previously calcu lated program re lat ive add ress (the 32-bit va lue contai ned in the temporary internal reg ister of the processor).

Operands of length greater than four bytes are t ransferred in increments of fou r bytes (operand parts) when possi ble. The main processor w i l l f i rst read a long word operand part from the operand CI R and then transfer th is part to the current effective address locat ion. The t ransfers cont inue in th is manner us ing ascending memory locat ions unt i l a l l of the long word operand parts are transferred and any remain ing operand part is then t ransferred using a one, two, or three byte transfer. For al l effective addresses in the memory category, the operand parts are stored in memory using ascending addresses beg i n n i ng with the address contai ned in the MC68020 tem porary reg ister.

The execution of th is pri m i t ive wi l l not mod i fy any of the reg isters that appear in the MC68020 programmers model. If the previously evaluated effective address ing mode ut i l ized any of the MC68020 i nternal address or data reg isters, the effective add ress value used w i l l be the last value generated by the evaluate and transfer effective address, eval uate effect ive address and transfer data, or transfer mul t ip le coprocessor reg isters pr imit ives. Thus, the write to previously evaluated effective add ress pr imit ive w i l l not modify any data or address reg isters even if the previously eva luated effective address is predecrement or post i ncrement mode.

Note that the take add ress and t ransfer data pr imit ive described in 8.6.9 Take Address and Transfer Data does not rep lace the effective address value which has been calcu lated by the MC68020. Thus, the address that the main processor obta ins i n response t o the take address and transfer data pr imit ive can not be referenced by the write to previously eva luated effect ive address pr imit ive.

It is possib le to i mplement read-mod ify-write i nstructions (but not ind iv is ible bus cycles) us ing th is pr imit ive and the eva luate effective address and t ransfer data pr imit ive.

8.6.9 Take Address and Transfer Data

The main processor t ransfers an operand between the coprocessor and an address supp l ied by the coprocessor. This pr imit ive can be used with general or cond it ional category i nstructions.

8.6.9.1 FORMAT. The format of the take address and t ransfer data pr imit ive is i l l ust rated in F igure 8-31 .

1 5 14 1 3 1 2 1 1 10 9 8 7 6 5 4 3

I CA I PC I DR I 0 I 0 I 1 I 0 I 1 Length

Figure 8·31 . Take Address and Transfer Data Primitive Format

8-36

o

The CA, PC, and DR bits are al lowed and are i nterpreted as descr ibed i n 8.5.1 Coprocessor Response Primitive Format. If th is pr imit ive is issued with CA = 0 during a cond i t ional category instruct ion, the main processor w i l l i n i t iate protocol violat ion except ion processing.

The operand length, which can be from zero to 255 bytes, is specif ied by bits [7·0] of the pr imit ive format.

8.6.9.2 OPERATION. The main processor f i rst reads a 32-bit address from the operand address C IR. The operand is then transferred, us ing a series of long word t ransfers, be· tween th is address and the operand C IR. The operand parts are read or written to ascending addresses start ing with the add ress read from the operand address CI R. I f the operand length is not a mu lt ip le of fou r bytes, the f i nal operand part is transferred us ing a one, two, or three byte transfer.

The funct ion code s ignals used wi th the address read f rom the operand add ress C IR ind i cate e i ther supervisor or user data space depend ing on whether the S bit i n the MC68020 status reg ister is one or zero respectively when th is pri mi t ive is received.

8.6.10 Transfer To/From Top of Stack

The main processor transfers an operand between the coprocessor and the top of the current ly act ive main processor stack (see 2.10 SYSTEM STACK). This pr imit ive can be used with general or condit ional category i nstructions.

8.6.1 0.1 FORMAT. The format of the transfer to/from top of stack pr imit ive is i l l ustrated in F igure 8-32.

15 14 13 12 1 1 10 9 8 6

I CA I PC I DR I 1 I 1 I 1 I 0

5 4 3 Length

2

Figure 8·32. Transfer To/From Top of Stack Primitive Format

o

The CA, PC, and DR bits are al lowed and are i nterpreted as described i n 8.5.1 Coproces· sor Response Primitive Format. I f th is prim i t ive is issued with CA = 0 dur ing a cond it ional category instruction, the main processor w i l l i n i t iate protocol violation except ion processing.

B its [7-0] of the pr imit ive format specify the length i n bytes of the operand to be transferred. The operand may be one, two, or four bytes in length; other length f ield val ues cause the main processor to in i t iate protocol violat ion exception process i ng.

8.6.10.2 OPERATION. I f DR = 0, the main processor transfers the operand from the current ly act ive system stack to the operand CIR . The imp l ied effective add ress used for the t ransfer is therefore the (A7) + address ing mode. Operands of length one cause the stack pointer to be i ncremented by two after the transfer to maintain word a l ignment of the stack.

If DR = 1 , the main processor transfers the operand from the operand C IR to the currently active stack. The imp l ied effect ive address used for the transfer is therefore the - (A7)

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addressing mode. Operands of length one cause the stack pointer to be decremented by two before the t ransfer to mainta in word a l ignment of the stack.

8.6. 1 1 Transfer Single Main Processor Register

The main processor t ransfers an operand between one of its data or add ress reg isters and the coprocessor. This pr imit ive can be used with general or condit ional category i nstructions.

8.6.1 1 .1 FORMAT. The format of the transfer s ing le main processor reg ister pr imit ive is i l l ust rated i n F igure 8-33.

15 14 13 12 1 1 10 9 8 7 6 5 I CA I PC I DR I 0 I 1 I 1 I 0 I 0 I 0 I 0 I 0 4 3 2 0 o 101 A I Register

Figure 8·33. Transfer Single Main Processor Register Primitive Format

The CA, PC, and DR bits are a l lowed and are i nterpreted as described i n 8.5.1 Coprocessor Response Primitive Format. I f th is pr imit ive is issued w i th CA = 0 duro ing a cond i t ional category i nstruction, the main processor w i l l i n i t iate protocol violation exception processi ng.

B i t [3], denoted by DIA, ind icates whether an address or data reg ister is referenced . DIA = 0 ind icates a data reg ister and DIA = 1 ind icates an address reg ister. B its [2-0] iden· t ify the reg ister nu mber referenced.

8.6.1 1 .2 OPERATION. I f DR = 0, the main processor writes the long word operand con· tai ned in the specif ied reg ister to the operand CIR . If DR = 1 , the main processor reads a long word operand f rom the operand C IR and transfers it to the ind icated data or address reg ister.

8.6. 1 2 Transfer Main Processor Control Register

The main processor transfers a long word operand between one of its control reg isters and the coprocessor. This pr imit ive can be used with general or cond it ional category i nstruct ions.

8.6.1 2.1 FORMAT. The format of the t ransfer main processor control reg ister pr imit ive is i l l ust rated i n F igure 8-34.

15 14 13 1 2 1 1 10 9 8 7 6 5 I CA I PC I DR I 0 I 1 I 1 I 0 I 1 o I 0 I 0 4 3 2

o I 0 I 0 1 0 o I 0

Figure 8-34. Transfer Main Processor Control Register Primtive Format

The CA, PC, and DR bits are a l lowed and are i nterpreted as descri bed i n 8.5.1 Coprocessor Response Primitive Format. I f t h i s pr imit ive is issued w i t h C A = 0 duro ing a cond i t ional category i nstruction, the main processor w i l l i n it iate protocol violat ion except ion proceSS ing .

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8.6.1 2.2 OPERATION. When the main processor receives th is pr imit ive it f i rst reads a control reg ister select code from the reg ister select CIR . This code determ ines which main processor contro l reg ister is referenced during the transfer. The control reg ister select codes recognized by the MC68020 are shown in Table 8·5. If the control reg ister selector code is not recogn ized by the MC68020, the MC68020 w i l l i n itate protocol viola· t ion except ion process ing (see 8.8.2.1 PROTOCOL VIOLATIONS).

Table 8·5. Main Processor Control Register Selector Codes

Hex Control Register xOOO Source Function Code I SFCI Register xOOl Destination Function Code IDFCI Register x002 Cache Control Register ICACRI xBOO User Stack Pointer IUSP) x801 Vector Base Register IVBR) x802 Cache Address Register ICAAR) x803 Master Stack Pointer IM SP) x804 Interrupt Stack Pointer l i SP)

All other codes cause a protocol violation exception

After read ing a val id code from the reg ister select C IR, if DR = 0, the main processor writes the long word operand from the spec if ied control reg ister to the operand CIA . I f DR = 1 , the ma in processor reads a long word operand from the operand CIR and p laces i t i n the spec if ied control reg ister.

8.6.1 3 Transfer Multiple Main Processor Registers

The main processor transfers long word operands between one or more of its data or address reg isters and the coprocessor. This pr imit ive can be used with general or cond i· t ional category i nstructions.

8.6.1 3.1 FORMAT. The format of the transfer mul t ip le main processor reg isters pr imit ive is i l l ustrated in F igure 8·35.

15 14 I CA I PC 13 12 DR I 0

1 1 10 9 8 7 6 5 4 3 o I 0

2 0 o I 0 I 0

Figure 8·35. Transfer Multiple Main Processor Registers Primitive Format

The CA, PC, and DR bits are a l lowed and are i nterpreted as descri bed in 8.5.1 Coprocessor Response Primitive Format. I f th is pr imit ive is issued with CA = 0 dur ing a condit ional category instruct ion, the main processor w i l l i n i t iate protocol violat ion ex· cept ion processing.

8.6.1 3.2 OPERATION. When the main processor receives th is pr imit ive it f i rst reads a 1 6·bit reg ister select mask from the reg ister select CIR. The format of the reg ister select mask is i l l ust rated in F igure 8·36. A reg ister w i l l be transferred if the bit correspond i ng to that reg ister in the reg ister select mask is set to one. The selected reg isters are trans· ferred i n the order 00·07 and then AO·A7.

8·39

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15 14 13 1 2 1 1 10 9 8 7 6 5 4 3 2 1 0 I A7 I A6 I A5 I A4 I A3 I A2 I A1 I AO I 07 I D6 I 05 I 04 I 03 I 02 I 01 I DO I Figure 8·36. Register Select Mask Format

If DR = 0, the main processor writes the contents of each reg ister ind icated in the reg ister select mask to the operand CIR us ing a sequence of long word transfers. If DR = 1 , the main processor reads a long word operand from the operand C I R into each reg ister i n· d icated i n the reg ister selector mask. The reg isters are transferred i n the same order regard less of the d i rection of transfer ind icated by the DR bit in the pr imit ive.

8.6.1 4 Transfer Multiple Coprocessor Registers

From zero to s ixteen operands are transferred between the effective address specif ied i n the coprocessor i nstruct ion and the coprocessor. This pr imit ive is a l lowed w i t h general category i nstruct ions. I f th is pr imit ive is issued by the coprocessor during the execution of a condi t ional category i nstruct ion, the main processor w i l l i n i t iate protocol violat ion exception proceSSing .

8.6.1 4.1 FORMAT. The format of the transfer mu l t ip le coprocessor reg isters pr imit ive is i l l ust rated i n F igure 8·37.

15 14 13 12 1 1 I CA I PC I DR I 0 I 0

10 9 8

o I 0 I 1 7 6 5 4 3

Length 2 o

Figure 8·37. Transfer Multiple Coprocessor Registers Primitive Format

The CA, PC, and DR bits are a l lowed and are i nterpreted as descri bed i n 8.5.1 Coprocessor Response Primitive Format.

Bits [7-0) of the pr imit ive format ind icate the length in bytes of each operand transferred. The operand length must be an even number of bytes, odd length operands w i l l cause the MC68020 to i n it iate protocol violat ion exception process ing (see 8.8.2.1 PROTOCOL VIOLATIONS).

8.6.1 4.2 OPERATION. When the main processor receives th is pr imit ive it w i l l calcu late the effective address spec if ied in the coprocessor i nstruction operat ion word. The scanPC should be poi nt ing to the f i rst of any necessary effective address extension words when th is pr imit ive is read from the response CIR and the scanPC w i l l be i ncremented by two for each extension word reference dur ing the effective address calcu lation. For transfers from the effective address to the coprocessor (DR = 0), the control address ing modes and the posti ncrement address ing mode are legal. For transfers from the coprocessor to the effective address (DR = 1 ), the a l terable control and predecrement address ing modes are lega l . I l legal addreSS ing modes causes the MC68020 to abort the i nstruction by wr it ing a $0001 to the control CIR and i n i t iate F- l i ne emulator exception process ing (see 8.8.2.2 F·LlNE EMULATOR EXCEPTIONS).

After perform ing the effective address calcu lation, the MC68020 reads a 1 6-bit reg ister select mask from the reg ister select CIR. Wh i le the coprocessor can use the reg ister

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select mask to ind icate which reg ister it w i l l t ransfer, the MC68020 s imply counts the number of ones in the reg ister select mask to determ ine the number of operands that w i l l be transferred. Thus, t h e order o f t h e ones i n t h e reg ister select mask is not relevant to the operat ion of the main processor and up to 16 operands can be t ransferred by the main processor in response to th is pr imit ive. Thus, the total number of bytes transferred is the product of the number of operands transferred and the length of each operand specif ied by bits [7-0] of the pr i m i t ive format.

If DR = 1 , the main processor wi l l read the number of operands specif ied in the reg ister select mask f rom the operand C IR and write these operands to the effective address spec if ied in the instruction operation word us ing long word transfers whenever poss ible. I f DR = 0, the main processor w i l l read the number of operands specif ied in the reg ister select mask from the effective address and write them to the operand CIA.

For the control address ing modes, the operands are transferred to/from memory us ing ascend ing addresses. For the post i ncrement add ress i ng mode, the operands are read from memory with ascending addresses and the address reg ister used is i ncremented by the s ize of each operand after that operand is t ransferred. Thus, the f ina l value of the add ress reg ister used with the (An) + address ing mode w i l l be i ncremented by the total number of bytes transferred during the pri m i t ive execution.

For the predecrement addressing mode, the operands are written to memory with descending addresses, wh i le the bytes with in each operand are written to memory with ascend ing addresses. As an example, the format i n a long word wide memory for two 1 2 byte operands t ransferred from the coprocessor to the effective add ress us ing the - (An) add ress ing mode is i l l ust rated in F igure 8-38. The address reg ister used is decremented by the s ize of each operand before that operand is transferred. The bytes wi th in each operand are then written to memory wi th ascending addresses. Thus, the add ress reg ister used is decremented by the total number of bytes transferred by the end of the pr imi t ive execution. The MC68020 w i l l t ransfer the data us ing long word transfers whenever poss ib le.

An - 2 * Length = Final An _

An - Length _

I n i tial An _

3 1 2 4 23 16 1 5 8 7

Op 1 , Byte 1O) I I I I

I

Op 0, Byte 101 I I I I I I I I

NOTE: O p 0, Byte 101 is the first byte written to memory

Op 0, Byte I L- l i IS the last byte of the f i rst operand written to memory Op 1 , Byte 101 is the first byte of the second operand written to memory O p 1 , Byte I L- 1 1 is the last byte written to memory

I I

I

I I I

Op 1 , Byte I L- 1 )

Op O, Byte l L- 1 1

Figure 8-38. Operand Format i n Memory for Transfer to - (An)

8_6_ 15 Transfer Status Register and Scan PC

°

The main processor t ransfers operands between the coprocessor and either the main processor status reg ister or both the status reg ister and scan PC, This pr imit ive is

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al lowed with general category i nstruct ions. I f th is pr imit ive i s used by the coprocessor dur ing the execution of a condit ional category i nstruction, the main processor w i l l i n i t iate protocol violation exception processing.

8_6_1 5_1 FORMAT. The format of the t ransfer status reg ister and scanPC pr imit ive is i l l ust rated i n F igure 8-39.

15 14 13 12 1 1 10 9 8 7 6 5 4 3 0 I CA I PC I DR I 0 I 0 I 0 I 1 I sp I 0 I 0 I 0 I 0 I 0 I 0 I 0 I 0

Figure 8·39. Transfer Status Register and ScanPC Primitive Format

The CA, PC, and DR bits are a l lowed and are i nterpreted as described in 8.5.1 Coprocessor Response Primitive Format.

Bit [8] of the pr imit ive format, denoted by SP, ind icates whether the scan PC, in add it ion to the status reg ister, w i l l be t ransferred dur ing the pr imit ive execution. I f SP = 1 , both the scanPC and status reg ister w i l l be t ransferred. If SP = 0, only the status reg ister w i l l be t ransferred.

8.6.1 5.2 OPERATION. If SP = 0 and DR = 0, the main processor w i l l write a 1 6-bit operand from its status reg ister to the operand CIR. If SP = 0 and DR = 1 , the main processor w i l l read a 1 6-bit operand from t h e operand CIR i nto the status reg ister .

If SP = 1 , operands w i l l be t ransferred between the status reg ister and the operand CIR and between the scan PC and i nstruction address CIR. The order and d i rect ion of the t ransfer depends on the DR bit in the pr imit ive format. I f SP = 1 and DR = 0, the main processor f i rst writes the long-word value in the scanPC to the i nstruction address CI R and then writes the status reg ister to the operand CIR. If SP = 1 and DR = 1 , the main processor f i rst reads a 1 6-bit va lue f rom the operand D I R i nto the status reg ister and then reads a long word va lue from the i nstruction address CIR into the scan PC.

Th is pr imit ive a l lows the imp lementation of instructions in the general i nstruct ion category which change the mai n processor program f low. The main processor change of f low can occur due to t ransfers to the status reg ister, the scan PC, or both. Access to the status reg ister enab les the coprocessor to determi ne and manipu late the main processor cond it ion codes, su pervisor status, t race modes, master or interrupt stack usage, and interru pt mask level .

Any i nstruction words that have been prefetched by the main processor beyond the current scan PC locat ion are d iscarded by the MC68020 when th is pr imit ive is issued with DR = 1 (transfer to main processor). The MC68020 w i l l then ref i l l the i nstruction p ipe from the scan PC add ress in the add ress space ind icated by the status reg ister S bit. If the scanPC was not a ltered by the pr imit ive, the i nstruction p ipe w i l l be ref i l led us ing the value of the scanPC before the pr imit ive execution.

I f T1ITO = 01 i n the MC68020 status resgister (trace on change of f low, see 6.3.9 Tracing) when the coprocessor instruct ion beg ins execution and th is pri mit ive is issued with

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DR = 1 , a trace except ion w i l l be made pend ing w i th in the MC68020. Th is trace exception w i l l be taken when the coprocessor s ignals that it has completed al l processing associated with the instruction by return ing the nu l l pr im i t ive with CA = 0 and PF = 1 (see 8.8.2.5 TRACE EXCEPTIONS).

8.6. 16 Exception Processing Request Primitives

There are three pr imi t ives defi ned for the M68000 coprocessor interface that a l low the coprocessor to cause exception processing based on its operat ions. When the main processor receives one of these three pr imit ives from the coprocessor, the main processor w i l l i n i t iate except ion processing. These pr imit ives enable a coprocessor to suspend or abort an i nstruction due to an exception that occurred dur ing the coprocessor operat ion.

The three "Take Except ion" coprocessor response prim i t ives d i ffer main ly i n the stack frame saved by the MC68020 in response to the pr imit ive. Si nce d i fferent stack frames are saved for each of the pr imit ives, the RTE i nstruct ion executed to exit the exception handler rout ine w i l l cause the M68020 to operate d ifferently for each of the stack frames. When the RTE i nstruction is executed in the exception hand ler, the MC68020 w i l l either restart the i nstruct ion during which the pr imit ive was received, cont inue the instruction, or proceed with the execution of the next i nstruction i n the instruction stream.

8.6.1 6.1 TAKE PRE·I NSTRUCTION EXCEPTION. The main processor i n i t iates exception processing us ing a coprocessor suppl ied exception vector and the pre- instruction except ion stack frame format. This pr imit ive can be used with general or cond it ional category i nstructions.

8.6. 16.1 . 1 Format. The format of the take pre- i nstruction exception pr imit ive is i l l ustrated in F igure 8-40.

1 5 14 13 1 2 I 0 I PC I 0 I 1 1 1 1 0 I 1 I 1

9 o

8 7 6 o

5 4 3 2 Vector Number

Figure 8·40. Take Pre-Instruction Exception Primitive Format

o

The PC bit is a l lowed and is i nterpreted as descri bed in 8.5.1 Coprocessor Response Primitive Format.

Bits [7·0] of the pr imit ive format are used to specify the exception vector number used by the main processor to i n it iate exception processing.

8.6.1 6.1 .2 Operation. When the main processor receives th is pr imit ive, it f i rst acknowledges the coprocessor exception req uest by writ ing a $0002 to the control C IR. The MC68020 then proceeds with exception processing as detai led i n 6.2.4 Exception Processing Sequence. The vector number for the exception is taken from bits [7-0] of the pr imit ive and the MC68020 uses the fou r word stack frame format i l l ustrated in F igure 8-4 1 .

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15 14 13 12 1 1 10 9 8 6 5 4 3 o SP � r-________________________

S_ta_tu_s_Re�g�is_te_r ______________________ � + 02 r- - - - - - - - - - - - - - Program Counter- - - - - - - - - - - -

+ 06 �0��0 ____ 0 __ �0_�I _________________ V�Bc�to�r_N_u_m�be_r ________________ �

Figure 8-41 . MC68020 Pre·lnstruction Stack Frame

The value of the program counter saved in th is stack frame is the operation word add ress of the coprocessor i nstruct ion dur ing which the pri mit ive was received. Thus, if no mod if iciat ions are made to the stack frame with i n the except ion handler rout i ne, an RTE i nstruction w i l l cause the MC68020 to retu rn to re- in i t iate the i nstruction dur ing which the take pre- inst ruct ion exception pr imit ive was received.

This pr imit ive can be used in a number of c i rcumstances in which the coprocessor must request except ion processing related to its operat ion. The take pre- i nstruction exception pr imit ive can be used when the coprocessor does not recogn ize a value wri tten to either i ts command CIR or condi t ion CIR to i n i t iate a general or condi t ional i nstruct ion respect ively. This pr imit ive can also be used if an exception occu rred in the coprocessor i nstruction before any program vis ib le resources where modi f ied by the i nstruction operat ion. Th is pr imit ive should not be used dur ing a coprocessor i nstruction if program vis ib le resources have been mod if ied by that i nstruction. Si nce the MC68020 w i l l re- in i t iate the i nstruct ion when i t returns from exception process i ng, the restarted i nstruction would receive the previously mod if ied resources i n an i nconsistent state.

One of the most important uses of the take pre- i nstruct ion exception pr imit ive is to s ignal an exception cond it ion in a cpG EN i nstruct ion that was execut ing concu rrently with the main processor's i nstruction execut ion. I f the coprocessor no longer requ i res the services of the main processor to complete a cpGEN instruction and the concurrent i nstruct ion completion is t ransparent to the programmer's model, the coprocessor can release the main processor by issu ing a prim i t ive with CA = O. Thus, the main processor w i l l genera l ly proceed to execute the next instruction in the instruction stream and the coprocessor w i l l complete its operat ions concurrently wi th the main processor operat ion. If an except ion occurs whi le the coprocessor is execut ing an i nstruction concurrently, the coprocessor must wait unt i l the main processor attempts to i n it iate the next general or condit ional i nstruction before the exception can be processed. After the main processor writes to the command or cond it ion CIR to in i t iate a general or condi t ional i nstruction respect ively, it w i l l then read the response C IR. At th is t ime, the coprocessor can return the take pre- instruction except ion pr imit ive. This protocol a l lows the main processor to proceed with exception processing related to the previous concurrent ly execut ing coprocessor i nstruction and then return to re- in i t iate the coprocessor i nstruct ion during which the except ion was s ig nal led.

The coprocessor should record the address of a l l general category i nstructions which can be executed concu rrent ly with the main processor i f exception processing and except ion recovery is to be su pported for that instruction. Si nce the exception w i l l not be reported unt i l the next coprocessor i nstruction is i n it iated, the instruction address i s genera l ly necessary to determ i ne wh ich i nstruction the coprocessor was execut ing when the exception occu rred. A coprocessor can record the i nstruction address by sett ing

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PC = 1 i n one of the pr imit ives used before the main processor is released after servic ing a pr imit ive with CA = O.

8.6.1 6.2 TAKE MID·INSTRUCTION EXCEPTION. The main processor i n i t iates except ion processing using a coprocessor suppl ied exception vector and the m id-i nstruction ex· cept ion stack frame format. Th is pr imit ive can be used with general or condit ional category i nstruct ions.

8.6.1 6.2.1 Format. The format of the take mid-instruction exception pri mit ive is i l · l ustrated i n F igure 8-42.

15 14 13 12 11 10 9 8 6 5

a I PC I a I 1 I 1 I 1 I a I 1 4 3

Vector Number 2

Figure 8-42. Take M id-Instruction Exception Primitive Format

a

The PC bit is a l lowed and is interpreted as descr ibed in 8.5.1 Coprocessor Response Primitive Format.

Bits [7-0] of the primi t ive format are used to specify the exception vector number used by the main processor to in i t iate except ion process i ng.

8.6.1 6.2.2 Operation. When the main processor receives this pr imit ive, it f i rst acknowledges the coprocessor exception request by wr it ing a $0002 to the control C IR . The MC68020 then proceeds with exception processing as detai led in 6.2.4 Exception Processing Sequence. The vector nu mber for the exception is taken from bits [7-0] of the pr imit ive and the MC68020 uses the ten word stack frame format i l l ust rated in F igure 8-43.

The value of the program counter saved in th is stack frame is the operation word address of the coprocessor i nstruct ion dur ing which the pr imit ive was received. The scan PC f ie ld contains the value of the MC68020 scan PC when the prim i t ive was received. I f no pr imit ive caused the eval uation of the effective address i n the coprocessor instruction operat ion word prior to the except ion request pr imit ive, the value of the effective address f ie ld in the stack frame is undefi ned.

15 14 13 12 11 10 9 8 7 6 5 4 3 SP- Status Register

a

+ 02 f- - - - - - - - - - - - - - -Scan PC - - - - - - - - - - - - - -

+ 06 a a 1 I Vector Number �--�--�--�L-----------------�--��---------------1 + 08 r- _ _ _ _ _ _ _ _ _ _ _ _ Program Counter - - - - - - - - - - - -

+ OC � ____________________ �ln�te�rn�a�I R�e�gis�te�r ______________________ -1 + OE � ______________________ o�p�er�at�io�n�W�or�d ______________________ -1 + 10 I- - - - - - - - - - - - Effective Address - - - - - - - - - - - -

Figure 8-43. MC68020 Mid-Instruction Stack Frame

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This pr imit ive al lows the coprocessor to req uest exception processing to handle an except ion that occurred wh i le the coprocessor is engaged in the i nstruction d ialog with the main processor. I f no mod if ications are made to the stack frame wi th in the exception hand ler, the MC68020 w i l l return from the except ion handler after an RTE i nstruction and read the response CIR. Thus, the main processor w i l l attempt to cont inue the execution of an i nstruction suspended by the take m id-instruction exception pr imit ive by read ing the response C IR and process ing the pr imit ive it receives.

8_6_1 6.3 TAKE POST· INSTRUCTION EXCEPTION. The main processor i n i t iates exception processing using a coprocessor suppl ied exception vector and the post- i nstruction exception stack frame format. This pr imit ive can be used with general or cond it ional category i nstructions.

8.6.1 6.3.1 Format. The format of the take post- i nstruction exception pr imit ive is i llustrated i n F igure 8-44.

1 5 14 13 1 2 0 1 PC 1 0 1 1

1 1 10 9 8 7 6 5 4 3 2 Vector Number

Figure 8-44. Take Post-Instruction Exception Primitive Format

o

The PC bit is a l lowed and is i nterpreted as described in 8.5.1 Coprocessor Response Primitive Format.

Bits [7-0] of the pr imit ive format are used to spec ify the except ion vector number used by the main processor to i n it iate exception process i ng.

8.6.1 6.3.2 Operation. When the main processor receives th is pr imit ive, it f i rst acknowledges the coprocessor except ion request by wr it ing a $0002 to the control CIR. The MC68020 then proceeds with exception processing as deta i led i n 6.2.4 Exception Processing Sequence. The vector nu mber for the exception is taken from bits [7-0] of the pr imit ive and the MC68020 uses the s ix word stack frame format i l l ustrated in F igure 8-45.

15 14 13 12 11 10 9 8 S P _ Status Register

6 5 4 3 2 o + 02 _ _ _ _ _ _ _ _ _ _ _ _ _ -Scan PC _ _ _ _ _ _ _ _ _ _ _ _ _ + oo�o ____ o _______ o�IL-________________

v_ec_to_r_N u_m_b_er ______________ � + 08 r- - - - - - - - - - - - - Program Counter- - - - - - - - - - - -

Figure 8·45. MC68020 Post-Instruction Stack Frame

The value of the main processor scanPC at the t ime th is pr imit ive is received is saved i n the scanPC f ie ld o f the post- i nstruction except ion stack frame. The value of the program counter saved is the operat ion word address of the coprocessor i nstruction dur ing which the pri mi t ive was received.

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When the MC68020 receives the take post- instruction exception pr imit ive it assu mes that the coprocessor either completed or aborted the i nstruction in progress with an except ion. If no mod if icat ions are made to the stack f rame w i th in the except ion hand ler, the MC68020 w i l l retu rn f rom the exception handler after an ATE instruction to beg in execut ion at the location specif ied by the scanPC f ie ld of the stack frame, which should be the address of the next i n st ruct ion to be executed.

This pr imit ive a l lows the coprocessor to request except ion processing when the coprocessor completes or aborts an i nstruct ion with an exception whi le the main processor was wai t ing for either a release (for general category i nstructions) or an eva luated true/false cond it ion i nd icator (for cond i t ional category i nstruct ions). Thus, the operat ion of the MC68020 i n response to this prim i t ive is analogous to standard M68000 Fam i ly i nstruct ion related exception process i ng, for example the d ivide-by-zero except ion.

8.7 COPROCESSOR CLASSIFICATIONS

M68000 coprocessors can be c lassif ied i nto two categories depending on their bus i nterface capab i l i t ies. The f i rst category, non-DMA coprocessors, a lways operate as bus s laves. The second category, DMA coprocessors, operate as bus slaves whi le commun icat ing with the main processor across the coprocessor i nterface, but also have the abi l ity to operate as bus masters and d i rectly control the system bus.

Si nce non-DMA coprocessors a lways operate as bus s laves, a l l external bus related fu nct ions that the coprocessor requ i res are hand led by the main processor. The main processor w i l l transfer operands f rom the coprocessor by f i rst read ing the operand from the appropriate CIA and then wr i t ing the operand to a specif ied effective address. Li kewise, the mai n processor transfers operands to the coprocessor by f i rst read ing the operand from a spec if ied effective address and then wr it ing that operand to the appropriate CIA . I f the operat ion of a coprocessor does not req u i re a large port ion of the avai lable bus bandwidth, that coprocessor can be eff ic iently imp lemented as a non-DMA coprocessor. Si nce non-DMA coprocessors on ly operate as bus s laves, the bus interface c i rcu i t ry of the coprocessor does not need to be as com plex as that of a device which can operate as a bus master.

DMA coprocessors have the capabi l ity to operate as bus masters. This imp l ies that the coprocessor implements al l control , address, and data signals necessary to req uest and obta in the bus, and then perform DMA t ransfers using the bus. I f the operation of a coprocessor req u i res a re latively h igh amount of bus bandwidth, that coprocessor can be imp lemented as a DMA coprocessor to improve the eff ic iency of operand transfers between memory and the coprocessor. DMA coprocessors, however, must st i l l act as bus s laves when they requ i re i nformat ion or services of the main processor us ing the M68000 coprocessor i nterface protocol . I n part icu lar, if the coprocessor must access data contai ned in the main processor reg isters, the coprocessor must communicate th is req uest to the main processor us ing the response pr imit ives and operate as a bus s lave during the execution of those pr imit ives.

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8.8 EXCEPTIONS

A number of except ion condi t ions may occur related to the execut ion of coprocessor i nstruct ions. Whi le these exceptions may be detected by either the main processor or the coprocessor, except ion process ing is coord inated and handled by the main processor. This protocol a l lows the service of coprocessor related exceptions to be a s imple extens ion of the protocol used to service standard M68000 Fami ly except ions. That is, when either the main processor detects an except ion or i s s ignal led by the coprocessor that an exception cond it ion has occurred, the main processor proceeds with except ion processing as described in 6.2.4 Exception Processing Sequence.

8.8.1 Coprocessor Detected Exceptions

Exceptions which are perceptible to the coprocessor, whether or not they are also perceptible to the main processor, are general ly c lassif ied as coprocessor detected except ions. These exceptions can ar ise from the M68000 coprocessor interface operations, i nternal operat ions, or other system re lated operat ions of the coprocessor.

M ost coprocessor detected except ions are s ignal led to the main processor through the use of one of the three "Take Exception" pr imit ives defi ned for the M6800 coprocessor i nterface. When the main processor receives one of these exception s ignal l i ng pr imit ives, it proceeds as described i n 8.6.1 6 Exception Processing Request Primitives. There is one type of coprocessor detected exception which is not s ignal led to the coprocessor by a response pri m i t ive. Coprocessor detected format errors dur ing the cpSAVE or cpRESTORE i nstruction are s igna l led to the main processor us ing the i nva l id format word as described i n 8.3.3.4.3 Invalid Format Words.

8.8.1 .1 COPROCESSOR DETECTED PROTOCOL VIOLATIONS. Protocol vio lat ion except ions are communication fai l u res between the main processor and coprocessor across the M68000 coprocessor i nterface. Coprocessor detected protocol violations occur when the main processor accesses entr ies in the coprocessor interface reg ister set i n a sequence that is determi ned to be i l legal by the coprocessor. The sequence of operat ions that the main processor w i l l perform for a g iven coprocessor instruct ion or coprocessor response pri mi t ive have been described previously in th is section. Thus, a g iven C IR access by the main processor can be considered i l l egal by the coprocessor if the coprocessor was not expect i ng that access to occur.

Coprocessors can be implemented with a range of in terface protocol violation detection capabi l i t ies. Accord ing to the M68000 coprocessor in terface protocol, the main processor a lways accesses the operation word, operand, reg ister select, i nstruction address, or operand add ress C IRs in a synchronous man ner with respect to the operation of the coprocessor. That is, both the main processor and the coprocessor are aware of the seq uence in which these f ive reg isters w i l l be accessed duri ng the execution of a g iven coprocessor response pr imit ive. As a m in imum, a l l M68000 coprocessors should detect a protocol violation if the main processor accesses any of these f ive reg isters when the coprocessor is expect ing an access to either the command or condit ion CIR. Likewise, i f the coprocessor is expect ing an access of the command or cond it ion C IR and the main processor accesses one of these five reg isters, the coprocessor should detect and s ignal a protocol violation.

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Accord ing to the M68000 coprocessor interface protocol, the main processor can perform a read of either the save or response CIRs or a write of either the restore or control C IRs asynchronously to the operat ion of the coprocessor. That is, val id accesses can be made to these reg isters without the coprocessor exp l ic i t ly expect ing these accesses at a g iven point i n i ts operation. Whi le the coprocessor can ant ic ipate certai n accesses to either the restore, response, and control coprocessor i nterface registers, these reg isters can also be accessed when not ant ic i pated by the coprocessor operat ion.

Protocol violat ions can not be s ignal led to the main processor during the execution of cpSAVE or cpRESTORE i nstructions. I f a coprocessor detects a protocol violat ion dur ing the cpSAVE or cpRESTORE i nstruct ion, it should s ignal the exception to the main processor when the next coprocessor i nstruction is i n it iated.

The main ph i losophy of the coprocessor detected protocol violat ion is that the coprocessor should a lways respond when one of its i nterface reg isters is accessed. I f the access is determ i ned to be not val id by the coprocessor, it should st i l l assert DSACKx to the main processor and s ignal a protocol violation when the main processor next reads the response CIA. This protocol ensures that an access to one of the coprocessor i nterface reg isters w i l l never halt the main processor by not having DSACKx asserted by the coprocessor.

Coprocessor detected protocol violat ions can be s ignal led to the main processor with the take mid-i nstruct ion except ion pr imit ive encoded with the coprocessor protocol violation except ion vector number 1 3 to mainta in consistency with main processor detected protocol violations. When the main proc�ssor reads th is pr imit ive, it w i l l p ro· ceed as described in 8.6.1 6.2 TAKE MID-INSTRUCTION EXCEPTION. If no modi f ications are made to the stack frame wi th in the exception handler, the MC68020 w i l l return from the except ion handler after an RTE instruction and read the response C IR.

A l l Motorola M68000 coprocessors s ignal protocol violations us ing the take m idi nstruction exception pr imit ive with the coprocessor protocol violation exception vector number.

8.8.1 .2 COPROCESSOR DETECTED I LLEGAL COMMAND OR CON DITION WORDS. I I · legal coprocessor command or cond it ion words are values written to the command CIR or cond it ion C IR respectively that are not recognized by the coprocessor. I f a value writ· ten to either of these reg isters is not val id , the coprocessor should p lace the take pre· i nstruction except ion prm im it ive in the response C IR. When it receives th is pr imit ive, the main processor w i l l proceed as described in 8.6.1 6.1 TAKE PRE·INSTRUCTION EXCEp· TION. I f no modif ications are made to the main processor stack frame with in the except ion hand ler, an RTE i nstruction w i l l cause the MC68020 to return to re- in i t iate the i n· struct ion dur ing which the take pre- i nstruct ion exception pr imit ive was received. The coprocessor des ig ner should ensure that the state of the coprocessor is not unrecoverably altered by an i l legal command or cond it ion except ion i f emu lat ion of the unrecogn ized command or condi t ion word is to be supported .

A l l Motorola M68000 coprocessors S igna l i l legal command and condit ion words by return ing the take pre- i nstruction exception pr imit ive with the F· l i ne emu lator exception vector nu mber 1 1 .

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8.8.1 .3 COPROCESSOR DATA PROCESSI NG EXCEPTIONS. Except ions related to the i n· ternal operat ion of a coprocessor are c lassif ied as data process ing re lated exceptions. These except ions are analogous to the d ivide·by·zero exception defi ned by M68000 microprocessors and should be s ignal led to the main processor us ing one of the three "Take Exception" pr imit ives conta in i ng an appropriate exception vector nu mber. Which of these three pr imit ives is used to s igna l the exception is general ly determ ined by the poin t in the i nstruct ion operat ion where the main processor should cont inue the prog ram flow after except ion processing . These considerat ions are d iscussed in 8.6.16 Except ion Processing Request Primitives.

8.8. 1 .4 COPROCESSOR SYSTEM RELATED EXCEPTIONS. System related exceptions detected by a DMA coprocessor i nc l ude those associated with bus activity, and any other except ions generated external to the coprocessor. These externa l ly generated ex· cept ions could i nclude non·bus cycle associated events ( l i ke i nterru pts) detected by the coprocessor. The actions taken by the coprocessor and the main processor depend on the type of exception encou ntered and are thus not genera l .

When an address or bus error is detected by a DMA coprocessor, any informat ion necessary for the main processor exception hand l i ng rout i nes should be recorded in system access ib le reg isters by the coprocessor. The coprocessor should p lace one of the three "Take Except ion" pr imit ives encoded with an appropriate except ion vector number in the response CIR. Which of the three pr imit ives is used depends upon the po int i n the coprocessor i nstruction at which the exception was detected , and the point i n the i nstruction execution where the main processor should continue the program f low after except ion processing .

8.8.1 .5 FORMAT ERROR. Format errors are the only coprocessor detected exceptions that are not s ig nal led to the main processor with one of the three "Take Except ion" coprocessor response pr imi t ives. When the main processor wr ites a format word to the restore C IR during the execution of a cpRESTORE i nstruction, the coprocessor decodes th is word to determ ine if it is val id (see 8.3.3.2 COPROCESSOR CONTEXT RESTORE). I f t h e format word is not va l id , the coprocessor w i l l p lace the i nva l id format code i n the restore C I R. When the main processor reads the i nval id format code, it w i l l f i rst abort the coprocessor i nstruction by wr i t ing a $0001 to the control C IR. The main processor then proceeds with exception process ing using a four word pre· i nstruction stack f rame and the format error except ion vector number 1 4. Thus, if the stack f rame is not mod if ied by the exception handler, the MC68020 w i l l restart the cpRESTORE i nstruction after an RTE is executed to exit the hand ler. I f the coprocessor retu rns the i nva l id format code when the main processor reads the save CI R to in i t iate a cpSAVE instruction the main processor w i l l proceed wi th format error except ion proceSSi ng as out l i ned above for the cpRESTORE i nstruction.

8.8.2 Main Processor Detected Exceptions

A number of except ions re lated to coprocessor i nstruction execut ion are not d i rect ly perceptible to the coprocessor, but can be detected and serviced by the main processor. These except ions can be re lated to the execution of coprocessor response pr imit ives, com mun icat ion across the M68000 coprocessor interface, or the completion of cond it ional coprocessor instruct ions by the main processor.

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8.8.2.1 PROTOCOL VIOLATIONS. The main processor detects a protocol violation when it reads a pr imit ive from the response CIR that is not a va l id pr imit ive encod i ng. The pro· tocol violations that can be generated by the MC68020 in response to the pr imit ives defi ned for the M68000 coprocessor i nterface are summarized in Table 8·6.

When the MC68020 detects a protocol violation it does not automatica l ly notify the coprocessor of the resu l t ing exception processing by wri t ing to the control C IR. The except ion hand l i ng rout ine may, however, use the MOVES instruction to re-read the response C IR and thus determ ine the prim i t ive that caused the MC68020 to i n i t iate protocol violation except ion process ing . The main processor in i t iates exception processing us ing the mid- i nstruction stack frame (see F igure 8-43) and the coprocessor protocol violat ion except ion vector number 1 3. If the stack frame is not mod if ied w i th in the except ion hand ler, the main processor w i l l return and read the response CIR fo l lowing the execution of an RTE i nstruction in the exception hand ler. Th is protocol a l lows extensions to the M68000 coprocessor i nterface to be emu lated i n software by a main processor that does not provide hardware support for these extensions. Thus, the protocol violation is t ransparent to the coprocessor if the pr imit ive execution can be emu lated in software by the main processor.

8.8.2.2 F·L lNE EMU LATOR EXCEPTIONS. The F-l ine emulator except ions detected by the MC68020 are either exp l ic i t ly or imp l ic i t ly re lated to the encod i ngs of F- l i ne operat ion words encountered in the i nstruct ion stream. I f the main processor determ ines the F- l i ne operat ion word is not a legal encod ing , i t w i l l i n i t iate F- l i ne emu lator exception processi ng. Any F- l i ne operat ion word with bits [8-6] = 1 1 0 or 1 1 1 causes the MC68020 to in i t iate exception processing without any communication be ing i n it iated with the coprocessor for that i nstruct ion. A lso, an operation word with bits [8-6] = 000-101 that does not map to one of the legal coprocessor i nstruct ion encod i ngs in APPENDIX B INSTRUCTION SET, causes the MC68020 to in i t iate F- l i ne emulator exception processing. If the F- l i ne emu lator exception is generated as a resu l t of one of these two situations, the main processor w i l l not write to the control C IR prior to i n it iat ing exception process ing.

F- l ine except ions can also occur i f the operat ions requested by a coprocessor response pr imit ive are not com pat ible wi th the effective address type encoded in bits [5-0] of the coprocessor instruction operat ion word. The F-l i ne emu lator exceptions that can resul t from the use of the M68000 coprocessor response pr imit ives are summarized in Table 8-6. I f the exception is caused by the rece ipt of a pr imit ive, the coprocessor i nstruction i n progress is aborted by the main processor wr i t ing a $0001 t o the control C IR prior to F- l ine emu lator exception process ing.

When the main processor i n i t iates F- l i ne emu lator exception process ing , i t uses a four word pre- i nstruction exception stack frame (see F igure 8-41 ) and the F- l i ne emu lator except ion vector number 1 1 . Thus, if the stack frame is not modif ied wi th in the exception handler, the main processor w i l l attempt to restart the i nstruction that caused the except ion after an RTE is executed.

General ly, i f the cause of the F- l i ne exception can be emu lated in software, the handler w i l l ref lect the results of the emu lation in the programmer's model and in the status reg ister f ie ld of the saved stack frame. The exception handler w i l l adj ust the program

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Table 8·6. Exceptions Related to Primitive Processing

Primitive Busy NULL Supervisory Check*

Other: Privilege Violation i f "S" B it = O Transfer Operation Word * Transfer from I nstruction Stream*

Protocol: I f Length Field i s Odd IZero Length Legal( Evaluate and Transfer Effective Address

Protocol: If Used with Conditional Instruction F-Line: I f EA in Op-Word is NOT Control Alterable

Evaluate Effective Address and Transfer Data Protocol :

1 . I f Used with Conditional Instructions 2. Length is Not 1, 2 , or 4 and EA = Register D i rect 3. If EA= Immediate and Length Odd and Greater Than 1 4. Attempt to Write to Non-A lterable Address Even if Address Declared Legal in

Primitive F-Line: Valid EA Field Does Not Match EA in Op-Word

Write to Previously Evaluated Effective Address Protocol: If Used with Conditional I nstruction

Take Address and Transfer Data * Transfer To/ From Top-of-Stack*

Protocol: Length Field Other Than 1 , 2, or 4 Transfer To/From Main Processor Register* Transfer To/From Main Processor Control Register

Protocol: Invalid Control Register Select Code Transfer Mu ltiple Main Processor Registers* Transfer Mu ltiple Coprocessor Registers

Protocol: 1 If Used with Conditional I nstructions 2. Odd Length Value

F-Line· 1 EA Not Control Alterable or IAnl + for CP to Memory Transfer 2. EA Not Control Alterable or - IAnl for Memory to CP Transfer

Transfer Status and/ or ScanPC Protocol: I f Used with Conditional Instruction Other:

1 Trace - Trace Made Pending If M C68020 in "Trace on Change of Flow" Mode and DR = l

2 . Address Error - I f Odd Value Written to ScanPC Take Pre-Instruction, Mid- I nstruction, or Post-I nstruction Exception

Exception Depends on Vector Supplied in Primitive * Use of thiS primitive with CA = 0 Will cause protocol violation on conditional Instructions. Abbreviations: EA = Effective Address

CP = Coprocessor

Protocol

X

X

X

X

X

X

X

X

X

F-Line Other

X

X

X

X

X

X X

counter f ie ld of the saved stack frame to point to the next i nstruction operat ion word and execute the RTE i nstruction. The MC68020 w i l l then proceed with the execution of the i nstruction fol lowing the i nstruct ion that was emulated.

8.8.2.3 PRIVILEGE VIOLATIONS. Privi lege violat ions can resu l t from the use of the cpSAVE and cpRESTORE i nstructions as well as from the use of the su pervisor check coprocessor response pr imit ive. The main processor w i l l i n i t iate priv i lege violat ion

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except ion process ing if it encou nters either the cpSAVE or cpRESTORE i nstruction when i t is in the user state (S = 0 in status reg ister). The main processor w i l l i n i t iate th is except ion process ing prior to any commun icat ion with the coprocessor associated wi th the cpSAVE or cpRESTORE i nstructions.

I f the main processor is in the user state whi le execut ing a coprocessor i nstruction when i t reads the su pervisor check pr imit ive, it w i l l f i rst abort the coprocessor i nstruction i n progress by wr it ing a $0001 t o the control C IR. The main processor w i l l then proceed with privi lege violat ion exception process ing.

I f a privi lege v io lat ion occu rs, the main processor i n it iates except ion processing us ing a four word pre- i nstruct ion stack frame (see Figure 8-41 ) and the privi lege violation except ion vector nu mber 8. Thus, if the stack frame is not mod i f ied with i n the exception hand ler, the main processor w i l l attempt to restart the instruction during which the except ion occurred after an RTE is executed to exit the hand ler.

8.8.2.4 cpTRAPcc INSTRUCTION TRAPS. The main processor may in i t iate trap exception processing during the execut ion of the cpTRAPcc instruction. If the coprocessor returns the TRU E cond it ion ind icator to the main processor with a nu l l pr imit ive, the main processor w i l l i n it iate trap exception process ing. The main processor w i l l use a six word post- i nstruction exception stack frame (see Figure 8-45) and the trap exception vector number 7. The scanPC f ie ld of th is stack frame w i l l conta in the address of the i nstruction fol lowing the cpTRAPcc i nstruction. The process ing associated with the cpTRAPcc i nstruction can then proceed and the exception handler can locate any immed iate operand words encoded in the cpTRAPcc i nstruction using the in format ion contai ned in the s ix word stack frame. I f the stack frame is not modi f ied wi th in the exception hand ler, the main processor w i l l proceed with the i nstruction fol lowing the cpTRAPcc i nstruction after an RTE is executed to exit the handler.

8.8.2.5 TRACE EXCEPTIONS. The MC68020 supports two modes of instruction trac ing which are d iscussed i n 6.3.9 Tracing. In the t race on i nstruction execution mode, the MC68020 takes a trace exception after the completion of each i nstruction. I n the trace on change of f low mode, the MC68020 takes a trace exception after each i nstruction that a l ters the status reg ister or causes the program cou nter to be u pdated in a nonsequent ia l manner.

The protocol used to execute coprocessor cpSAVE, cpRESTORE, or cond it ional category i nstructions does not change when a trace exception is pend ing in the main processor. The main processor w i l l proceed with a pend ing trace on i nstruction execution exception after complet ing the execut ion of that i nstruction. I f the main processor i s in trace on change of f low mode, it w i l l take a trace except ion after the i nstruction execut ion i f the i nstruction caused the program counter to be updated in a non-sequent ia l fashion, for example a branch was taken.

The cond it ions on which the main processor w i l l termi nate commun ication with the coprocessor during the execut ion of a cpGEN i nstruction and proceed with the next i nstruction are altered when the main processor is i n a trace mode. When a trace except ion is pend ing, the main processor w i l l not take the t race exception unti l the coprocessor i nd icates that a l l processing associated with a cpG EN instruction has completed.

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I f a trace except ion is not pend ing dur ing a general category i nstruction, the main processor w i l l term i nate commun ication with the coprocessor after read ing any pr imit ive with CA = O. This protocol a l lows the coprocessor to complete a cpGEN i nstruction concurrently with the i nstruction execut ion of the main processor. When a trace exception is pend ing , however, the main processor must insure that a l l process ing associated wi th cpG EN i nstruct ion has been completed before the trace except ion is taken. Under these c i rcumstances, the main processor w i l l cont inue to read the response CIR and service the pr imit ives received unt i l it receives ei ther a nu l l , CA = 0, PF = 1 pr imit ive or after exception processing caused by a take post-i nstruction exception pr imit ive. The coprocessor should return the nu l l , CA = 0 pr imit ive with PF = 0 whi le it is com plet ing the execution of the cpG EN i nstruction. The main processor may service pending interrupts between reads of the response CIR i f IA = 1 i n these n u l l , CA = 0 pr imit ives (see Table 8-3). This protocol insures that a t race except ion w i l l not be taken unt i l a l l processing associated with a cpG EN instruction has been completed.

If T1 1T0 = 01 in the MC68020 status reg ister (trace on change of f low) when a general category i nstruction is i n it iated, a trace except ion w i l l be taken after the i nstruction only when the transfer status reg ister and scan PC pr imit ive is issued with DR = 1 during the execution of that i nstruct ion. If an i nstruction fol lowing the cpGEN i nstruction does cause a change of f low, the coprocessor may be execut ing the previous cpGEN i nstruct ion concurrently when the main processor beg ins execution of the trace exception hand ler. A cpSAVE instruct ion used wi th in the trace on change of f low exception handler could thus suspend the execut ion of a concurrently operat ing cpGEN instruction.

8.8.2.6 INTERRU PTS. I nterrupt processing by the main processor can occur at any i nstruction boundary and is d iscussed in 6.3. 10 Interrupts. I nterrupts may also be serviced dur ing the execut ion of a general or cond it ional category i nstruction under either of two condit ions. If the main processor reads a n u l l pr imit ive with CA = 1 and IA = 1 the main processor wi l l service any pend ing i nterrupts pr ior to reading the response CIR. Likewise, i f a trace exception is pend ing during cpGEN i nstruction execution and the main processor reads a n u l l pr imit ive with CA = 0, IA = 1 , and PF = 0 (see 8.8.2.5 TRACE EXCEp· TIONS) the main processor w i l l service pend ing i nterrupts prior to re-read ing the response CIR .

The MC68020 uses the ten word mid-instruction stack frame when i t services i nterrupts dur ing the execution of a general or cond i t ional category coprocessor i nstruction. The use of th is stack frame a l lows the main processor to perform all necessary processing and then return to read the response C IR and thus cont inue the coprocessor i nstruction dur ing which the i nterrupt except ion was taken.

The MC68020 w i l l a lso service i nterrupts i f i t reads the not ready format word from the save CIR dur ing a cpSAVE i nstruction. The MC68020 uses the normal fou r word prei nstruction stack frame when it services i nterrupts after reading the not ready format word. Thus, the processor can service any pend ing i nterrupts and execute an RTE to return and re- in i t iate the cpSAVE i nstruction by read ing the save CIR.

8.8.2.7 ADDRESS AND BUS ERRORS. Coprocessor i nstruction related bus faults can occur dur ing main processor bus cycles to CPU space to commun icate with a

8-54

coprocessor or during memory cycles run as part of the coprocessor instruction execut ion. If a bus error occurs dur ing the coprocessor i nterface reg ister access that is used to init iate a coprocessor i nstruct ion, the main processor assumes that the coprocessor is not present i n the system and takes an F- l ine emu lator exception as descri bed i n 8_8_2_2 F-Li N E EMULATOR EXCEPTIONS_ Thus an F- l i ne emulator except ion w i l l be taken i f a bus error occu rs during the in i t ia l access to the command, cond i t ion, restore, or save CIR that was made to in i t iate a genera l , condit ional , context restore, or context save i nstruction respect ively. I f a bus error occu rs on any other coprocessor access or on a memory access made during the execution of a coprocessor i nstruction, the main processor proceeds with bus error except ion process ing as descri bed i n 6.3.3. Bus Error. After the exception handler has corrected the cause of the bus error, the main processor can return to the point in the coprocessor instruction at which the fault occu rred.

An address error w i l l occur if the MC68020 attempts to prefetch an instruction from an odd address. This can occur if the calcu lated dest ination address of a cpBcc or cpDBcc i nstruct ion is odd, or if an odd va lue is transferred to the scan PC with the transfer status reg ister and scanPC response pr imit ive. If an add ress error occurs, the MC68020 proceeds with exception process ing as descr ibed in 6.3.2 Address Error.

8.8.2.8 MAIN PROCESSOR DETECTED FORMAT ERRORS. The MC68020 can detect a format error during the execution of a cpSAVE or cpRESTORE i nstruction if the length f ield of a va l i d format word is not a mu l t iple of four bytes in length. I f the MC68020 reads a format word with an i nval id length f ield from the save C IR dur ing the cpSAVE instruct ion, it w i l l abort the coprocessor instruction by wr it ing a $0001 to the control C IR and i nit iate format error except ion processing. I f the MC68020 reads a format word with an i nva l id length f ie ld from the effective address specif ied in the cpRESTORE i nstruction, the MC68020 w i l l write that format word to the coprocessor restore CIR and then read the coprocessor response from the restore C IR. The MC68020 w i l l then abort the cpRESTORE i nstruct ion by wr i t ing a $0001 to the control CIR and i n it iate format error except ion processing .

The MC68020 uses the four word pre- i nstruction stack frame and the format error vector number 1 4 when it i n i t iates format error except ion processi ng. Thus, if the stack frame is not mod if ied w i th in the exception hand ler, the main processor w i l l attempt to restart the i nstruction dur ing which the except ion occu rred after an RTE is executed to exit the hand ler.

8.8.3 Coprocessor Reset

When a system (hardware) reset occurs, the coprocessor should be reset and i n it ia l ized appropriately. At the d iscretion of the system designer, there may be a d isti nction made between an ent i re system reset and the execut ion of the RESET instruction by the main processor. In keeping with the funct ion of the RESET i nstruct ion, it is genera l ly desi rable that the i nternal state of a coprocessor is only affected by an external system reset and not by the RESET i nstruction. This convent ion is des i rable s i nce the coprocessor is viewed as an extension to the main processor programming model , and thus an extension to the i nternal state of the MC68020.

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8.9 COPROCESSOR INSTRUCTION FORMAT SUM MARY

A summary of the coprocessor i nstruction formats is presented in F igure 8-46.

8.1 0 COPROCESSOR RESPONSE PRIM ITIVE FORMAT SUM MARY

The M68000 coprocessor response pr imit ive formats are i l l ustrated in APPENDIX C IN· STRUCTION FORMAT SUMMARY. Any response pri mi t ive wi th b i ts [1 3-8] = $00 or $3F w i l l a lways cause a protocol violation. Response pr imit ives with bits [1 3-8] = $OB, $ 18-$1 B, $1 F, $28-$2B, and $38-$3E current ly cause a protocol, but are u ndefi ned and reserved for future use by Motorola.

1 5 14 13 1 2 1 1 10 9 cpGEN 8 7 6

1 I 1 I 1 I 1 I Cp- ID I 0 I 0 I 0 Coprocessor Command

5 4 3 2

I Effective Address

Optional Effective Address or Coprocessor Defined Extension Words

15 14 13 12 1 1 10 9 cpBcc.W 8 7 6 5 4

1 I 1 I 1 I 1 I Cp- ID I 0 I 1 I 0 I Optional Coprocessor Defined Extension Words

Displacement

15 14 13 12 1 1 1 0 9 cpBcc. L

8 7 6 5 4 1 I 1 I 1 I 1 I Cp-ID I 0 I 1 I 1 I

Optional Coprocessor Defined Extension Words Displacement - High Displacement - Low

cpScc

3 2 Condition Selector

3 2 Condition Selector

15 14 13 12 1 1 10 9 8 7 6 5 4 3

1 I 1 I 1 I 1 I Cp- I D I 0 I o I 1 I Effective Address

1 Reservedl I Cond,tlon Selector

Optional Coprocessor Defined Extension Words

Optional Ef fective Address Extension Words 10-5 Wordsl

cpDBcc 15 14 13 12 11 10 9 8 7 6 5 4 3 1 I 1 I 1 I 1 I Cp- ID I 0 I 0 I 1 I 0 I o I 1 I Register

I Reservedl I Condition Selector Optional Coprocessor Defined Extension Words

Displacement

Figure 8-46. Coprocessor Instruction Formats (Sheet 1 of 2)

8-56

o

o

o

o

o

15 1 I

1 5

15

14 13 1 2 1 I 1 I 1 I

14 13 1 2

14 13 1 2

1 1 1 0 9 Cp- ID

cpTRAPcc 8 7 6

I 0 I 0 I 1 5

I 1 4 3 I 1 I 1 I Opmode

I Reserved! I Condition Selector

Optional Coprocessor Defined Extension Words Optional Word

or Long Word Operand

SAVE 1 1 1 0 9 8 7 5 4 3

Cp- ID Effective Address Effective Address Extension Words 10-5 Words!

RESTORE 1 1 10 9 8 6 5 4 3 2

Cp- I D Effective Address Effective Address Extension Words 10-5 Words!

Figure 8·46. Coprocessor Instruction Formats (Sheet 2 of 2)

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0

0

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SECTION 9 I NSTRUCTION EXECUTION T IMING

This sect ion descr ibes the i nstruct ion execut ion t i mes o f the MC68020 in terms o f external clock cyc les.

9.1 TIM ING ESTIMATION FACTORS

The advanced architecture of the MC68020 makes exact i nstruct ion t iming calcu lat ions d iff icult due to the effects of:

1) An On-Ch ip I nst ruct ion Cache and I nstruction Prefetch, 2) Operand M i sal ign ment, and 3) I nstruct ion Execut ion Overlap.

These factors make MC68020 i nstruct ion set t im ing d iff icult to calcu late on a s ing le i nstruct ion bas is s i nce i nstruct ions vary i n execution t ime from one context to another. A detai led explanation of each of these factors fol lows.

9.1 .1 Instruction Cache and Prefetch

The on-ch ip cache of the MC68020 is an i nstruct ion-only cache. I ts purpose is to i ncrease execution eff iciency by provid i ng a qu ick-store for i nstruct ions.

I nstruct ion prefetches that hit in the cache w i l l occur with no delay in i nstruct ion execut ion. I nstruct ion prefetches that miss in the cache w i l l cause an external memory cyc le to be performed, which may overlap with i nternal i nstruct ion execution. Thus, wh i le the execut ion unit of the m icroprocessor is busy, the bus control ler prefetches the next i nstruct ion from external memory. Both cases are i l l ustrated i n later examples.

When prefetching i nstruct ions from external memory, the m icroprocessor w i l l ut i l ize long word read cycles. When the read is a l igned on a long word address boundary, the processor reads two words, which may load two i nstructions at once, or two words of a mult i-word i nstruct ion. The subsequent i nstruct ion prefetch w i l l f ind the second word is a l ready avai lable and there is no need to run an external bus cyc le (read).

The MC68020 always prefetches long words. When an i nstruct ion prefetch fal ls on an odd word boundary (e.g . , due to a branch to an odd word locat ion), the MC68020 w i l l read the even word associated with the long word base address at the same t ime as (32-bit memory) or before (8- or 1 6-bit memory) the odd word is read. When an i nstruct ion prefetch fal ls on an even word boundary (as would be the normal case), the MC68020 reads both words at the long word address, thus effect ively prefetch ing the next two words.

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9.1 .2 Operand Misalignment

Another s ign if icant factor affect ing i nstruction t im ing is operand m isa l ignment. Operand misal ignment has impact on performance when the microprocessor is read i ng or wr i t ing external memory. I n th is case the address of a word operand fal ls across a long word boundary or a long word operand fal ls on a byte or word address which is not a long word boundary. Whi le the MC68020 w i l l automat ical ly handle a l l occurrences of operand m isal ignment, i t must use mu l t iple bus cycles to complete such transfers.

9.1 .3 Concurrency

The MC68020 al lows concurrency to take p lace when execut ing instruct ions. The main e lements part ic i pat ing i n th is concurrency are the bus control ler and the sequencer. The bus contro l ler is responsible for a l l bus activity. The sequencer controls the bus con· t ro l ler, i nstruction execution, and i nternal processor operat ion, such as calcu lation of ef· fect ive addresses and sett ing of condit ion codes. The sequencer is responsible for i n· i t iat ing i nstruction prefetches, decod i ng and va l idating incoming i nstructions i n the p ipe.

The bus contro l ler and sequencer can operate on an i nstruction concurrent ly. The bus control ler can perform a read or write whi le the sequencer controls an effective address calcu lation or sets the condit ion codes. The sequencer may also request a bus cyc le that the bus control ler cannot immediately perform. I n th is case the bus cycle is q ueued and the bus control ler runs the cycle when the current cycle is complete.

Concurrency of operat ion between the sequencer and bus control ler introduces ambigu ity into the calcu lation of i nstruction t im ing due to potentia l overlap of i nstruction execut ion .

9.1 .4 Overlap

Overlap is the t ime, measured in c locks, when two i nstructions execute s imu ltaneously. Overlap is measured as the t ime that an instruction is execut ing concurrent to the previous instruction. In F igure 9·1 , i nstructions A and B execute s imultaneously and the overlapped port ion of instruction B is absorbed in the instruction execut ion t ime of A (the previous i nstruct ion). The overlap t ime is deducted from the execut ion t ime of instruction B. Simi larly, there is an overlap period between i nstruction B and i nstruction C, which reduces the attributed execut ion t ime for C.

� - - - - Instruction A -------I � - - - - lnstruction B ------i

r - - - - I nstruction C -------l

Overlap Overlap

Figure 9·1 . Simultaneous Instruction Execution

9-2

The execut ion t ime attr ibuted to i nstructions A, B, and C (after consideri ng the overlap) is depicted in F igure 9·2.

I----- �nstruction A------;

I---- Instruction B -----i

Overlap Period

(Absorbed by Instruction AI

Overlap Period

(Absorbed by Instruction B I

�-- Instructlon C --...,

Figure 9·2. Instruction Execution for Instruction Timing Purposes

It is poss ible that the execut ion t ime of an i nstruction w i l l be absorbed by the overlap with a previous i nstruction for a net execut ion t ime of zero c locks.

9.1 .5 Instruction Stream Timing Examples

A programming example al lows a more detai led exam i nation of these effects. The effect of i nstruction execut ion overlap on i nstruction t im ing is i l l ustrated by the fol lowing ex· ample i nstruction stream:

Instruction #1 ) MOVE.L D4,(A1 ) + #2) ADD.L D4, D5 #3) MOVE.L (A1), - (A2) #4) ADD.L D5, D6

For the f i rst example, the assumpt ions are: 1) The data bus is 32 bits, 2) The f i rst i nstruction is prefetched from an ODD word address, 3) Memory access with no wait states, and 4) The i nstruction cache is d isabled.

For this example, the i nstruction stream is posit ioned i n 32·bit memory as:

Address n

n + 4

n + 8

. . .

ADD #2

ADD #4

9·3

MOVE #1

MOVE #3

. . .

•

Figure 9-3 shows processor activity on the f i rst exam ple i nstruct ion stream. It shows the act ivity of the external bus, and bus control ler, the sequencer, and the attributed instruction execution t i me.

2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 16 1 7 Clock

Bus Activity ( Prefetch X,-__ w_rit_e _...JX,-__ R_ea_d_-,X Prefetch

Bus Controller

Sequencer

Instruction Execution Time

Write � '--------',.,------,

Clock Count 1----- (61 ------ir--------- 191 ---------111- 1 1 ,-1 LEGEND:

#11 MDVE. L D4,(A l l + _ 121 ADD.L 04,D5 C=:J 131 MOVE.L (A1 1 , - (A21 _ 141 ADD . L D5,D6 C:=J

Figure 9-3. Processor Activity Example 1

For the f i rst three c locks of this example, the bus control ler and seq uencer are both perform i ng tasks associated with the MOVE #1 i nstruct ion. The next th ree c locks (clocks four, five, and six) demonstrate i nstruction overlap. The bus control ler is performing a write to memory as part of the MOVE #1 i nstruction. The sequencer, on the other hand, is perform ing the ADD #2 i nstruction for two clocks (clocks four and five) and beginn ing source effective address (EA) calcu lat ions for the MOVE #3 instruction. The bus controller act ivity completely overlaps the execution of the ADD #2 i nstruct ion, causing the ADD #2 attributed execution t ime to be zero clocks. This overlap a lso shortens the effective execution t ime of the M OVE #3 i nstruct ion by the one clock because the bus controller completes the MOVE #1 write operation whi le the seq uencer begins the MOVE #3 effective address calcu lation.

The sequencer cont i n ues the source EA calculat ion for one more clock period (clock seven) whi le the bus control ler beg ins a read for MOVE #3. When counting i nstruction

9-4

execution t ime i n bus c locks, the MOVE #1 completes at the end of c lock 6 and the execution of MOVE #3 beg ins on c lock 7.

Both the sequencer and bus contro l ler cont inue with MOVE #3 unti l the end of clock 1 4, when the sequencer beg ins to perform ADD #4. T iming for MOVE #3 cont inues, because the bus control ler is st i l l performing the write to the desti nation of MOVE #3. The bus act ivity for MOVE #3 completes at the end of clock 1 5. The effective execution t ime for MOVE #3 is 9 c locks.

The one c lock cycle (c lock 1 5) when the sequencer is performing ADD #4 and the bus cont rol ler is wr i t ing to the dest i nation of MOVE #3 is absorbed by the execution t ime of MOVE #3. This shortens the effective execut ion t ime of ADD #4 by one c lock, g iving it an attri buted execution t ime of one clock.

Us ing the same i nstruct ion stream, the second example demonstrates the d i fferent ef· fects of i nstruction execut ion overlap on i nstruction t iming when the same i nstructions are pos it ioned s l ight ly d i fferently, in 32-bit memory:

Address n

n + 4

n + 8

MOVE #1

MOVE #3

. . .

ADD #2

ADD #4

. . .

The assumptions for the second example i n F igure 9-4 are: 1) The data bus is 32 bits, 2) The f i rst inst ruction is prefetched from an EVEN word address, 3) Memory access occur w i th no wait states, and 4) The cache is d i sabled.

Whi le the total execut ion t ime of the i nstruction segment does not change in this example, the i nd ividual i nstruction t imes are s ign i f icantly d i fferent. This demonstrates that the effects of overlap are not on ly i nstruction sequence dependent, but are also depen· dent upon the a l ig nment of the i nstruction stream in memory.

Both F igures 9-3 and 9-4 show inst ruction execution without benefi t of the MC68020 i nstruction cache. F igure 9-5 shows a th i rd example for the same i nstruction stream execut ing in the cache. The assumptions for Example 3 are:

1 ) The data bus is 32 bits, 2) The cache is enabled and i nstructions are in the cache, and 3) Memory access occur with no wait states.

9-5

•

2 3 4 5 6 7 8 9 10 1 1 1 2 1 3 14 15 16 1 7 Clock

Bus Activity f------1( Write X Prefetch X Read X Write X Prefetch )

Bus Controller Prefetch

Bvtes n+ 1 2 • Sequencer Next

Instruction --

Instruction Execution Time ADD.L D5,06

Clock Counter 141 131 16) (3) ----1 LEGEND : 1 1 ) MOVE .L D4, IA1 ) + • #2) ADD .L D4,D5 D #3) MOVE. L IA1 ) , - IA2) • #4) ADD . L D5,D6

LEGEND:

Figure 9·4. Processor Activity for Example 2

2 3 4 5 6 7 8 9 10 1 1 1 2

Clock

Bus Activity f------l('-__ w_r_ite _____ >------< _____ R_e_a_

d __ ...IX'-___ W_r_it_e __ -')-----i

Bus Controller

Sequencer


Clock Counter f------ (4) -----+-------- (7) --------+-1 ( 1 ) --1

D

1 3

' 1 ) MOVE. L D4, IA1 ) + • #2) ADD . L D4,D5 0 '3) MOVE . L IA1 ) , - IA2) • #4) ADD . L D5,D6 0


9-6

Note that once the instructions are i n the cache, the original locat ion in external memory is no longer a factor in t iming.

F igure 9-5 i l l ustrates the benefits of the instruction cache. The total number of c lock cycles is reduced from 16 to 1 2 c locks. S ince the i nstructions are res ident in the cache, the i nstruction prefetch activity does not requ i re the bus contro l ler to perform external bus cycles. Prefetch occurs with no delay, and subsequently, the bus control ler is idle more often.

Such idle c lock cycles are usefu l in M C68020 systems that requ i re wait states when acceSSing external memory. This is i l l ustrated by the fourth example i n Figure 9-6 with the following assumpt ions:

1 ) The data bus is 32 bits, 2) The cache is enabled and i nstructions are in the cache, and 3) Memory access occur with one wait state.

2 3 4 5 6 7 8 9 10 1 1 1 2 13 Clock

Bus Activity � Write X Read X Write '" ��. --------� �--------� �--------��

Bus Controller

Sequencer


Clock Count 1------ (5) -----+-------- (8) ---------

LEGEND:

11) MOVE.L D4.(A l l + .. #21 AOO .L 04,05 CJ #31 MOVE .L (Al l , - (A21 .. #41 AOO.L 05,06


9-7

14

•

•

Figure 9-6 shows the same i nstruction stream execut ing with four c locks for every read and write. The id le bus cyc les coincide with the wait states of the memory access, so the total execut ion t ime is only 13 c locks.

These examples demonstrate the complexity of i nstruct ion t im ing calculat ion for the MC68020. I t is impossible to ant ic ipate i nd ividual i nstruct ion t im ing as an absol ute number of c lock cyc les due to the dependency of overlap on the instruction sequence and a l ignment, as wel l as the nu mber of wait states in memory. Th is can be seen by compari ng ind ividual and composite t ime for F igure 9-3 through 9-6. These i nstruction t imi ngs are compared i n Table 9-1 , where t i m i ng varies for each i nstruction as the context varies.

Table 9-1 . Example Instruction Stream Execution Comparison

Example 4 Example 1 Example 2 Example 3 (Cache With

Instruction (Odd Alignment! ( Even Alignment) (Cache) Wait States) # 1 1 MOVE. L 04, IAl I + 6 4 4 5 #2) AOO .L 04,05 0 3 0 0

#3) MOVE . L IAl I , - IA2) 9 6 7 8 #41 AOO.L 05,06 1 3 1 0

Total Clock Cycles 16 16 1 2 1 3

9.2 INSTRUCTION TIMING TABLES

The i nstruction t imes below i nclude the fol lowing assumptions about the MC68020 system:

1) A l l operands are long word a l igned as is the stack, 2) 32-bit data bus, and 3) No wait state memory (3 cyc le read/write).

There are three values g iven for each instruction and address ing mode: 1) The best case (BC) which ref lects the t ime ( in clocks) when the i nstruction is in the

cache and benef its from max imum overlap due to other i nstructions. 2) Cache-only-case (CC) when the i nstruction is in the cache but has no overlap, and 3) Worst case (WC) when the i nstruction is not in cache or the cache is d isabled and

there is no i nstruction overlap.

The only i nstances for which the s ize of the operand has any effect are the i nstruct ions with immediate operands. Un less specif ied otherwise, immediate byte and word operands have ident ical execut ion t imes.

9-8

With in each set or column of i nstruction t im ings are fou r sets of numbers, three of which are enclosed i n parentheses. The outer number is the total nu mber of c locks for the i nstruction. The f i rst number i nside the parentheses is the number of operand read cycles performed by the i nstruct ion. The second val ue i nside parentheses is the nu mber of i n· struction accesses performed by the i nstruction, i nc lud ing a l l prefetches to keep the i n· struction p ipe f i l led. The th i rd value wi th in parentheses is the nu mber of write cyc les performed by the instruction. One example from the i nstruction t im ing table is:

24 @/�/Q)

Total N umber Of CIOCkS �� I N umber of Read CYCles --.J

N u mber of I nstruct ion Access Cyc les

N u mber of Write Cyc les

The total number of bus activity c locks for the above example is derived in the fol lowing way:

(2 Reads * 3 Clocks/Read) + (3 I nstruction Accesses * 3 Clocks/Access) + (0 Writes * 3 ClockslWrite) = 1 5 Clocks of Bus Activity

24 Total C locks - 1 5 C locks (Bus Activity) = 9 I nternal Clocks

The example used here was taken from a worst-case "fetch effect ive address" t ime. The addressing mode was ([d32,B] , I ,d32). The same addressing mode under the best case ent ry is 1 7 (2/0/0). For the best case, there are no i nstruction accesses because the cache is enabled, and the sequencer does not have to go to externa l memory for the instruct ion words.

The f i rst tables deal exclus ively with fetch ing and calculat ing effective addresses and immediate operands. The tables are arranged in th is manner because some i nstructions do not requ i re effective address calculation or fetch i ng. For example, the i nstruction CLR < ea > (found in the table u nder 9.2.1 1 Single Operand Instruction) only needs to have a calcu lated EA t ime added to its table entry because no fetch of an operand is req u i red. This i nstruction only wr ites to memory or a reg ister. Some i nstructions use specif ic address ing modes which exc lude t im ing for calcu lat ion or fetch ing of an operand. When these i nstances arise, they are footnoted to ind icate which other tables are needed in the t im ing calcu lat ion.

The MOVE i nstruct ion t im ing tables i nclude al l necessary t im ing for extension word fetch, address calcu lation, and operand fetch.

The i nstruction t im ing tables are used to calcu late a best case and worst case bounds for some target i nstruct ion stream. Calcu lat ing exact t im ing from the t im ing tables is imposs ible because the tables cannot ant ic ipate how the combi nation of factors w i l l i nf luence every part icu lar sequence of i nstruct ions. This is i l l ustrated by compar ing the observed i nstruct ion t im ing from the prior four examples with i nstruction t im ing derived from the i nstruct ion t im ing tables.

9-9

•

•

Table 9-2 shows the orig i nal instruction stream and the correspond i ng c lock t im ing from the appropriate t i m i ng tables for the best case (BC), cache on ly case (CC), and worst case (WC).

Table 9·2. Instruction Timings from Timing Tables

I nstruction Best Case Cache Case Worst Case # 1 1 MOVE.L 04 , IA1 1 + 4 4 6 #21 AOO . L 04,05 0 2 3 #31 MOVE. L IAl I , - IA21 6 7 9 #41 AOO . L 05,06 0 2 3

Total 10 1 5 2 1

Table 9-3 summarizes the observed i nstruction t imings for the same i nstruction stream as executed accord ing to the assumpt ions of the four examples. For each example, Table 9·3 shows which entry (BC/CC/WC) from the t iming tables corresponds to the observed t im ing for each of the four instruct ions. Some of the observed instruction t imings cannot be found in the t iming tables and appear in Table 9-3 wi th in parenthes is in the most appropriate column. These occur when i nstruction execution overlap dynamical ly a lters what wou ld otherwise be a BC, CC, or WC t iming.

Table 9·3. Observed Instruction Timings

Example 1 Example 2 Example 3 Example 4 I nstruction BC CC WC BC CC WC BC CC WC BC CC WC

# 1 1 MOVE.L 04, IAl I + 6 4 4 151 #21 AOO. L 04,05 0 3 0 0 #31 MOVE. L IA1 1 , - IA21 9 6 7 181 #41 AOO. L 05,06 1 1 1 3 I I I 0

Total 1 1 61 1 161 1 1 21 1 1 31

Compari ng Tables 9-2 and 9-3 demonstrates that calculat ion of instruction t im ing cannot be a s imple lookup of on ly BC or on ly WC t im i ngs. Even when the assumptions are known and f ixed, as in the four examples summarized in Table 9-3, the m icroprocessor can somet imes achieve best case t imings u nder worst case assumpt ions.

Looking across the four examples in Table 9-3 for an i ndiv idual instruction, it is d i ff icu lt to pred ict which t im ing table entry is used, s i nce the inf luence of i nstruction overlap may or may not improve the BC, WC, or CC t im ings. When looking at the observed i nstruction t im ings for one example, it is also d iff icult to determine which combination of BC/CC/wC t im ing is req u i red. J ust how the i nstruction stream w i l l f i t and run with cache enabled, how i nstructions are posit ioned in memory, and the degree of i nstruction overlap are factors that are impossible to be accounted for i n a l l combinations of the t im ing tab les.

Although the t iming tables cannot accurately pred ict the i nstruction t im ing that wou ld be observed when execut ing an i nstruction stream on the MC68020, the tables can be used to calcu late best case and worst case bounds for i nstruction t im ing . Absol ute i nstruction t iming must be measu red by us ing the microprocessor itself, to execute the target i nstruction stream.

9-1 0

9.2.1 Fetch Effective Address

The fetch effective address table ind icates the number of c lock periods needed for the processor to calcu late and fetch the specif ied effective address. The total nu mber of c lock cyc les i s outside the parentheses, the number of read, prefetch, and write cyc les are g iven i nside the parentheses as (r/p/w). They are inc luded in the total c lock cyc le nu mber.

Address Mode Best Case Cache Case Worst Case On o 10/0/01 o 10/0/01 o 10/0/01 An o 10/0/01 o 10/0/01 o 10/0/01 IAnl 3 1 1 /0/01 4 1 1 /0/01 4 1 1 /0/01 IAnl + 4 1 1 /0/01 4 1 1 /0/01 4 1 1 /0/01 - IAnl 3 1 1 /0/01 5 1 1 /0/01 5 1 1 /0101 I d16,Anl of I d 16,PCI 3 1 1 /0/01 5 1 1 /0/01 6 1 1 / 1 101 Ixxxl .W 3 1 1 /0/01 4 1 1 /0/01 6 1 1 / 1 101 I xxxl . L 3 1 1 /0/01 4 1 1 /0/01 7 1 1 / 1 101 # < data > . B o 10/0/01 2 10/0/01 3 10/ 1 101 # < data > .W o 10/0/01 2 10/0/01 3 10/ 1 /01 # < data> . L o 10/0/01 4 10/0/01 5 10/ 1 /01 Ids,An,Xnl or I dS, PC, Xnl 4 1 1 /0/01 7 1 1 /0/01 S 1 1 / 1 101 Id1 6,An,Xnl or Id 16, PC,Xnl 4 1 1 /0/01 7 1 1 /0/01 9 1 1 / 1 /01 I B I 4 1 1 10/01 7 1 1 /0/01 9 1 1 / 1 /01 Id 16, BI 6 1 1 /0/01 9 1 1 /0/01 12 1 1 / 1 /01 Id32, BI 10 1 1 /0/01 13 1 1 /0/01 16 1 1 /2/01 I [ B ] . I I 9 12/0/01 12 12/0/01 13 12/ 1 /01 I [ B l . I , d 1 61 1 1 12/0/01 14 12/0/01 16 12/ 1 101 I [ B l . I , d321 1 1 12/0/01 14 12/0/01 17 12/2/01 ( [ d16, B] . 1 J 1 1 12/0/01 14 12/0/01 16 12/ 1 101

l [ d16, Bl . I , d 1 61 13 12/0/01 16 12/0/01 19 12/2/01 ( [ d16, B] . I , d321 13 12/0/01 16 12/0/01 20 12/2/01 ( [ d32 , B l . I I 1 5 12/0/01 lS 12/0101 20 12/2/01 ( [ d32, B l . I , d 1 61 1 7 12/0101 20 12/0101 22 12/2/01 ( [d32, B l . I , d321 17 12/0101 20 12/0101 24 12/3/01

B = Base address; 0, An, PC, Xn, An + Xn, PC + Xn. Form does not affect timing.

1 = I ndex; 0, Xn

NOTE: Xn cannot be in B and I at the same t ime. Scaling and size of Xn does not affect timing.

9.2.2 Fetch Immediate Effective Address

The fetch i mmed iate effective address table ind icates the number of c lock periods need· ed for the processor to fetch the immediate sou rce operand, and calcu late and fetch the spec if ied dest i nation operand. The total number of c lock cyc les is outside the parentheses, the number of read, prefetch, and write cyc les are g iven inside the parentheses as (r/p/w). They are i nc l uded in the total c lock cyc le number.

9-1 1

•

Address Mode Best Case Cache Case Worst Case # < data > .W,On o 10/0/01 2 10/0/01 3 10/ 1 /01 # < data > . L,On 1 10/0/01 4 10/0/01 5 10/ 1 /01 # < data > .W,IAnl 3 1 1 /0/01 4 1 1 /0/01 4 1 1 / 1 /01 # < data > . L, IAnl 3 1 1 /0/01 4 1 1 /0/01 7 1 1 / 1 /01 # < data > .W, IAnl + 4 1 1 /0/01 6 1 1 /0/01 7 1 1 / 1 /01 # < data > . L, IAnl + 5 1 1 /0/01 8 1 1 /0/01 9 1 1 / 1 /01 # < data > .W, - IAnl 3 1 1 /0/01 5 1 1 /0/01 6 1 1 / 1 /01 # < data > .L , - IAnl 4 ( 1 /0/01 7 1 1 /0/01 8 1 1 / 1 /01 # < data > .W, lbd,Anl 3 ( 1 /0/01 5 1 1 /0/01 7 1 1 / 1 /01 # < data> . L, l bd ,Anl 4 1 1 /0/01 7 1 1 /0/01 10 1 1 /2/01 # < data > .W,xxx.W 3 1 1 /0/01 5 1 1 /0/01 7 1 1 / 1 /01 # < data > . L,xxx.W 4 1 1 /0/01 7 1 1 /0/01 10 1 1 /2/01 # < data> .W,xxx.L 3 1 1 /0/01 6 1 1 /0/01 10 1 1 /2/01 # < data> . L,xxx . L 4 1 1 /0/01 8 1 1 /0/01 12 1 1 /2/01 # < data > .W,# < data > . B ,W o 10/0/01 4 10/0/01 6 10/2/01 # < data > .W,# < data> . B ,W 1 10/0/01 6 10/0/01 8 10/2/01 # < data > .W,# < data > . L o 10/0/01 6 10/0/01 8 10/2/01 # < data> .L ,# < data > . L 1 10/0/01 8 10/0/01 10 10/2/01 # < data > .W, ld8,An,Xnl or IdS,PC,Xnl 4 1 1 /0/01 9 1 1 /0/01 11 1 1 /2/01 # < data > .L , l d8, An,Xnl or Id8, PC ,Xnl 5 1 1 /0/01 1 1 1 1 /0/01 13 1 1 /2/01 # < data > .W, ld16,An,Xnl or Id1 6, PC ,Xnl 4 1 1 /0/01 9 1 1 /0/01 12 1 1 /2/01 # < data> . L, ld16,An,Xnl or Id 16,PC,Xnl 5 1 1 /0/01 1 1 1 1 /0/01 15 1 1 /2/01 # < data > .W, IB I 4 1 1 /0/01 9 1 1 /0/01 12 1 1 /2/01 # < data > . L, I B I 5 1 1 /0/01 1 1 1 1 /0/01 14 1 1 /2/01 # < data > .W,lbd,PCI 10 1 1 /0/01 15 1 1 /0/01 19 1 1 /3/01 # < data > . L, lbd,PCI 11 1 1 /0/01 17 1 1 /0/01 21 1 1 /3/01

• # < data > .W,ld 16,B I 6 1 1 /0/01 1 1 1 1 /0/01 15 1 1 /2/01 # < data > . L, ld16, BI 7 1 1 /0/01 13 1 1 /0/01 17 1 1 /2/01 # < data> .W,ld32,B I 10 1 1 /0/01 15 1 1 /0/01 19 1 1 / 3/01 # < data> . L, l d32,B I 1 1 1 1 /0/01 17 1 1 /0/01 21 1 1 /3/01 # < data> W, ( [ B l . I l 9 12/0/01 14 12/0/01 16 12/2/01 # < data > . L, ( [B ] . 1 I 10 12/0/01 16 12/0/01 1 8 12/2/01 # < data> W, ( [B J . l . d161 1 1 12/0/01 16 12/0/01 1 9 12/2/01 # < data> . L, I [ B J . l . d 161 12 12/0/01 1 8 12/0/01 2 1 12/2/01 # < data> .W, ( [B J . l . d321 1 1 12/0/01 16 12/0/01 20 12/3/01 #< data > . L . I l d 16, B] . I , d321 12 12/0/01 1 8 12/0/01 22 12/3/01 # < data > W, ( (d16, B l . I l 1 1 12/0/01 16 12/0/01 19 12/2/01 # < data> .L , ( [d 16,B l . I l 1 2 12/0/01 18 12/0/01 21 12/2/01 # < data > .W, ( (d 16,B ] . I , d 16) 13 12/0/01 18 12/0/01 22 12/3/01 # < data> . L . I ld 16,B J . l .d 16) 14 12/0/01 20 12/0/01 24 12/3/01 # < data > .W, ( (d32, B] . 1 I 1 5 12/0/01 20 12/0/01 23 12/3/01 # < data > . L, l [d32, Bl . I ) 16 12/0/01 22 12/0/01 25 12/3/0) # < data> . W, I [d32, B J , I , d16) 17 12/0/01 22 12/0/01 25 12/3/01 # < data > . L , l l d32, B J . l . d161 18 12/0/01 24 12/0/01 27 12/3/01 # < data > .W, ( (d32, B ] . I ,d32) 17 12/0/01 22 12/0/0) 27 12/4/01 #< data > . L , ( (d32, BL I , d321 18 12/0/01 24 12/0/0) 29 12/4/01

B = Base address; 0, An, PC, Xn, An+ Xn, PC + Xn. Form does not affect timing.

I = I ndex 0, Xn

NOTE: Xn cannot be in B and I at the same time. Scaling and size of Xn does not affect timing.

9-1 2

9.2.3 Calculate Effective Address

The calcu late effective address table ind icates the number of c lock periods needed for the processor to calcu late the specif ied effect ive address. Fetch t ime is only i nc l uded for the f i rst level of ind i rection on memory ind i rect add ress ing modes. The total number of c lock cycles is outside the parentheses, the number of read, prefetch, and write cyc les are g iven i nside the parentheses as (r/p/w). They are i ncluded in the total c lock cyc le number.

Address Mode Best Case Cache Case Worst Case On o (010101 o 1010/01 o 10/0/01 An o 10/0/01 o 10/0/01 o 10/0/01 IAnl 2 1010lOJ 2 1010lOJ 2 1010lOJ IAnl + 2 (0/0/01 2 1010/01 2 10/0/01 - IAnl 2 1010lOJ 2 (010101 2 1010/01 I d1 6.Anl or Id 16. PCI 2 1010lOJ 2 10/0/01 3 10/ 1 101 < data > .W 2 10/0/01 2 10/0/01 3 101 1 10J < data > . L 1 10/0/01 4 10/0/01 5 10/ 1 101 I d8.An.Xnl or I d8. PC .Xnl 1 10/0/01 4 10/0/01 5 10/ 1 IOJ Id 16.An.Xnl or I d16. PC.Xnl 3 1010lOJ 6 10/0/01 7 10/ 1 101 I BI 3 10/0/01 6 1010lOJ 7 10/ 1 101 I d16.B I 5 10/0/01 8 10/0/01 10 10/ 1 101 I d32. BI 9 1010lOJ 12 10/0/01 15 10/2/01 I I B I . I I 8 1 1 /0/01 1 1 1 1 /0/01 12 1 1 / 1 /01 I [ BI . I . d 161 10 1 1 /0/01 13 1 1 /0/01 15 1 1 / 1 /01 I [ B l . I . d321 10 1 1 /0/01 13 1 1 /0/01 16 1 1 /2101 l [ d 16. B l . I I 10 1 1 /0/01 13 1 1 /0/01 15 1 1 / 1 /01 I [ d 16. B I . I . d 161 1 2 1 1 /0/01 15 1 1 /0/01 18 1 1 /2/01 l [ d 16. B l . I . d321 1 2 1 1 /0/01 15 1 1 /0/01 19 1 1 /2/01 l [ d32 .B I . I I 14 1 1 /0/01 17 1 1 /0/01 19 1 1 /2/01 l [ d32 .B I . I . d 1 61 16 1 1 /0/01 19 1 1 /0/01 21 1 1 /2/01 l [ d32 . B l . I . d321 16 1 1 /0/01 19 1 1 /0/01 24 1 1 /3/01

B = Base address; O. An. PC. Xn. An + Xn. PC + Xn. Form does not affect timing.

I = I ndex; O. Xn

NOTE: Xn cannot be in B and I at the same time. Scaling and size of Xn does not affect timing.

9.2.4 Calculate Immediate Effective Address

The calcu late immediate effect ive add ress table i nd icates the nu mber of c lock periods needed for the processor to fetch the immed iate source operand and calcu late the spec if ied dest i nation effect ive address. Fetch t ime is on ly i nc luded for the f i rst level of i nd i rection on memory ind i rect addressing modes. The total nu mber of c lock cyc les is outs ide the parentheses, the nu mber of read, prefetch, and wr i te cyc les are g iven i nside the parentheses as (r/p/w). They are i ncluded i n the total c lock cyc le nu mber.

9·1 3

•

Address Mode Best Case Cache Case Worst Case # < data > .W,Dn o 1010101 2 1010101 3 10/ 1 101 # < data > . L,Dn 1 1010101 4 1010101 5 10/ 1 101 # < data > .W, IAnl o 1010/01 2 1010/01 3 10/ 1 101 # < data > . L, IAn) 1 1010101 4 1010/01 5 10/ 1 /01 # < data > .W, IAnl + 2 (0/0/0) 4 10/0/01 5 10/1 101 # < data > . L, IAnl + 3 10/0101 6 1010101 7 10/1 /01 # < data > .w, lbd.An) 1 1010/01 4 10/0/01 5 10/1 101 # < data > . L, lbd,Anl 3 10/0/01 6 10/0/01 8 (0/2/0) # < data > .W, lxxx) .W 1 1010/01 4 (0/0/0) 5 10/ 1 /01 # < data > . L, lxxxl. W 3 10/0/01 6 10/0/01 8 10/2/01 # < data > .W, lxxxl . L 2 10/0/01 4 10/0/01 6 10/2/01 # < data > . L, l xxxl . L 3 10/0/01 8 10/0/01 10 10/2/01 # < data > .W, ld8,An,Xn) o r Id8, PC,Xn) o 1010/01 6 10/0/01 8 10/2/01 # < data> . L, l d8,An,Xnl or Id8,PC,Xnl 2 10/0/01 8 1010101 10 10/2/01 # < data > .W, ld1 6.An,Xnl or Id16, PC,Xnl 3 10/0/01 8 1010101 10 10/2/01 # < data > L . ld16,An,Xn) or Id 16. PC,Xnl 4 (0/0/0) 10 (0/010) 12 10/2/01 # < data > W, IB ) 3 10/0/01 8 10/0101 10 10/2/01 # < data > . L, I B ) 4 10/0/01 10 (0/0/0) 12 (0/2/0) # < data > .W, lbd,PCI 9 10/0/01 14 (0/0/0) 18 1013101 # < data > .L , l bd, PC) 10 10/0/01 16 10/0/01 20 (0/3/0) # < data > .W, ld16, B) 5 1010/01 10 10/0/01 13 10/2/01 # < data > .L , ld 16, B ) 1 6 10/0/01 12 10/0/01 15 10/2/01 # < data > .W, ld32, B) 9 10/0/01 14 10/0/01 18 10/3/01 # < data > . L, Id32, BI 10 10/0/01 16 1010/01 20 10/3/01 # < data > .W,I [ B l , l I 8 1 1 /0/01 13 1 1 /0101 15 1 1 /2/01 # < data > . L , I [ B l , l l 9 1 1 /0/01 15 1 1 /0/01 17 1 1 /2/01 .

• # < data > W, I [B l . I ,d 16) 10 ( 1 /010) 15 1 1 /0/01 18 1 1 /2/01 # < data > . L, I [ B l , l , d 161 1 1 1 1 /0101 17 1 1 /0101 20 1 1 /2/01 # < data > .W, ( [B l . I ,d32) 10 1 1 /0/01 15 1 1 /0/01 19 1 1 / 3/01 # < data> L, I [ Bl . I ,d321 1 1 1 1 /0/01 17 1 1 /0101 21 1 1 / 3/01 # < data > .w, ( [d16, Bl . I I 10 1 1 /0/01 15 1 1 /0101 18 1 1 /2/01 # < data > .L , ( [d16, B l , l I 1 1 1 1 /0/01 17 1 1 /0101 20 1 1 /2/01 #< data > .w, ld16, B l , l , d 161 : 1 2 1 1 /0/01 17 1 1 /0/01 21 ( 1 /3/0)

# < data > L, ( [d16,B l . I . d 16) 13 1 1 /0/01 19 1 1 /0/01 23 1 1 /3/0) # < data > ( [d16, Bl . I , d321 12 1 1 /0/01 17 ( 1 /0/0) 22 1 1 /3/01 #< data > ( [ d16, Bl . l , d32) 13 ( 1 /0/0) 19 1 1 /0/01 24 ( 1 /3/0) # < data > .W, I [d32, Bl . l I 14 1 1 /0/01 19 1 1 /0/01 22 ( 1 /3/0) # < data > . L, I [ d32,B l . I I 1 5 1 1 /0/01 21 1 1 /0/01 24 1 1 /3/01 # < data > .W,I [d32, B l . I , d 16) 16 ( 1 /0/0) 21 1 1 /0/01 24 1 1 / 3/0) # < data> . L, I [ d32, Bl . l , d 161 17 1 1 /0/01 23 1 1 /0/01 26 1 1 / 3/01 # < data> .w, I [d32, B l . l ,d321 16 ( 1 /0/0) 21 1 1 /0/01 24 1 1 / 3/01 # < data> 1 . I [d32,B l . I , d321 17 1 1 /0/0) 23 1 1 /0/01 29 1 1 / 3/01

B = Base address; 0, An, PC, Xn, An + Xn, PC + Xn. Form does not affect timing.

I = Index; 0, Xn

NOTE: Xn cannot be in B and I at the same t ime. Scaling and s ize of Xn does not affect timing.

9-1 4

9.2.5 Jump Effective Address

The jump effective address table i nd icates the number of c lock periods needed for the processor to calcu late and jump to the specif ied effective address. Fetch t ime is on ly i n· c luded for the f i rst level of ind i rect ion on memory ind i rect address ing modes. The total number of c lock cycles is outside the parentheses, the nu mber of read, prefetch, and write cycles are g iven ins ide the parentheses as (r/p/w). They are i ncluded in the total c lock cycle number.

Address Mode Best Case Cache Case Worst Case

IAnl o 1010101 2 1010101 2 1010101 Id 16.Anl 1 1010/01 4 1010101 4 1010101 Ixxxl .W o 10/0101 2 10/0/01 2 10/0/01 Ixxxl . L o 1010/01 2 10/0/01 2 1010101 I ds.An.Xnl or Ids.PC.Xnl 3 1010/01 6 1010/01 6 1010/01 I d16.An.Xnl or Id 16. PC.Xnl 3 1010/01 6 1010/01 6 1010/01 I B I 3 10/0/01 6 10/0/01 6 10/0/01 I B . d 161 5 10/0/01 S 10/0/01 S 101 1 101 I B . d321 9 1010/01 12 1010/01 12 101 1 101 I [ B ] . I I S 1 1 /0101 1 1 1 1 /0/01 1 1 1 1 / 1 /01 I [ B ] . I . d161 10 1 1 /0/01 13 1 1 /0/01 14 1 1 1 1 /01 I [ B ] . I . d321 10 1 1 /0101 13 1 1 /0101 14 1 1 1 1 /01 l [d 16. B] . 1 1 10 1 1 /0101 13 1 1 /0101 14 1 1 / 1 /01 ( [ d16. B] . I . d 161 1 2 1 1 /0101 15 1 1 /0101 17 1 1 1 1 /01 ( [ d16. Bl . I . d321 1 2 1 1 /0101 15 1 1 /0101 17 1 1 / 1 /01 ( [ d32. B] . I I 14 1 1 /0101 17 1 1 / 0101 19 1 1 /2/01 ( [ d32. Bl , l . d161 16 1 1 /0/01 19 1 1 /0101 21 1 1 / 2/01 ( [ d32. B l . I . d321 16 1 1 /0101 19 1 1 /0101 23 1 1 /3/01

B = Base address; O. An. PC. Xn. An + Xn. PC + Xn. Form does not affect timing.

I = Index ; O. Xn

NOTE: Xn cannot be in B and I at the same t ime. Scaling and size of Xn does not affect timing.

9.2.6 MOVE Instruction

The MOVE i nstruction t i m i ng table ind icates the number of c lock periods needed for the processor to fetch, calcu late, and perform the MOVE or MOVEA with the spec if ied source and dest i nation effective addresses, inc lud ing both levels of ind i rect ion on memory ind i rect address ing modes. No add it ional tables are needed to calcu late the total effective execut ion t ime for the MOVE or MOVEA i nstruct ion. The total number of c lock cycles is outside the parentheses, the number of read, prefetch, and wri te cyc les are g iven i nside the parentheses as (r/p/w). They are inc l uded in the total c lock cyc le number.

9· 1 5

BEST CASE Source

Address Destination

Mode An On (An) (An) + - (An) (d16.An) (xxx).W (xxxl . L

An o (0/0/0) o (0/0/0) 3 (0/01 1 ) 4 (0/0/ 1 ) 3 (0/0/ 1 ) 3 10/01 1 ) 3 10/011 I 5 10/0/ 1 ) # < data> . B ,W o (0/0/0) o (0/0/0) 3 (0/01 1 ) 4 (0/01 1 ) 3 (0/0/ 1 ) 3 (0/01 1 ) 3 10/011 I 5 10/01 1 1 # < data> . L o (0/0/01 o (0/0/0) 3 (0/0/ 1 ) 4 (0/01 1 ) 3 (0/01 1 1 3 (0/01 1 ) 3 (0/0/ 1 1 5 10/01 1 1 (An) 3 1 1 /0/01 3 ( 1 /0/0) 6 ( 1 /0/ 1 ) 6 ( 1 /01 1 ) 6 ( 1 /0/ 1 ) 6 ( 1 /0/ 1 ) 6 1 1 /0/ 1 ) 8 ( 1 /01 1 1 (Anl + 4 ( 1 /0/0) 4 ( 1 /0/0) 7 ( 1 /01 1 ) 7 ( 1 /0/ 1 ) 7 1 1 /0/ 1 1 7 ( 1 /01 1 ) 7 1 1 /0/ 1 ) 9 1 1 /0/ 1 1 - (An) 3 ( 1 /0/0) 3 ( 1 /0/01 6 ( 1 /01 1 ) 6 ( 1 /01 1 ) 6 ( 1 /0/ 1 ) 6 ( 1 /01 1 1 6 1 1 /0/ 1 ) 8 ( 1 /01 1 1 I d 16.An) or ( d 16, PC) 3 ( 1 /0/0) 3 ( 1 /0/0) 6 ( 1 /0/ 1 ) 6 1 1 /01 1 ) 6 ( 1 /0/ 1 ) 6 ( 1 /01 1 1 6 ( 1 /01 1 ) 8 ( 1 /01 1 ) (xxx) .W 3 ( 1 /0/0) 3 ( 1 /0/0) 6 ( 1 /0/ 1 ) 6 1 1 /0/ 1 ) 6 ( 1 /01 1 ) 6 ( 1 /0/ 1 ) 6 ( 1 /0/ 1 ) 8 ( 1 /01 1 ) Ixxx) . L 3 ( 1 /0/01 3 ( 1 /0/01 6 ( 1 10/ 1 ) 6 ( 1 /0/ 1 ) 6 1 1 /01 1 ) 6 1 1 /01 1 1 6 ( 1 /0/ 1 ) 8 ( 1 /0/ 1 ) I d8,An,Xn) o r I d8, PC,Xnl 4 ( 1 /0/0) 4 ( 1 /0/0) 7 ( 1 /01 1 ) 7 1 1 /01 1 ) 7 ( 1 /0/ 1 ) 7 ( 1 /01 1 ) 7 1 1 /01 1 1 9 1 1 /01 1 1 ( d16.An,Xnl o r I d 16, PC,Xnl 4 ( 1 /0/01 4 ( 1 /0/01 7 ( 1 /01 1 1 7 ( 1 /0/ 1 1 7 1 1 /0/ 1 ) 7 1 1 /01 1 1 7 1 1 /01 1 1 9 ( 1 / 01 1 1 I B I 4 ( 1 /0/01 4 ( 1 /0/01 7 1 1 /01 1 1 7 1 1 /01 1 1 7 1 1 /01 1 1 7 ( 1 /0/ 1 ) 7 1 1 /01 1 1 9 1 1 /01 1 1 ( d 16, B I 6 1 1 /0/01 6 ( 1 /0/01 9 ( 1 /0/ 1 1 9 1 1 /011 I 9 1 1 /01 1 1 9 ( 1 /01 1 1 9 ( 1 /01 1 1 1 1 1 1 /0/ 1 ) Id32, B I 1 0 1 1 /0/01 10 1 1 /0/01 1 3 1 1 /0/ 1 1 1 3 1 1 /011 I 13 1 1 /01 1 1 1 3 ( 1 /01 1 1 1 3 1 1 /01 1 1 1 5 1 1 /0/ 1 ) I [ B ] , I I 9 12/0/01 9 (2/0/01 12 (2/01 1 1 1 2 12/0/ 1 1 1 2 12/01 1 1 1 2 (2/01 1 1 1 2 12/0/ 1 ) 1 4 12/01 1 1 ( [ B l , I , d161 1 1 12/0/01 1 1 (2/0/01 14 12/0/ 1 1 14 12/0/ 1 1 1 4 (2/0/ 1 1 1 4 (2/0/ 1 1 1 4 (2/0/ 1 1 16 12/01 1 1 I [ B l , I , d321 1 1 (2/0/01 1 1 12/0/01 14 12/011 I 14 (2/01 1 1 1 4 (2/0/ 1 1 1 4 12/0/ 1 1 1 4 (2/01 1 1 1 6 12/01 1 1 l [ d16, B] ' 1 I 1 1 12/0/01 11 12/0/01 14 (2/01 1 1 1 4 (2/0/ 1 1 1 4 (2/0/ 1 ) 14 12/01 1 1 1 4 (2/01 1 1 1 6 12/0/ 1 1 ( [ d 16, B] , I , d 161 13 (2/0/01 13 (2/0/01 16 (2/01 1 1 1 6 12/0/ 1 ) 1 6 12/01 1 1 1 6 12/01 1 1 1 6 12/01 1 1 1 8 12/01 1 1 ( [ d1 6, Bl , I , d321 13 12/0/01 1 3 (2/0/01 1 6 (2/0/ 1 ) 1 6 (2/01 1 1 1 6 12/0/ 1 1 1 6 (2/01 1 1 1 6 12/0/ 1 1 18 12/0/ 1 1 ( [ d32, B] , I 1 1 5 12/0/01 15 12/0/01 18 12/01 1 1 1 8 (2/0/ 1 1 1 8 12/0/ 1 1 1 8 12/01 1 1 1 8 12/01 1 1 20 12/0/ 1 1 l [ d32, B l , I , d 161 1 7 (2/0/01 1 7 (2/0/01 20 12/01 1 1 20 (2/01 1 1 20 (2/0/ 1 ) 20 12/01 1 1 20 (2/01 1 1 22 12/0/ 1 1 l [ d32, B ] , I , d321 1 7 (2/0/01 1 7 (2/0/01 20 (2/0/ 1 ) 20 (2/0/ 1 ) 20 (2/0/ 1 1 20 12/0/ 1 1 20 (2/0/ 1 1 22 12/0/ 1 1

• BEST CASE (Continued) Source Destination

Address Mode (ds,An,Xnl Id1 6.An,Xnl ( B ) ( d1 6,BI (d32,BI ( [ B] , I I ( [B ] , I ,d161 ( [B ] ' I ,d321

An 4 10/01 1 1 6 (0/01 1 1 5 (0/0/ 1 ) 7 (0/0/ 1 ) 1 1 10/01 1 1 9 1 1 /01 1 1 1 1 1 1 /01 1 1 1 2 1 1 /01 1 1 # < data > . B,W 4 10/01 1 1 6 (0/01 1 1 5 (0/01 1 1 7 10/0/ 1 1 1 1 10/01 1 1 9 ( 1 /01 1 1 1 1 1 1 /01 1 1 1 2 1 1 /01 1 1 # < data > . L 4 10/0/ 1 ) 6 (0/01 1 1 5 (0/01 1 1 7 10/01 1 I 1 1 10/01 1 1 9 1 1 /0/ 1 1 1 1 1 1 /01 1 1 1 2 1 1 /01 1 1 IAnl 8 ( 1 /01 1 1 1 0 1 1 /01 1 1 9 1 1 /0/ 1 1 1 1 1 1 /0/ 1 ) 1 5 ( 1 /01 1 1 1 3 (2/0/ 1 1 1 5 (2/01 1 1 1 6 (2/01 1 1 IAnl + 9 ( 1 /0/ 1 1 1 1 ( 1 /0/ 1 1 1 0 1 1 /01 1 1 1 2 1 1 /01 1 1 1 6 1 1 /01 1 1 1 4 12/01 1 1 1 6 12/01 1 1 1 7 12/0/ 1 1 - IAnl 8 1 1 /0/ 1 1 1 0 ( 1 /0/ 1 1 9 1 1 /0/ 1 1 1 1 1 1 /011 I 15 ( 1 /01 1 1 1 3 12/0/ 1 1 1 5 12/01 1 1 1 6 12/0/ 1 1 I d 16,Anl o r I d 16, PCI 8 ( 1 /01 1 1 1 0 1 1 /0/ 1 1 9 ( 1 /01 1 1 1 1 ( 1 /01 1 1 1 5 1 1 /01 1 1 1 3 12/01 1 1 1 5 12/0/ 1 1 1 6 12/0/ 1 1 Ixxxl .W 8 ( 1 /0/ 1 1 1 0 1 1 /01 1 1 9 ( 1 /01 1 1 1 1 1 1 /01 1 1 1 5 ( 1 /01 1 1 1 3 12/01 1 1 1 5 12/01 1 1 1 6 12/01 1 1 Ixxxi . L 8 ( 1 /01 1 1 1 0 1 1 /01 1 1 9 ( 1 /01 1 1 1 1 ( 1 /01 1 1 1 5 1 1 /0/ 1 1 13 12/01 1 1 1 5 12/01 1 1 1 6 12/01 1 1 I d8,An,Xnl o r I d8, PC,Xnl 9 1 1 /0/ 1 1 1 0 1 1 /0/ 1 1 1 0 1 1 /01 1 1 1 2 1 1 /01 1 1 1 6 1 1 /0/ 1 1 14 (2/0/ 1 1 1 6 12/01 1 I 1 7 12/01 1 I I d16,An,Xnl or I d 16, PC,Xnl 9 ( 1 /0/ 1 ) 1 1 ( 1 /01 1 1 1 0 ( 1 /01 1 1 1 2 ( 1 /01 1 1 1 6 1 1 /01 1 1 14 (2/0/ 1 1 1 6 12/01 1 I 1 7 12/0/ 1 1 I B I 9 1 1 /01 1 1 1 1 1 1 /0/ 1 1 1 0 1 1 /0/ 1 1 1 2 1 1 /0/ 1 1 1 6 1 1 /0/ 1 1 1 4 12/01 1 1 1 6 12/01 1 1 1 7 12/0/ 1 1 I d16,B I 1 1 1 1 /01 1 1 1 3 1 1 /01 1 1 1 2 1 1 /01 1 1 1 4 1 1 /01 1 1 1 8 1 1 /0/ 1 1 1 6 12/01 1 1 1 8 12/01 1 I 19 12/01 1 I I d32,B I 1 5 1 1 /0/ 1 1 1 7 1 1 /0/ 1 1 1 8 1 1 /0/ 1 1 1 8 1 1 /0/ 1 1 22 1 1 /01 1 1 20 12/01 1 1 22 12/01 1 1 23 12/01 1 1 ( [ B ] ' I I 14 12/01 1 1 1 6 12/01 1 1 1 7 (2/01 1 1 1 7 12/01 1 1 2 1 12/0/ 1 1 19 (3/01 1 1 2 1 13/01 1 1 22 13/0/ 1 1 ( [ B ] , I , d1 61 16 12/01 1 1 1 8 (2/0/ 1 ) 1 9 (2/0/ 1 ) 1 9 12/01 1 1 23 12/01 1 I 21 13/01 1 1 23 13/0/ 1 1 24 (3/01 1 1 ( [ B ] , I , d321 16 (2/01 1 1 1 8 12/01 1 1 1 9 12/0/ 1 1 1 9 12/01 1 1 23 12/01 1 1 2 1 13/0/ 1 1 23 (3/01 1 1 24 13/0/ 1 1 l [ d 16, B I . I I 16 12/01 1 1 1 8 12/01 1 1 1 9 (2/0/ 1 1 1 9 12/0/ 1 1 23 (2/0/ 1 ) 2 1 13/01 1 1 23 13/0/ 1 1 24 13/01 1 1 l [ d 16, B ] , I , d 161 18 (2/01 1 I 20 12/011 I 21 12/01 1 I 21 12/0/ 1 ) 25 12/01 1 1 23 13/01 1 1 25 13/0/ 1 1 26 13/0/ 1 1 l [ d 16 , B ] , I , d321 18 12/0/ 1 1 20 12/0/ 1 1 21 12/011 I 21 12/01 1 1 25 12/01 1 1 23 13/01 1 1 25 13/01 1 1 26 13/0/ 1 1 l [ d32 , B ] , 1 1 20 12/01 1 1 22 12/01 1 1 23 12/0/ 1 1 23 12/0/ 1 1 27 12/0/ 1 1 25 13/0/ 1 1 2 7 13/01 1 1 28 13/01 1 1 l [ d32 , B ] , I , d 1 61 22 12/0/ 1 1 24 12/0/ 1 1 25 12/0/ 1 1 25 12/0/ 1 1 29 12/01 1 1 27 13/0/ 1 1 29 (3/01 1 1 30 13/01 1 1 ( [ d32, B l , I , d321 22 12/0/ 1 1 24 12/01 1 1 25 12/0/ 1 1 25 12/0/ 1 1 29 12/0/ 1 1 27 13/0/ 1 1 29 13/01 1 1 30 13/01 1 1

9-1 6

BEST CASE (Concluded) Source Destination

Address Mode ( [d16,Bl, l I ( [d16, Bl, l,d161 ( [d16,Bl,I,d321 ( [d32,Bl , I I ([d32, Bl, l ,d161 ([d32, Bl , l ,d321

Rn 1 1 1 1 /0/ 1 1 1 3 1 1 /0/ 1 1 14 1 1 /0/ 1 1 1 5 1 1 /0/ 1 1 1 7 1 1 /0/ 1 1 1 8 1 1 /0/ 1 1 # < data > . B ,W 11 1 1 /0/ 1 1 1 3 1 1 /0/ 1 1 1 4 1 1 /0/ 1 1 1 5 1 1 /0/ 1 1 1 7 1 1 /0/ 1 1 1 8 1 1 /0/ 1 1 # < data > . L 1 1 1 1 /0/ 1 1 1 3 1 1 /0/ 1 1 14 1 1 /0/ 1 1 1 5 1 1 /0/ 1 1 1 7 1 1 /0/ 1 1 1 8 1 1 /0/ 1 1 IAnl 15 12/0/ 1 1 1 7 12/0/ 1 1 1 8 12/0/ 1 1 19 12/0/ 1 1 2 1 12/0/ 1 1 2 2 12/0/ 1 I IAnl + 16 12/0/ 1 1 1 8 12/0/ 1 1 19 12/0/ 1 1 20 12/0/ 1 1 2 2 12/0/ 1 1 23 12/0/ 1 1

IAnl 15 12/0/ 1 1 1 7 12/0/ 1 1 1 8 12/0/ 1 1 19 12/0/ 1 1 21 12/0/ 1 1 22 12/0/ 1 I Id16,Anl or Id16, PCI 1 5 12/0/ 1 I 1 7 12/0/ 1 1 1 8 12/0/ 1 1 19 12/0/ 1 1 21 12/0/ 1 1 2 2 12/0/ 1 I Ixxxl .W 1 5 12/0/ 1 I 1 7 12/0/ 1 I 18 12/0/ 1 1 19 12/0/ 1 1 21 12/0/ 1 1 2 2 12/0/ 1 I Ixxxl . L 1 5 12/0/ 1 1 1 7 12/0/ 1 1 1 8 12/0/ 1 1 19 12/0/ 1 1 2 1 12/0/ 1 I 22 12/0/ 1 1 I d8,An,Xnl o r Id8, PC ,Xnl 1 6 12/0/ 1 1 1 8 12/0/ 1 1 19 12/0/ 1 1 20 12/0/ 1 1 2 2 12/0/ 1 1 23 12/0/ 1 I Id 16,An,Xnl or I d16, PC,Xnl 1 6 12/0/ 1 1 1 8 12/0/ 1 1 19 12/0/ 1 1 20 12/0/ 1 1 22 12/0/ 1 1 23 12/0/ 1 1 I B I 1 6 12/0/ 1 1 1 8 12/0/ 1 1 19 12/0/ 1 1 20 12/0/ 1 1 2 2 12/0/ 1 1 23 12/0/ 1 1 I d16,B I 1 8 12/0/ 1 1 20 12/0/ 1 1 2 1 12/0/ 1 1 22 12/0/ 1 1 24 12/0/ 1 1 25 12/0/ 1 1 Id32,B I 22 12/0/ 1 1 24 12/0/ 1 1 2 5 12/0/ 1 1 26 12/0/ 1 1 28 12/0/ 1 1 29 12/0/ 1 I I [ B] ' I I 2 1 13/0/ 1 1 23 13/0/ 1 I 24 13/0/ 1 I 25 13/0/ 1 1 27 13/0/ 1 I 28 13/0/ 1 I I [ B] , I , d1 61 23 13/0/ 1 1 25 13/0/ 1 1 26 13/0/ 1 1 2 7 13/0/ 1 1 29 13/0/ 1 1 30 13/0/ 1 1 I [ Bl , I , d321 23 13/0/ 1 I 25 13/0/ 1 1 26 13/0/ 1 I 27 13/0/ 1 1 29 13/0/ 1 1 30 13/0/1 I l [d 16, BL l I 23 13/0/ 1 1 2 5 13/0/1 I 26 13/0/ 1 I 27 13/0/ 1 I 29 13/0/ 1 I 30 13/0/ 1 I l [d1 6, Bl , I ,d161 25 13/0/ 1 1 2 7 13/0/ 1 1 28 13/0/ 1 1 29 13/0/ 1 1 3 1 13/0/ 1 1 32 13/0/ 1 I I [ d1 6,8 l , 1 ,d321 25 13/0/ 1 1 2 7 13/0/ 1 1 28 13/0/ 1 1 29 13/0/ 1 1 31 13/0/ 1 1 32 13/0/ 1 I I [d32, B] . I I 2 7 13/0/ 1 1 29 13/0/ 1 I 30 13/0/ 1 1 3 1 13/0/ 1 1 33 13/0/ 1 1 34 13/0/ 1 1 l [d32,B l , I , d1 61 29 13/0/ 1 1 31 13/0/ 1 1 32 13/0/ 1 I 33 13/0/1 I 35 13/0/ 1 I 36 13/0/ 1 I l [d32, B l , I , d321 29 13/0/ 1 I 31 13/0/ 1 I 32 13/0/ 1 I 33 13/0/ 1 I 35 13/0/ 1 1 36 13/0/ 1 I

CACHE CASE Source

Address Destination

Mode An On IAnl IAnl + - IAn) I�An) ( xxxl .W (xxx) . L

Rn 2 (01010) 2 1010101 4 1010/ 1 I 4 1010/ 1 ) 5 1010/ 1 1 5 1010/ 1 I 4 1010/ 1 I 6 1010/ 1 1 # < data > . B,W 4 1010101 4 (01010) 6 (010/ 1 ) 6 1010/ 1 1 7 1010/ 1 I 7 1010/ 1 ) 6 1010/ 1 1 8 1010/ 1 1 # < data > . L 6 1010101 6 1010/01 8 1010/ 1 1 8 1010/ 1 1 9 1010/ 1 1 9 1010/ 1 1 8 1010/ 1 1 10 1010/ 1 1 IAnl 6 1 1 /0/01 6 1 1 /0101 7 1 1 10/ 1 1 7 1 1 10/ 1 1 7 1 1 /0/ 1 1 7 1 1 /0/ 1 1 7 1 1 /0/ 1 1 9 1 1 /0/ 1 1 IAnl + 6 1 1 / 0/01 6 1 1 /0/01 7 1 1 /0/ 1 1 7 1 1 /0/ 1 1 7 1 1 /0/ 1 1 7 1 1 /0/ 1 1 7 1 1 /0/ 1 1 9 1 1 /0/ 1 1 - IAnl 7 1 1 /0101 7 1 1 /0101 8 1 1 /0/ 1 1 8 1 1 /0/ 1 1 8 1 1 /0/ 1 1 8 1 1 /0/ 1 1 8 1 1 /0/ 1 1 10 1 1 /0/ 1 1 Id16,Anl o r Id1 6, PCI 7 1 1 /0101 7 1 1 /0/01 8 1 1 /0/ 1 1 8 1 1 /0/ 1 1 8 1 1 /0/ 1 1 8 1 1 /0/ 1 1 8 1 1 /0/ 1 1 10 1 1 /0/ 1 1 Ixxx l .W 6 1 1 /0/01 6 1 1 /0/01 7 1 1 /0/ 1 1 7 1 1 10/ 1 1 7 1 1 10/ 1 1 7 1 1 /0/ 1 1 7 1 1 /0/ 1 1 9 1 1 /0/ 1 1 Ixxxl . L 6 1 1 /0101 6 1 1 10/01 7 1 1 10/ 1 1 7 1 1 /0/ 1 1 7 1 1 /0/ 1 1 7 1 1 /0/ 1 1 7 1 1 10/ 1 I 9 1 1 /0/ 1 1 Id8,An, Xnl or I d8, PC,Xnl 9 1 1 /0101 9 1 1 /0101 10 1 1 /0/ 1 1 10 1 1 /0/ 1 1 10 1 1 /0/ 1 1 10 1 1 /0/ 1 1 10 1 1 /0/ 1 1 1 2 1 1 /0/1 I Id16,An,Xnl or Id 16,PC,Xnl 9 1 1 /0101 9 1 1 /0101 10 1 1 /0/ 1 1 10 1 1 /0/ 1 1 10 1 1 /0/ 1 1 10 1 1 /0/ 1 1 10 1 1 /0/ 1 1 1 2 1 1 /0/ 1 1 I B I 9 1 1 /0101 9 1 1 /0101 10 1 1 /0/ 1 1 10 1 1 /0/ 1 1 10 1 1 /0/ 1 1 10 1 1 /0/ 1 1 10 1 1 /0/ 1 1 1 2 1 1 /0/ 1 1 Id16, BI 1 1 1 1 /0101 1 1 1 1 /0101 12 1 1 /0/ 1 1 1 2 1 1 /0/ 1 1 1 2 1 1 /0/ 1 1 1 2 1 1 /0/ 1 1 1 2 1 1 /0/ 1 1 14 1 1 /0/ 1 1 Id32 ,B I 1 5 1 1 / 0/01 15 1 1 /0101 16 1 1 /0/ 1 1 1 6 1 1 /0/ 1 1 1 6 1 1 /0/ 1 1 1 6 1 1 /0/ 1 1 1 6 1 1 /0/ 1 1 1 8 1 1 /0/ 1 1 I [ B] ' I I 14 12/0101 14 12/0101 15 12/0/ 1 I 15 12/0/ 1 1 15 12/0/ 1 1 1 5 12/0/ 1 1 1 5 12/0/ 1 I 17 12/0/ 1 1

I [ B l , I , d 1 61 16 12/0/01 16 12/0/01 17 12/0/ 1 1 1 7 12/0/ 1 1 1 7 12/0/ 1 1 1 7 12/0/ 1 1 1 7 12/0/ 1 I 19 12/0/ 1 1

I [ B l , I , d321 16 12/0101 1 6 12/0/01 17 12/0/ 1 1 1 7 12/0/ 1 1 1 7 12/0/ 1 1 1 7 12/0/ 1 I 17 12/0/ 1 1 1 9 12/0/ 1 1

l [d 16,B ] . 1 I 1 6 12/0/01 1 6 12/0/01 17 12/0/ 1 1 1 7 12/0/ 1 1 1 7 12/0/ 1 1 1 7 12/0/ 1 I 17 12/0/ 1 I 19 12/0/ 1 1

l [d 16, B l , I ,d1 61 18 12/0101 1 8 12/0/01 19 12/0/ 1 1 1 9 12/0/ 1 1 1 9 12/0/ 1 1 19 12/0/ 1 1 19 12/0/ 1 I 21 12/0/ 1 1

l [d 16, BL I , d321 18 12/0101 1 8 12/0/01 19 12/0/ 1 1 1 9 12/0/ 1 1 1 9 12/0/ 1 1 19 12/0/ 1 1 19 12/0/ 1 I 21 12/0/ 1 1

l [d32, BLiI 20 12/0101 20 12/0101 21 12/0/ 1 1 2 1 12/0/ 1 1 2 1 12/0/ 1 1 2 1 12/0/ 1 1 2 1 12/0/ 1 I 23 12/0/ 1 I

l [d32, Bl , I ,d161 22 12/0/01 22 12/0/01 23 12/0/ 1 I 23 12/0/ 1 I 23 12/0/ 1 I 23 12/0/ 1 I 23 12/0/ 1 1 25 12/0/ 1 I

l [d32, B l , I , d321 22 12/0/01 22 12/0101 23 12/0/ 1 1 23 12/0/ 1 1 23 12/0/ 1 I 23 12/0/ 1 I 23 12/0/ 1 I 25 12/0/ 1 1

9-1 7

•

CACHE CASE (Continued) Source Destination

Address Mode Ide,An,Xnl Id16,An,Xnl I B) Id16,BI Id32,BI ( [ BI. l l ( [ B I . I ,d161

Rn l < data > . B ,W # < data > . L IAnl IAnl + - IAn) Id1 6,Anl or Id16,PCI I xxx ) .W I xxxl . L I d8,An,Xnl o r Id8,PC,Xnl I d16,An,Xnl or I d16, PC,Xnl IBI Id 16,B I I d32, BI ( [B l , I l ( [B l , I ,d 161 ( [ B ] ' I ,d32) I Id 16,B] ' 1 I I Id16,B ] , I ,d161 I Id1 6,B ] ' I , d32) I Id32,B ] , I I I Id32, B] ' I ,d 16) I I d32,B ] , I ,d32)

7 1010/ 1 I 7 1010/ 1 1 9 1010/ 1 1 9 1 1 /0/ 1 1 9 1 1 /0/ 1 1

1 0 1 1 /0/ 1 1 10 1 1 /0/ 1 1 9 1 1 /0/ 1 ) 9 1 1 /0/ 1 1

1 2 1 1 /0/ 1 I 12 1 1 /0/ 1 ) 1 2 1 1 /0/ 1 1 14 1 1 /0/ 1 1 1 8 1 1 /0/ 1 1 1 7 12/0/ 1 1 19 12/0/ 1 1 19 (2/0/ 1 ) 19 (2/0/ 1 ) 2 1 12/0/ 1 ) 2 1 (2/0/ 1 ) 23 12/0/ 1 1 25 12/0/ 1 I 25 12/0/ 1 )

9 1010/ 1 1 9 (010/ 1 )

1 1 (010/ 1 ) 1 1 1 1 /0/ 1 ) 1 1 1 1 /0/ 1 1 1 2 ( 1 /0/ 1 ) 1 2 12/0/ 1 1 1 1 1 1 /0/ 1 ) 1 1 1 1 /0/ 1 ) 14 1 1 /0/ 1 1 1 4 ( 1 /0/ 1 ) 1 4 1 1 /0/ 1 1 1 6 1 1 /0/ 1 1 20 1 1 /0/ 1 1 19 12/0/ 1 1 2 1 12/0/ 1 1 2 1 12/0/ 1 1 2 1 12/0/ 1 I 23 12/0/ 1 1 23 (2/0/ 1 ) 25 12/0/ 1 ) 2 7 12/0/ 1 1 27 12/0/ 1 )

CACH E CASE (Concluded)

Source Address

Mode ( [ d16, BI . I I Rn 14 1 1 /0/ 1 1 # < data > .B ,W 1 4 1 1 /0/ 1 ) # < data > . L 16 1 1 /0/ 1 ) IAn) 16 12/0/ 1 ) IAn) + 16 (2/0/ 1 ) - IAn) 1 7 12/0/ 1 ) Id 16,Anl or Id 16,PCI 1 7 12/0/ 1 ) I xxx) .W 16 12/0/ 1 ) Ixxx ) . L 1 6 12/0/ 1 1 Id8,An,Xnl o r Id8,PC,Xn) 19 12/0/ 1 1 I d16,An,Xnl o r I d16,PC,Xnl 19 12/0/ 1 1 I B) 19 12/0/ 1 1 Id 16, B) 21 12/0/ 1 1 Id32, B) 25 12/0/ 1 1 I I B ] ' I I 24 13/0/ 1 ) I [ B] ' I , d 16) 26 13/0/ 1 ) I I B I , I , d32) 26 13/0/ 1 1 I I d16,B ] ' 1 I 26 (3/0/ 1 ) I Id16,B ] ' I ,d 16) 28 13/0/ 1 ) I Id 16,BL I , d32) 28 13/01 1 1 I Id32, B ] , I I 30 13/0/ 1 1 I Id32, BL I ,d 16) 32 (3/0/ 1 ) I Id32, BL I , d321 32 13/0/ 1 1

8 1010/ 1 1 10 1010/ 1 I 14 1010/ 1 1 1 2 1 1 /0/ 1 1 1 4 1 1 /0/ 1 1 8 10/0/ 1 1 10 1010/ 1 I 14 1010/ 1 I 1 2 1 1 /0/ 1 1 14 1 1 /0/ 1 1

10 1010/ 1 1 1 2 10101 1 1 1 6 1010/ 1 1 14 ( 1 /0/ 1 ) 1 6 1 1 /0/ 1 1 10 1 1 /0/ 1 1 1 2 1 1 /0/ 1 1 1 6 1 1 /0/ 1 1 14 12/0/ 1 I 16 12/0/ 1 1 10 1 1 /0/ 1 1 1 2 1 1 /0/ 1 1 1 6 1 1 /0/ 1 1 14 12/0/ 1 ) 16 12/0/ 1 1 1 1 1 1 /0/ 1 1 1 3 1 1 /0/ 1 1 1 7 1 1 /0/ 1 1 1 5 12/0/ 1 1 1 7 12/0/ 1 ) 1 1 1 1 /0/ 1 1 1 3 1 1 /0/ 1 1 1 7 1 1 /0/ 1 1 1 5 12/0/ 1 1 1 7 12/0/ 1 I 10 1 1 /0/ 1 ) 1 2 1 1 /0/ 1 ) 16 1 1 /0/ 1 ) 1 4 (2/0/ 1 ) 16 12/0/ 1 ) 1 0 1 1 /0/ 1 ) 1 2 1 1 /0/ 1 1 16 ( 1 /0/ 1 ) 1 4 12/0/ 1 1 16 12/0/ 1 ) 1 3 1 1 /0/ 1 ) 1 5 1 1 /0/ 1 ) 1 9 1 1 /0/ 1 1 1 7 12/0/ 1 ) 1 9 12/0/ 1 1 1 3 1 1 /0/ 1 ) 1 5 1 1 /0/ 1 1 1 9 1 1 /0/ 1 1 1 7 12/0/ 1 ) 1 9 12/0/ 1 1 1 3 1 1 /0/ 1 1 1 5 1 1 /0/ 1 1 1 9 1 1 /0/ 1 1 1 7 12/0/ 1 1 19 12/0/ 1 1 1 5 1 1 /0/ 1 1 1 7 1 1 /0/ 1 1 2 1 1 1 /0/ 1 1 19 12/0/ 1 ) 2 1 12/0/ 1 ) 1 9 1 1 /0/ 1 1 2 1 1 1 /0/ 1 1 25 1 1 /0/ 1 ) 23 12/0/ 1 I 25 12/0/ 1 ) 1 8 12/0/ 1 1 20 12/0/1 I 24 12/0/ 1 1 22 13/0/ 1 1 24 13/0/ 1 ) 20 12/0/ 1 ) 2 2 12/0/ 1 1 26 12/0/ 1 I 24 13/0/ 1 1 26 13/0/ 1 1 20 12/0/ 1 ) 22 12/0/ 1 ) 26 12/0/ 1 I 24 13/0/ 1 ) 26 13/0/ 1 ) 20 12/0/ 1 1 22 12/0/ 1 1 26 12/0/ 1 I 24 13/0/ 1 ) 26 13/0/ 1 I 22 12/0/ 1 1 24 12/0/ 1 1 28 12/0/ 1 1 26 13/0/ 1 ) 28 13/0/ 1 1 22 12/0/ 1 ) 24 12/0/ 1 ) 28 12/0/ 1 I 26 13/0/ 1 I 28 13/0/ 1 ) 24 12/0/1 I 26 12/0/ 1 1 30 12/0/ 1 I 28 13/0/ 1 I 30 13/0/ 1 1 26 12/0/ 1 1 28 12/0/ 1 ) 32 12/0/ 1 ) 30 13/0/ 1 1 32 13/01 1 1 26 12/0/ 1 ) 28 12/0/ 1 1 32 12/0/ 1 1 30 13/01 1 1 32 13/0/ 1 )

Destination

([ d16,BI . I ,d1 61 l [d16,BI . I ,d321 ( [ d32,BI . I I I Id32, Bl. I.d161 16 1 1 /0/ 1 1 1 7 1 1 /0/ 1 1 1 8 1 1 /0/ 1 1 20 1 1 /0/ 1 1 16 1 1 10/ 1 1 1 7 1 1 /0/ 1 1 1 8 1 1 /0/ 1 1 20 1 1 /0/ 1 1 1 8 1 1 /0/ 1 ) 19 1 1 /0/ 1 ) 20 1 1 /0/ 1 ) 2 2 1 1 /0/ 1 1 1 8 (2/0/ 1 ) 19 12/0/ 1 ) 20 12/0/ 1 1 2 2 12/0/ 1 ) 1 8 12/0/ 1 1 19 (2/0/ 1 ) 20 12/0/ 1 ) 22 12/0/ 1 I 19 (2/0/ 1 ) 20 12/0/ 1 ) 2 1 12/0/ 1 1 23 12/0/ 1 ) 1 9 (2/0/ 1 ) 20 12/0/ 1 ) 2 1 12/0/ 1 ) 23 12/0/ 1 ) 1 8 (2/0/ 1 ) 19 12/0/ 1 1 20 12/0/ 1 ) 22 12/0/ 1 ) 1 8 12/0/ 1 ) 1 9 12/0/ 1 1 20 12/0/ 1 ) 22 12/0/ 1 ) 21 12/0/ 1 1 2 2 12/0/ 1 1 23 12/0/ 1 1 25 12/0/ 1 1 2 1 12/0/ 1 1 22 12/0/ 1 1 23 12/0/ 1 ) 25 12/0/ 1 1 2 1 12/0/ 1 ) 22 12/0/ 1 ) 23 12/0/ 1 1 25 12/0/ 1 ) 23 12/0/ 1 1 24 12/0/ 1 ) 25 12/0/ 1 ) 27 12/0/ 1 I 27 12/0/ 1 1 28 12/0/ 1 ) 29 12/0/ 1 ) 3 1 12/0/ 1 ) 26 13/0/ 1 ) 27 13/0/ 1 1 28 13/0/ 1 1 30 (3/0/ 1 ) 28 (3/0/ 1 ) 29 13/0/ 1 I 30 13/0/ 1 1 32 13/0/ 1 ) 28 13/0/ 1 1 29 13/0/ 1 ) 30 13/0/ 1 ) 32 13/0/ 1 1 28 13/0/ 1 ) 29 13/0/ 1 ) 30 13/0/ 1 1 32 13/0/ 1 ) 30 13/0/ 1 ) 3 1 13/0/ 1 ) 32 13/0/ 1 ) 34 13/0/ 1 ) 30 13/0/ 1 ) 3 1 13/0/ 1 ) 32 13/0/ 1 ) 34 13/0/ 1 ) 32 13/0/ 1 1 33 13/0/ 1 ) 34 13/0/ 1 1 36 13/0/ 1 ) 34 13/0/ 1 ) 35 13/0/ 1 ) 36 13/01 1 1 38 13/0/ 1 ) 34 13/0/ 1 I 35 (3/0/ 1 ) 36 13/0/ 1 1 38 13/0/ 1 )

9-1 8

( [ Bl , I , d321 1 5 1 1 /0/ 1 ) 1 5 1 1 /0/ 1 1 1 7 1 1 /0/ 1 1 1 7 12/0/ 1 1 1 7 12/0/ 1 1 1 8 12/0/ 1 ) 18 12/0/ 1 I 17 12/0/ 1 ) 1 7 12/0/ 1 1 20 12/0/ 1 I 20 12/0/ 1 ) 20 12/0/ 1 ) 22 12/0/ 1 1 26 12/0/ 1 ) 25 13/0/ 1 ) 2 7 13/0/ 1 ) 27 13/0/ 1 ) 27 13/0/ 1 1 29 (3/0/ 1 ) 29 13/0/ 1 1 3 1 13/0/ 1 ) 33 13/0/ 1 ) 33 13/0/01

( [ d32, BI . I ,d321 21 1 1 /0/ 1 1 2 1 1 1 /0/ 1 1 23 1 1 /0/ 1 ) 23 12/0/ 1 1 23 12/0/ 1 ) 24 12/0/ 1 ) 24 12/0/ 1 ) 23 12/0/ 1 ) 23 12/0/ 1 1 26 12/0/ 1 1 26 12/0/ 1 ) 26 (2/0/ 1 ) 28 (2/0/ 1 ) 32 12/0/ 1 1 3 1 (3/0/ 1 ) 33 13/0/ 1 1 33 13/0/ 1 ) 33 13/0/ 1 1 35 13/0/ 1 ) 35 13/0/ 1 ) 37 13/0/ 1 1 39 13/0/ 1 1 39 13/0/ 1 )

WORST CASE Source Destination

Address Mode An Dn (An) (An) + - IAn) Idls.An) (xxx).W I xxxl. L

A n 3 101 1 /01 3 101 1 /01 5 101 1 /01 5 (01 1 1 1 ) 6 (01 1 1 1 ) 7 (01 1 1 1 ) 7 (01 1 1 1 ) 9 (0/2/ 1 )

l < data > . B .W 3 (01 1 10) 3 101 1 /01 5 (01 1 10) 8 (01 1 1 1 ) 6 (01 1 1 1 ) 7 (01 1 1 1 ) 7 (0/ 1 1 1 ) 9 (012/ 1 )

l < data > . L 5 101 1 /01 5 (01 1 1 0) 7 (010/ 1 ) 7 (01 1 1 1 ) 8 (01 1 1 1 ) 9 (01 1 1 1 ) 9 (01 1 1 1 ) 1 1 (0/21 1 )

IAn) 7 ( 1 1 1 10) 7 ( 1 1 1 10) 9 ( 1 1 1 1 1 ) 9 ( 1 1 1 1 1 ) 9 ( 1 1 1 1 1 ) 1 1 ( 1 / 1 1 1 ) 1 1 ( 1 1 1 1 1 ) 1 3 ( 1 121 1 )

IAn) + 7 1 1 / 1 /0) 7 1 1 1 1 /01 9 1 1 / 1 / 1 1 9 ( 1 / 1 / 1 ) 9 1 1 1 1 1 1 1 1 1 ( 1 / 1 / 1 ) 1 1 ( 1 / 1 / 1 ) 1 3 ( 1 /2/ 1 )

- IAn) 8 1 1 / 1 101 8 1 1 / 1 /01 10 ( 1 1 1 1 1 ) 1 0 ( 1 1 1 / 1 ) 1 0 ( 1 / 1 1 1 ) 1 2 ( 1 / 1 1 1 ) 1 2 ( 1 1 1 / 1 ) 1 4 ( 1 12/ 1 )

Id 1 6.Anl o r I d1 6. PCI 9 1 1 / 2/01 9 1 1 / 2/01 1 1 ( 1 /21 1 ) 1 1 1 1 /21 1 1 1 1 ( 1 / 2/ 1 ) 1 3 ( 1 / 2 1 1 ) 13 ( 1 /2/ 1 ) 1 5 ( 1 / 3/ 1 )

Ixxxl . W 8 1 1 / 2/01 8 1 1 /2/01 10 ( 1 /2/ 1 ) 1 0 ( 1 12 1 1 ) 1 0 ( 1 12/ 1 ) 1 2 ( 1 /2/ 1 ) 1 2 ( 1 /2/ 1 ) 1 4 1 1 / 31 1 1

Ixxx) . L 10 1 1 /2/01 10 1 1 / 2/0) 1 2 1 1 / 21 1 ) 1 2 1 1 /21 1 1 1 2 1 1 / 21 1 ) 1 4 1 1 /21 1 1 1 4 1 1 /2/ 1 1 1 6 1 1 / 3/ 1 )

Id8.An.Xn) o r Id8. PC.Xnl 1 1 1 1 /2/01 1 1 1 1 /2/01 13 ( 1 /2/ 1 ) 1 3 ( 1 /2/ 1 ) 1 3 ( 1 /21 1 ) 15 ( 1 / 2/ 1 ) 15 ( 1 /21 1 ) 1 7 1 1 /31 1 1

Id1 6.An.Xnl o r Id1 6. PC.Xnl 12 1 1 / 2/01 1 2 1 1 /2/0) 14 1 1 /21 1 1 1 4 1 1 / 2/ 1 1 1 4 1 1 /2/ 1 ) 1 6 1 1 /2/ 1 ) 1 6 1 1 /2/ 1 ) 18 1 1 /31 1 1

I B) 12 1 1 / 2/01 1 2 1 1 12101 14 1 1 /21 1 1 1 4 1 1 / 21 1 1 1 4 ( 1 /21 1 ) 1 6 ( 1 12 1 1 ) 16 1 1 /2/ 1 ) 1 8 ( 1 / 3/ 1 )

I d1 6. B) 1 5 1 1 / 2/01 15 1 1 12101 1 7 1 1 /21 1 1 1 7 ( 1 / 21 1 ) 1 7 ( 1 / 31 1 ) 1 9 1 1 /2/ 1 ) 1 9 1 1 /2/ 1 ) 2 1 ( 1 /31 1 )

I d32. B) 19 ( 1 /3/0) 1 9 1 1 /3/01 21 1 1 /31 1 ) 2 1 1 1 / 3/ 1 ) 2 1 ( 1 / 3/ 1 ) 23 ( 1 / 31 1 ) 23 ( 1 / 31 1 ) 25dl l / 4/ 1 )

I I B ] ' I I 1 6 12/2101 1 6 (2/2/0) 1 8 (2/2/ 1 ) 1 8 12/2/ 1 1 1 8 12/21 1 ) 20 (2/21 1 ) 20 (2/21 1 ) 22d(2/3/ 1 )

I [ B LI.d1 61 19 12/2/01 1 9 12/2/01 1 2 1 12/21 1 ) 21 12/21 1 1 2 1 12/2/ 1 ) 23 12/2/ 1 1 23 (2/21 1 ) 25 12/3/ 1 1

I I B L I . d321 20 12/3/01 20 12/3/01 22 12/31 1 1 22 12/3/ 1 1 22 12/3/ 1 ) 24 12/3/ 1 ) 24 (2/31 1 ) 26 (2/41 1 )

I I d 1 6. B ] ' 1 I 19 12/2/01 1 9 12/2/01 21 12/21 1 1 2 1 12/21 1 1 2 1 12/21 1 1 23 12/2/ 1 ) 23 12/21 1 1 25 12/31 1 1

I Id 1 6. B ] , I . d1 61 22 12/3/01 22 12/3/01 24 12/3/ 1 1 24 12/31 1 1 24 12/31 1 1 26 12/31 1 1 26 12/31 1 1 28 12/4/ 1 1

I Id 16. B l , l .d321 23 12/3/01 23 12/3/01 25 12/3/ 1 1 25 12/31 1 1 25 12/31 1 1 27 12/31 1 1 27 12/31 1 1 29 (2/41 1 )

I Id32. B ] , I I 23 12/3/01 23 12/3/01 25 12/3/ 1 1 25 12/31 1 1 25 12/31 1 1 27 12/31 1 1 27 12/31 1 1 29 12/41 1 1

I I d32. Bl . I . d1 61 25 12/3/01 25 12/3/01 27 12/31 1 1 27 12/31 1 1 27 12/31 1 1 29 12/3/ 1 ) 29 12/31 1 1 3 1 (2/41 1 )

l [d32.BLI.d32) 27 12/4/0) 27 12/4/01 29 (2/41 1 ) 29 12/4/ 1 1 29 12/4/ 1 ) 3 1 (2/41 1 ) 3 1 12/4/ 1 ) 33 12/51 1 1

WORST CASE (Continued) • Source Destination Address

Mode (da.An.Xn) [dls.An•Xn) ( B) IdlS.B) (d32.B) ( [ B ] ' I I ( [ B ] , I .d1 6) ( [ BI , I .d32)

A n 9 (01 1 1 1 ) 1 2 1012/ 1 ) 1 0 (01 1 1 1 ) 1 4 1012/ 1 ) 1 9 10/21 1 1 1 4 ( 1 1 1 1 1 ) 1 7 1 1 /21 1 ) 20 ( 1 /21 1 )

# < data> . B. W 9 101 1 / 1 ) 1 2 10/21 1 ) 1 0 101 1 1 1 1 1 4 1012/ 1 ) 19 10/21 1 ) 1 4 ( 1 / 1 1 1 ) 1 7 ( 1 1 21 1 ) 20 ( 1 1 21 1 )

# < data > . L 1 1 101 1 1 1 1 1 4 10/21 1 ) 1 2 10/ 1 / 1 1 1 6 10/2/ 1 ) 2 1 10/21 1 ) 16 1 1 / 1 1 1 ) 1 9 1 1 /21 1 ) 22 1 1 /21 1 )

IAn) 11 ( 1 1 1 1 1 ) 1 4 ( 1 /21 1 ) 1 2 1 1 1 1 / 1 ) 1 6 1 1 /21 1 ) 21 ( 1 /21 1 ) 1 2 (2/ 1 / 1 ) 1 9 (2/2/ 1 ) 22 (2/21 1 )

IAn) + 1 1 ( 1 1 1 1 1 ) 1 4 ( 1 12/ 1 ) 1 2 1 1 1 1 / 1 ) 1 6 1 1 /2/ 1 ) 2 1 1 1 /21 1 1 1 2 (21 1 1 1 ) 1 9 12/2/ 1 ) 22 (2/21 1 )

- I Anl 1 2 ( 1 1 1 1 1 ) 1 5 1 1 /21 1 1 1 3 ( 1 1 1 1 1 ) 1 7 1 1 /2/ 1 ) 2 2 1 1 / 21 1 1 1 3 (21 1 1 1 ) 20 12121 1 1 23 12/21 1 )

I d I 6.An) o r Id 1 6. PC) 1 3 ( 1 / 21 1 ) 1 6 (2/31 1 ) 1 4 ( 1 /21 1 ) 1 8 1 1 /31 1 ) 23 1 1 /3/ 1 1 1 4 12/21 1 1 2 1 12/31 1 1 24 (2/31 1 )

I xxx) .W 1 2 1 1 / 21 1 ) 1 5 ( 1 / 31 1 ) 1 3 ( 1 / 21 1 ) 1 7 1 1 /3/ 1 ) 22 1 1 /31 1 1 1 3 (2/21 1 ) 20 12/3/ 1 ) 23 (2/3/ 1 )

Ixxx) . L 1 4 1 1 /21 1 ) 1 7 1 1 /3/ 1 ) 1 5 1 1 /2/ 1 ) 1 9 1 1 / 3/ 1 ) 24 1 1 /31 1 1 1 5 (2121 1 ) 22 12/31 1 ) 25 (2/31 1 )

I d8.An.Xn) or Id8. PC.Xn) 15 1 1 /21 1 ) 1 8 1 1 /31 1 1 1 6 1 1 /21 1 ) 20 1 1 / 31 1 ) 25 ( 1 /3/ 1 ) 1 6 (2/21 1 ) 23 (2/3/ 1 ) 26 (2/31 1 )

Id I 6.An.Xn) or I d I 6. PC.Xn) 16 ( 1 /21 1 ) 1 9 ( 1 / 31 1 ) 1 7 ( 1 /21 1 ) 2 1 1 1 / 31 1 ) 26 ( 1 /3/ 1 ) 1 7 12/21 1 ) 24 (2/3/ 1 ) 27 (2/31 1 )

I B ) 16 ( 1 /21 1 ) 1 9 ( 1 /31 1 ) 1 7 1 1 /21 1 1 2 1 ( 1 /31 1 ) 26 ( 1 /31 1 ) 1 7 (2/21 1 ) 24 (2/31 1 ) 27 (2/31 1 )

Id I 6. B ) 19 ( 1 /2/ 1 ) 22 ( 1 /31 1 ) 20 ( 1 /21 1 ) 24 ( 1 /31 1 ) 29 ( 1 /31 1 ) 20 (2121 1 ) 27 (2131 1 ) 30 (2/31 1 )

Id32. B I 2 3 ( 1 /31 1 ) 26 1 1 /4/ 1 ) 24 ( 1 /31 1 ) 28 ( 1 /41 1 ) 33 ( 1 /4/ 1 ) 24 (2/31 1 ) 3 1 (2/41 1 ) 34 (2/41 1 )

I I B L I ) 2 0 (2/21 1 ) 23 (2/3/ 1 ) 2 1 (2/2/ 1 ) 25 (2/3/ 1 ) 30 (2/3/ 1 ) 2 1 (3/21 1 ) 28 (3/31 1 ) 3 1 (3/3/ 1 )

II BL I . d I 6) 23 (2/21 1 ) 26 (2/3/ 1 ) 24 12/2/ 1 ) 28 (2/31 1 ) 33 12/31 1 ) 24 (3/21 1 ) 3 1 (3/31 1 ) 34 (3/31 1 )

I I B L I . d32) 24 (2/3/ 1 ) 27 (2/41 1 ) 25 12/31 1 ) 29 (2/41 1 ) 34 12/4/ 1 ) 25 (3/3/ 1 ) 32 (3/41 1 ) 35 (3/4/ 1 )

( [ d I 6. B ] , 1 I 23 12/2/ 1 ) 26 (2/3/ 1 ) 24 (2/21 1 ) 28 12/31 1 ) 33 (2/31 1 ) 24 (3/21 1 ) 3 1 (3/3/ 1 ) 34 (3/31 1 )

l [ dI 6. B LI . d I 6) 26 (2/31 1 ) 29 (2/4/ 1 ) 27 (2/31 1 ) 31 (2/41 1 ) 36 (2/4/ 1 ) 27 (3/3/ 1 ) 34 (3/4/ 1 ) 37 (3/41 1 )

I IdI 6. B ] ' I .d32) 27 (2/31 1 ) 30 (2/4/ 1 ) 28 12/3/ 1 1 32 (2/41 1 ) 3 7 (2/41 1 ) 28 13/31 1 1 35 (3/41 1 ) 38 (3/41 1 )

( [ d32. B ] , I ) 2 7 (2/3/ 1 ) 30 12/41 1 1 28 (2/31 1 ) 32 12/41 1 1 37 (2/4 1 1 ) 28 (3/31 1 ) 35 (3/41 1 ) 38 (3/41 1 )

I I d32. 8 1 , 1 . d I 6) 29 12/31 1 ) 32 12/41 1 1 30 12/31 1 ) 34 (2/41 1 ) 39 12/4/ 1 ) 30 (3/31 1 ) 37 (3/41 1 ) 40 (3/41 1 )

I Id32. B I . I . d32) 31 (2/41 1 ) 34 (2/5/ 1 ) 32 (2/41 1 ) 36 (2/51 1 ) 4 1 (2/5/ 1 ) 32 (3/41 1 ) 39 (3/51 1 ) 42 (3/51 1 )

9-1 9

WORST CASE (Concluded) Source Destination

Address Mode I Id16,BI , I ) I Id16,BI , I ,d1 61 I Id1 6, BI , I ,d321 l [ d32,BI , I ) I Id32,BI , I ,d 161 I Id32,BI , I,d321

Rn 1 7 1 1 / 21 1 1 20 1 1 / 2/ 1 1 23 1 1 / 31 1 1 22 1 1 /21 1 1 25 1 1 /31 1 1 27 1 1 /31 1 1 # < data > . B ,W 17 1 1 / 2/ 1 1 20 1 1 / 2/ 1 1 23 1 1 /3 / 1 1 2 2 1 1 /21 1 1 25 1 1 /31 1 1 27 1 1 /3/ 1 1 # < data > . L 19 1 1 / 2/ 1 1 22 1 1 / 2/ 1 1 25 1 1 /31 1 1 24 1 1 /21 1 1 27 1 1 /3/ 1 1 29 1 1 /3/ 1 1 IAnl 1 9 12/21 1 1 22 12/21 1 1 25 12/31 1 1 24 12/21 1 1 27 12/31 1 1 29 12/31 1 1 IAnl + 19 12/2/ 1 1 22 12/2/ 1 1 25 12/3/ 1 1 24 12/21 1 1 27 12/3/ 1 1 29 12/3/ 1 1 - IAnl 20 12/2/ 1 1 23 12/2/ 1 1 26 12/31 1 1 25 12/21 1 1 28 12/31 1 1 30 12/31 1 1 I dl6.Anl o r I d1 6, PCI 21 12/31 1 1 24 12/31 1 1 2 7 12/41 1 1 26 12/3/ 1 1 29 12/41 1 1 3 1 12/41 1 1 Ixxxl . W 20 12/31 1 1 23 12/3/ 1 1 26 12/4/ 1 1 27 12/3/ 1 1 28 12/4/ 1 1 30 12/41 1 1 Ixxxl . L 22 12/31 1 1 25 12/31 1 1 28 12/41 1 1 29 12/31 1 1 30 12/41 1 1 32 12/4/ 1 1 I d8,An,Xnl or I d8, PC,Xnl 23 12/3/ 1 1 26 12/3/ 1 1 29 12/41 1 1 30 12/31 1 1 3 1 12/4/ 1 1 33 12/4/ 1 1 I d16.An,Xnl or Id16, PC,Xnl 24 12/31 1 1 27 12/31 1 1 30 12/41 1 1 3 1 12/3/ 1 1 32 12/4/ 1 1 34 12/4/ 1 1 I B I 24 12/31 1 1 27 12/31 1 1 30 12/4 / 1 1 3 1 12/31 1 1 32 12/4/ 1 1 34 12/4/ 1 1 I d I6, BI 27 12/31 1 1 30 12/31 1 1 33 12/4/ 1 1 34 12/31 1 1 35 12/4/ 1 1 37 12/4 / 1 1 I d32, BI 31 12/41 1 1 34 12/41 1 1 37 12/51 1 1 38 12/41 1 1 39 12/5/ 1 1 4 1 12/5/ 1 1 I [ B I , I I 28 13/31 1 1 3 1 13/3/ 1 1 34 13/4/ 1 1 35 13/31 1 1 36 13/41 1 1 38 13/4/ 1 1 I [ B l , I , d I61 31 13/3/ 1 1 34 13/31 1 1 37 13/4/ 1 1 38 13/3/ 1 1 39 13/41 1 1 4 1 13/4/ 1 1 I [ B I , I , d321 32 13/41 1 1 35 13/41 1 1 38 13/51 1 1 39 13/41 1 1 40 13/5/ 1 1 42 13/51 1 1 l [ d 16, Bl , I l 31 13/3/ 1 1 34 13/3/ 1 1 37 13/41 1 1 38 13/31 1 1 39 13/41 1 1 4 1 13/41 1 1 l [d I 6, Bl , I , d I61 34 13/4/ 1 1 37 13/41 1 1 40 13/51 1 1 41 13/4/ 1 1 42 13/51 1 1 44 13/5/ 1 1 l [ d 16, Bl , I , d321 35 13/4/ 1 1 38 13/41 1 1 4 1 13/51 1 1 42 13/41 1 1 43 13/5/ 1 1 45 13/51 1 1

l [ d32, BI , I I 35 13/4/ 1 1 38 13/41 1 1 41 13/51 1 1 42 13/41 1 1 43 13/51 1 1 45 13/51 1 1

I I d32, Bl , I , d I61 37 13/4/ 1 1 40 13/4/ 1 1 43 13/51 1 1 44 13/4/ 1 1 45 13/51 1 1 47 13/5/ 1 1 ( [ d32, B I , I , d321 39 13/5/ 1 1 42 13/51 1 1 45 13/6/ 1 1 46 13/51 1 1 47 13/6/ 1 1 49 13/61 1 1

•

9-20

9.2.7 Special Purpose MOVE Instruction

The specia l pu rpose MOVE t im ing table i nd icates the number of c lock periods needed for the processor to fetch, calcu late, and perform the special pu rpose MOVE operation on the control reg isters or specif ied effective address. The total number of c lock cyc les is outside the parentheses, the number of read, prefetch, and write cyc les are g iven i ns ide the parentheses as (r/p/w). They are inc luded in the total c lock cyc le number.

Instruction EXG RY, Rx MOVEC Cr ,Rn MOVEC Rn ,Cr MOVE PSW, Rn

# MOVE PSW, Mem . MOVE EA, CCR . MOVE EA. S R # . MOVEM EA, R L # . MOVEM R L,EA

MOVEPW Dn,ld1 6,Anl MOVEP .L Dn, ld 16.Anl MOVEP.W Id 16. Anl ,Dn MOVEP . L Id 16. Anl ,Dn

#+ MOVES EA, Rn # . MOVES Rn,EA

MOVE USP SWAP RX ,Ry

n = number of registers to transfer RL = Register List

Add Fetch Effective Address time Add Calculate Effective Address time

#+ Add Calculate Immediate Address time

Best Case Cache Case Worst Case

o 1010/01 2 1010/01 3 10/ 1 /01 3 1010/01 6 1010101 7 10/1 101 9 10/0/01 12 10/0/01 1 3 10/ 1 101 1 10/0/01 4 10/0/01 5 10/ 1 101 5 10/0/ 1 1 5 10/0/1 I 7 10/ 1 / 1 1 4 10/0/01 4 10/0/01 5 10/ 1 10 8 10/0/01 8 10/0/01 1 1 1012101

8 + 4n In/O/Oi 8 + 4n In/O/OI 9 + 4n In/ 1 /OI 4 + 3n 10/01 nl 4 + 3n 10/0/ni 5+ 3n 1O/ 1 / nl

8 10/0/21 1 1 10/0/21 1 1 10/ 1 12 1 14 10/0/41 17 10/0/41 17 10/ 1 141 10 12/0/01 12 12/0/01 12 12/ 1 101 1 6 14/0/01 1 8 14/0/01 1 8 14/ 1 101 7 1 1 /0/01 7 1 1 /0/01 8 1 1 / 1 101 5 10/0/ 1 I 5 10/0/ 1 1 7 10/ 1 / 1 1 a 10/0/01 2 10/0/01 3 10/ 1 101 1 10/0/01 4 10/0/01 4 10/ 1 101

9-21

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•

9.2.8 Arithmetic/Logical Operations

The arithmetic/log ical operations t iming table ind icates the number of c lock periods needed for the processor to perform the specif ied arithmet ic/logical operat ion us ing the specif ied addressing mode. I t a lso i ncludes, in worst case, the amount of time needed to prefetch the i nstruct ion. Footnotes specify when to add either fetch address or fetch i mmediate effective address t ime. This sum g ives the total effective execution t ime for the operat ion us ing the spec if ied addressing mode. The total number of c lock cycles is outside the parentheses, the number of read, prefetch, and write cyc les are g iven i nside the parentheses as (r/p/w). They are i ncluded in the total clock cyc le number.

Instruction * ADD EA,Dn * ADD EA,An * ADD Dn, EA * AND EA, Dn * AND Dn ,EA * EOR Dn,Dn * EOR Dn, Mem * OR EA,Dn * OR Dn,EA * SUB EA,Dn * SUB EA,An * SUB Dn,EA * CMP EA,Dn * CMP EA,An * * CMP2 EA, Rn * MUL.W EA, Dn * * MUL.L EA,Dn * DIVU.W EA, Dn * * DIVU . L EA,Dn * DIVS .W EA,Dn * * DIVS . L EA, Dn

* Add Fetch Effective Address time * * Add Fetch Immediate Address time

Best Case

o (0/0/01 o (0/0/01 3 (0/0/ 1 1 o (0/0/01 3 (0/0/ 1 1 o (0/0/01 3 (0/0/ 1 1 o (0/0/01 3 (0/0/ 1 1 o (0/0/01 o (0/0/01 3 (0/0/ 1 1 o (0/0/01 1 (0/0/01

16 ( 1 / 0/01 25 (0/0/01 41 (0/0/01 42 (0/0/01 76 (0/0/01 54 (0/0/01 88 (0/0/01

9.2.9 Immediate Arithmetic/Logical Operations

Cache Case

2 (0/0/01 2 10/0/01 4 (0/0/ 1 1 2 (0/0/01 4 (0/0/ 1 1 2 (0/0/01 4 (0/0/ 1 1 2 (0/0/01 4 (0/0/ 1 1 2 (0/0/01 2 (0/0/01 4 (0/0/ 1 1 2 (0/0/01 4 (0/0/01

18 ( 1 /0/01 27 (0/0/01 43 (0/0/01 44 (0/0/01 78 (0/0/01 56 (0/0/01 90 (0/0/01

Worst Case

3 (0/ 1 /01 3 (0/ 1 /01 6 (0/ 1 / 1 1 3 (0/ 1 /01 6 (0/ 1 / 1 1 3 (0/ 1 /01 6 (0/ 1 / 1 1 3 (0/ 1 /01 6 (0/ 1 / 1 1 3 (0/ 1 /01 3 (0/ 1 /01 6 (0/ 1 / 1 1 3 (0/ 1 /01 4 (0/ 1 /01

18 ( 1 / 1 /01 28 (0/ 1 /01 44 (0/ 1 /01 44 (0/ 1 /01 78 (0/ 1 /01 56 (0/ 1 /01 90 (0/ 1 /01

The i mmediate arithmetic/log ical operat ions t iming table i nd icates the number of clock periods needed for the processor to fetch the source i mmediate data val ue, and perform the specif ied arithmet icl logical operat ion us ing the specif ied dest i nation addressing mode. Footnotes i ndicate when to add appropriate fetch effective or fetch immediate effective address t imes. This computation w i l l g ive the total execution t ime needed to perform the appropriate i mmediate arithmet icllogical operat ion. The total number of clock cycles is outside the parentheses, the number of read, prefetch, and write cyc les are g iven i nside the parentheses as (r/p/w). They are i nc l uded in the total clock cyc le number.

9-22

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.

. .

. .

. -

. -

. -

- -

- -

. -

. -

_ .

. .

Instruction

MOVEO # < data > , On ADDO # < data > , Rn ADDO # < data > ,Mem SUBO # < data> ,Rn SUBO # < data > ,Mem ADDI # < data > ,Dn ADDI # < data > ,Mem ANDI # < data > ,On ANDI # < data > ,Mem EORI # < data > ,On EORI # < data > , Mem OR I # < data > ,Dn OR I # < data > , Mem SUB I # < data > , On SUB I # < data > , Mem CMPI # < data > , EA

Add Fetch Effective Address time Add Fetch Immediate Address time

Best Case

o 1010/01 o 1010101 3 1010/ 1 1 o 1010/01 3 10101 1 1 o 1010101 3 1010/ 1 1 o 1010101 3 10101 1 1 o 1010101 3 10101 1 1 o 1010101 3 10101 1 1 o 10/0101 3 10/01 1 1 o 10/0101

9.2.1 0 Binary Coded Decimal Operations

Cache Case Worst Case

2 1010101 3 10/ 1 /01 2 1010/01 3 10/ 1 /01 4 1010/ 1 1 6 10/ 1 1 1 1 2 1010101 3 101 1 /01 4 1010/ 1 1 6 101 1 1 1 1 2 1010/01 3 101 1 101 4 10101 1 1 6 101 1 1 1 1 2 1010101 3 101 1 /01 4 1010/ 1 1 6 101 1 / 1 1 2 1010101 3 101 1 /01 4 10101 1 1 6 101 1 1 1 1 2 1010101 3 101 1 /01 4 10101 1 1 6 101 1 / 1 1 2 1010/01 3 10/ 1 /01 4 1010/ 1 1 6 10/ 1 / 1 1 2 1010/01 3 101 1 /01

The bi nary coded decimal operat ions table ind icates the number of c lock periods needed for the processor to perform the spec ified operation us ing the g iven addressing modes, with complete execut ion t imes g iven. No addit ional tables are needed to calcu late total effective execution time for these i nstructions. The total nu mber of c lock cyc les is outside the parentheses, the n umber of read, prefetch, and write cyc les are g iven i nside the parentheses as (r/p/w). They are inc luded in the total c lock cyc le number.

Instruction Best Case Cache Case Worst Case

ABCD Dn,Dn 4 10/0101 4 1010/01 5 10/ 1 /01 ABeD - IAnl, - IAnl 14 12/01 1 1 1 6 12/0/ 1 1 1 7 12/ 1 1 1 1 SBCD Dn,Dn 4 1010/01 4 1010/01 5 10/ 1 /01 SBCD - IAnl , - IAnl 14 12/0/ 1 1 1 6 12/01 1 1 1 7 121 1 1 1 1 ADDX Dn,Dn 2 10/0101 2 1010/01 3 10/ 1 /01 ADDX - IAnl, - IAnl 10 12/0/ 1 1 1 2 12/0/ 1 1 1 3 121 1 1 1 1 SUBX Dn ,Dn 2 10/0101 2 10/0101 3 101 1 101 SUBX - IAnl, - IAnl 10 12/01 1 1 1 2 12/0/ 1 1 1 3 121 1 1 1 1 CMPM IAnl + , IAnl + 8 12/0101 9 12/0/01 10 1211 101 PACK Dn,Dn,# < data > 3 10/0101 6 1010/01 7 101 1 101 PACK - IAnl, - IAnl , #< data> 1 1 1 1 /01 1 1 1 3 1 1 /01 1 1 1 3 1 1 / 1 1 1 I UNPK Dn,Dn,# < data > 5 1010/01 8 10/0101 9 101 1 /01 UNPK - IAnl , - IAnl ,# < data > 1 1 1 1 /011 I 13 1 1 /01 1 1 1 3 1 1 1 1 1 1 1

9-23

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9.2.1 1 Single Operand Instructions

The s ing le operand i nstructions table ind icates the number of c lock periods needed for the processor to perform the specif ied operat ion on the g iven addressing mode. Footnotes ind icate when i t is necessary to add another table entry to calcu late the total effect ive execution t ime for the i nstruction. The total number of clock cycles is outside the parentheses, the n umber of read, prefetch, and write cycles are g iven i nside the parentheses as (r/p/w). They are i ncl uded in the total clock cycle number.

Instruction

CLR On # CLR Mem

NEG On · NEG Mem

NEGX On · NEGX Mem

NOT On · NOT Mem

EXT On NBCO On Sec On

# Scc Mem TAS On

# TAS Mem · TST EA

• Add Fetch Effective Address time Add Calculate Effective Address time

9_2.1 2 Shift/Rotate Instructions

Best Case Cache Case Worst Case

a 10/0/01 2 10/0/01 3 10/ 1 /01 3 10/01 1 1 4 10/0/ 1 1 6 101 1 1 1 1 a 10/0/01 2 10/0/01 3 101 1 /01 3 10/0/ 1 1 4 10/01 1 1 6 101 1 1 1 1 a 10/0/01 2 10/0/01 3 10/ 1 /01 3 10/01 1 1 4 10/01 1 1 6 10/ 1 1 1 1 a 10/0/01 2 10/0/01 3 101 1 /01 3 10/01 1 1 4 10/01 1 1 6 101 1 1 1 1 1 10/0/01 4 10/0/01 4 10/ 1 /01 6 10/0/01 6 10/0/01 6 1011 /01 1 10/0/01 4 10/0/01 4 101 1 /01 6 10/01 1 1 6 10/0/ 1 1 6 101 1 1 1 1 1 10/0/01 4 10/0/01 4 1011 /01

12 1 1 /01 1 1 1 2 1 1 /01 1 1 1 3 1 1 / 1 / 1 1 a 10/0/01 2 10/0/01 3 101 1 /01

The sh ift/rotate i nstruct ions table ind icates the n umber of c lock periods needed for the processor to perform the specif ied operat ion on the g iven addressing mode. Footnotes i nd icate when it is necessary to add another table entry to calculate the total effective execution t ime for the i nstruction. The nu mber of bits sh ifted does not affect execut ion t i me. The total number of clock cyc les is outside the parentheses, the number of read, prefetch, and write cycles are g iven i nside the parentheses as (r/p/w). They are i ncluded i n the total c lock cyc le number.

9-24

I nstruction lS l On I Staticl lSR On IS tatiel lSl On ! Dynamiel lSR On I Dynamic)

* lSl Mem by 1 * lSR Mem by 1

ASl On ASR On

* ASl Mem by 1 * ASR Mem by 1

ROl On ROR On

* ROl Mem by 1 * ROR Mem by 1

ROXl On ROXR On

* ROXd Mem by 1

Add Fetch Effective Address time d Is d i rection of shiftl rotate; l or R

9.2.1 3 Bit Manipulation Instructions

Best Case

1 (01010) 1 (01010) 3 (01010) 3 (01010) 5 (010/ 1 ) 5 10/0/ 1 ) 5 (01010) 3 (01010) 6 (010/ 1 ) 5 1010/ 1 ) 5 1010/01 5 (01010) 7 10/0/ 1 ) 7 1010/ 1 1 9 10/0/01 9 1010/01 5 1010/ 1 )

Cache Case

4 (01010) 4 (01010) 6 (01010) 6 (01010) 5 1010/ 1 ) 5 1010/ 1 ) 8 (01010) 6 1010/01 6 1010/ 1 ) 5 1010/ 1 1 8 1010/01 8 1010/01 7 10/0/ 1 ) 7 1010/ 1 )

1 2 (01010) 12 1010/01 5 1010/ 1 )

Worst Case

4 10/ 1 101 4 10/ 1 101 6 10/1 10) 6 10/1 101 6 10/ 1 / 1 ) 6 10/ 1 / 1 1 8 10/1 10 6 10/ 1 101 7 10/ 1 / 1 ) 6 10/ 1 1 1 1 8 (0/ 1 /0) 8 10/ 1 10) 7 10/ 1 / 1 ) 7 10/ 1 / 1 )

1 2 10/ 1 101 12 10/ 1 101 6 10/ 1 / 1 )

The b i t manipu lation i nstructions table ind icates the number o f c lock periods needed for the processor to perform the specif ied bit operation on the g iven addressing mode. Foot· notes ind icate when it is necessary to add another table entry to calcu late the total effect ive execut ion t ime for the instruction. The total number of c lock cyc les is outside the parentheses, the number of read, prefetch, and write cyc les are g iven i nside the parentheses as (r/p/w). They are i nc l uded in the total c lock cycle number.

* *

*

* *

*

* *

*

* *

*

Instruction

BTST # < data > ,On BTST On,On BTST # < data > , Mem BTST On, Mem BCHG # < data> ,On BCHG On,On BCHG # < data > , Mem BCHG On, Mem BClR # < data > ,On BClR On,On BClR # < data > , Mem BClR On, Mem BSET # < data > ,On B SET On,On BSET # < data > , Mem BSET On, Mem

Add Fetch Effective Address time Add Fetch Immediate Address time

Best Case

1 1010/01 1 (01010) 4 (01010) 4 1010/01 1 (01010) 1 (01010) 4 1010/ 1 1 4 1010/ 1 ) 1 (01010) 1 (01010) 4 1010/ 1 ) 4 1010/ 1 1 1 1010/01 1 1010/01 4 1010/ 1 ) 4 1010/ 1 )

9-25


4 (01010) 5 10/ 1 10) 4 (01010) 5 10/ 1 101 4 1010/01 5 10/ 1 10) 4 101010) 5 (01 1 /0) 4 (01010) 5 10/ 1 10) 4 101010) 5 10/ 1 10) 4 1010/ 1 ) 5 10/ 1 / 1 ) 4 1010/ 1 ) 5 10/ 1 / 1 ) 4 1010/01 5 10/ 1 10) 4 1010/01 5 10/ 1 10) 4 1010/ 1 ) 5 10/ 1 / 1 ) 4 (010/ 1 ) 5 10/ 1 / 1 1 4 (01010) 5 10/ 1 101 4 1010/01 5 (0/ 1 /0) 4 1010/ 1 1 5 10/ 1 / 1 1 4 1010/ 1 ) 5 10/ 1 / 1 )

•

•

9.2. 14 Bit Field Manipulation Instructions

The bit f ield manipu lation i nstruct ions table i nd icates the number of c lock periods need· ed for the processor to perform the specif ied bit f ield operat ion using the g iven add ress· ing mode. Footnotes i nd icate when it is necessary to add another table entry to calcu late the total effective execution t ime for the i nstruction. The total nu mber of c lock cyc les is outside the parentheses, the number of read, prefetch, and write cyc les are g iven i nside the parentheses as (r/p/w). They are i ncluded in the total c lock cycle number.

I nstruction Best Case Cache Case Worst Case BFTST Dn 3 1010101 6 1010101 7 10/ 1 /01

#. B FTST Mem 1 < 5 bytesl 1 1 1 1 /0101 11 1 1 /0101 1 2 1 1 / 1 /01 # . BFTST Mem 15 bytesl 15 12/0/01 15 12/0101 16 12/ 1 /01

B FCHG Dn 9 1010101 12 1010101 12 10/ 1 /01 # . B FCHG Mem 1 < 5 bytesl 16 1 1 /0/ 1 1 1 6 1 1 /0/ 1 1 1 6 1 1 I 1 1 1 1 h BFCHG Mem 15 bytesl 24 12/0/21 24 12/0/21 24 12/0/21

BFCLR Dn 9 1010101 12 10/0/01 12 10/ 1 101 # . BFCLR Mem 1 < 5 bytesl 16 1 1 /0/ 1 1 1 6 1 1 /0/ 1 1 1 6 1 1 / 1 / 1 1 # . BFCLR Mem 15 bytesl 24 12/0/21 24 12/0/21 24 12/0/21

BFSET Dn 9 1010101 12 1010101 12 10/ 1 101 # . BFSET Mem 1 < 5 bytesl 16 1 1 /0/ 1 1 1 6 1 1 /0/ 1 1 16 1 1 / 1 / 1 1 # . BFSET Mem 15 bytesl 24 12/0/21 24 12/0/21 24 12/0/21

BFEXTS Dn 5 1010/01 8 1010101 8 10/ 1 /01 BFEXTS Mem 1 < 5 Bytesl 13 1 1 /0101 1 3 1 1 /0/01 13 11 I 1 101 BFEXTS MEM 15 Bytesl 18 12/0101 1 8 12/0101 1 8 12/ 1 /01 B FEXTU Dn 5 1010101 8 1010/01 8 10/ 1 /01 B FEXTU Mem 1 < 5 Bytesl 13 1 1 /0101 13 1 1 /0101 13 1 1 / 1 /01 B FEXTU Mem 15 Bytesl 18 12/0/01 1 8 12/0101 18 12/ 1 /01 BF INS Dn 7 1010101 10 1010101 10 10/ 1 /01 BF INS Mem 1 < 5 Bytesl 14 1 1 /0/ 1 1 1 4 1 1 /0/ 1 1 1 5 1 1 / 1 / 1 1 BF INS Mem 15 Bytesl 20 12/0/21 20 12/0/21 21 12/1 121 B FFFO Dn 1 5 1010/01 18 1010101 18 10/ 1 /01 BFFFO Mem 1 < 5 Bytesl 24 1 1 10101 24 1 1 /0/01 24 1 1 / 1 /01 BFFFO Mem 1 5 Bytesl 32 12/0101 32 (2/0/01 32 12/1 /01

h Add Calculate Immediate Address time NOTE: A bit field of 32 bits may span 5 bytes that requires two operand cycles to access, or may span 4 bytes that requires only one

operand cycle to access.

9.2. 15 Conditional Branch Instructions

The cond it ional branch i nstructions table i nd icates the number of c lock periods needed for the processor to perform the specif ied branch on the g iven branch s ize, with complete execution t imes g iven. No add it ional tables are needed to calcu late total effective execu· t ion t ime for these i nstruct ions. The total number of c lock cyc les is outside the paren· theses, the number of read, prefetch, and write cyc les are g iven i nside the parentheses as (r/p/w). They are inc luded in the total c lock cycle number.

I nstruction Best Case Cache Case Worst Case

Bcc (takenl 3 10/0/01 6 10/0/01 9 (0/2/01 Bcc. B Inot takenl 1 (0/0/01 4 10/0/01 5 (0/ 1 101 Bcc.W (not takenl 3 10/0/01 6 (010/01 7 10/1 101 Bcc .L I not takenl 3 10/0/01 6 10/0/01 9 10/2/01 DBcc Icc= false, count not expiredl 3 10/0/01 6 10/0/01 9 1012101 D8cc (cc = false, count expiredl 7 (0/0/01 10 (0/0/01 10 10/3/01 DBcc ( cc = truel 3 (0/0/01 6 10/0/01 7 (0/ 1 101

9·26

9.2.1 6 Control Instructions

The control i nstructions table i nd icates the number of c lock periods needed for the pro· cessor to perform the specified operation. Footnotes specify when i t is necessary to add an entry from another table to calcu late the total effective execution t ime for the g iven in· struction. The total number of c lock cycles is outside the parentheses, the number of read, prefetch, and write cycles are g iven ins ide the parentheses as (r/p/w). They are i nc luded i n the total c lock cyc le nu mber.

Instruction ANDI to S A EOAI t o S A O A I t o SA ANDI to CCA EOAI to CCA OA I to CCA BSA

* * CALLM Itype 01 * * CALLM Itype 1 1 - no stack copy -* * CALLM I type 1 1 - no stack copy -* * CALLM Itype 1 1 - stack copy -, . CAS Isuccessful comparel

CAS lunsuccessful comparel CAS2 Isuccessful comparel CAS2 l unsuccessful comparel

* CHK * * CHK2 EA,An % J M P % J S A # LEA

L lNK .w LlNK . L NOP

# PEA RTD ATM Itype 01 ATM Itype 1 1 ATA ATS UNLK

n number of operand transfers required Add Fetch Effective Address time Add Calculate Effective Address time

% Add J ump Effective Address time Add Fetch Immediate Address time

,. Add Calculate Immediate Address time

Best Case Cache Case Worst Case 9 10/0/01 12 10/0/01 15 10/2/01 9 10/0/01 12 10/0/01 15 10/2/01 9 10/0/01 12 10/0/01 15 10/2/01 9 10/0/01 12 10/0/01 15 10/2/01 9 10/0/01 12 10/0/01 15 10/2/01 9 10/0101 12 1010/01 15 10/2/01 5 10/01 1 I 7 10/01 1 I 13 10/21 1 I

28 12/0/61 30 12/0/61 36 12/2/61 48 15/0/81 50 15/0/81 56 15/2/81 55 16/0/81 57 16/0/81 64 16/2/81

63 + 6n 1 7 + n/0/8+ nl 65 + 6n 17 + n/0/8+ nl 7 1 + 6n 17 + n/2/8+ nl 15 1 1 /01 1 1 1 5 1 1 /01 1 1 1 6 1 1 1 1 1 1 1 1 2 1 1 /0101 12 1 1 10/01 13 1 1 1 1 101 23 12/0/21 25 12/0/21 28 12/2/21 1 9 12/0/01 22 12/0/01 25 12/2/01 8 10/0/01 8 10/0/01 8 101 1 /01

16 12/0/01 1 8 12/0/01 18 12/ 1 /01 1 10/0/01 4 10/0/01 7 10/2/01 3 10/0/ 1 1 5 10/0/ 1 1 1 1 10/2/ 1 1 2 10/0/01 2 10/0/01 3 101 1 101 3 10/0/ 1 1 5 10/011 I 7 101 1 / 1 1 4 10/01 1 1 6 10/0/ 1 1 10 10/211 I 2 10/0/01 2 10/0/01 3 101 1 101 3 1010/ 1 1 5 10/01 1 I 6 101 1 / 1 1 9 1 1 10/01 10 1 1 /0/01 12 1 1 /2/01

18 14/0/01 19 14/0/01 22 14/2/01 31 16/0/ 1 I 32 16/01 1 I 35 16/21 1 I 13 12/0/01 14 12/0/01 15 12/2/01 9 1 1 /0/01 10 1 1 /0/01 12 1 1 / 2/01 5 1 1 /0/01 6 1 1 /0/01 7 1 1 1 1 101

9-27

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9.2.1 7 Exception Related Instructions

The except ion related i nstruct ions table i nd icates the nu mber of clock periods needed for the processor to perform the specif ied exception related act ion. Footnotes spec ify when it is necessary to add the entry from another table to calcu late the total effective execution t ime for the g iven i nstruction. The total number of c lock cyc les is outside the parentheses, the number of read, prefetch, and write cyc les are g iven ins ide the parentheses as (r/p/w). They are inc luded in the total clock cyc le number.

I nstruction Best Case Cache Case Worst Case BKPT 9 1 1 /010) 10 1 1 /010) 10 1 1 /0/01 Interrupt I I-stack) 26 12/0/4) 26 12/0/4) 33 12/2/4) Interrupt 1 M-stack) 41 12/0/8) 41 12/0/8) 48 12/2/8) R ES ET Instruction 518 101010) 518 101010) 519 10/ 1 /01 STOP 8 101010) 8 1010/01 8 1010/01 Trace 25 1 1 /0/5) 25 1 1 /0/5) 32 1 1 12/5) TRAP #n 20 1 1 10/4) 20 1 1 /0/4) 27 1 1 12/4) Illegal Instruction 20 1 1 10/4) 20 1 1 /0/4) 27 1 1 /2/4) A-Line Trap 20 1 1 / 0/4) 20 1 1 /0/4) 27 1 1 /2/4) F-Line Trap 20 1 1 /0/4) 20 1 1 /0/4) 27 1 1 /2/4) Privilege Violation 20 1 1 /0/4) 20 1 1 /0/4) 27 1 1 /2/4) TRAPcc Itrap) 23 1 1 /0/5) 25 1 1 /0/5) 32 1 1 / 2/5) TRAPcc Ino trap) 1 101010) 4 101010) 5 101 1 /01 TRAPcc.W Itrap) 23 1 1 /0/5) 25 1 1 /0/5) 33 1 1 /3/5) TRAPcc.W Ino trap) 3 101010) 6 1010/01 7 101 1 /0) TRAPcc.L Itrap) 23 1 1 /0/5) 25 1 1 /0/5) 33 1 1 /3/5) TRAPcc.L I no trap) 5 101010) 8 101010) 10 10/2/0) TRAPV Itrap) 23 1 1 /0/5) 25 1 1 /0/5) 32 1 1 /2/5) TRAPV Ino trap) 1 101010) 4 1010/01 5 10/ 1 /0)

9.2. 1 8 Save and Restore Operations

The save and restore operat ions table i nd icates the number of c lock periods needed for the processor to perform the spec if ied state save, or return from except ion, with comp lete execut ion t imes and stack length g iven. No add it ional tables are needed to calcu late total effective execut ion t ime for these operat ions. The total number of clock cyc les is outside the parentheses, the number of read, prefetch, and write cycles are g iven i nside the parentheses as (r/p/w). They are i nc luded in the tota l c lock cyc le number.

Operation

Bus Cycle Fault I Short) Bus Cycle Fault I Long) RTE INormal! RTE IS ix-Word) RTE !Throwaway) * R TE l Coprocessor) RTE I Short Fault! RTE I Long Fault)

* Add the time for RTE on second stack frame.

Best Case

42 1 1 /0/ 10) 79 1 1 /0/24) 20 14/010) 20 14/010) 1 5 141010) 31 17/0/01 42 ( 1 0/010) 91 124/010)

9-28


43 1 1 /01 10) 50 1 1 /21 101 79 1 1 /0/24) 86 1 1 /2/24) 21 14/010) 24 14/2/01 21 14/0/01 24 1412/0) 16 14/010) 39 14/0/01 32 (7/010) 33 (71 1 10) 43 1 1 0/0/01 45 1 1 012/01 92 124/010) 94 124/2/0)

SECTION 1 0 ELECTRICAL SPECI FICATIONS

Th is section conta ins electrical specif ications and associated t im ing i nformat ion for the MC68020.

10.1 MAXIM U M RATINGS

Rating Symbol Value Unit Supply Voltage VCC - 0.3 to + 7.0 V Input Voltage Vin - 0.3 to + 7 .0 V Operating Temperature Range TA o to 70 °c Storage Temperature Range Tstg - 55 to 1 50 ° c

1 0.2 TH ERMAL CHARACTERISTICS - PGA PACKAG E

Characteristic Symbol Value Rating

Thermal Resistance - Ceramic Junction to Ambient 8JA 30* °C/W Junction to Case 8JC 15*

* Estimated

1 0.3 POWER CONSIDERATIONS

This device contains protective circuitry against damage due to high static voltages or electrical fields; however. i t is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliabil ity of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g . . either GND or VCCI .

The average ch ip-ju nction temperature, TJ , in °C can be obta i ned from: T J = TA + (PO-OJA) ( 1 )

Where: T A = Ambient Temperature, °C OJA = Package Thermal ReSistance, J unction-to-Ambient, °C/W Po = PINT + PlIO PI NT = I CC x VCC, Watts - Chip I nternal Power PlIO = Power Dissipat ion on I nput and Output Pins - User Determi ned

For most appl ications PI/O < PINT and can be neg lected.

An approximate re lationsh ip between Po and T J (if P lIO is neglected) is: PO = K + �J + 2noq �

Solvi ng equations 1 and 2 for K g ives: K = PO-(TA + 273°q + OJA- P02 (3)

Where K is a constant pertai n i ng to the part icu lar part. K can be determi ned from eq uat ion 3 by measur ing Po (at equ i l i br ium) for a known T A. Us ing this value of K the values of Po and T J can be obtained by solving equations ( 1 ) and (2) iterat ively for any value of T A·

1 0-1

•

II

The total thermal res istance of a package (OJA) can be separated i nto two components, OJC and OCA, representing the barrier to heat f low from the sem iconductor ju nction to the package (case) surface (OJC) and from the case to the outside ambient (OCA). These terms are related by the equation:

OJA = OJC + OCA (4)

OJC is device related and cannot be inf luenced by the user. However, OCA is user dependent and can be min im ized by such thermal management techn iques as heat s inks, ambient a i r coo l ing and thermal convention. Thus, good thermal management on the part of the user can s ign if icantly reduce OCA so that OJA approx imately equals OJC. Subst i tut ion of OJC for OJA in equat ion (1) w i l l resu l t in a lower semiconductor j unct ion temperature.

Values for thermal res istance presented in th is data sheet, un less est imated, were derived using the procedure described in Motorola Rel iabi l ity Report 7843, "Thermal Resistance Measurement Method for MC68XX M icrocomponent Devices," and are provided for design purposes on ly. Thermal measurements are complex and dependent on procedure and setup. User derived values for thermal res istance may differ.

10.4 DC ELECTRICAL CHARACTERISTICS (VCC = 5.0 Vdc ± 5% ; VSS = O Vdc, TA = O to 70 · C; see Figures 1 0-1 , 1 0-2, and 1 0-3)

Characteristic Symbol Min Max Unit

Input High Voltage VIH 2 .0 VCC V I nput low Voltage Vi l - 0.5 0 .8 V Input leakage Current BER�R . BGACK. ClK. IPLO-ru.

VS S :s Vin:S VCC AVEC. COIS. OSACKO. OSACKl l in - 2 .5 2 .5 p.A HALT, RES ET - 20 20 p.A

Hi-l 10ff-Statel leakage AO-A31 , AS , OBEN, OS, 00-031 , Current @ 2.4 V /0.5 V FCO-FC2, R /iii, RMC, S ilO-Sill ITS I - 20 20 p.A

Output High Voltage AO-A31 , AS, im, 00-031 , OBEN, [)S, ECS, 10H = - 400 p.A R/iN, I PENO, OCS, RMC, SilO-S ill , FCO-FC2 VOH 2.4 - V

Output low Voltage 10l = 3. 2 mA AO-A31 , FCO-FC2, SilO-S ill , BG , 00-031 - 0.5 V 10l = 5.3 mA AS, OS , R/W, RMC, OBEN, IPEND VOL - 0.5 V IOl = 2 .0 mA ECS, OCS - 0.5 V 10l = 10 .7 mA HALf, R ESET - 0.5 V

Power Dissipation IT A = O°CI Po - 1 .75 W Capacitance Isee Note 1 1

Vin = O V, TA = 25°C, f = l MHz Cin - 20.0 pF NOTE:

1 . Capacitance is periodically sampled rather than 100% tested.

+ 5 V + 5 V

420 420

I l 30 PF I l 30 PF

Figure 1 0·1 . RESET Test Load Figure 1 0-2. HALT Test Load

1 0-2

Cl = 50 pF for ECS and OCS

+ 5 V

A *

MMD7000 or Equivalent

Cl = 1 30 pF for All Other ( I ncludes all Parasiticsl Al = 6.0 kO

* A = 1 .22 kO for AO-A31 , DO-D31 , BG , FCO-FC2, S ilO-Sill A = 2 kO for ECS, OCS A = 740 0 for AS, 55, A/W, AMC, DBEN, IPEND

Figure 1 0·3. Test Loads

10.5 AC ELECTRICAL SPECIFICATIONS - CLOCK I NPUT (See Figure 1 0-4) MC68020AC12 MC68020AC16

Num Characteristic Symbol Min Max Min Max

Frequency of Operation f 8 12 .5 8 1 6.7 1 Cycle Time tcvc 80 1 25 60 1 25

2, 3 Clock Pu lse Width tCl, tCH 32 1 25 24 95 4, 5 Aise and Fall Times tCr, tCf - 5 - 5

NOTE

Unit

MHz ns ns ns

Timing measurements are referenced to and from a low voltage of 0.8 volt and a high voltage of 2.0 volts, unless otherwise noted. The voltage swing through this range should start outside, and pass through, the range such that the rise or fall will be linear between 0.8 volt and 2.0 volts.

Figure 1 0·4. Clock Input Timing Diagram

1 0-3

II

10.6 AC ELECTRICAL SPECI FICATIONS - READ AND WRITE CYCLES (VCC = 5.0 Vdc ± 5 % ; G N D = 0 Vdc; TA = 0 to 70° C; see Figures 1 0-5, 1 0-6, and 1 0-7)

MC68020RC12 MC68020RC16

Num Characteristic Symbol Min Max Min Max Unit

6 Clock High to Address/ FC/ Size/RMC Valid tC HAV 0 40 0 30 ns 6A Clock High to ECS , OCS Asserted tC HEV 0 30 0 20 ns 7 Clock High to Address, Data, FC, RMC, S ize

H igh Impedance tCHAZx 0 80 0 60 ns 8 Clock High to Address/ FC/ Size/RMC Invalid tC HAZn 0 - 0 - ns 9 Clock low to AS , DS Asserted tC lSA 3 40 3 30 ns

9Al AS to DS Assertion l Read) I S kew) tSTSA - 20 20 - 1 5 15 ns 10 ECS Width Asserted tECSA 25 - 20 - ns

lOA OCS Width Asserted tOCSA 25 - 20 - ns 1 16 Address/ FC/ S ize/ RMC Valid to AS (and DS Asserted

Read) tAVSA 20 - 1 5 - ns 1 2 Clock low t o A S , DS Negated tcuN 0 40 0 30 ns

12A Clock low 1 0 ECS/ OCS Negated !CliN 0 40 0 30 ns 13 AS , DS Negated to Address, FC, Size Invalid tSNAI 20 - 1 5 - ns 14 AS land DS Read) Width Asserted tSWA 120 - 100 - ns

14A OS Width Asserted Write tSWAW 50 - 40 - ns 15 AS , DS Width Negated tS N 50 - 40 - ns 16 Clock H igh to AS, OS, R/W, DBEN High Impedance tcsz - 80 - 60 ns 1 76 AS, DS Negated 10 R/W High tSNRN 20 - 1 5 - ns 18 Clock High to R/W High tCHRH 0 40 0 30 ns 20 Clock High to R/W low tCH Rl 0 40 0 30 ns 2 16 R/W High to AS Asserted tRAAA 20 - 1 5 - ns 226 R/W low 10 DS Asserted IWrite) tRASA 90 - 70 - ns 23 Clock High to Data Out Valid l.GJ:!QQ - 40 - 30 ns 256 DS Negated to Data Out Invalid tSND I 20 - 15 - ns 266 Data Out Valid to DS Asserted (Write) tDVSA 20 - 15 - ns 27 Data- In Valid to Clock low (Data Setup) tD ICl 10 - 5 - ns

27A late BERR/HAl T Asserted to Clock low Setup Time tBElCl 25 - 20 - ns

• 28 AS, DS Negated to DSACKx, BERR , HALT, AVEC Negated tSNDN 0 1 1 0 0 80 ns

29 DS Negated to Data- In Invalid l Data-ln Hold Time) tSND I 0 - 0 - ns 29A DS Negated to Data- In ( H igh Impedance) tSND I - 80 - 60 ns 31 2 DSACKx Asserted to Data-In Valid tDADI - 60 - 50 ns

3 1A3 DSACKx Asserted to DSACKx Valid tDADV - 20 - 1 5 ns I DSACK Asserted Skew)

32 R ES ET Input Transition Time tH Rrf - 2.5 - 2.5 Clk Per 33 Clock low to BG Asserted tClBA 0 40 0 30 ns 34 Clock low to BG Negated tClBN 0 40 0 30 ns 35 BR Asserted to BG Asserted (RMC Not Asserted) tBRAGA 1 .5 3 .5 1 .5 3.5 Clk Per 37 BGACK Asserted to BG Negated tGAGN 1 .5 3 .5 1 .5 3.5 Clk Per 39 BG Width Negated tG_N 120 - 90 - ns

39A BG Width Asserted tGA 120 - 90 - ns 40 Clock High to DBEN Asserted ( Read) tCHDAR 0 40 0 30 ns

1 0-4

1 0.6 AC ELECTRICAL SPECI FICATIONS - READ AND WRITE CYCLES (Continued) (VCC = 5.0 Vdc ± 5 % ; G N D = 0 Vdc; TA = 0 to 70°C; see Figures 1 0-5, 1 0-6, and 1 0-7)

MC68020RC12 MC68020RC16

Num Characteristic Symbol Min Max Min Max Un it 41 Clock Low to DB EN Negated IReadl tCLDNR 0 40 0 30 ns 42 Clock Low to DB EN Asserted (Writel tCLDAW 0 40 0 30 ns 43 Clock High to DB EN Negated (Writel tCHDNW 0 40 0 30 ns 440 R/W Low to DBEN Asserted (Writel tRADA 20 - 1 5 - ns 455 DBEN Width Asserted Read tDA 80 - 60 - ns

Write 1 60 - 1 20 - ns 46 R/W Width Asserted (Write or Readl tRWA 180 - 150 - ns

47a Asynchronous Input Setup Time tAIST 10 - 5 - ns 47b Asynchronous Input Hold Time tA IHT 20 - 15 - ns 48'l DSACKx Asserted to BERR . HALT Asserted tDABA - 35 - 30 ns 53 Data Out Hold from Clock High tDOCH 0 - 0 - ns 55 R/W Asserted to Data Bus Impedance Change tRADC 40 - 40 - ns 56 R ES ET Pulse Width (Reset Instructionl tHRPW 512 - 512 - Clks 57 BERR Negated to HALT Negated IRerunl tBNHN 0 - 0 - ns

NOTES: 1 . This number can be reduced to 5 nanoseconds if strobes have equal loads. 2. I f the asynchronous setup time (#471 requi rements are satisfied, the DSACKx low to data setup time 1#3 1 1 and DSACKx low to

BERA low setup time (#481 can be ignored. The data must only satisfy the data-in to clock low setup time (#271 for the following clock cycle, BERR must only satisfy the late BERR low to clock low setup time (#27AI for the following clock�

3. This parameter specifies the maximum a l lowable skew between DSACKO to DSACK 1 asserted or DSACK 1 to DSACKO asserted, specification #47 must be met by DSACKO or DSACK 1

4. In the absence of DSACi(X, BERR is an asynchronous input using the asynchronous input setup time (#471. 5. i5'i3'EN may stay asserted on consecutive write cycles. 6. Actual value depends on the clock input waveform.

Timing Diagrams (F igures 1 0-5, 1 0-6, and 1 0-7) are located on foldout pages at the end of th is document.

1 0-5

•

•

1 0.7 AC ELECTRICAL CHARACTERISTICS - TYPICAL CAPACITANCE DERATING CURVES

Figures 1 0·8 through 1 0· 13 provide the capacitance derat ing cu rves for the MC68020. These graphs may not be l i near outside of range shown. Capac itance i nc ludes stray capacitance.

45

40

35

30

v; 25 c -

20

15

10

5

o 20 40 60 60 100 1 20 140 160 180 200 220 240 260

Cin IpFI

Figure 1 0·8. Address Capacitance Derating Curve

tCLSL 30 ns tCLSH 30 ns

o 20 40 60 60 100 1 20 140 160 180 200 220 240 260 Cin IpFI

Figure 1 0·9. DS, AS, IPEN D, and BG Capacitance Derating Curve

1 0-6

v; c:

45

40

35

30

25

20

15

10

5

45

40

35

30

25

20

1 5

10

5

tCLDNR. tCHDNW 30 ns tCHDAR. tCLDAW 30 ns

o 20 40 60 80 100 120 140 160 180 200 220 240 260

Cin (pFI

Figure 1 0·10. DBEN Capacitance Derating Curve

_ .... .... -.... -....... ...... .... ....

........

-- - - tCHEV 20 ns -- tCLEN 30 ns

o 20 40 60 80 100 120 140 1 60 180 200 220 240

Cin (pFI

Figure 1 0·1 1 . ECS and OCS Capacitance Derating Curve

1 0·7

-

•

45

40

35

30

Vi 25

.:: -

20

1 5

10 tCHRL 30 ns tCHRH 30 ns

5

o 20 40 60 80 100 120 140 160 180 200 220 240 260

Cin IpFI

Figure 1 0·12. RIW, FC, SIZO·SIZ1 , and RMC Capacitance Derating Curve

45

40

35

30 25 Vi

c

20

1 5

10

5

tCHDH 30 ns tCHDL 30 ns

o 20 40 60 80 100 1 20 140 160 180 200 220 240 260

Cin IpFI

Figure 1 0·1 3. Data Capacitance Derating Curve

1 0·8

SECTION 1 1 ORDERING I N FO RMATION AND M ECHANICAL DATA

This section contains the p in assignments and package d imensions of the MC68020. I n add it ion, detai led i nformat ion is provided t o be used a s a gu ide when ordering.

1 1 .1 STANDARD MC68020 O RDERING I N FORMATION

Package Type

Pin G rid Array RC Suffix

Frequency (MHz)

1 2.5 1 6.7

Temperature

O°C to 70 ° C O°C t o 70 ° C

1 1 -1

Order Number

MC68020RC 1 2 MC68020RC16

•

1 1 .2 PACKAGE DIM ENSIONS AND PIN ASSIGNMENT

M C68020 R C S uffix Package

Prel im ina ry

Mechanical

Detail

Top 1 View A

� II--. -- B ------+I

1 1 -2

DIM

A

B C

DO

G K V

MILLIMETERS INCHES

MIN MAX MIN MAX

34. 1 8 34.90 1 .345 1 .375

34. 1 8 34.90 1 .345 1 .375

2.67 3. 1 7 . 1 00 . 1 50

.46 .5 1 .0 1 7 . 0 1 9

2 . 5 4 BSe . 1 00 BSe

4.32 4.82 . 1 70 . 1 90

1 .74 2.2B .065 I .095

Pin Number Function Pin Number Function Pin Number Function

A1 BGACK 01 VCC K 1 GNO A2 A1 02 VCC K2 HALT A3 A31 03 VCC K3 GNO A4 A28 04-01 1 - K 1 2 0 1 A5 A26 012 A4 K 1 3 DO A6 A23 013 A3 A7 A22 L 1 AS A8 A19 L2 R/IN A9 VCC E1 FCO L3 030 AlO GNO E2 RMC L4 027 Al l A14 E3 VCC L5 023 A12 A l l E 12 A2 L6 019 A13 A8 E 13 OCS L7 GNO

L8 015 L9 0 1 1 L10 07

B 1 GNO F 1 SIZO L 1 1 G N O B2 BG F2 FC2 L 1 2 03 B3 SA F3 FC1 L13 02 B4 A30 F 12 GNO B5 A27 F13 IPENO M 1 OS B6 A24 M2 029 B7 A20 M3 026 B8 A18 M4 024 B9 GNO G 1 ECS M5 021 B10 A15 G2 S IZ1 M6 018 B 1 1 A13 G3 OBEN M7 016 B12 A10 G 1 1 VCC M8 VCC B13 A6 G 1 2 GNO M9 013

G13 VCC M10 010 M 1 1 06 M 1 2 05

C1 RESET M13 04 C2 CLOCK H1 COIS C3 G N O H2 AVEC N1 031 C4 AO H3 OSACKO N2 028 C5 A29 H 1 2 I PL2 N3 025 C6 A25 H 13 G N O N4 022 C7 A21 N5 020 C8 A17 N6 017 C9 A16 N7 GNO C 10 A12 J 1 OSACK 1 N8 VCC C 1 1 A9 J2 BERR N9 0 14 C 1 2 A7 J3 G N O N 1 0 0 1 2 C 1 3 A5 J 1 2 I PLO N 1 1 09

J 13 iPLT N 12 08 N13 VCC

The Vee and G N D p ins are separated i nto three groups to provide i ndiv idual power supply connections for the address bus buffers, data bus buffers, and a l l other output buffers and i nternal log ic.

Group VCC GNO

Address 8us A9, 03 A 10, B9, C3, F 12 Data Bus M8 , N8, N 13 L7 , L 1 1 , N7 , K3 Logic 0 1 , 02, E3, G 1 1 , G 13 G 12 , H 13 , J3 , K 1 Clock B 1

1 1 -3/1 1 -4

-

A.1 INTRODUCTION

APPEN DIX A CON DITION CODES COMPUTATION

This appendix provides a d iscussion of how the condit ion codes were developed, the meanings of each bit, how they are computed, and how they are represented in the i n· struction set detai ls.

Two criteria were used i n developing the condit ion codes: • Consistency - across i nstruction, uses, and i nstances • Mean i ngfu l Resu lts - no change un less it provides usefu l i nformation

The cons istency across instructions means that i nstructions which are spec ial cases of more general i nstructions affect the condit ion codes in the same way. Consistency across i nstances means that i f an instruction ever affects a condit ion code, it w i l l always affect that condit ion code. Consistency across uses means that whether the condit ion codes were set by a compare, test, or move i nstruct ion, the cond it ional i nstructions test the same situation. The tests used for the condit ional instructions and the code computations are g iven in paragraph A.5.

A.2 CON DITION CODE REG ISTER

The condit ion code reg ister port ion of the status reg ister contains f ive bits: N - Negative Z - Zero V - Overflow C - Carry X - Extend

The f i rst fou r bits are true condit ion code bits in that they reflect the condition of the resu l t of a processor operat ion. The X bit is an operand for mu l t iprecis ion computations. The carry bit (C) and the mult iprec ision operand extend bit (X) are separate in the M68000 Fam i ly to s imp l i fy the programming model .

A.3 CON DITION CODE REGISTER NOTATION

In the i nstruct ion set detai ls g iven in APPENDIX B, the descript ion of the effect on the condit ion codes is g iven in the fol lowing form:

Cond it ion Codes: X N Z V C

A-1

•

•

where: N (negat ive) Z (zero) V (overflow)

C (carry)

X (extend)

Set i f the most s ign i f i cant bit of the resu l t is set. Cleared otherwise. Set i f the resu l t equals ze'ro. Cleared otherwise. Set if there was an arithmet ic overflow. This imp l ies that the resu l t is not representable in the operand s ize. Cleared otherwise. Set i f a carry is generated out of the most s ign if icant bit of the operands for an add it ion. Also, set i f a borrow is generated in a subtract ion. Cleared otherwise. Transparent to data movement. When affected, by arithmetic opera· t ions, it is set the same as the C bit.

The convention for the notation that is used in the condit ion code reg ister representation is:

* set accord ing to the resu l t of the operation not affected by the operation

o cleared 1 set U u ndefined after the operat ion

A.4 CON DITION CODE COMPUTATION

M ost operations take a source operand and a dest i nation operand, compute, and store the resu l t in the dest ination location. Unary operat ions take a desti nation operand, com· pute, and store the resu l t in the dest i nation location. Table A-1 detai ls how each i nstruc· t ion sets the condit ion codes.

A.5 CON DITION TESTS

Table A-2 l ists the cond it ion names, encod i ngs, and tests for the condit ion branch and set i nstructions. The test associated with each cond it ion is a logical formula based on the current state of the condit ion codes. I f th is formula evaluates to one, the condit ion succeeds, or is true. I f the formu la evaluates to zero, the condit ion is u nsuccessful , or false. For example, the T condit ion always succeeds, wh i le the EQ condit ion succeeds on ly i f the Z bit is cu rrently set in the condit ion codes .

A-2

Table A·1 . Condition Code Computations

Operations X

ABCD ·

ADD, ADDI , ADDO ·

ADDX ·

AND, ANDI , EaR, EaRl , -MOVEO, MOVE, OR , OR I , CLR , EXT, NOT , TAS , TST CHK -CHK2, CMP2 -

SUB , SUB I , SUBO ·

SUBX ·

CAS, CAS2, CMP, -CMPI , CMPM DIVS , DIVU -MULS, MULU -SBCD, NBCD ·

N EG ·

NEGX ·

BTST, BCHG, BSET, BCLR -BFTST, BFCHG, BFSET, -BFCLR BFEXTS , BFEXTU, BFFFO -

BFINS -

ASL ·

ASL I r = OI -LSL, ROXL ·

LSR I r = OI -ROXL I r = OI -ROL -ROL I r = OI -ASR , LSR , ROXR ·

ASR , LSR I r = OI -ROXR I r = OI -ROR -ROR I r = OI -

Not Affected U Undefined, result meaningless

Other - See Special Definition General Case X= C N = Rm Z = Rm fl . fl RO

N Z

U ?

· ·

· ,

· ·

· U U ,

· ·

· 7

· ·

· ·

· ·

U 7

· ·

· 7

- ? 7 ?

? 7

7 7

· ·

· ·

· ·

· ·

· ·

· ·

· ·

· ·

· ·

· ·

· ·

· ·

S m Om

Source Operand - most significant bit Destination Operand - most significant bit

V

U

,

7

0

U U

,

7

7

7 7 U

7 7

-0

0

0

,

0 0 0 0 0 0 0 0 0 0 0

C

7

,

7

0

U ,

7

?

7

0 0 ?

7 ?

-0

0

0

7

0 ? 0 7 7 0 7 0 7 ? 0

Rm R n

LB U B

V Rm

A·3

Special Definition

C = Decimal Carry Z = Z fl Rm fl fI RO V = S m fl Dm fl RmVS m fl Dm fl Rm C = Sm fl DmVRm fl DmVSm fi R m V = Sm fl Dm fl R mVS m fl Dm fl Rm C = Sm fl DmVR m fl DmVS m fl Rm Z = Z fl R m fl fl RO

Z = I R = LBI V I R = UB I c = I LB< = UB I fl I IR < LB IV IR > U B I IV

I U B < LB I fl I R > UB I fl I R < LBI V= Sm fl Om fl R mVSm fl Dm fl Rm C = S m fl DmVRm fl DmVSm fl R m V = Sm fl Dm fl RmVSm fl Dm fl Rm C = Sm fI DmVRm fI DmVSm fI R m Z = Z fl R m fl fI RO V = Sm fl Dm fl R mVSm fl Dm fl Rm C = S m fl DmVRm fl DmVSm fl Rm V = Division Overflow V = Multiplication Overflow C = Decimal Borrow Z = Z fl Rm fl fl RO V = Dm fl Rm, C = DmVRm V = Dm fl R m, C = DmVRm Z = Z fl Rm fl . fI RO Z= On N = Dm Z = Dm fl Dm- 1 f1 . N = Sm Z = Sm flSm- 1 f1 N = Dm Z = Dm fl Dm - 1 f1 V = Dm fl lDm - lV . C = Dm - r + 1

C = Dm - r + 1

C = X C = Dm - r + 1

C = Dr - 1

C = X C = Dr - 1

fl DO

fI SO

. fl DO .VDm - rlVOm fl lDm- lV .

Result Operand - most significant bit Register Tested Bit Number Shift Count Lower Bound Upper Bound Boolean AND Boolean OR NOT Rm

+ Dm - ri

-

•

Table A·2. Conditional Tests

Mnemonic

T * F* H I LS

CC IHS I CS ILOI

NE EO VC VS PL M I GE LT GT LE

• = Boolean ANO + = Boolean OR

Condition

True False High

Low or Same Carry Clear Carry Set Not Equal

Equal Overflow Clear Overflow Set

Plus Minus

G reater or Equal Less Than

Greater Than Less or Equal

N = Boolean NOT N

• Not available for the Bee instruction

A·4

Encoding

0000 0001 0010 001 1 0100 0101 0 1 1 0 01 1 1 1000 1001 1010 101 1 1 100 1 101 1 1 10 1 1 1 1

Test

1 0

C·Z C + Z

C C Z Z V V N N

N·V + N.V N · V + N.V

N.V.Z+ N ·V·Z Z + N . V + N·V

APPEN DIX B I NSTRUCTION SET DETAI LS

B.1 INTRODUCTION

This appendix conta ins detai led i nformat ion about each i nstruction in the MC68020 i n· struction set. They are arranged i n a lphabetical order with the mnemonic head ing set i n large bold type for easy reference.

B.2 ADDRESSING CATEGORIES

Effect ive address modes may be categorized by the ways i n which they may be used. The fol lowing c lassif ications w i l l be used in the i nstruction def in i t ions.

Data

Memory

Alterable

Control

I f an effect ive address mode may be used to refer to data operands, it is considered a data address ing effective address mode.

I f an effective address mode may be used to refer to memory operands, it is considered a memory address ing effective address mode.

I f an effective add ress mode may be used to refer to a lterable (writeable) operands, i t is considered an alterable addressing effec· t ive address mode.

If an effective address mode may be used to refer to memory operands without an associated s ize, it is considered a control addressing effective address mode.

Table 8-1 shows the various categories to which each of the effective address modes belong.

8-1

•

•

Table B·1 . Effective Addressing Mode Categories

Assembler Address Modes Mode Register Data Memory Control Alterable Syntax

Data Register Direct 000 reg. no. X - - X On Address Register D i rect 001 reg. no. - - - X An Address Register Indirect 010 reg. no. X X X X IAnl Address Register Indirect

with Postincrement 01 1 reg. no. X X - X IAnl + Address Register Indirect

with Predecrement 100 reg. no. X X - X - IAnl Address Register Indirect

with Displacement 101 reg. no X X X X Id 16.Anl Address Register Indirect with

Index IS-Bit Displacement! 1 10 reg. no. X X X X Ids,An,Xnl Address Register Indirect with

Index I Base Displacementl 1 10 reg. no. X X X X I bd,An,Xnl Memory Indirect Post-Indexed 1 10 reg. no. X X X X I [bd,Anl .Xn ,odl Memory Indirect Pre-Indexed 1 10 reg. no. X X X X I [bd,An,Xnl .odl Absolute S hort 1 1 1 000 X X X X Ixxxl .W Absolute Long 1 1 1 001 X X X X Ixxxl . L Program Counter Indi rect

with Displacement 1 1 1 0 1 0 X X X - Id 16,PC I Program Counter Indirect with

Index IS-Bit Displacement! 1 1 1 01 1 X X X - Ids ,PC ,Xnl Program Counter Indirect with

Index I Base Displacement! 1 1 1 01 1 X X X - Ibd,PC,Xnl PC Memory Indirect

Post-Indexed 1 1 1 01 1 X X X - I [bd,PCl .Xn ,odl PC Memory Indirect

Pre-Indexed 1 1 1 01 1 X X X - I [bd, PC,Xnl .odl Immediate 1 1 1 100 X X - - # < data >

These categories may be combined so that add it ional , more restrict ive, c lassif ications may be defi ned. For example, the instruction descriptions use such c lassifications as a lterable memory or data alterable. The former refers to those address ing modes which are both alterable and memory addresses, and the latter refers to addressing modes which are both data and alterable .

8·2

B.3 INSTRUCTION DESCRIPTION

The formats of each i nstruction are g iven i n the fol lowing pages. F igure B·1 i l l ustrates what i nformation is g iven.

I nstruction Name --------------.+-ABeD Add

Operation Descript ion (see paragraph B.4) ------------- Operation: Source1 Q + DestinatiOl

__ ------.... Assembler

Assembler Syntax for th is I nstruction - Syntax: ABCD DY,Dx ABCD - (Ay), - (Ax)

Text Descript ion of I nstruct ion Operation

Attributes: Size = (Byte)

Description: Add the source operar bit, and store the result in the d binary coded decimal arithmeti ways: 1. Data register to data registe,

specified in the i nstruction. 2. Memory to memory: The oper

ing mode using the address I This operation is a byte operati

Condit ion Code Effects (see Appendix A) --------i_� Condition Codes:

I nstruct ion Format - Specif ies the bit pattern and fields of the operat ion word and any other words which are part of the i nstruction. The ef· fect ive address extensions are not expl ic i t ly i l · l ustrated. The extensions ( i f there are any) would fol low the i l l ust rated port ions of the i nstructions. For the MOVE instruction, the source effective address extension is the f i rst, fol lowed by the dest i nation effect ive address extension.

x N z V c * ! u ! * ! u ! * ! N Undefined. Z Cleared if the result is n· V Undefined. e Set if a carry (decimal) '" X Set the same as the can

Normally the Z conditior � an operation. This al lows

� multiple-precision opera

Instruction Format: 15 14 13 12 1 1 1 0

Register Ax

Register Rx field - Specifies t � Instruction Fields:

Meanings and a l lowed values of the various If RIM = 0, specifies a data r!

f· Id . d b th . t t · f t If RIM = 1 , speCifies an addre Ie s requ i re y e inS rue Ion orma ; RIM field _ Specifies the oper

o - The operation is data re 1 - The operation is memor

Figure B·1 . Instruction Description Format

B-3

•

•

B.4 OPERATION DESCRIPTION DEFINITIONS

The fol lowing def i n it ions are used for the operation description in the deta i ls of the i nstruction set.

OPERANDS: An On An PC SA CCA SSP USP SP X Z V Immediate Data d Source Dest i nation Vector ea

address reg ister data reg ister any data or address reg ister program counter status reg ister cond it ion codes (lower order byte of status reg ister) supervisor stack pointer user stack poi nter active stack pOi nter (equ ivalent to A7) extend operand (from condition codes) zero cond it ion code overflow condit ion code immediate data from the i nstruction address d isplacement source contents dest ination contents location of except ion vector any va l id effective address

SUBFI ELDS AND aUALI FIERS: < bit > OF < operand > < ea > (offsetwidth) ( < operand > ) < operand > 1 0

« address reg ister» - « address reg ister » « address reg ister » +

#xxx or # < data>

selects a s ing le b i t of the operand selects a bit f ield the contents of the referenced locat ion the operand is binary coded dec imal ; operat ions are to be performed in decimal . the reg ister i nd i rect operator which ind icates that the operand reg ister pOints to the memory locat ion of the instruct ion operand. The opt ional mode qua l i f iers are - , + , (d) and (d, ix); these are expla i ned in SECTION 2 DATA ORGAN IZATION AND ADDRESSI NG CAPABILITIES. immediate data located with the i nstruct ion is the operand.

8-4

OPERATIONS: Operat ions are grouped i nto b inary, unary, and other.

Binary-These operations are written < operand > < op > < operand > where < op > is one of the fol lowing:

+

* I 1\ V e <

>

sh ifted by

rotated by

Unary:

the left operand is moved to the r ight operand the two operands are exchanged the operands are added the r ight operand is subtracted from the left operand the operands are mult ip l ied the f i rst operand is div ided by the second operand the operands are logical ly AN Oed the operands are logica l ly ORed the operands are logical ly exclus ively ORed relational test, true if left operand is less than right operand relational test, true i f left operand is g reater than right operand the left operand is sh i fted or rotated by the number of pos it ions specif ied by the r ight operand

- < operand > the operand is logica l ly complemented < operand > s ign-extended the operand is s ign extended, a l l bits of the upper port ion

are made equal to high order bit of the lower port ion < operand > tested the operand is compared to 0, the resu lts are used to set

the cond it ion codes

Other: TRAP

STOP

eq u ivalent to Format/Offset Word - (SSP); SSP - 2 - SSP; PC - (SSP); SSP - 4 - SSP; SR - (SSP); SSP - 2 - SSP; (vector) - PC enter the stopped state, wait ing for i nterru pts

I f < cond it ion > then < operations > else < operations > . The cond it ion is tested. If true, the operat ions after the "then" are performed. I f the cond it ion is false and the optional "else" clause is present, the operat ions after the "else" are performed. I f the condit ion is false and the optional "else" c lause is absent, the i nstruction performs no operat ion.

8-5

•

•

ABCD

Operation:

Assembler Syntax:

Attributes:

Add Decimal with Extend ABCD

Sou rce1 Q + Dest ination1 0 + X -- Dest ination

ABCD DY,Dx ABCD - (Ay), - (Ax)

Size = (Byte)

Description: Add the source operand to the dest i nation operand along with the extend bit, and store the resu l t in the dest i nation locat ion. The add it ion is performed using binary coded dec imal ar ithmetic. The operands may be addressed i n two d i fferent ways: 1 . Data reg ister to data reg ister: The operands are contai ned in the data reg isters

specif ied in the i nstruct ion. 2. Memory to memory: The operands are addressed with the predecrement address

ing mode us ing the address reg isters specif ied in the i nstruct ion. This operation is a byte operation only.

Condition Codes: x N z V c

* l u l * l u l * 1 N Undefined. Z Cleared if the resu l t is non-zero. Unchanged otherwise. V Undefined. C Set if a carry (dec imal) was generated. Cleared otherwise. X Set the same as the carry bit .

NOTE Normal ly the Z cond it ion code bit is set via programming before the start of an operat ion. This a l lows successfu l tests for zero resu lts upon completion of mu l t i ple-prec ision operat ions.


Instruction Fields:

1 1 10 9

Register Rx

8 7 6 5 4 3

Reg ister Rx f ield - Specif ies the dest ination reg ister: I f RIM = 0, specifies a data reg ister

2 0 Register

Ry

If RIM = 1 , specif ies an address reg ister for the predecrement addressing mode RIM f ie ld - Specif ies the operand addressing mode:

o - The operat ion is data reg ister to data reg ister 1 - The operat ion is memory to memory

Register Ry f ie ld - Specif ies the source reg ister: I f RIM = 0, spec if ies a data reg ister If RIM = 1 , spec if ies an address reg ister for the predecrement address ing mode

B-6

A D D

Operation:

Assembler Syntax:

Attributes:

Add

Source + Dest i nat ion -+ Dest ination

ADD < ea > ,Dn ADD Dn, < ea >

Size = (Byte, Word, Long)

A D D

Description: Add the source operand to the destination operand using binary addition, and store the resu l t in the dest i nation locat ion. The s ize of the operation may be specif ied to be byte, word, or long. The mode of the i nstruction i nd icates which operand is the source and which is the dest i nation as wel l as the operand size.


* 1 * 1 * 1 * 1 *

N Set if the resu l t is negative. Cleared otherwise. Z Set if the resu l t is zero. Cleared otherwise. V Set if an overflow is generated. Cleared otherwise. C Set if a carry is generated. Cleared otherw ise. X Set the same as the carry bit.

Instruction Format:

Instruction Fields:

11 10 9 8 7 6 5 4 3 2 0

Register Dn Op·Mode


Reg ister f ield - Specif ies any of the eight data reg isters. Op-Mode f ield -

Byte Word Long 000 001 0 10 1 00 1 01 1 1 0

Operation < ea > + < On > -+ < On > < O n > + < ea > -+ < ea >

Effective Address Field - Determines address ing mode: a. If the location specif ied in a sou rce operand, the a l l addreSSing modes are

a l lowed as shown:

B-7

•

•

A D D Add A D D

Addr. Mode Mode Register Addr. Mode Mode Register

On 000 reg. number:On (xxx).w 1 1 1 000 A n * 001 reg. number:An (xxx).L 1 1 1 001 (An) 010 reg. number:An #< data> 1 1 1 100

(An) + 0 1 1 reg. number:An

- (An) 1 00 reg. number:An (d16,An) 101 reg. number:An (d16, PC) 1 1 1 010

(dS,An,Xn) 1 1 0 reg. number:An (dS,PC,Xn) 1 1 1 0 1 1 (bd,An,Xn) 1 1 0 reg. number:An (bd,PC,Xn) 1 1 1 0 1 1

([bd,An,XnJ,od) 1 10 reg. number:An ([bd,PC,XnJ,od) 1 1 1 0 1 1 ([bd,AnJ,Xn,od) 1 10 reg. number:An ([bd,PCJ,Xn,od) 1 1 1 01 1

* Word and Long only.

b. If the locat ion specif ied is a dest i nation operand, then only alterable memory address ing modes are al lowed as shown:


On - - (xxx).w 1 1 1 000

An - - (xxx).L 1 1 1 001

(An) 010 reg. number:An #< data> - -


- (An) 1 00 reg. number:An

(d1 6,An) 1 01 reg. number:An (d16,PC)

(ds,An,Xn) 1 10 reg. number:An (dS,PC,Xn) - -

(bd,An,Xn) 1 1 0 reg. number:An (bd,PC,Xn) - -

([bd,An,XnJ,od) 1 10 reg. number:An ([bd,PC,XnJ,od) - -

([bd,AnJ,Xn,od) 1 1 0 reg. number:An ([bd,PCJ,Xn,od) - -

Notes: 1 . If the dest i nation is a data reg ister, then it cannot be spec if ied by us ing the dest ination < ea > mode, but must use the dest ination On mode i nstead .

2. ADDA is used when the dest i nation is an address reg ister. ADDI and ADDQ are used when the sou rce is immediate data. Most assemblers automat ica l ly make th is d ist inct ion .

8-8

A D DA Add Address

Operation: Sou rce + Dest i nat ion -+ Dest i nation

Assembler Syntax: ADDA < ea > ,An

Attributes: Size = (Word, Long)

A D DA

Description: Add the source operand to the dest i nation address reg ister, and store the resu l t in the address reg ister. The size of the operation may be spec if ied to be word or long. The ent i re dest i nation address reg ister is used regard less of the operat ion size.

Condition Codes: Not affected.

Instruction Format: 15 14 13 12 11 10 9

Instruction Fields:

Register

An

s 7

Op·Mode

6 5 4 3 2

Effective Address

Mode Register

o

Reg ister f ield - Specif ies any of the eight address reg isters. This is always the dest i nat ion.

Op-Mode f ield - Specif ies the s ize of the operat ion: 01 1 -word operat ion. The source operand is s ign-extended to a long operand and

the operat ion is performed on the address reg ister using a l l 32 bits. 1 1 1 - long operat ion.

Effect ive Address f ield - Specif ies the sou rce operand. A l l addressing modes are al lowed as shown:


Dn 000 reg. number:Dn (xxx).W 1 1 1 000

An 001 reg. number:An (xxx).L 1 1 1 001

(An) 010 reg. number:An # < data > 1 1 1 100

(An) + 011 reg. number:An

- (An) 100 reg. number:An (d16,An) 101 reg. number:An (d16,PC) 1 1 1 010

(ds,An,Xn) 1 1 0 reg. number:An (ds,PC,Xn) 1 1 1 0 1 1

(bd,An,Xn) 1 1 0 reg. number:An (bd,PC,Xn) 1 1 1 0 1 1

([bd,An,Xn],od) 1 1 0 reg. number:An ([bd,PC,Xnj,od) 1 1 1 011 ([bd,Anj,Xn,od) 1 1 0 reg. number:An ([bd,PC),Xn,od) 1 1 1 0 1 1

8-9

•

•

A D D I Add Immediate

Operation: Immed iate Data + Dest i nation -- Dest i nation

Assembler Syntax: ADDI # < data > , < ea >

Attributes: Size = (Byte, Word, Long)

A D D I

Description: Add the immed iate data to the destination operand, and store the resu l t i n the dest ination location. The s ize o f the operation may b e specified to b e byte, word, or long. The s ize of the immed iate data matches the operation s ize.


* 1 * 1 * 1 * 1 * 1

N Set if the resu l t is negative. Cleared otherwise. Z Set if the resl,l l t is zero. Cleared otherwise. V Set if an overflow is generated. Cleared otherwise. C Set if a carry is generated. Cleared otherw ise. X Set the same as the carry bit .

Instruction Format: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 0 1 0 1 0 J 0 I 0 1 1 1 1 1 0 1 Size I Word Data I

Long Data (Includes Previous Word)

Instruction Fields: Size f ield - Specifies the s ize of the operat ion:

OO- byte operat ion. 01 -word operat ion. 10- long operation.

Effective Address Mode I Register

Byte Data

Effective Address f ield - Specif ies the dest i nation operand. Only data alterable address ing modes are a l lowed as shown:

B·1 0

A D D I A D D I Add Immediate


Dn 000 reg. number:Dn (xxx).w 1 1 1 000 An - - (xxx).L 1 1 1 001

(An) 010 reg. number:An # < data> - -

(An) + 01 1 reg. number:An

- (An) 1 00 reg. number:An (d16,An) 101 reg. number:An (d1 6,PC) - -

(de,An,Xn) 1 10 reg. number:An (de,PC,Xn) - -


([bd,An,XnJ,od) 1 1 0 reg. number:An ([bd,PC,XnJ,od) - -

([bd,AnJ,Xn,od) 1 10 reg. number:An ([bd,PCJ,Xn,od) - -

Immediate f ield - (Data immediately fol lowing the i nstruction): [f size = 00, then the data is the low order byte of the immediate word. If size = 01 , then the data is the ent ire immed iate word. If size = 1 0, then the data is the next two immediate words.

8·1 1

•

•

A D DQ Add Quick

Operation: Immediate Data + Dest i nat ion -+ Dest ination

Assembler Syntax: ADDQ # < data > , < ea >


A D DQ

Description: Add the immediate data to the operand at the dest ination locat ion. The data range is from 1 to 8. The size of the operation may be spec if ied to be byte, word, or long. Word and long operat ions are also al lowed on the address reg isters, in which case the condit ion codes are not affected. When add ing to address reg isters, the ent i re dest i nation address reg ister is used, regard less of the operation s ize.

Condition Codes: x N Z V c * 1 * 1 * 1 * 1 * N Set if the resu l t is negat ive. Cleared otherwise. Z Set if the resu l t is zero. Cleared otherwise. V Set if an overflow is generated. Cleared otherwise. C Set if a carry is generated . Cleared otherwise. X Set the same as the carry bit .

The cond it ion codes are not affected if the dest i nation is an address reg ister.

Instruction Format:

Instruction Fields:

1 1 10 9 Data

6 5 4 3 2 o Effective Address

Mode Register

Data f ield - Three bits of immediate data, 0, 1 -7 represent ing a range of 8, 1 to 7 respect ively.

Size field - Specifies the size of the operat ion: OO-byte operat ion. 01 -word operat ion . 10- long operat ion.

Effective Address f ield - Specifies the dest i nation locat ion. On ly alterable add ressing modes are a l lowed as shown:

B-1 2

A D DQ Add Quick A D DQ



An· 001 reg. number:An (xxx).L 1 1 1 001



- (An) 100 reg. number:An

(d1 6,An) 101 reg. number:An (d16,PC) - -

(de,An,Xn) 1 1 0 reg. number:An (de,PC,Xn) - -


([bd,An,Xnj,od) 1 10 reg. number:An ([bd,PC,Xnj,od) - -

([bd,Anj,Xn,od) 1 10 reg. number:An ([bd,PC],Xn,od) - -

* Word and Long Only.

•

B·1 3

•

A D DX

Operation:

Assembler Syntax:

Attributes:

Add Extended A D DX

Source + Dest i nat ion + X -+ Dest i nation

ADDX DY,Dx ADDX - (Ay), - (Ax)


Description: Add the source operand to the desti nation operand along with the extend bit and store the result in the destination location. The operands may be addressed in two different ways: 1 . Data reg ister to data reg ister: the operands are contained in data reg isters

specif ied in the i nstruction. 2. Memory to memory: the operands are addressed with the predecrement address

ing mode us ing the address reg isters specif ied in the i nstruction. The s ize of the operat ion may be spec if ied to be byte, word, or long.


* 1 * 1 * 1 * 1 * 1 N Set if the resu l t is negative. Cleared otherwise. Z C leared i f the resu l t is non-zero. U nchanged otherw ise. V Set if an overflow is generated. Cleared otherwise. C Set i f a carry is generated. Cleared otherwise. X Set the same as the carry bit .

NOTE Normaliy the Z condition code bit is set via programming before the start of an operation. This al iows successful tests for zero results upon completion of multiple-precision operat ions.

Instruction Format: 15 14 13 12 11 10 9

Register Rx

B-1 4

4 3 2 Register

Ry

o

A D DX Add Extended A D DX

Instruction Fields: Reg ister Rx f ield - Specifies the dest ination reg ister:

If RIM = 0, specifies a data reg ister. If RIM = 1 , specifies an address reg ister for the predecrement addressing mode.

Size field - Specif ies the size of the operat ion: OO- byte operation. 01 -word operation. 10- long operat ion.

RIM field - Specifies the operand address mode: 0-The operation is data reg ister to data reg ister. 1 -The operat ion is memory to memory.

Register Ry f ield - Specif ies the source reg ister: If RIM = 0, spec ifies a data reg ister. If RIM = 1 , specif ies an address reg ister for the predecrement address ing mode .

8-1 5

•

•

A N D

Operation:

Assembler Syntax:

Attributes:

AND Logical

Source" Dest i nat ion - Dest i nation

AND < ea > ,Dn AN D Dn, < ea >


A N D

Description: AN D the source operand to the dest ination operand and store the resul t i n the dest i nation location. The s ize o f the operation may be speci fied t o be byte, word, or long. The contents of an address reg ister may not be used as an operand.

Condition Codes: x N z V c 1 - 1 · 1 · 1 0 0 \ N Set if the most s ign i f icant bit of the resu l t is set. Cleared otherwise. Z Set if the resu l t is zero. Cleared otherwise. V Always cleared. C A lways cleared. X Not affected.

Instruction Format: 15 14 1 3 12 1 1 10 9 8 7 6 5 4 3 2 0

Instruction Fields:

Register

On Op·Mode

Effective Address

Mode Register

Register field - Specifies any of the eight data reg isters. Op-Mode f ield -

Byte Word Long Operation 000 001 0 10 « ea » A« Dn » - Dn 1 00 1 01 1 1 0 « Dn » "« ea » - ea

Effective Address f ield - Determines address ing mode: I f the location specif ied is a source operand then on ly data addressing modes are a l lowed as shown:

B-1 6

A N D AND Logical AN D


On 000 reg. number:On (xxx).w 1 1 1 000

An - - (xxx).L 1 1 1 001 (An) 010 reg. number:An # < data> 1 1 1 100


- (An) 1 00 reg. number:An (d16,An) 1 01 reg. number:An (d1 6,PC) 1 1 1 010

(de,An,Xn) 1 10 reg. number:An (de,PC,Xn) 1 1 1 0 1 1 (bd,An,Xn) 1 10 reg. number:An (bd,PC,Xn) 1 1 1 0 1 1

([bd,An,Xnj,od) 1 10 reg. number:An ([bd,PC,Xnj,od) 1 1 1 0 1 1 ([bd,An],Xn,od) 1 10 reg. number:An ([bd,PC),Xn,od) 1 1 1 0 1 1

I f the locat ion specif ied is a dest i nation operand then only alterable memory addressing modes are al lowed as shown:


On - - (xxx).W 1 1 1 000

An - - (xxx).L 1 1 1 001



- (An) 100 reg. number:An (d16,An) 101 reg. number:An (d16,PC) - -

(de,An,Xn) 1 1 0 reg. number:An (de,PC,Xn) - -


([bd,An,Xnj,od) 1 1 0 reg. number:An ([bd,PC,Xnj,od) - -

([bd,Anj.Xn,od) 1 1 0 reg. number:An ([bd,PC),Xn,od) - -

Notes: 1 . I f the dest i nation is a data reg ister, then it cannot be spec if ied by us ing the dest i nat ion < ea > mode, but must use the dest i nation Dn mode instead.

2. ANDI is used when the source is i mmediate data. Most assemblers automatical ly make th is d ist inction.

8-1 7

II

•

AN DI AND Immediate

Operation: Immed iate Data A Dest i nation - Dest i nation

Assembler Syntax: AN DI # < data > , < ea >


AN DI

Description: A N D the immediate data to the dest i nation operand and store the resu l t i n the dest i nation location. The s ize o f the operation may b e specif ied to b e byte, word, or long. The s ize of the i mmediate data matches the operation s ize.


1 - 1 * 1 * 1 0 1 0

N Set if the most s ign i f icant b i t of the resu l t is set. Cleared otherw ise. Z Set if the resu l t is zero. Cleared otherwise. V A lways c leared. C A lways c leared. X Not affected.

Instruction Format: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 0 1 0 1 0 1 0 1 0 1 0 1 1 1 0 1 Size 1

Word Data I Long Data (I ncludes Previous Word)

Instruction Fields: Size f ield - Specif ies the s ize of the operation:

OO-byte operat ion. 01 -word operation. 10- long operat ion.

Effective Address Mode I Register

Byte Data

Effective Address f ield - Specif ies the dest i nation operand. Only data alterable addressing modes are al lowed as shown:

B-1 8

A N DI AN 0 Immediate AN DI


On 000 reg. number:On (xxx).W 1 1 1 000

An - - (xxx).L 1 1 1 001 (An) 010 reg. number:An # > data > - -


- (An) 100 reg. number:An (d16,An) 1 01 reg. number:An (d16, PC) - -

(da,An,Xn) 1 10 reg. number:An (da,PC,Xn) - -



([bd,Anj,Xn,od) 1 1 0 reg. number:An ([bd,PC].Xn,od) -

Immediate f ield - (Data immediately fol lowing the i nstruction): If size = 00, then the data is the low order byte of the immediate word. If size = 01 , then the data is the ent ire immed iate word. I f s ize = 1 0, then the data is the next two i mmediate words.

8-1 9

•

•

A N DI to CC R AN 0 Immediate to Condition Codes

Operation: Sou rce A CCR - CCR

Assembler Syntax: A N DI # < data > ,CCR


AN DI to CC R

Description: A N D the immediate operand with the cond it ion codes and store the resu l t in the low-order byte of the status reg ister.

Condition Codes: x N z V c * 1 * 1 * 1 * 1 *

N Cleared if b i t 3 of immediate operand is zero. Unchanged otherwise. Z Cleared if bit 2 of immediate operand is zero. Unchanged otherwise. V Cleared if b i t 1 of i mmediate operand is zero. Unchanged otherwise. C Cleared if bit 0 of immediate operand is zero. Unchanged otherwise. X Cleared if bit 4 of immed iate operand is zero. Unchanged otherwise.

Instruction Format:

B-20

A N DI to S R

AND Immediate to the Status Register (Privileged Instruction)

Operation: If su pervisor state

Assembler

then Sou rce A SR - SR else TRAP

Syntax: ANDI # < data > ,SR

Attributes: Size = (Word)

AN DI to S R

Description: A N D the immed iate operand with the contents of the status reg ister and store the resu l t in the status reg ister. A l l bits of the status reg ister are affected.


* 1 * 1 * 1 * * 1 N Cleared if bit 3 of immed iate operand is zero. Unchanged otherw ise. Z Cleared if bit 2 of immed iate operand is zero. Unchanged otherw ise. V Cleared if bit 1 of immed iate operand is zero. Unchanged otherwise. C Cleared if b i t 0 of immediate operand is zero. Unchanged otherwise. X C leared if bit 4 of immed iate operand is zero. Unchanged otherw ise.

Instruction Format: 15 1 4 1 3 1 2 1 1 0 0 1 0 1 0 0

10 9 8 7 6 5 4 3 2

Word Data (16 Bits)

8-21

1 0

o I 0

•

•

AS L, AS R Arithmetic Shift

Operation:

Assembler Syntax:

Dest i nation Shifted by < count > -- Dest i nation

ASd DX,Dy ASd # < data > , Dy ASd < ea > where d is d i rection, L o r R


AS L, AS R

Description: Arithmetical ly sh ift the bits of the operand i n the d i rect ion (L or R) specif ied. The carry b it receives the last b i t sh ifted out of the operand. The sh ift cou nt for the shift ing of a reg ister may be specif ied in two d i fferent ways: 1 . Immed iate: the sh ift count is spec if ied in the i nstruction (shift range, 1 -8). 2. Reg ister: the sh ift count is contai ned in a data reg ister specif ied in the i nstruction

(shift cou nt is modulo 64). The s ize of the operation may be spec if ied to be byte, word, or long. The content of memory may be sh ifted one bit on ly, and the operand s ize is restricted to a word.

For ASL, the operand is sh ifted left; the nu mber of pos it ions sh ifted is the sh ift count. Bits sh i fted out of the high order bit go to both the carry and the extend bits; zeroes are sh ifted i nto the low order bit . The overflow bit i nd icates i f any s ign changes occur dur ing the sh ift .

ASL:

�+-__ --� ____ o_pe

_ra_

n_d __ �14

For ASR, the operand is sh ifted r ight; the nu mber of pos it ions sh ifted is the sh ift count. Bits sh ifted out of the low order b it go to both the carry and the extend bits; the sign bit (MSB) is rep l icated i nto the high order bit.

ASR: .----�.I MS B Operand

B-22

AS L, AS R Arithmetic Shift AS L, AS R

Condition Codes: x N z V x

* 1 * 1 * 1 * * 1 N Set if the most s ign if icant bit of the resu l t is set. Cleared otherwise. Z Set if the resu l t is zero. Cleared otherw ise. V Set if the most s ign if icant b i t is changed at any t ime dur ing the sh ift opera

t ion. Cleared otherwise. C Set accord ing to the last bit sh ifted out of the operand. Cleared for a sh ift

count of zero. X Set accord i ng to the last b i t sh ifted out of the operand. Unaffected for a sh ift

cou nt of zero.

Instruction Format (Register Shi fts): 15 1 4 1 3 12 1 1 10 9 8 7 6 5 4 3 2 0

Count

Register

Instruction Fields (Reg ister Sh i fts):

Register

Count/Reg ister f ield - Specif ies sh ift cou nt or reg ister where count is located: If i/r = O, the sh ift cou nt is specif ied in th is f ie ld . The va lues 0, 1 -7 represent a

range of 8, 1 to 7 respect ive ly. I f i/r = 1 , the sh ift cou nt (modu lo 64) is contai ned in the data reg ister specif ied

i n th is f ie ld . dr f ield - Specif ies the d i rection of the sh ift:

O-shift r ight. 1 -sh i ft left.

Size field - Specif ies the s ize of the operat ion: OO-byte operat ion. 01 -word operat ion. 1 0- long operat ion.

i / r f ield -If i/r = 0, specif ies immed iate sh ift count. I f i/r = 1 , specifies reg ister sh ift count.

Register f ield - Specif ies a data reg ister whose content is to be sh ifted .

8-23

•

•

AS L, AS R Arithmetic Shift AS L, AS R Instruction Format (Memory Shi fts):

15 1 4 1 3 1 2 1 1 10 9 7 6

Instruction Fields (Memory Shifts): dr f ield - Specif ies the d i rect ion of the sh ift:

O-shift r ight 1 -shi ft left

5 4 3 2


o

Effective Address f ield - Specif ies the operand to be shifted. Only memory alterable address ing modes are al lowed as shown:


On - - (xxx).W 1 1 1 000 An - - (xxx).L 1 1 1 001



- (An) 100 reg. number:An (d16,An) 101 reg. number:An (d16,PC) - -

(dS,An,Xn) 1 1 0 reg. number:An (ds,PC,Xn) -


([bd,An,Xn],od) 1 1 0 reg. number:An ([bd,PC,Xn],od) - -

([bd,An],Xn,od) 1 10 reg. number:An ([bd,PC],Xn,od) - -

8-24

Bee Branch Conditionally

Operation: If (cond it ion true) then PC + d - PC

Assembler Syntax: Bee < labe l >


Bee

Description: I f the specif ied cond it ion is met, program execution cont i nues at locat ion (PC) + disp lacement. The disp lacement is a twos complement i nteger which counts the relat ive d istance i n bytes. The value in the PC is the S ign-extended i nstruct ion locat ion p lus two. I f the 8-bit d isplacement in the i nstruct ion word is zero, then the 1 6-bit d isplacement (word immediately fol lowing the i nstruct ion) is used. If the 8-bit d isp lacement in the i nstruction word is all ones ($FF), then the 32-bit d isplacement (long word immediately fol lowing the i nstruction) is used. "cc" may specify the fol lowing cond it ions:

cc carry clear 0100 C LS low or same 001 1 CS carry set 0101 C LT less than 1 1 01 EQ equal 01 1 1 Z MI minus 101 1 GE greater or equal 1 1 00 N .V + N.V NE not equal 01 10 GT greater than 1 1 1 0 N .V.Z + N.V.Z PL plus 1010 H I high 0010 C.Z VC overflow clear 1000 LE less or equal 1 1 1 1 Z + N.V+ N.V VS overflow set 1001


Instruction Format: 15 1 4 1 3 1 2 11 10 9 8 7 6 5 4 3 2 0

o I 1 I 1 I o I Condition I 8·Bit Displacement 16·Bit Displacement if 8·Bit Displacement = $00

32·Bit Displacement if 8·Bit Displacement = $FF

Instruction Fields: Condit ion f ie ld - One of fourteen cond it ions d iscussed in descript ion.

C + Z N.V + N.V N Z N V V

8-Bit Displacement f ie ld - Twos complement i nteger spec ifying the relat ive d istance ( in bytes) between the branch i nstruct ion and the next instruction to be executed if the cond it ion is met.

1 6-B it Displacement f ie ld - Al lows a larger d isp lacement than 8 bits. Used only if the 8-bit d isplacement is equal to $00.

32-B it D isplacement f ield - Al lows a larger d isp lacement than 1 6 bits. Used only i f the 8-bit d isplacement is equal to $FF.

Note: A short branch to the immediately fol lowing i nstruct ion cannot be generated, because it wou ld resu l t in a zero offset, which forces a word branch i nstruct ion def in it ion.

B-25

II

II

B C H G Test a Bit and Change BC H G

Operation: - « bit number > of Desti nation) - Z; - « bit number> of Dest i nation) - < bit number> of Dest i nation

Assembler Syntax:

Attributes:

BCHG Dn, < ea > BCHG # < data > , < ea >

Size = (Byte, Long)

Description: A bit in the dest i nat ion operand is tested and the state of the spec if ied bit i s reflected i n the Z cond it ion code. After the test, the state of the specif ied bit is changed i n the dest i nat ion. I f a data reg ister is the dest i nation, then the bit numberi ng is modulo 32 al lowing bit manipu lation on a l l b its i n a data reg ister. If a memory locat ion is the dest i nation, a byte is read from that location, the bit operation is performed using the bit number, modulo 8, and the byte is written back to the locat ion. In a l l cases, b i t zero refers to the least s ign i f icant bit . The bit number for th is operat ion may be specif ied i n two d i fferent ways: 1 . Immediate - the bit number is specif ied in a second word of the i nstruction. 2. Reg ister - the bit number is contained i n a data reg ister specif ied i n the i nstruc

t ion.

Condition Codes: x N z V c I - I - I * I N Not affected. Z Set if the bit tested is zero. Cleared otherw ise. V Not affected. C Not affected. X Not affected.

Instruction Format (Bit Number Dynamic specif ied by a reg ister): 15 1 4 1 3 1 2 11 1 0 9 8 7 6 5 4 3 2 0

Register

Dn

Instruction Fields (Bit N umber Dynamic):

Effective Address

Mode Register

Register f ield - Specif ies the data reg ister whose content i s the bit number. Effect ive Address f ield - Specif ies the desti nation locat ion. Only data alterable

address ing modes are al lowed as shown:

B-26

B C H G Test a Bit and Change BC H G


Dn * 000 reg. number:Dn (xxx).W 1 1 1 000

An - - (xxx).L 1 1 1 001




(d16,An) 101 reg. number:An (d16,PC) - -

(dS,An,Xn) 1 10 reg. number:An (dsPC,Xn) - -

(bd,An,Xn) 1 10 reg. number:An (bd,PC,Xn) - -

([bd,An,Xn),od) 1 10 reg. number:An ([bd,PC,Xnl,od) - -

([bd,Anl,Xn,od) 1 10 reg. number:An ([bd,PCJ,Xn,od) - -

* Long only; all others are byte only.

Instruction Format (Bit N u mber Static, specif ied as immediate data): 15 14 1 3 1 2 1 1 10 9 s 7 6 5 4 3 2 o

o I 1 I Effective Address 0 0 0 0 1 0 0 0 I Mode Register

0 0 0 0 0 0 0 0 Bit Number

Instruction Fields (Bit N umber Stat ic): Effective Address field - Specif ies the dest ination location. On ly data alterable ad

dressing modes are al lowed as shown:



An - - (xxx).L 1 1 1 001





(ds,An,Xn) 1 1 0 reg. number:An (ds,PC,Xn) - -


([bd,An,Xnl,od) 1 10 reg. number:An ([bd,PC,Xnl,od) - -

([bd,Anl,Xn,od) 1 1 0 reg. number:An ([bd,PCJ,Xn,od) - -

* Long only, al l others are byte only.

Bit N umber f ield - Specif ies the bit number.

B-27

•

•

BC L R

Operation:

Assembler Syntax:

Attributes:

Test a Bit and Clear

- « b it number> of Destination) - Z; 0 - < bit number > of Dest i nation

BClR On, < ea > BClR # < data > , < ea >

Size = (Byte, long)

B C L R

Description: A bit i n the dest i nat ion operand is tested and the state of the spec i f ied bit is reflected i n the Z condit ion code. After the test, the spec i f ied bit is cleared i n the dest inat ion. I f a data reg ister is the dest ination, then the bit numbering is modulo 32 al lowing bit manipu lation on a l l bits i n a data reg ister. If a memory locat ion is the dest i nation, a byte is read from that locat ion, the bit operation performed using the bit number, modu lo 8, and the byte written back to the locat ion. In al l cases, bit zero refers to the least S ign i f icant bit . The bit number for th is operation may be specif ied in two d i fferent ways: 1 . I mmed iate - the bit number is specif ied in a second word of the i nstruction. 2. Register - the bit number is contai ned in a data reg ister specif ied in the instruc

t ion.


I - I - I * I N Not affected . Z Set if the b it tested is zero. Cleared otherw ise. V Not affected. C Not affected. X Not affected.

Instruction Format (Bit N umber Dynamic, specif ied in a reg ister): 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0

Register

Dn

Instruction Fields (Bit Nu mber Dynamic):

Effective Address

Mode Register

Register f ie ld - Specif ies the data reg ister whose content is the bit nu mber. Effect ive Address f ie ld - Speci f ies the dest i nation locat ion. Only data alterable ad


B-28

BC L R Test a Bit and Clear BC L R


O n * 000 reg. number:On (xxx)W 1 1 1 000

An - - (xxx).L 1 1 1 001




(d1 6,An) 1 01 reg. number:An (d1 6,PC) - -

(dS,An,Xn) 1 10 reg. number:An (ds,PC,Xn) - -

(bd,An,Xn) 1 10 reg. number:An (bd, PC,Xn) - -

([bd,An,Xn],od) 1 10 reg. number:An ([bd ,PC,Xn],od) - -

([bd,Anj,Xn,od) 1 10 reg. number:An ([bd,PGj,Xn,od) - -

* Long only; al l others are byte only

Instruction Format (Bit N u mber Stat ic, spec if ied as immediate data): 15 1 4 1 3 1 2 1 1 10 9 s 7 6 5 4 3 2 o

I I Effective Address 0 0 0 0 1 0 0 0 1 0 I Mode Register

0 0 0 0 0 0 0 0 Bit Number

Instruction Fields (Bit N u mber Stat ic): Effective Address field - Specifies the dest i nation locat ion. Only data alterable ad



On * 000 reg. number:On (xxx).w 1 1 1 000

An - - (xxx).L 000 001

(An) 010 reg. number:An # < data > - -



(d1 6,An) 101 reg. number:An (d16, PC) - -

(dS,An,Xn) 1 1 0 reg. number:An (dS,PC,Xn) - -



([bd,Anj,Xn,od) 1 1 0 reg. number:An ([bd,PGj,Xn,od) - -

* Long only; al l others are byte only.

Bit N umber f ield - Spec i f ies the bit number.

B-29

--

•

B FC H G Test Bit Field and Change

Operation: - « bit f ie ld > of Dest i nat ion) - < bit f ield > of Desti nat ion

Assembler Syntax: BFCHG < ea > [offset:widthl

Attributes: Uns ized

B FC H G

Description: Complement a bit f ield at the specif ied effective address locat ion. The cond i t ion codes are set accord ing to the va lue in the field before it is changed.

The field select ion is specif ied by a field offset and field width. The field offset denotes the start i ng bit of the f ield. The f ield width determi nes the number of bits to be i ncluded in the f ie ld.

Condition Codes: x N z V C

* I * I 0 I 0 N Set if the most s ignif icant bit of the f ield is set. Cleared otherwise. Z Set if a l l bits of the f ield are zero. Cleared otherwise. V A lways c leared. C A lways c leared. X Not affected.

Instruction Format: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 o 1 1 1 0 1 1 1 Effective Address 1 1 1 0 1 1 I Mode Register 0 0 0 0 Do Offset Dw I Width

Instruction Fields: Effective Address field - Specif ies the base locat ion for the bit f ield. On ly data

reg ister d i rect or a l terable control addressing modes are al lowed, as shown below:

Do f ie ld - Determi nes how the field offset is spec if ied. O-the f ield offset is i n the Offset f ield. 1 -bits [8:6] of the extension word specify a data reg ister which contains the off

set; bits [1 0:9] are O. Offset f ield - Specif ies the f ie ld offset, depend ing on Do.

If Do = O-the Offset field is an i mmed iate operand; the operand value is in the range 0-31 , specifying a f ield offset of 0-31 .

I f Do = 1 -the Offset f ield specif ies a data reg ister which contains the offset. The value is in the range - 231 to 231 - 1 .

8-30

B FC H G Test Bit Field and Change B FC H G

Dw field - Determ i nes how the f ield width is spec ified . O-the f ie ld width is i n the Width field. 1 -bits [2:0] of the extension word specify a data reg ister which contains the

width; bits [3:4] are O. Width field - Specif ies the field width, depending on Dw. If Dw = O-the Width field is an i mmediate operand; the operand va lue is in the

range 0, 1 -31 specifying a f ield width of 32, 1 -31 respectively. If Dw = 1 -the Width f ield specifies a data reg ister which contains the width. The

operand value is taken modu lo 32, w i th values 0, 1 -31 spec ifying a f ield width of 32, 1 -31 .



An - - (xxx).L 1 1 1 001


(An) + - -

- (An) - -

(d16,An) 101 reg. number:An (d1 6, PC) - -

(ds,An,Xn) 1 10 reg. number:An (ds,PC,Xn) - -




8-31

•

•

B FC L R Test Bit Field and Clear

Operation: 0 -+ < bit f ield > of Dest i nat ion

Assembler Syntax: BFCLR < ea > [offsetwidth]

Attributes: Unsized

B FC L R

Description: Clear a b it f ield at the spec if ic effective address locat ion. The condit ion codes are set accord ing to the value i n the f ield before it is c leared.

The field selection is specif ied by a f ield offset and field width. The f ield offset denotes the start i ng bit of the field. The f ield width determines the number of bits to be i nc l uded in the f ield.


1 - 1 * 1 * 1 0 1 0

N Set if the most s ign i f icant b i t of the f ield is set. Cleared otherwise. Z Set if a l l bits of the f ield are zero. Cleared otherwise. V Always c leared. C Always c leared. X Not affected.

Instruction Format: 15 1 4 1 3 12 1 1 10 9 8 7 6 5 4 3 2 0 I 0 I 0 I 1 I Effective Address 1 1 1 0 1 1 1

Mode I Register

0 0 0 0 Do Offset Dw I Width

Instruction Fields: Effective Address f ield - Specif ies the base locat ion for the bit f ield. Only data

reg ister d i rect or a lterable control addressing modes are al lowed, as shown below:

Do field - Determines how the field offset is spec if ied. O-the f ield offset is i n the Offset f ield. 1 - bits [8:6] of the extension word specify a data reg ister which conta ins the off

set; b its [ 10 :9] are O. Offset f ield - Specif ies the f ield offset, depend ing on Do.

I f Do = O-the Offset f ie ld is an immediate operand; the operand value is in the range 0-31 , specifying a f ield offset of 0-31 .

If Do = 1 -the Offset f ield specifies a data reg ister which conta ins the offset. The value is in the range - 231 to 231 - 1 .

8-32

B FC L R Test Bit Field and Clear B FC L R

Ow field - Determines how the f ield width is specif ied. O-the f ield width is i n the Width f ie ld. 1 - bits [2:0] of the extension word specify a data reg ister which contains the

width; bits [4:3] are O. Width f ield - Specif ies the f ield width, depend ing on Ow.

If Ow = O-the Width field is an immed iate operand; the operand value is in the range 0, 1 -31 specifying a field width of 32, 1 -31 .

I f Ow = 1 -the Width f ield specif ies a data reg ister which conta i ns the width. The operand va lue is taken modu lo 32, with val ues 0, 1 -31 spec ifying a f ie ld width of 32, 1 -31 .



An - - (xxx).L 1 1 1 001


(An) + - -

- (An) - -

(d1 6,An) 1 01 reg. number:An (d16,PC) - -

(dS,An,Xn) 1 10 reg. number:An (dS,PC,Xn) - -



([bd,Anj,Xn,od) 1 10 reg. number:An ([bd,PCI,Xn,od) - -

8-33

•

•

B F EXTS Extract Bit Field Signed

Operation: <bit f ield > of Source - On

Assembler Syntax: BFEXTS < ea > [ offsetwidth) ,Dn

Attributes: U nsized

B F EXTS

Description: Extract a bit field from the specif ied effective address locat ion, s ign extend to 32 b its, and load the resu l t i nto the dest i nation data reg ister.

The f ield selection is spec if ied by a field offset and field width. The field offset denotes the start ing bit of the field. The f ield width determines the number of bits to be inc luded in the f ield.


1 - 1 * 1 * 1 0 1 0

N Set if the most s ign if icant bit of the f ield is set. Cleared otherwise. Z Set if a l l bits of the field are zero. Cleared otherw ise. V A lways c leared. C Always cleared. X Not affected.

Instruction Format: 15 1 4 1 3 12 11 10 9 8 7 6 5 4 3 2 0

1 1 1 0 o 1 1 1 1 1 1 1 Effective Address 1 1 1 1 I Mode Register

0 Register Do Offset Dw I Width

Instruction Fields: Effective Address field - Specif ies the base location for the bit f ie ld . Only data

reg ister d i rect or control addressing modes are al lowed as shown below: Reg ister field - Specifies the dest ination reg ister . Do f ield - Determi nes how the f ield offset is spec if ied.

O-the f ield offset is i n the Offset f ie ld. 1 - bits [8:6] of the extension word spec ify a data reg ister which conta i ns the off

set; bits [1 0:9] are o. Offset field - Specif ies the field offset, depending on Do.

If Do = O-the Offset f ield is an immediate operand; the operand value is in the range 0-31, speCify ing a f ield offset of 0-31 .

I f Do = 1 -the Offset field spec ifies a data-reg ister which contains the offset. The val ue is in the range - 231 to 231 - 1 .

8-34

B F EXTS Extract Bit Field Signed B F EXTS

Dw field - Determ i nes how the field width is specif ied. O-the field width is in the Width f ield. 1 - bits [2:0] of the extension word specify a data reg ister which contains the

width; bits [4:3] are O. Width f ield - Specif ies the f ie ld width, depending on Dw.

I f Dw = O-the Width f ield is an i mmediate operand; the operand va lue is i n the range 0, 1 -31 , specifying a f ie ld width of 32, 1 -31 .

I f Dw = 1 -the Width f ie ld specifies a data reg ister which contains the width. The operand value is taken modu lo 32, w i th values 0, 1 -31 specify ing a f ield width of 32, 1 -31 .



An - - (xxx).L 1 1 1 001


(An) + - -

- (An) - -

(d1 6,An) 1 01 reg. number:An (d16, PC) 1 1 1 010

(ds,An,Xn) 1 10 reg. number:An (ds,PC,Xn) 1 1 1 01 1

(bd,An,Xn) 1 10 reg. number:An (bd,PC,Xn) 1 1 1 0 1 1

([bd,An,Xnj,od) 1 10 reg. number:An ([bd,PC,Xnj,od) 1 1 1 011

([bd,Anj,Xn,od) 1 10 reg. number:An ([bd,PC],Xn,od) 1 1 1 0 1 1

8-35

II

II

B F EXTU Extract Bit Field Unsigned B F EXTU

Operation: < bi t f ield > of Sou rce - On

Assembler Syntax: BFEXTU < ea > {offsetwidth} ,Dn

Attributes: Unsized

Description: Extract a b it f ield from the specif ied effective address locat ion, zero extend to 32 bits, and load the results i nto the dest i nation data reg ister.

The field select ion is spec if ied by a field offset and field width. The f ield offset denotes the start ing bit of the f ie ld. The f ield width determines the number of bits to be inc luded in the f ield.


1 - 1 * 1 * 1 0 1 0

N Set if the most s ign i f icant bit of the source f ield is set. Cleared otherwise. Z Set if a l l bits of the f ie ld are zero. Cleared otherw ise. V Always cleared. C A lways c leared. X Not affected.

Instruction Format: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0

I 1 I 0 o I 0 I 1 I 1 I Effective Address 1 1 1 1

Mode I Register


Instruction Fields: Effect ive Address f ield - Specif ies the base locat ion for the bit f ie ld. On ly data

reg ister d i rect or control addressing modes are a l lowed as shown below: Register field - Speci fies the dest ination data reg ister. Do field - Determi nes how the field offset is specif ied.

O-the field offset is in the Offset f ie ld. 1 - bits [8:6] of the extension word specify a data reg ister which conta i ns the off

set; b its [1 0:9] are O. Offset f ield - Specif ies the f ield offset, depend ing on Do.

I f Do = O-the Offset f ield is an immediate operand; the operand value is in the range 0-31, specifying a f ield offset of 0-31 .

If Do = 1 -the Offset f ield spec if ies a data reg ister which conta ins the offset. The value is in the range - 231 to 231 - 1 .

8-36

B F EXTU Extract Bit Field Unsigned B F EXTU

Ow field - Determines how the f ield width is spec if ied. O-the field width is in the Width f ield. 1 - bits [2:0] of the extension word specify a data reg ister which contains the

width; bits [4:3] are O. Width f ield - Specif ies the field width, depending on Ow.

If Ow = O-the Width field is an immediate operand; the operand value is in the range 0, 1 ·31 , spec ifying a f ield width of 32, 1 ·31 .

If Ow = 1 -the Width f ie ld specifies a data reg ister which contains the width. The operand val ue is taken modu lo 32, w i th val ues 0, 1 ·31 spec ifying a field width of 32, 1 ·31 .



An - - (xxx).L 1 1 1 001


(An) + - -

- (An) - -

(d1 6,An) 1 01 reg. number:An (d1 6,PC) 1 1 1 010

(dS,An,Xn) 1 10 reg. number:An (dS,PC,Xn) 1 1 1 0 1 1

(bd,An,Xn) 1 10 reg. number:An (bd,PC,Xn) 1 1 1 01 1

([bd,An,Xn),od) 1 10 reg. number:An ([bd,PC,Xn),od) 1 1 1 01 1

([bd,An),Xn,od) 1 10 reg. number:An ([bd,PC),Xn,od) 1 1 1 0 1 1

B·37

•

•

B F F FO Find First One in Bit Field

Operation: < bit f ield > of Source B i t Scan -- On

Assembler Syntax: BFFFO < ea > {offsetwidth) ,Dn


B F F FO

Description: The source operand is searched for the most S igni ficant b i t pos i t ion that contains a set bit . The bit offset (the orig i nal bit offset p lus the offset of the f i rst set b i t) of that bit is then p laced in On. I f no bit of the bit f ield is set, the value p laced i n On i s t h e f ield offset plus f ield width. The cond it ion codes are set accord ing t o the bit f ield operand.

The field selection is specif ied by a f ield offset and field width. The f ield offset denotes the start i ng bit of the field. The f ield width determines the number of bits to be inc luded in the f ield.


1 - 1 * 1 * 1 0 1 0

N Set if the most s ign if icant bit of the f ield is set. Cleared otherwise. Z Set if a l l bits of the f ield are zero. Cleared otherw ise. V Always c leared. C Always c leared. X Not affected.


1 1 1 0 J 0 1 1 1 1 1 Effective Address 1 1 1 1 1 I Mode Register

0 Register Do Offset Ow I Width

Instruction Fields: Effective Address f ield - Specifies the base locat ion for the bit f ield. Only data

reg ister d i rect or control addressing modes are a l lowed as shown below: Register f ie ld - Specifies the dest ination data reg ister operand. Do field - Determines how the field offset is spec ified.

O-the f ield offset is i n the Offset f ie ld . 1 - bits [8:61 of the extension word specify a data reg ister which conta i ns the off

set; bits [1 0:91 are O. Offset f ield - Specif ies the f ield offset, depending on Do.

It Do = O-the Offset f ield is an immed iate operand; the operand value is in the range 0-31 , specify ing a f ield offset of 0-31 .

I f Do = 1 -the Offset f ield spec ifies a data reg ister which contains the offset. The val ue is in the range - 231 to 231 - 1 .

B-38

B F F FO Find First One in Bit Field B F F FO

Dw field - Determi nes how the field width is specif ied. O-the field width is in the Width f ield. 1 - bits [2:0] of the extension word specify a data reg ister which conta ins the

width; bits [4:3] are O. Width f ield - Specif ies the f ield width, depending on Dw.

If Dw = O-the Width field is an i mmediate operand; the operand value is in the range 0, 1 ·31 , spec ify ing a f ield width of 32, 1 ·31 .

I f Dw = 1 -the Width f ie ld specifies a data reg ister which contains the width. The operand value is taken modulo 32, w i th va lues 0, 1 ·31 spec ifying a f ield width of 32, 1 ·31 .



An - - (xxx).L 1 1 1 001


(An) + - -

- (An) - -

(d1 6,An) 1 01 reg. number:An (d16,PC) 1 1 1 010

(dS,An,Xn) 1 10 reg. number:An (ds,PC,Xn) 1 1 1 011


([bd,An,XnJ,od) 1 10 reg. number:An ([bd,PC,XnJ,od) 1 1 1 0 1 1

([bd,AnJ,Xn,od) 1 10 reg. number:An ([bd,PCJ,Xn,od) 1 1 1 0 1 1

8·39

•

•

B FI NS Insert Bit Field

Operation: On -+ < bit f ield > of Dest i nation

Assembler Syntax: BFINS Dn, < ea > (offsetwidth)


B FI NS

Description: M ove a bit f ield from the low-order bits of the specif ied data reg ister to a bit f ield at the specif ied effective address locat ion. The condit ion codes are set accord ing to the i nserted val ue.

The f ield select ion is specif ied by a f ield offset and f ield width. The f ield offset denotes the start i ng bit of the f ield. The f ield width determi nes the number of bits to be i nc luded in the f ie ld.

Condition Codes: x N Z V c

1 - 1 * 1 * 1 0 1 0

N Set if the most s ign if icant b i t of the f ield is set. Cleared otherwise. Z Set if a l l bits of the f ield are zero. Cleared otherwise. V A lways c leared. C A lways c leared. X Not affected.


1 1 1 0 1 1 1 1 1 1 1 1 Effective Address 1 1 1 1 I Register Mode


Instruction Fields: Effective Address f ield - Specif ies the base locat ion for the bit f ield. Only data

reg ister d i rect or alterable control addressing modes are a l lowed as shown below: Register field - Specif ies the source data reg ister operand. Do f ield - Determines how the field offset is spec if ied.

O-the field offset is i n the Offset f ield. 1 - bits [8:61 of the extension word specify a data reg ister which contains the off

set; bits [1 0:91 are O. Offset f ield - Specif ies the f ield offset, depending on Do.

It Do = O-the Offset f ie ld is an i mmediate operand; the operand value is in the range 0-31 , specify ing a f ield offset of 0-31 .

If Do = 1 -the Offset f ield specifies a data reg ister which contains the offset. The value is i n the range - 231 to 231 - 1 .

B-40

B FI NS Insert Bit Field B F I N S

Dw f ie ld - Determi nes how the f ield width is specif ied. O-the f ield width is i n the Width f ield. 1 - bits [2:0] of the extens ion word spec ify a data reg ister which contains the

width; bits [4:3] are 0. Width f ield - Specif ies the f ield width, depend ing on Dw.

If Dw = O-the Width field is an immediate operand; the operand va lue is in the range 0, 1 -31 , specify ing a f ield width of 32, 1 -31 .

I f Dw = 1 -the Width f ield specif ies a data reg ister which contai ns the width. The operand va lue is taken modulo 32, with va lues 0, 1 -31 spec ifying a f ield width of 32, 1 -31 .



An - - (xxx).L 1 1 1 001


(An) + - -

- (An) - -

(d16,An) 1 01 reg. number:An (d16,PC) - -

(ds,An,Xn) 1 1 0 reg. number:An (dS,PC,Xn) - -




8-41

•

•

B FSET Set Bit Field

Operation: 1 s - < bit f ield > of Dest i nation

Assembler Syntax: 8FSET < ea > (offsetwidth)


B FS ET

Description: Set a l l bits of a bit f ie ld at the specif ied effective address locat ion. The cond it ion codes are set accord ing to the value in the f ield before i t is set.

The f ie ld select ion is specif ied by a f ield offset and f ield width. The f ield offset denotes the start i ng bit of the f ield. The f ield width determines the number of bits to be inc luded in the f ield.


1 - 1 * 1 * 1 0 1 0

N Set if the most s ign if icant bit of the f ield is set. Cleared otherw ise. Z Set if a l l bits of the f ield are zero. Cleared otherwise. V Always c leared. C A lways c leared. X Not affected.

Instruction Format: 15 14 13 12 1 1 10 9 8 7 6 5 4 3 2 0 1 1 1 0 1 1 1 Effective Address 1 1 1 0 1 1 1 I Mode Register

0 0 0 0 Do Offset Ow I Width

Instruction Fields: Effective Address f ield - Specifies the base locat ion for the bit f ield. On ly data

reg ister d i rect or alterable control addressing modes are al lowed as shown below: Do field - Determ i nes how the field offset is spec if ied .

O-the f ield offset is i n the Offset f ield. 1 - bits [8:6] of the extension word specify a data reg ister which contains the off

set; bits [1 0:9] are O. Offset f ield - Specif ies the f ield offset, depend ing on Do.

If Do = O-the Offset f ield is an i mmediate operand; the operand va lue is in the range 0-31 , spec ifying a f ield offset of 0-31 .

I f Do = 1 -the Offset f ie ld specif ies a data reg ister which contains the offset. The val ue is i n the range - 231 to 231 - 1 .

8-42

B FSET Set Bit Field B FSET

Dw field - Determi nes how the f ield width is spec if ied. O-the f ield width is i n the Width field. 1 -bits [2:0] of the extension word specify a data reg ister which contains the

width; bits [4:3] are O. Width f ie ld - Specif ies the field width, depend ing on Dw.

If Dw = O-the Width f ield is an immed iate operand; the operand value is in the range 0, 1 ·31 , specifying a f ield width of 32, 1 ·31 .

I f Dw = 1 -the Width field specif ies a data reg ister which contains the width. The operand va lue is taken modulo 32, with values 0, 1 ·31 specify ing a f ield width of 32, 1 ·31 .


Dn 000 reg. number:Dn (xxx)W 1 1 1 000

An - - (xxx).L 1 1 1 001


(An) + - -

- (An) - -

(d16,An) 1 01 reg. number:An (d1 6, PC) - -



(lbd,An,XnJ,od) 1 10 reg. number:An ([bd,PC,Xn],od) - -

([bd,AnJ,Xn,od) 1 10 reg. number:An ([bd,PCJ,Xn,od) - -

8·43

..

•

B FTST Test Bit Field

Operation: < bit f ield > of Dest i nation

Assembler Syntax: 6FTST < ea > [offsetwidth}


B FTST

Description: Extract a b it f ield from the specif ied effective address locat ion, and set the condit ion codes accord ing to the value in the field.

The field selection is specif ied by a f ield offset and f ield width. The f ie ld offset denotes the start ing bit of the f ield. The f ield width determi nes the number of bits to be inc luded in the f ield.


1 - 1 * 1 * 1 0 1 0

N Set if the most S ign i f icant bit of the f ield is set. Cleared otherwise. Z Set if a l l bits of the f ield are zero. Cleared otherwise. V A lways cleared. C A lways c leared. X Not affected.

Instruction Format: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 0 1 0 I 0 1 1 1 Effective Address 1 1 1 0 1 1 I Mode Register

0 0 0 0 Do Offset Ow I Width

Instruction Fields: Effective Address f ie ld - Specif ies the base locat ion for the bit f ie ld. Only data

reg ister d i rect or control address ing modes are a l lowed as shown below: Do f ield - Determ i nes how the f ie ld offset is specif ied .

O-the f ield offset is i n the Offset f ie ld. 1 - bits [8:6] of the extension word specify a data reg ister which conta ins the off

set; bits [1 0:9] are O. Offset f ie ld - Specif ies the f ie ld offset, depending on Do.

I f Do = O-the Offset f ie ld is an immed iate operand; the operand va lue is in the range 0-31 , spec ify ing a f ield offset of 0-31 .

I f Do = 1 -the Offset f ield specif ies a data reg ister which conta ins the offset. The value is in the range - 231 to 231 - 1 .

6-44

B FTST Test Bit Field B FTST

Dw field - Determines how the field width is specif ied. O-the field width is in the Width f ield. 1 - bits [2:0] of the extension word specify a data reg ister which conta ins the

width; bits [4:3] are O. Width f ield - Specif ies the field width, depend ing on Dw.

I f Dw = O-the Width f ield is an immediate operand; the operand value is in the range 0, 1 -31 , spec ifying a f ield width of 32, 1 -31 .

If Dw = 1 -the Width f ield specifies a data reg ister which conta ins the width. The operand value is taken modu lo 32, with values 0, 1 -31 specify ing a f ield w idth of 32, 1 -31 .


Dn 000 reg. number:Dn (xxx).w 1 1 1 000 An - - (xxx).l 1 1 1 001


(An) + - -

- (An) - -

(d16,An) 101 reg. number:An (d1 6,PC) 1 1 1 010 (dS,An,Xn) 1 10 reg. number:An (ds,PC,Xn) 1 1 1 0 1 1 (bd,An,Xn) 1 10 reg. number:An (bd,PC,Xn) 1 1 1 01 1

([bd,An,Xnl,od) 1 10 reg. number:An ([bd,PC,Xnl,od) 1 1 1 01 1 ([bd,Anl,Xn,od) 1 10 reg. number:An ([bd,PC1,Xn,od) 1 1 1 01 1

8-45

•

•

B KPT· Breakpoint

Operation: I f breakpoint vector acknowledged then execute returned operat ion word else Trap as I l legal i nstruction

Assembler Syntax: BKPT # < data >

Attributes: Unsized

B KPT

Description: This i nstruct ion is used to support the program breakpoint function for debug monitors and real-t ime hardware emulators, and the operation w i l l be dependent on the implementat ion. Execution of th is instruction w i l l cause the MC68020 to run a breakpoint acknowledge bus cycle, with the i mmed iate data (val ue 0-7) presented on address l ines A2, A3, and A4, and zeros on address l ines AO and A 1 . Two responses are permitted: normal and except ion.

The normal response to the MC68020 is an operation word (typical ly an i nstruct ion, or ig inal ly replaced by the breakpoint i nstruction) on the data l ines with the DSACKx signal asserted. This operat ion word w i l l then be executed in p lace of the breakpoint instruction.

For the except ion response, a bus error signal w i l l cause the MC68020 to take an i llegal i nstruct ion exception.


Instruction Format: 15 14 13 12 1 1 10 9 8 7 6 5 4 3 2 0 I 0 I 1 I 0 I 0 I 1 0 I 0 I 0 I 0 I 1 0 I 0 I 1 I Vector

Instruction Fields:

Vector field - Specif ies the breakpOint for which the processor is to request the correspond ing operation word .

B-46

B RA

Operation: PC + d - PC

Assembler Syntax: BRA < label >

Branch Always


B RA

Description: Program execution cont i nues at location (PC) + displacement. The disp lacement is a twos complement i nteger, which counts the relative d istance i n bytes. The value i n the P C i s the i nstruction locat ion plus two. I f the 8-bit displacement in the i nstruct ion word is zero, then the 1 6-bit displacement (word immediately fol lowing the instruction) is used. I f the 8-bit d isplacement in the instruction word is al l ones ($FF), then the 32-bit displacement (long word immediately fol lowing the instruction) is used.



o I 1 I 1 I 0 I o I 0 I o I o I 8·Bit Displacement

16-Bit Displacement if 8-BIt Displacement = $00

32-Bit Displacement if 8-Bit Displacement = $FF

Instruction Fields: 8-Bit D isp lacement field - Two complement i nteger specify ing the relative d istance

(in bytes) between the branch i nstruction and the next i nstruct ion to be executed. 1 6-Bit Displacement field - Al lows a larger displacement than 8 bits. Used on ly if

the 8-bit displacement is equal to $00_ 32-Bit Displacement f ield - Al lows a larger displacement than 8 bits_ Used on ly if

the 8-bit displacement is equal to $FF.

Note: A short branch to the i mmediately fol lowing i nstruction cannot be generated because it wou ld result in a zero offset, which forces a word branch i nstruction def in i t ion.

B-47

II

•

BSEl

Operation:

Assembler Syntax:

Attributes:

Test a Bit and Set

- « b it number> of Dest i nation) - Z; 1 - < bit number> of Dest i nation

BSET Dn, < ea > BSET # < data > , < ea >

Size = (Byte, Long)

BSEl

Description: A bit i n the dest i nation operand i s tested, and the state of the spec if ied bit is reflected i n the Z condit ion code. After the test, the specif ied bit is set i n the desti nat ion. I f a data reg ister is the desti nation, then the bit number ing is modu lo 32, a l lowing bit manipu lation on a l l bits in a data reg ister. If a memory locat ion is the dest i nat ion, a byte is read from that locat ion, the bit operat ion performed us ing the bit number, modulo 8, and the byte wri tten back to the location. B i t zero refers to the least s ign i f icant bit . The bit number for this operat ion may be spec if ied in two d ifferent ways: 1 . I mmediate - the bit number is spec if ied in a second word of the i nstruction. 2. Register - the bit number is contai ned in a data reg ister specif ied in the i nstruc

t ion.


1 - I - I * I N Not affected. Z Set if the bit tested is zero. Cleared otherwise. V Not affected. C Not affected. X Not affected.

Instruction Format (B i t N umber Dynam ic, specif ied in a reg ister): 15 14 13 12 1 1 10 9 8 7 6 5 4 3 2 0

Effective Address Register

Mode Register

Instruction Fields (Bit N umber Dynamic): Register field - Specif ies the data reg ister whose content is the bit number. Effective Address f ield - Specif ies the dest i nation locat ion. Only data alterable


B-48

BSET Test a Bit and Set BSET


Dn · 000 reg. number:Dn (xxx)W 1 1 1 000

An - - (xxx).L 1 1 1 001




(d16,An) 101 reg. number:An (d16, PC) - -

(dS,An,Xn) 1 10 reg. number:An (dsPC,Xn) - -


([bd,An,Xn].od) 1 10 reg. number:An ([bd,PC,Xnl,od) - -


• Long only; al l others are byte only.

Instruction Format (Bit N umber Stat ic , specif ied as immed iate data): 15 14 1 3 12 11 10 9 s 7 6 5 4 3 2 o

1 1 1 Effective Address 0 0 0 0 1 0 0 0 1 I Mode Register

0 0 0 0 0 0 0 0 Bit Number

Instruction Fields (Bit Nu mber Stat ic) : Effective Address f ield - Specif ies the dest i nation locat ion. Only data alterable

add ress ing modes are al lowed as shown:


Dn· 000 reg. number:Dn (xxx).w 1 1 1 000

An - - (xxx).L 1 1 1 001





(ds,An,Xn) 1 10 reg. number:An (dS,PC,Xn) - -




• Long only; al l others are byte only.

Bit Nu mber f ield - Specif ies the bit number.

B-49

•

•

BSR Branch to Subroutine

Operation: SP - 4 -+ SP; PC -+ (SP); PC + d -+ PC

Assembler Syntax: BSR < label >


BSR

Description: The long word address of the i nstruction i mmediately fol lowing the BSR i nstruction is pushed onto the system stack. Program execution then cont inues at location (PC) + displacement. The d isplacement i n a twos complement integer which counts the relative d istances i n the bytes. The val ue i n the PC is the instruction locat ion p lus two. If the 8-bit d i splacement in the i nstruction word is zero, then the 1 6-bit d isplacement (word immediately fol lowing the i nstruction) is used. I f the 8-bit d isplacement i n the i nstruction word is al l ones ($FF), then the 32-bit d isplacement ( long word immediately fol lowing the i nstruction) is used.



o I 1 I 1 I o I o I 0 I o I 1 I 8·Bit Displacement

16·Bit Displacement if 8·Bit Displacement = $00

32·Bit Displacement if 8·Bit Displacement = $FF

Instruction Fields: 8-Bit Displacement field - Twos complement i nteger specifying the relat ive

d istance ( in bytes) between the branch i nstruction and the next instruction to be executed.

1 6-Bit Displacement field - Al lows a larger d isplacement than 8 bits. Used only if the 8-bit d isplacement is equal to $00.

32-Bit D isplacement f ield - Al lows a larger d isplacement than 8 bits. Used only i f the 8-bit d isplacement is equal to $FF.

Note: A short subrout ine branch to the immediately fol lowing i nstruct ion cannot be generated because it would resu lt in a zero offset, which forces a word branch i nstruction def in it ion .

B-50

8TST

Operation:

Assembler Syntax:

Attributes:

Test a Bit 8TST

- « bit number> of Dest i nation) - Z;

BTST Dn, < ea > BTST # < data > , < ea >

S ize = (Byte, Long)

Description: A bit in the destination operand is tested, and the state of the specified bit is reflected in the Z cond it ion code. I f a data reg ister is the destination, then the bit numbering is modu lo 32, al lowing bit manipu lation on a l l bits i n a data reg ister. I f a memory location is the dest ination, a byte is read from that locat ion, and the bit operat ion performed using the bit number, modu lo 8, with zero referring to the least s ign if icant bit. The bit number for th is operat ion may be specified in two d i fferent ways: 1 . Immediate - the bit number is spec if ied in a second word of the instruction. 2. Register - the bit number is contained in a data reg ister spec if ied in the

i nstruct ion.


I - I - I * I - I N Not affected. Z Set if the bit tested is zero. Cleared otherw ise. V Not affected. C Not affected. X Not affected.

Instruction Format (Bit N umber Dynam ic, spec ified in a reg ister): 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0

Register

Dn

Instruction Fields (Bit Number Dynamic):

Effective Address

Mode Register

Register f ield - Specif ies the data reg ister whose content is the bit number. Effective Address f ield - Specif ies the desti nation locat ion. On ly data addressing

modes are al lowed as shown:

B-51

II

•

8TST Test a Bit 8TST


On * 000 reg. number:On (xxx).W 1 1 1 000 An - - (xxx).L 1 1 1 001

(An) 010 reg. number:An # < data > 1 1 1 1 00



(d1 6,An) 101 reg. number:An (d1 6,PC) 1 1 1 010 (dS,An,Xn) 1 1 0 reg. number:An (dSPC,Xn) 1 1 1 0 1 1


([bd,An,Xn),od) 1 1 0 reg. number:An ([bd,PC,Xn],od) 1 1 1 0 1 1

([bd,An),Xn,od) 1 10 reg. number:An ([bd,PC],Xn,od) 1 1 1 0 1 1

* Long only; al l others are byte only.

Instruction Format (Bit N u mber Stat ic, spec if ied as i mmediate data): 15 14 13 12 1 1 10 9 s 7 6 5 4 3 2 o

I I Effective Address 0 0 0 0 1 0 0 0 0 0

I Mode Register

0 0 0 0 0 0 0 0 Bit Number

Instruction Fields (Bit N u mber Stat ic): Effective Address f ield - Specif ies the dest ination locat ion. On ly data addressing



On * 000 reg. number:On (xxx).w 1 1 1 000

An - - (xxx).L 1 1 1 001




(d1 6,An) 101 reg. number:An (d1 6,PC) 1 1 1 010

(ds,An,Xn) 1 1 0 reg. number:An (ds,PC,Xn) 1 1 1 011


([bd,An,Xn),od) 1 10 reg. number:An ([bd,PC,Xn),od) 1 1 1 0 1 1

([bd,An),Xn,od) 1 10 reg. number:An ([bd,PC),Xn,od) 1 1 1 01 1

* Long only; al l others are byte only .

Bit Number f ield - Specif ies the bit number.

B-52

CAL L M CALL Module

Operation: Save current module state on stack; Load new module state from dest ination

Assembler Syntax: CALLM # < data > , < ea >


CAL L M

Description: The effective address of the i nstruction is the locat ion of an external module descriptor. A modu le frame is created on the top of the stack, and the current module state is saved i n the frame. The i mmediate operand specif ies the number of bytes of arguments to be passed to. the cal led modu le. A new module state is loaded from the descri ptor addressed by the effective address. Add it ional i nformat ion is presented i n Appendix D.


Instruction Format: 15 14 13 12 1 1 10 9 s 7 6 5 4 3 2 o 1 1 1 Effective Address 0 0 0 0 0 1 1 0 1 J Mode Register

0 0 0 0 0 0 0 0 Argument Count

Instruction Fields: Effective Address field - Specif ies the address of the module descr iptor. Only con

trol addressing modes are al lowed as shown:


On - - (xxx),W 1 1 1 000

An - - (xxx).L 1 1 1 001


(An) + - -

- (An) - -


(ds,An,Xn) 1 10 reg. number:An (ds,PC,Xn) 1 1 1 0 1 1




Agrument Count f ie ld - Specif ies the nu mber of bytes of arguments to be passed to the cal led modu le. The 8-bi t f ield can specify from 0 to 255 bytes of argu ments. The same number of bytes is removed from the stack by the RTM i nstruction.

8-53

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•

CAS CAS2 Compare and Swap with Operand

Operation: CAS Dest i nat ion - Compare Operand -- cc; i f Z, Update_Operand -- Dest i nation

Assembler Syntax:

Attributes:

else Dest ination -- Compare_Operand

CAS2 Dest i nat ion 1 - Compare 1 -- cc; i f Z, Dest i nat ion 2 - Compare 2 -- cc

if Z, Update 1 -- Dest i nation 1 Update 2 -- Dest i nation 2 else Dest i nat ion 1 -- Compare 1 Dest i nation 2 -- Compare 2

CAS Dc, Du, < ea > CAS2 Dc1 : Dc2, Du1 : Du2,(Rn1):(Rn2)

Size = (Byte· , Word, Long)

CAS CAS2

Description: The Effective Address operand(s) is fetched and compared to the compare operand data reg ister(s). If the operands match, the update operand data reg ister(s) is (are) written to the dest ination locat ion(s); otherwise, the memory operand locat ion is left unchanged and the compare operand is loaded with the memory operand. The operat ion is i ndiv isible (using a read-modify-write memory cycle) to al low synchron izat ion of several processors. Addit ional informat ion is presented i n Appendix D_


1 - 1 · 1 · 1 * 1 * 1 N Set if the resu l t is negat ive. Cleared otherw ise. Z Set if the resu l t is zero. Cleared otherwise. V Set if an overflow is generated. Cleared otherwise. C Set if a carry is generated. Cleared otherwise. X Not affected.

Instruction Format: (Sing le Operand): 15 1 4 13 1 2 11 10 9 8 7 6 5 4 3 2 0

o I 1 I Effective Address 0 0 0 0 1 Size 1 I Mode Register

0 0 0 0 0 0 1 0 Du o I 0 I 0 I Dc

Instruction Fields: Size f ield - Specif ies the s ize of the operation.

01 -byte operat ion. 10-word operat ion. 1 1 - long operation.

Effective Address f ie ld - Specif ies the locat ion of the tested operand. Only alterable memory addressing modes are al lowed as shown below:

Du field - Specif ies the data reg ister which holds the update va lue to be wri tten to the memory operand locat ion i f the comparison is successfu l .

---

·S ing le Operand Form Only B-54

CAS CAS2 Compare and Swap with Operand

CAS CAS2

Dc field - Specif ies the data reg ister which conta ins the test value to be compared against the memory operand.

Addr. Mode Mode Register Addr. Mode

On - - (xxx).w

An - - (xxx).l

(An) 010 reg. number:An # < data >



(d16,An) 101 reg. number:An (d16, PC)

(ds,An,Xn) 1 10 reg. number:An (ds,PC,Xn)

(bd,An,Xn) 1 10 reg. number:An (bd,PC,Xn)

([bd,An,Xn],od) 1 10 reg. number:An ([bd,PC,Xn],od)

([bd,An],Xn,od) 1 10 reg. number:An ([bd,PC],Xn,od)

Instruction Format (Dual Operand): 15 1 4 13 12 11 10 9 s 7 6 5 4

0 o I 0 I 0 1 Size o I 1 I 1 1 1

O/A1 Rn1 0 0 1 0 Ou1 0 0

O/A2 Rn2 0 o I 0 Ou2 0 0

Instruction Fields: Size f ield - Specif ies the s ize of the operation.

10-word operat ion. 1 1 - long operat ion.

Mode Register

1 1 1 000

1 1 1 001 - -

- -

- -

- -

- -

- -

3 2 o 1 1 0 0

0 Oc1

0 Oc2

D/A 1 , D/A2 f ie lds - Specify whether Rn1 and Rn2 reference data or address reg isters, respect ively. 0-The correspond ing reg ister is a data reg ister. 1 -The correspond ing reg ister is an address reg ister.

Rn1 ,Rn2 fields - Specify the numbers of the reg isters which conta in the address of the f i rst and second tested operands, respectively. If the operands overlap i n memory, the resu lts o f any memory update are undefi ned.

Du1 , Du2 f ields - Specify the data reg isters which hold the update va lues to be writ- a. ten to the f i rst and second memory operand locations i f the comparison is successfu l .

Dc1 ,Dc2 f ie lds - Specify the data reg isters which contai n the test va lues to be compared against the f i rst and second memory operands, respectively. I f Dc1 and Dc2 specify the same data reg ister and the comparison fai ls, the data reg ister is loaded from the f i rst memory operand.

Programming Note: The CAS and CAS2 i nstructions may be used to perform secure update operat ions on system control data structu res i n a mu lt i processing environment.

8-55

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C H K Check Register Against Bounds

Operation: I f On < 0 or On > Source then TRAP

Assembler Syntax: CHK < ea > ,On


C H K

Description: The content of the data register specified in the instruction is exami ned and compared to the upper bound. The upper bound is a twos complement integer. If the register value is less than zero or greater than the upper bound, then the processor in it iates exception processing. The vector number is generated to reference the CHK instruction except ion vector.


I * I u I u I u

N Set if On < 0; c leared if O n > Source. Undefi ned otherwise. Z U ndefined. V U ndefined. C Undefined. X Not affected.


Instruction Fields:

Register

Dn Size

Effective Address

Mode Register

Register f ield - Specif ies the data register whose content is checked. Size field - Specifies the size of the operation.

1 1 0-word operation. 1 00- long operation.

Effective Address field - Specifies the upper bound operand word. On ly data addressing modes are al lowed as shown:

8-56

C H K Check Register Against Bounds C H K



An - - (xxx).L 1 1 1 001

(An) 010 reg. number:An I# < data> 1 1 1 100



(d16,An) 101 reg. number:An (d16,PC) 1 1 1 010

(ds,An,Xn) 1 1 0 reg. number:An (dSPC,Xn) 1 1 1 01 1


([bd,An,Xn),od) 1 1 0 reg. number:An ([bd,PC,Xnj,od) 1 1 1 0 1 1

([bd,Anj,Xn,od) 1 1 0 reg. number:An ([bd,PC],Xn,od) 1 1 1 0 1 1

•

8-57

•

C H K2 Check Register Against Bounds

Operation: I f Rn < Sou rce-lower-bound or

Assembler

Rn > Source- upper-bound Then TRAP

Syntax: CHK2 < ea > ,Rn


C H K2

Description: Check the value i n Rn against the bounds pai r at the effective address locat ion. The lower bound is at the address spec ified by the effective address, with the upper bound at that address plus the operand length. For s igned comparisons, the arithmet ical ly smaller value should be the lower bound, wh i le for u nsigned comparison, the logical ly smal ler val ue should be the lower bound.

The s ize of the data to be checked, and the bounds to be used, may be spec if ied as byte, word, or long. I f the checked reg ister is a data reg ister and the operation size is byte or word, only the appropriate low-order part of Rn is checked. I f the checked reg ister is an address reg ister and the operat ion s ize is byte or word, the bou nds operands are sign-extended to 32 bits and the resu ltant operands compared against the fu l l 32 bits of An.

I f the upper bound equals the lower bound, then the valid range is a single value. If the reg ister operand is out of bounds, the processor in i t iates except ion processing. The vector number is generated to reference the CH K i nstruction except ion vector. Otherwise, the next instruction is executed.


1 - l u l * l u * 1 N U ndefi ned. Z Set if Rn is equal to either bound. Cleared otherwise. V U ndefi ned. C Set if Rn is out of bounds. Cleared otherwise. X Not affected .


o I 0 I 0 Effective Address 0 0 Size 0 1 1 I Mode Register

D/A Register 1 0 1 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0

B-58

C H K2 Check Register Against Bounds

Instruction Fields: Size field - Specif ies the s ize of the operation.

�O- byte operation. 0 1 - word operation. 1 0- long operat ion.

C H K2

Effective Address f ield - Specif ies the location of the bounds operands. On ly cont rol address ing modes are al lowed as shown below: D/A f ield - Specif ies whether an address reg ister or data reg ister is to be

checked. O- Data reg ister. 1 -Address reg ister.

Reg i ster f ield - Specifies the address or data reg ister whose content is to be checked.


On - - (xxx).W 1 1 1 000

An - - (xxx).L 1 1 1 001


(An) + - -

- (An) - -


(da,An,Xn) 1 10 reg. number:An (da,PC,Xn) 1 1 1 0 1 1



([bd,AnJ,Xn,od) 1 10 reg. number:An ([bd,PC].Xn,od) 1 1 1 0 1 1

8-59

II

•

C L R

Operation: 0 - Dest i nation

Assembler Syntax: CLR < ea >

Clear a n Operand


C L R

Description: The dest i nat ion is cleared to a l l zero. The s ize of the operat ion may be specif ied to be byte, word, or long.

Condition Codes: x N x V c

1 - I 0 I 1 0 0 I N Always c leared. Z Always set. V Always c leared. C Always c leared . X Not affected.

Instruction Format: 1 5 1 4 1 3 1 2 1 1 10 9 a 7 6 5

Instruction Fields: Size f ie ld - Specif ies the s ize of the operation.

OO-byte operat ion. 01 -word operat ion. 10- long operat ion.

4 3 2

Effective Address

Mode Register

o

Effective Address f ield - Specif ies the dest i nation locat ion. Only data alterable address ing modes are a l lowed as shown:



An - - (xxx).L 1 1 1 001





(da,An,Xn) 1 1 0 reg. number:An (da,PC,Xn) - -




B-60

C M P

Operation: Dest i nat ion - Sou rce

Assembler Syntax: CMP < ea > , Dn


Compare C M P

Description: Subtract the sou rce operand from the spec if ied data reg ister and set the cond it ion codes accord i ng to the resu l t; the data reg ister is not changed. The s ize of the operation may be byte, word, or long.


1 - 1 · 1 · 1 · 1 · 1 N Set if the resu l t is negat ive. Cleared otherwise. Z Set if the resu l t is zero. Cleared otherwise. V Set if an overflow is generated. Cleared otherw ise. C Set if a borrow is generated. Cleared otherwise. X Not affected.


Instruction Fields:

Register

On Op·Mode

Effective Address

Mode Register

Register f ield - Specif ies the dest i nat ion data reg ister. Op-Mode field -

Byte Word Long Operation 000 001 0 10 Dn - ( < ea > )

Effective Address f ie ld - Specif ies the source operand. A l i addressing modes are al lowed as shown:

B-61

•

•

C M P Compare C M P


Dn 000 reg. number:Dn (xxx).w 1 1 1 000

An * 001 reg. number:An (xxx).L 1 1 1 001





(de,An,Xn) 1 10 reg. number:An (de,PC,Xn) 1 1 1 0 1 1


([bd,An,Xnl,od) 1 10 reg. number:An ([bd,PC,Xnl,od) 1 1 1 01 1

([bd,AnJ,Xn,od) 1 10 reg. number:An ([bd,PCJ,Xn,od) 1 1 1 01 1

* Word and Long only.

Note: C M PA is used when the dest i nation is an address register. CMPI is used when the source is i mmediate data. CMPM is used for memory to memory compares. Most assemblers automat ical ly make th is dist i nction.

8·62

C M PA

Operation: Dest i nat ion - Source

Assembler Syntax: CMPA < ea > ,An


Compare Address C M PA

Description: Subtract the source operand from the desti nat ion address reg ister and set the condit ion codes accord ing to the resu lt; the address reg ister is not changed. The s ize of the operation may be specified to be word or long. Word length source operands are s ign extended to 32-bit quant i t ies before the operation is done.


1 - 1 * 1 * 1 * 1 * N Set if the resu l t is negat ive. Cleared otherw ise. Z Set i f the resu l t is zero. C leared otherwise. V Set if an overflow is generated. Cleared otherwise. C Set if a borrow is generated. Cleared otherw ise. X Not affected.


Instruction Fields:

Register

An Op·Mode

Regi ster f ield - Specifies the dest i nation data reg ister. Op-Mode field - Specif ies the size of the operat ion:

Effective Address

Mode Register

01 1 -word operat ion. The source operand is s ign-extended to a long operand and the operat ion is performed on the address reg ister using a l l 32 bits.

1 1 1 - long operat ion. Effective Address f ield - Specif ies the source operand. Al l addressing modes are

al lowed as shown:

8-63

•

C M PA Compare Address C M PA








(dB,An,Xn) 1 10 reg. number:An (dB,PC,Xn) 1 1 1 0 1 1



([bd,AnJ,Xn,od) 1 1 0 reg. number:An ([bd,PCJ,Xn,od) 1 1 1 0 1 1

•

8-64

C M PI Compare Immediate

Operation: Dest i nation - Immediate Data

Assembler Syntax: CMPI # < data > , < ea >


C M PI

Description: Subtract the immediate data from the dest i nation operand and set the cond i t ion codes accord ing to the resu lt; the dest i nation locat ion is not changed. The s ize of the operation may be specif ied to be byte, word, or long. The s ize of the immediate data matches the operation s ize.

Condition Codes: x N Z V c 1 - 1 * 1 * 1 * * 1

N Set if the resu l t is negat ive. Cleared otherwise. Z Set if the resu l t is zero. Cleared otherwise. V Set if an overflow is generated . Cleared otherw ise. C Set if a borrow is generated . Cleared otherw ise. X Not affected.

Instruction Format: 15 14 13 12 1 1 10 9 8 7 6 5 4 3 2 0 o 1 0 1 0 I 0 I 1 I 1 I 0 I 0 Size I

Word Data

Long Data

Instruction Fields: Size f ield - Specif ies the s ize of the operat ion:

OO- byte operat ion. 01 -word operation. 1 0- long operat ion.

Effective Address

Mode I Register

Byte Data

Effective Address f ie ld - Specif ies the dest i nation operand. Only data address ing modes are al lowed as shown:

B-65

• ,

•

C M PI Compare Immediate C M PI

Addr. Mode Mode Register Addr. Mode Mode Register On 000 reg. number:On (xxx).W 1 1 1 000

An - - (xxx).L 1 1 1 001




(d1 6,An) 1 01 reg. number:An (d1 6,PC) 1 1 1 010 (da,An,Xn) 1 10 reg. number:An (da,PC,Xn) 1 1 1 0 1 1 (bd,An,Xn) 1 1 0 reg. number:An (bd,PC,Xn) 1 1 1 0 1 1

([bd,An,Xnj,od) 1 10 reg. number:An ([bd,PC,Xnj,od) 1 1 1 0 1 1

([bd,Anj,Xn,od) 1 1 0 reg. number:An ([bd,PC],Xn,od) 1 1 1 0 1 1

Immediate f ield - (Data immediately fol lowing the instruct ion): If s ize = 00, then the data is the low order byte of the immediate word. I f size = 01 , then the data is the ent ire immediate word. If size = 1 0, then the data is the next two i mmed iate words.

8·66

C M P M

Operation: Destination - SOurce

Assembler Syntax: CMPM (Ay) + ,(Ax) +

Compare Memory


C M P M

Description: Subtract the source operand from the dest i nation operand, and set the cond it ion codes accord ing to the resu l ts; the dest i nation location is not changed. The operands are always addressed with the posti ncrement addressing mode, us ing the address reg isters specif ied in the i nstruct ion. The size of the operat ion may be spec if ied to be byte, word, or long.


1 - 1 * 1 * 1 * 1 * N Set if the result is negat ive. Cleared otherwise. Z Set if the resu l t is zero. Cleared otherw ise. V Set if an overflow is generated. Cleared otherwise. C Set if a borrow is generated. Cleared otherwise. X Not affected.


I nstruction Fields:

1 1 10 9

Register

Ax

8 7 6

Size

5 4 3 2 0

Register

Ay

Register Ax field - (always the dest i nat ion) Spec if ies an address reg ister for the post i ncrement addressing mode.

S ize field - Specifies the s ize of the operation: �O-byte operat ion. 01 -word operat ion. 10- long operation.

Register Ay f ield - (always the source) Spec if ies an address reg ister for the post i ncrement address ing mode.

B-67

--

•

C M P2 Compare Register Against Bounds

Operation: Compare An < Source- lower-bou nd or A n > Source- upper-bou nd

and Set Cond it ion Codes

Assembler Syntax: C M P2 < ea > ,An


C M P2

Description: Compare the va lue i n An against the bounds pai r at the effective address location and set the cond it ion codes accord ing ly. The lower bou nd is at the address specif ied by the effect ive address, with the upper bound at that address p lus the operand length. For s igned comparisons, the arithmet ical ly smal ler value should be the lower bound, wh i le for u ns igned comparison, the logica l ly smal ler value should be the lower bound.

The s ize of the data to be compared, and the bou nds to be used, may be spec if ied as byte, word, or long. I f the compared reg ister is a data reg ister and the operation size is byte or word, on ly the appropriate low-order part of Dn is checked. I f the checked reg ister is an address reg ister and the operation s ize is byte or word, the bounds operands are S ign-extended to 32 bits and the resu ltant operands compared against the fu l l 32 bits of An.

I f the upper bou nd equals the lower bound, then the va l id range is a s ing le value.

NOTE: This i nstruction is analougous to C H K2, but avoids causing except ion process ing to hand le the out-of-bou nds case.


1 - l u l * l u * 1 N Undefi ned. Z Set if An is equal to either bou nd. Cleared otherwise. V Undefi ned. C Set if An is out of bounds. Cleared otherwise . X Not affected.


o I 0 I 0 Effective Address 0 0 Size 0 1 1 1 Mode Register

D/A Register 0 0 1 0 0 0 0 0 1 0 1 0 [ 0 1 0 1 0

B-68

C M P2 Compare Register Against Bounds

Instruction Fields: Size field - Specifies the s ize of the operat ion.

OO-byte operat ion. 01 -word operation. 1 0- long operat ion.

C M P2

Effective Address field - Specifies the location of the bou nds pair. Only control addressing modes are al lowed as shown:


Dn - - (xxx).w 1 1 1 000

An - - (xxx).L 1 1 1 001

(An) 010 reg. number:An lI < data > - -

(An) + - -

- (An) - -

(d1 6,An) 1 01 reg. number:An (d16, PC) 1 1 1 010





D/A f ie ld - Specifies whether an address reg ister or data reg ister is to be compared. O- Data reg ister. 1 -Address reg ister.

Register f ield - Specifies the address or data reg ister whose content is to be checked.

8-69

•

•

cp Bcc Branch on Coprocessor Condition

Operation: I f cpcc true then PC + d - PC

Assembler Syntax: cpBcc < label >


cp Bcc

Description: If the specif ied coprocessor condit ion is met, program execution cont i nues at location (PC) + displacement. The d isplacement is a twos complement i nteger which counts the relat ive d istance in bytes. The value in the PC is the address of the d isplacement word(s). The disp lacement may be either 16 bits or 32 bits. The copro· cessor determi nes the spec if ic cond it ion from the cond it ion f ield i n the operat ion word.



1 I 1 I 1 I 1 I Cp·ld I 0 J 1 I W/L I Coprocessor Condition


Word or

Long Word Displacement

Instruction Fields: Cp·ld field - Identif ies the coprocessor that is to process th is operat ion. W/L f ield - Specif ies the size of the d isp lacement.

O-the d isplacement is 16 bits. 1 -the displacement is 32 bits.

Coprocessor Cond it ion f ield - Specif ies the coprocessor cond it ion to be tested. This field is passed to the coprocessor, which provides d i rectives to the main processor for processing th is instruction.

1 6·Bit Displacement f ield - The shortest d isplacement form for coprocessor branches is 16 bits.

32·Bit Displacement field - Al lows a disp lacement larger than 1 6 bits .

B·70

cp D Bcc Test Coprocessor Condition Decrement and Branch cp D Bcc

Operation: If cpcc false then (Dn - 1 - Dn; I f Dn * - 1 then PC + d - PC) l

Assembler Syntax:

Attributes:

cpDBcc Dn, < label >

S ize = (Word)

Description: If the specif ied coprocessor cond it ion is met, execut ion continues with the next i nstruction. Otherwise, the low order word in the specif ied data reg ister is decremented by one. I f the resu lt is equal to - 1 , execut ion cont i nues with the next i nstruction. I f the resu lt is not equal to - 1 , execution continues at the locat ion i ndicated by the current value of PC p lus the s ign extended 1 6-bit d isplacement. The value in the pC is the address of the displacement word. The coprocessor determ i nes the specif ic condit ion from the condit ion word which follows the operation word.


Instruction Format: 15 14 13 12 1 1 10 9 8 7 6 5 4 3 2 0 1 1 1 1 1 1 1 1 Cp·ld 1 0 1 0 1 1 1 0 1 0 1 1 1 Register

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Coprocessor Condition


Displacement

Instruction Fields: Cp-Id f ield - Ident if ies the coprocessor that is to process th is operat ion. Register f ield - Specif ies the data reg ister which is the counter. Coprocessor Condit ion f ie ld - Specif ies the coprocessor cond it ion to be tested .

Th is f ield is passed to the coprocessor, which provides d i rectives to the main processor for processing this i nstruction.

Disp lacement f ield - Specif ies the d istance of the branch ( in bytes) .

8-71

•

•

cpG E N Coprocessor General Function

Operation: Pass Command Word to Coprocessor

Assembler

cpG E N

Syntax: cpG EN < parameters as defi ned by coprocessor >


Description: This i nstruction is the form used by coprocessors to spec ify the general data processing and movement operations. The coprocessor determ ines the specif ic operation f rom the command word which fol lows the operation word. Usual ly a coprocessor def ines specif ic i nstances of this i nstruction to provide its i nstruction set.

Condition Codes: May be modi f ied by coprocessor. Unchanged otherwise.


I 1 I 1 I 1 I I 0 I 0 I 0 I Effective Address 1 Cp·ld

Mode I Register

Coprocessor Command


Instruction Fields: Cp-Id f ield - Identif ies the coprocessor that is to process th is operat ion. Effective Address f ie ld - Specif ies the locat ion of any operand outside the

coprocessor. The al lowable addressing modes are determi ned by the operation to be performed.

Coprocessor Command f ie ld - Specif ies the coprocessor operat ion to be performed. This word is passed to the coprocessor, which provides d i rectives to the main processor for proceSS ing th is i nstruction .

8-72

cp R ESTO R E Coprocessor Restore Functions cpR ESTO R E (Privileged Instruction)

Operation: Restore I nternal State of Coprocessor

Assembler Syntax: cpRESTORE < ea >

Attributes: Unsized

Description: This i nstruct ion is used to restore the i nternal state of a coprocessor.


Instruction Format: 15 14 13 12 1 1 10 9 s 7 6 5 4 3 2 o

Effective Address Cp·ld

Mode Register

Instruction Field: Cp-Id field - Identif ies the coprocessor that is to be restored. Effective Address field - Specif ies the locat ion where the i nternal state of the co

processor is located. Only post i ncrement or control addressing modes are al lowed as shown:


Dn - - (xxx).w 1 1 1 000

An - - (xxx).L 1 1 1 00.1


(An) + 011 reg. number:An

- (An) - -

(d16,An) 1 01 reg. number:An (d16,PC) 1 1 1 010



([bd,An,XnJ,od) 1 10 reg. number:An ([bd,PC,XnJ,od) 1 1 1 01 1

([bd,AnJ,Xn,od) 1 1 0 reg. number:An ([bd,PCJ,Xn,od) 1 1 1 01 1

Programmer's Note: I f the format word returned by the coprocessor indicates "come again" , pending i nterrupts are not serviced.

8-73

•

•

cpSAVE Coprocessor Save Function (Privileged Instruction)

Operation: Save I nternal State of Coprocessor

Assembler Syntax: cpSA VE < ea >


cpSAV E

Description: This i nstruction is used to save the i nternal state of a coprocessor.


Instruction Format:

Instruction Fields:

1 1 10 9

Cp·ld

s 7 6 5 4 3 2

Effective Address

Mode Register

Cp-Id f ield - Identif ies the coprocessor that is to save its state.

o

Effective Address f ield - Specif ies the locat ion where the i nternal state of the coprocessor is to be saved. On ly predecrement or a lterable control address ing modes are a l lowed as shown:


Dn - - (xxx)W 1 1 1 000

An - - (xxx).l 1 1 1 001


(An) + - -





([bd,An,Xn),od) 1 10 reg. number:An ([bd,PC,Xn),od) - -

([bd,An),Xn,od) 1 10 reg. number:An ([bd,PC),Xn,od) - -

8-74

cpScc Set o n Coprocessor Condition

Operation: I f cpcc t rue then 1 s - Destination else Os - Destination

Assembler Syntax: cpScc < ea >


cpScc

Description: The specif ied coprocessor condit ion code is tested; if the cond ition is t rue, the byte specif ied by the effective address is set to TRUE (al l ones), otherwise that byte is set to FALSE (al l zeros). The coprocessor determines the specif ic cond i t ion from the cond it ion word which fol lows the operat ion word.


Instruction Format: 15 14 13 1 2 1 1 10 9 a 7 6 5 4 3 2 o

Effective Address 1 1 1 1 Cp·ld 0 0 1 1 Mode Register

0 0 0 0 o I o I 0 0 0 0 Coprocessor Condition


Instruction Fields: Cp-Id f ield - Identif ies the coprocessor that is to process th is operat ion. Effect ive Address field - Specif ies the dest ination locat ion. Only data alterable

addressing modes are a l lowed as shown:


Dn 000 reg. number:Dn (xxx).w 1 1 1 000 An - - (xxx).L 1 1 1 001




(d16,An) 1 01 reg. number:An (d1 6, PC) - -



([bd,An,Xn],od) 1 10 reg. number:An ([bd,PC,Xn],od) - -

([bd,An],Xn,od) 1 10 reg. number:An ([bd,PC),Xn,od) - -

Coprocessor Cond it ion f ie ld - Specif ies the coprocessor cond it ion to be tested . This f ield is passed to the coprocessor, which provides d i rect ives to the main processor for processing this instruction.

B-75

•

•

cpT RAPcc Trap on Coprocessor Condition

Operation:

Assembler Syntax:

Attributes:

If cpcc t rue then TRAP

cpTRAPcc cpTRAPcc # < data >

Uns ized or Size = (Word, Long)

cpTRAPcc

Description: I f the selected coprocessor cond it ion is true, the processor i n it iates except ion process i ng. The vector number is generated to reference the cpTRAPcc except ion vector, the stacked program counter is the address of the next instruct ion. I f the selected cond it ion i s not true, no operation is performed, and execution cont in ues with the next i nstruct ion. The coprocessor determ i nes the specif ic cond it ion from the condit ion word which fol lows the operat ion word . Fol lowing the cond it ion word is a user-def i ned data operand spec if ied as immediate data data, to be used by the t rap hand ler.


Instruction Format: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 1 1 1 1 1 1 1 1 Cp-Id 1 0 1 0 1 1 1 1 1 1 1 '1 I Op·Mode

o 1 0 1 o 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Coprocessor Condition


Optional Word or Long Word Operand

Instruction Fields: Cp- Id f ield - Ident if ies the coprocessor that is to process th is operat ion. Op-Mode f ield - Selects the i nstruction form.

01O-i nstruct ion is fol lowed by one operand word . 01 1 - l nstruction is fol lowed by two operand words. 1 00-l nstruction has no fol lowinQ operand words.

Coprocessor Condit ion field - Specif ies the coprocessor cond it ion to be tested. This f ield is passed to the coprocessor, which provides d i rect ives to the main processor for processi ng th is i nstruction .

8-76

O Bee Test Condition, Decrement, and Branch O Bee

Operation: If cond it ion false then (Dn - 1 - Dn; I f Dn :;:. - 1 then PC + d - PC)

Assembler Syntax: OSce On, < label >


Description: This i nstruction is a looping prim it ive of three parameters: a condit ion, a counter (data reg ister), and a displacement. The instruction f i rst tests the cond it ion to determine i f the termination condition for the loop has been met, and if so, no operat ion is performed. I f the termination cond it ion is not t rue, the low order 16 bits of the counter data reg ister are decremented by one. I f the resu l t is - 1 , the counter is exhausted and execution cont inues with the next i nstruction. I f the resu l t is not equal to - 1 , execution cont i nues at the locat ion i nd icated by the current value of the PC plus the s ign-extended 1 6-bit d isplacement. The value in the PC is the current i nstruction location plus two.

"cc" may specify the fol lowing cond it ions:

cc carry clear 0100 C CS carry set 0101 C EQ equal 01 1 1 Z F never true 0001 0 GE greater or equal 1 100 N . V + N.Y GT greater than 1 1 10 N.V.Z+ N.V.Z HI high 0010 C·z LE less or equal 1 1 1 1 Z + N .V+ N.V


Instruction Format:

Instruction Fields:

1 1 10 9 Condition

8

Displacement

LS LT M I N E PL T VC VS

low or same 001 1 C + Z less than 1 101 N .V + N.V minus 101 1 N not equal 01 10 Z plus 1010 N always true 0000 1 overflow clear 1000 V overflow set 1001 V

2 o Register

Condit ion f ield - One of the sixteen condit ions d iscussed in description . Register f ie ld - Specifies the data reg ister which is the counter. Displacement f ie ld - Specifies the d istance of the branch ( i n bytes).

Notes: 1 . The term inat i ng condit ion is l i ke that defined by the UNTI L loop constructs of h igh-level languages. For example: DBMI can be stated as "decrement and branch unt i l m inus".

B-77

•

•

D Bee Test Condition, Decrement, and Branch D Bee

2. M ost assemblers accept OBRA for OBF for use when no condition is requ i red for termi nation of a loop.

3. There are two basic ways of entering a loop: at the beg inn ing or by branching to the tra i l ing OBcc instruction. I f a loop structure terminated with OBcc is entered at the beg i nn ing, the control index count must be one less than the number of loop executions desired. This count is useful for i ndexed addressing modes and dynamically specified bit operations. However, when enteri ng a loop by branching d i rect ly to the trai l i ng OBcc instruction, the control index should equal the loop execution count. I n this case, if a zero count occurs, the OBcc instruction w i l l not branch, causing a complete bypass of the main loop.

B-78

DIVS DIVSL Signed Divide

Operation: Dest i nat ion/Source - Dest i nation

Assembler Syntax:

DIVS.W < ea > ,Dn DIVS. L < ea > , Dq DIVS. L < ea > ,Dr:Dq D IVSL. L < ea > , Dr: Dq

Attrib4tes: Size = (Word, Long)

32/16 - 1 6r: 1 6q 32/32 - 32q 64/32 - 32r:32q 32/32 - 32r:32q

DIVS DIVS L

Description: Divide the desti nation operand by the source and store the result i n the destination. The operation is performed using s igned arithmetic.

The i nstruct ion has a word form and three long forms. For the word form, the dest i nation operand is a long word and the source operand is a word. The resu l t is 32·bits, such that the quotient is in the lower word ( least s ign i f icant 16 bits) of the dest i nation and the remai nder is in the upper word (most s ign if icant 16 bits) of the dest i nation. Note that the s ign of the remainder is the same as the s ign of the d ividend.

For the f i rst long form, the dest inat ion operand is a long word and the source operand is a long word. The resu l t is a long quotient, and the remainder is d iscarded.

For the second long form, the dest i nation operand is a quad word, contained in any two data reg isters, and the sou rce operand is a long word. The resu l t is a long word quotient and a long word remainder.

For the th i rd long form, the dest i nation operand is a long word and the sou rce operand is a long word. The resu lt is a long word quotient and a long word remai nder.

Two specia l cond it ions may arise during the operat ion: 1 . D ivision by zero causes a trap. 2. Overlow may be detected and set before completion of the instruction. If overflow

is detected, the condition is f lagged but the operands are u naffected.


1 - 1 * 1 * 1 * 1 0

N Set if the quotient i s negat ive. Cleared otherwise. Undefi ned if overf low or d ivide by zero.

Z Set if the quotient is zero. Cleared otherw ise. U ndefined if overflow or divide by zero.

V Set if d iv ision overflow is detected. Cleared otherwise. C Always c leared. X Not affected.

8·79

II

•

DIVS DIVSL

Instruction Format (word form): 15 1 4 1 3 1 2 11 10 9

Instruction Fields:

Register

Dn

Signed Divide

5 4 3 2

Effective Address

Mode Register

DIVS DIVS L

o

Register f ield - Specifies any of the eight data reg isters. This f ield always specif ies the destination operand.

Effective Address f ield - Specifies the sou rce operand. Only data address ing modes are a l lowed as shown:


Dn 000 reg. number:Dn (xxx).W 1 1 1

An - - (xxx).L 1 1 1

(An) 010 reg. number:An # < data > 1 1 1



(d1 6,An) 101 reg. number:An (d1 6, PC) 1 1 1

(ds,An,Xn) 1 10 reg. number:An (dS,PC,Xn) 1 1 1

(bd,An,Xn) 1 10 reg. number:An (bd,PC,Xn) 1 1 1

([bd,An,Xn),od) 1 1 0 reg. number:An ([bd,PC,Xn),od) 1 1 1

([bd,An),Xn,od) 1 10 reg. number:An ([bd,PC),Xn,od) 1 1 1

Note: Overflow occurs if the quotient is larger than a 1 6-bit s igned in teger.

Instruction Format ( long form): 15 1 4 13 1 2 11 10 9 s 7 6 5 4 3 2 o

I 0 I 0 Effective Address

0 1 1 1 0 0 0 1 Mode Register

0 Register

Dq 1 Sz 0 0 0 0 0 I 0 I 0

Register

Dr

Instruction Fields:

000

001

100

010

011

011

01 1

0 1 1

Effective Address f ield - Specif ies the sou rce operand. Only data address ing modes are al lowed as shown:

8-80

DIVS DIVSL

Addr. Mode

Dn

An

(An)

(An) +

- (An)

(d1 6,An)

(da,An,Xn)

(bd,An,Xn)

([bd,An,XnJ,od)

([bd,AnJ,Xn,od)

Mode

000 -

010

01 1

100

1 01

1 1 0

1 1 0

1 10

1 1 0

Signed Divide

Register Addr. Mode

reg. llumber:Dn (xxx).w - (xxx).L

reg. number:An # < data >

reg. number:An

reg. number:An

reg. number:An (d1 6,PC)

reg. number:An (da,PC,Xn)

reg. number:An (bd,PC,Xn)

reg. number:An ([bd,PC,XnJ,od)

reg. number:An ([bd,PCJ,Xn,od)

Mode

1 1 1

1 1 1

1 1 1

1 1 1

1 1 1

1 1 1

1 1 1

1 1 1

DIVS DIVS L

Register

000

001

1 00

010

011

011

011

01 1

Reg ister Dq f ield - Specif ies a data reg ister for the dest i nation operand. The low order 32 bits of the d ividend comes from th is reg ister, and the 32-bit quotient is loaded i nto this reg ister.

Sz f ie ld - Selects a 32 or 64 bit d iv is ion operat ion. 0-32-bit d ividend is i n Register Dq. 1 -64-bit d ividend is i n Dr:Dq.

Reg ister Dr field - After the d iv is ion, the 32-bit remainder is loaded i nto th is reg ister. I f Dr = Dq, on ly the quotient is retu rned. I f Sz is 1 , th is f ie ld a lso spec if ies the data reg ister i n which the h igh order 32 bits of the d ividend is located.

Note: Overflow occu rs i f the quotient is larger than a 32-bit s igned integer.

8-81

•

•

DIVU DIVU L Unsigned Divide

Operation: Dest i nation/Source ...... Dest i nat ion

Assembler Syntax:

DIVU.w < ea > ,Dn DIVU . L < ea > , Dq DIVU. L < ea > , Dr:Dq DIVUL. L < ea > , Dr: Dq


32/1 6 ...... 1 6r: 1 6q 32/32 ...... 32q 64/32 ...... 32r:32q 32/32 ...... 32r:32q

DIVU DIVU L

Description: Divide the dest i nation operand by the sou rce and store the resu l t i n the dest i nat ion. The operation is performed us ing uns igned arithmetic.

The i nstruction has a word from and three long forms. For the word form, the dest i nation operand is a long word and the source operand is a word. The resu l t is 32·bits, such that the quotient is in the lower word ( least s ign if icant 16 b its) of the dest i nation and the remainder is in the upper word (most s ign i f icant 16 bits) of the dest ination. Note that the s ign of the remainder is the same as the s ign of the d ividend.

For the f i rst long form, the dest i nation operand is a long word and the source operand is a long word. The resu l t is a long word quotient, and the remainder is d iscarded.

For the second long form, the desti nation operand is a quad word, contained in any two data reg isters, and the source operand is a long word. The resu l t is a long word quotient and a long word remainder.

For the th i rd long form, the dest i nat ion operand is a long word and the sou rce operand is a long word. The resu l t is a long word quotient and a long word remai nder.

Two specia l cond i t ions may arise: 1 . Divis ion by zero causes a t rap. 2. Overlow may be detected and set before completion of the i nstruction. If overflow

is detected, the condit ion is f lagged but the operands are u naffected.


1 - 1 * 1 * 1 * 1 0 1 N Set if the quotient is negat ive. Cleared otherw ise. Undefi ned if overflow or

d ivide by zero. Z Set if the quotient is zero. Cleared otherw ise. Undef i ned if overflow or d ivide

by zero. V Set if d iv is ion overflow is detected. Cleared otherwise. C Always c leared. X Not affected.

8·82

DIVU DIVU L

Instruction Format (word form): 15 14 13 1 2 1 1 10 9

Instruction Fields:

Register

Dn

Unsigned Divide

e 7 6 5 4 3 2

Effective Address

Mode Register

DIVU DIVU L

o

Reg ister f ield - Specif ies any of the eight data reg isters. This field always spec if ies the destination operand.

Effective Address f ield - Specifies the sou rce operand. On ly data addressing modes are a l lowed as shown:



An - - (xxx).l 1 1 1 001





(de,An,Xn) 1 10 reg. number:An (de,PC,Xn) 1 1 1 01 1




Note: Overf low occurs if the quot ient is larger than a 1 6-bit uns igned in teger.

Instruction Format ( long form): 15 1 4 13 1 2 11 10 9 e 7 6 5 4 3 2 o


0 1 1 1 0 0 0 1 I Mode Register

0 Register

0 Sz 0 0 0 0 o I 0 I 0 I Register

Dq Dr

Instruction Fields: Effective Address f ield - Specifies the sou rce operand. On ly data address ing


8-83

•

II

DIVU DIVU L

Addr. Mode

On

An

(An)

(An) +

- (An)

(d16,An)

(dB,An,Xn)

(bd,An,Xn)

([bd,An,Xnl,od)

([bd,Anl,Xn,od)

Mode

000 -

010

011

1 00

101

1 10

1 10

1 10

1 10

Unsigned Divide

Register Addr. Mode

reg. number:On (xxx).W - (xxx).L

reg. number:An #< data>

reg. number:An

reg. number:An

reg. number:An (d1 6,PC)

reg. number:An (dB,PC,Xn)


reg. number:An ([bd,PC,Xnl,od)

reg. number:An ([bd,PCJ,Xn,od)

Mode

1 1 1

1 1 1

1 1 1

1 1 1

1 1 1

1 1 1

1 1 1

1 1 1

DIVU DIVU L

Register

000

001

100

010

01 1

0 1 1

0 1 1

0 1 1

Register Dq f ield - Specif ies a data reg ister for the dest i nation operand. The low order 32 bits of the d ividend come from th is reg ister, and the 32-bit quotient is loaded into th is reg ister.

Sz field - Selects a 32 or 64 bit d iv is ion operation. 0-32-bi t d ividend is in Register Dq. 1 -64-bit d ividend is in Dr:Dq.

Reg ister Dr f ield - After the d ivision, the 32-bit remai nder is loaded intp th is reg ister. I f Dr = Dq, on ly the quotient is returned. I f Sz is 1 , th is f ie ld also specif ies the data reg ister in which the high order 32 bits of the d ividend are located.

Note: Overflow occurs if the quotient is larger than a 32-bit uns igned integer.

8-84

EO R Exclusive OR Logical

Operation: Source e Dest i nation - Dest i nation

Assembler Syntax: EOR On, < ea >


EO R

Description: Exclus ive OR the source operand to the desti nation operand and store the resu l t in the dest i nation locat ion. The s ize of the operat ion may be specified to be byte, word, or long. This operat ion is restricted to data registers as the source operand. The dest ination operand is specif ied in the effective address f ield.


1 - 1 * 1 * 1 0 1 0

N Set if the most s ign i f icant bit of the resu l t is set. Cleared otherwise. Z Set if the resu l t is zero. C leared otherwise. V Always c leared. C Always c leared. X Not affected.

Instruction Format (word form): 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0

Instruction Fields:

Register

On Op·Mode

Effective Address

Mode Register

Regi ster f ield - Specif ies any of the eight data reg isters. Op·Mode f ield -

Byte Word Long Operation 1 00 1 01 1 1 0 < ea > e < Dx > - < ea >

Effective Address f ield - Specif ies the dest i nation operand. On ly data alterable addressing modes are al lowed as shown:

B·85

•

•

EO R Exclusive OR Logical EO R



An - - (xxx).l 1 1 1 001





(ds,An,Xn) 1 1 0 reg. number:An (ds,PC,Xn) - -


([bd,An,XnJ,od) 1 10 reg. number:An ([bd,PC,Xnl,od) - -

([bd,Anl,Xn,od) 1 10 reg. number:An ([bd,PC1,Xn,od) - -

Note: Memory to data reg ister operat ions are not a l lowed. EORI is used when the sou rce is immediate data. M ost assemblers automat ical ly make th is d ist inction .

8-86

EO RI Exclusive O R Immediate

Operation: I mmediate Data Ell Dest i nation - Dest ination

Assembler Syntax: EORI # < data > , < ea >


EO RI

Description: Exc lus ive O R the i mmediate data to the dest i nation operand and store the resu l t in the dest i nation location. The s ize of the operation may be specif ied to be byte, word, or long. The i mmediate data matches the operation s ize.


1 - 1 * 1 * 1 0 0 1 N Set if the most s ign i f icant bit of the resu l t is set. Cleared otherwise. Z Set if the resu l t is zero. Cleared otherwise. V Always c leared. C Always c leared. X Not affected.


0 1 0 1 0 1 0 1 1 1 0 1 1 1 0 Size 1 Effective Address

Mode I Word Data ( 1 6 Bits) Byte Data (8 Bits)

Long Data (32 Bits, including Previous Word)

Instruction Fields: Size f ield - Specif ies the s ize of the operat ion:


Register

Effective Address field - Specif ies the dest i nation operand. Only data alterable address ing modes are a l lowed as shown:

B-87

•

iii

EO R I Exclusive O R Immediate EO RI



An - - (xxx).L 1 1 1 001







([bd,An,Xn),od) 1 1 0 reg. number:An ([bd,PC,Xn),od) - -

([bd,An),Xn,od) 1 1 0 reg. number:An ([bd,PC),Xn,od) - -

Immediate f ie ld - (Data i mmediately fol lowing the i nstruction): If size = 00, then the data is the low order byte of the immediate word. If s ize = 01 , then the data is the ent i re immediate word. I f s ize = 1 0, then the data is next two immediate words.

B·88

EO RI to CCR Exclusive OR Immediate to Condition Code

Operation: Sou rce E9 CCR - CCR

Assembler Syntax: EORI # < data > ,CCR

Attributes: Size = (8yte)

EO RI to CC R

Description: Exclus ive OR the immediate operand with the condition codes and store the resu l t in the low-order byte of the status register.

Condition Codes: x N Z V c * 1 * 1 * 1 * 1 * 1 N Changed if bit 3 of immediate operand is one. Unchanged otherw ise. Z Changed if bit 2 of immed iate operand is one. Unchanged otherw ise. V Changed if bit 1 of immediate operand is one. Unchanged otherw ise. C Changed if bit 0 of immediate operand is one. U nchanged otherw ise. X Changed if bit 4 of immed iate operand is one. Unchanged otherw ise.

Instruction Format: 1 4 1 3 1 0 9 8 6 5 4 3 2

8-89

•

EO RI to S R

Exclusive OR Immediate to the Status Register (Privileged Instruction)

Operation: If su pervisor state

Assembler

then Sou rce E9 SR - SR else TRAP

Syntax: EORI # < data > ,SR


EO RI to S R

Description: Exc lusive OR the i mmediate operand with the contents of the status reg ister and store the resu l t i n the status reg ister. Al l bits of the status reg ister are affected.


* I * I * I * I *

N Changed if bit 3 of immediate operand is one. U nchanged otherw ise. Z Changed if bit 2 of immediate operand is one. Unchanged otherwise. V Changed if bit 1 of immediate operand is one. Unchanged otherwise. C Changed if bit 0 of immediate operand is one. Unchanged otherwise. X Changed if b i t 4 of immediate operand is one. Unchanged otherwise.

Instruction Format: 1 5 1 4 1 3

o 0 I 0

1 2 1 1

o I 1

10 9 8 7 6 5 4 3 2 o o o

Word Data (16 Bits)

8-90

EXG

Operation:

Assembler Syntax:

Attributes:

Rx - Ry

EXG DX, Dy EXG AX,Ay EXG DX,Ay

Size = (Long)

Exchange Registers EXG

Description: Exchange the contents of two reg isters. This exchange is always a long (32 bit) operat ion. Exchange works i n three modes: 1 . Exchange data reg isters. 2. Exchange address reg isters. 3. Exchange a data reg ister and an address reg ister.

Condition Codes: N ot affected.


Instruction Fields:

8 7 6 5 4

Op·Mode

3 2 0

Register

Ry

Reg ister Rx f ield - Specif ies either a data reg ister or an address reg ister dependi ng on the mode. I f the exchange is between data and address reg isters, th is f ie ld always specifies the data reg ister.

Op-Mode field - Specif ies whether exchang ing: 01 000-data reg isters. 0 1001 -address reg isters. 1 0001 -data reg ister and address reg ister.

Reg ister Ry f ield - Specifies either a data reg ister or an address reg ister depending on the mode. If the exchange is between data and address reg isters, th is f ie ld a lways specif ies the address reg ister.

8-91

II

•

EXT EXTB Sign Extend

Operation: Dest i nat ion S ign-extended - Dest i nation

Assembler Syntax:

EXT.w Dn EXT. L Dn EXTB.L Dn

extend byte to word extend word to long word extend byte to long word


EXT EXTB

Description: Extend the s ign bit of a data reg ister from a byte to a word, from a word to a long word, or from a byte to a long word operand, depend ing on the size selected. I f the operation is word, b i t [7] of the designated data reg ister is copied to bits [1 5:8] of that data reg ister. If the operat ion is long, bit [1 5] of the des ignated data reg ister is copied to bits [31 : 1 6] of the data reg ister. The EXTB form copies bit [7] of the designated reg ister to bits [31 :8] of the data reg ister.


1 - 1 * 1 * 1 0 0 1 N Set if the resu l t is negative. Cleared otherwise. Z Set if the resu l t is zero. Cleared otherw ise. V Always c leared. C Always c leared . X Not affected.

Instruction Format: 15 14 1 3 12 11 10 9 8 7 6 I 0 I 1 I 0 I 0 I 1 I 0 I 0 Op·Mode

Instruction Fields:

5 4 3

o I 0 I 0 2 0

Register On

Op-Mode f ield - Specif ies the s ize of the s ign-extension operat ion: 01 0-Sign-extend low order byte of data reg ister to word . 01 1 -Sign-extend low order word of data reg ister to long. 1 1 1 -Sign-extend low order byte of data reg ister to long.

Register f ie ld - Specif ies the data reg ister whose content is to be S ign-extended.

B-92

I L L EGAL Take I l legal Instruction Trap

Operation: SSP - 2 - SSP; Vector Offset - (SSP); SSP - 4 - SSP; PC - (SSP); SSP - 2 - SSP; SR - (SSP); I l legal I nstruction Vector Address - PC

Assembler Syntax: I LLEGAL


I L LEGAL

Description: This bit pattern causes a n i l legal instruction exception. A l l other i l legal i nstruction bit patterns are reserved for future extension of the i nstruction set.



8-93

1 0

o 0 I

•

•

J M P

Operation: Desti nation Address - PC

Assembler Syntax: J M P < ea >


J ump J M P

Description: Program execution cont inues at the effective address spec ified by the i nstruction. The address is specif ied by the control addressing modes.


Instruction Format: 15 14 1 3 12 1 1 10 9 a 7 6

Instruction Fields:

5 4 3 2

Effective Address

Mode Register

o

Effective Address field - Specifies the address of the next i nstruction. On ly control addressing modes are a l lowed as shown:


Dn - - (xxx).W 1 1 1 000

An - - (xxx).L 1 1 1 001


(An) + - -

- (An) - -

(d16,An) 101 reg. number:An (d1 6,PC) 1 1 1 010

(da,An,Xn) 1 1 0 reg. number:An (da,PC,Xn) 1 1 1 0 1 1




8·94

J S R Jump to Subroutine

Operation: SP - 4 -- S�; PC -- (SP) Dest ination Address -- PC

Assembler Syntax: JSR < ea >


J S R

Description: The long word address of the i nstruction immediately fol lowing the JSR i nstruct ion is pushed onto the system stack. Program execut ion then cont i nues at the address specif ied i n the i nstruction.


Instruction Format: 1 4

Instruction Fields:

12 1 1 1 0 9 5 4 3 2

Effective Address

Mode Register

o

Effective Address f ield - Specif ies the address of the next instruction. Only contro l addressing modes are al lowed as shown:


On - - (xxx).w 1 1 1 000

An - - (xxx).L 1 1 1 001


(An) + ,

- -

- (An) - -

(dI6,An) 1 01 reg. number:An (dI6,PC) 1 1 1 010

(da,An,Xn) 1 1 0 reg. number:An (da,PC,Xn) 1 1 1 01 1


([bd,An,Xn],od) 1 10 reg. number:An ([bd,PC,Xn],od) 1 1 1 01 1

([bd,An],Xn,od) 1 10 reg. number:An ([bd,PC],Xn,od) 1 1 1 01 1

8-95

L EA

Operation: < ea > - A n

Assembler Syntax: LEA < ea > ,An

Attributes: Size = (Long)

Load Effective Address L EA

Description: The effective address is loaded i nto the spec if ied address reg ister. A l l 32 bits of the address reg ister are affecfed by this i nstruction.



Instruction Fields:

Register

An

s 7 6 5 4 3 2 o Effective Address

Mode Register

Register f ield - Specifies the address reg ister which is to be loaded with the effect ive address.

Effective Address f ield - Specif ies the address to be loaded into the address reg ister. On ly control addressing modes are al lowed as shown:

, Addr. Mode Mode Register Addr. Mode Mode Register

On - - (xxx)W 1 1 1 000

An - - (xxx).L 1 1 1 001


(An) + - -

- (An) - -


(ds,An,Xn) 1 10 reg. number:An (dS,PC,Xn) 1 1 1 0 1 1

(bd,An,Xn) 1 1 0 reg, number:An (bd,PC,Xn) 1 1 1 0 1 1

([bd,An,Xnl,od) 1 1 0 reg, number:An ([bd,PC,Xnl,od) 1 1 1 0 1 1

([bd,Anl,Xn,od) 1 1 0 reg, number:An ([bd,PCJ,Xn,od) 1 1 1 0 1 1

8-96

LI N K Link and Allocate

Operation: SP - 4 - SP; An - (SP); SP - An; SP + d - SP

Assembler Syntax: L INK An, # < disj:)lacement >


LI N K

Description: The current content of the specif ied address reg ister is pushed onto the stack. After the push, the address reg ister is loaded from the updated stack poi nter. Final ly, the d isp lacement operand is added to the stack pointer. For word size operat ion, the d isplacement is the s ign-extended word fol low i ng the operat ion word. For long s ize operat ion, the d isp lacement is the long word fol lowing the operat ion word. The content of the address reg ister occupies one long word on the stack. A negat ive d isplacement is specif ied to a l locate stack area.


Instruction Format: 15 14 13 1 1 10 9 8 6 5 4 3 2 o

Register

15 14 13 12 1 1 1 0 9 8 7 6 5 4 3 2 0 o I 1 I 0 I 0 I 1 I 0 I 0 I 0 I 0 I 0 I 0 I 0 1 1 1 Register

Long Displacement (High)

Long Displacement (Low)

Instruction Fields: Register f ield - Specif ies the address reg ister through which the l ink is to be

constructed. D isp lacement field - Specif ies the twos complement i nteger which is to be added

to the stack poi nter.

Note: LI N K and U N LK can be used to maintain a l i nked l i st of local data and parameter areas on the stack for nested su brout ine cal ls .

B-97

•

•

LSL, LS R Logical Shift

Operation:

Assembler Syntax:

Destination Sh ifted by < count > - Destination

LSd DX,Dy LSd # < data > ,Dy LSd < ea > where d i s d i rection, L o r R


LS L, LS R

Description: Shift the bits of the operand in the d i rection (L or R) specified. The carry bit receives the last bit sh ifted out of the operand. The shift count for the shift ing of a reg ister may be specified i n two d ifferent ways: 1 . Immediate - the sh ift count is specified in the instruct ion (shift range 1 -8). 2. Register - the sh ift count is contained in a data reg ister specified in the i nstruc

t ion (sh ift count modu lo 64). The size of the operat ion may be specified to be byte, word, or long. The content of memory may be sh ifted one bit on ly, and the operand size is restricted to a word.

For LSL, the operand is shifted left; the nu mber of positions sh ifted is the sh ift count. Bits shifted out of the h igh order bit go to both the carry and the extend bits; zeroes are sh ifted i nto the low order bit.

� __ ��-4�---L ______ O

_p_e_ra_

n_d ____ ��---I�

LSL:

For LSR, the operand is sh ifted right; the nu mber of positions sh ifted is the shift count. Bits shifted out of the low order bit go to both the carry and the extend bits; zeroes are sh ifted i nto the high order bit.

LSR: ,---O�--.l·I,--_Op_eran_

d ----'1-----11.....--�:

- Cont inued -

B-98

LS L, LS R

Condition Codes: x N Z v c

o * I

Logical Shift

N Set if the resu l t is negative. Cleared otherw ise. Z Set if the resu l t is zero. Cleared otherwise. V A lways cleared.

LSL, LS R

C Set accord i ng to the last bit sh ifted out of the operand. Cleared for a shift count of zero.

X Set accord ing to the last bit sh ifted out of the operand. U naffected for a sh ift count of zero.

Instruction Format (Register Shifts): 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0

Countl

Register

I nstruction Field (Reg ister Shifts): Count/Register f ield -

Register

If i/r = O, the sh ift count is spec if ied i n th is f ield. The val ues 0, 1 -7 represent a range of 8, 1 to 7 respectively.

If i/r = 1 , the sh ift count (modu lo 64) is contained in the data reg ister spec if ied in th is f ield.

d r f ield - Specif ies the d i rection of the sh ift: O-shift right. 1 -sh ift left.

S ize field - Specif ies the s ize of the operat ion: OO- byte operat ion. 01 -word operat ion. 1 0- long operation.

i / r f ield -I f i/r = 0, Specifies immed iate sh ift count. I f i/r = 1 , Specif ies reg ister sh ift count.

Reg ister f ield - Specif ies a data reg ister whose content is to be sh ifted.

Instruction Format (Memory Shifts):

Instruction Fields (Memory Shi fts): dr f ield - Specif ies the d i rection of the shift:

O-shift r ight. 1 -sh ift left.

5 4 3 2 0

Effective Address

Mode Register

Effective Address f ield - Specif ies the operand to be sh ifted. On ly memory alterable address ing modes are al lowed as shown:

8-99

•

LS L, LS R Logical Shift LS L, LS R


Dn - - (xxx).W 1 1 1 000

An - - (xxx).L 1 1 1 001




(d16,An) 101 reg. number:An (d1 6,PC) - -

(de,An,Xn) 1 10 reg. number:An (de,PC,Xn) - -




•

8-1 00

M OVE Move Data from Source to Destination

Operation: Sou rce - Dest i nation

Assembler Syntax: MOVE < ea > , < ea >


M OVE

Description: M ove the content of the source to the destination location. The data is exam ined as it is moved, and the condition codes set accord ing ly. The s ize of the operation may be specif ied to be byte, word, or long.

Condition Codes: x N z V c I - I * I * I 0 0 I N Set if the resu lt is negat ive. Cleared otherwise. Z Set if the resu lt is zero. Cleared otherwise. V Always c leared. C Always c leared. X Not affected.

Instruction Format: 15 1 4 13 1 2 1 1 10 9 a 7 6 5 4 3 2

Destination Source

Instruction Fields:

Register Mode Mode Register

Size f ield - Specif ies the s ize of the operand to be moved: 01 - byte operation. 1 1 -word operat ion. 1 0- long operat ion.

o

Destination Effective Address f ield - Specif ies the desti nation location. Only data alterable addressing modes are al lowed as shown:


Dn 000 reg. number:An (xxx).w 1 1 1 000

An - - (xxx).L 1 1 1 001




(d16,An) 1 01 reg. number:An (d1 6,PC) - -




([bd,Anj,Xn,od) 1 10 reg. number:An ([bd,PC),Xn,od) - -

B·101

•

•

M OVE Move Data from Source to Destination M OVE

Source Effective Address f ield - Specif ies the source operand. A l l address ing modes are al lowed as shown:



An* 001 reg. number:An (xxx).L 1 1 1 001

(An) 010 reg. number:An # < data> 1 1 1 100




(de,An,Xn) 1 10 reg. number:An (de,PC,Xn) 1 1 1 01 1




* For byte size operation, address register direct is not al lowed.

Notes: 1 . MOVEA is used when the dest ination is an address reg ister. Most assemblers automat ical ly make th is dist i nction.

2. M OVEQ can also be used for certain operat ions on data reg isters .

8-1 02

M OV EA Move Address M OVEA

Operation: Source -- Dest i nation

Assembler Syntax: MOVEA < ea > ,An


Description: Move the content of the source to the dest i nation address reg ister. The s ize of the operat ion may be specif ied to be word or long. Word size sou rce operands are s ign extended to 32 bit quantit ies before the operation is done.



Instruction Fields:

Destination

Register

B 7 6 5 4 3 2

Source

Mode Register

Size field - Specif ies the s ize of the operand to be moved:

o

1 1 -Word operation. The source operand i s s ign-extended to a long operand and al l 32 bits are loaded i nto the address reg ister.

10-Long operat ion. Dest i nation Register f ield - Specif ies the desti nation address reg ister. Sou rce Effective Address f ield - Specif ies the locat ion of source operand. A l l





(An) 010 reg. number:An #< data> 1 1 1 1 00




(dB,An,Xn) 1 1 0 reg. number:An (dB,PC,Xn) 1 1 1 0 1 1


([bd,An,Xnl,od) 1 10 reg. number:An ([bd,PC,Xnl,od) 1 1 1 0 1 1

([bd,Anl,Xn,od) 1 1 0 reg. number:An ([bd,PCJ,Xn,od) 1 1 1 01 1

8-1 03

•

II

M OVE from CC R

Move from the Condition Code Register

M OVE from C C R

Operation: GGR - Dest ination

Assembler Syntax: MOVE GGR, < ea >


Description: The content of the status reg ister is moved to the dest i nation location. The source operand is a word, but only the low order byte conta ins the cond it ion codes. The upper byte is all zeroes.


Instruction Format: 15 14 13 12 1 1 10 9 a 7 6

Instruction Fields:

5 4 3 2

Effective Address

Mode Register

o

Effective Address f ield - Specif ies the dest ination locat ion. On ly data alterable address ing modes are a l lowed as shown:



An - - (xxx).L 1 1 1 001









Note: MOVE from GGR is a word operation. ANDI , ORI , and EORI to GGR are byte operat ions.

8-1 04

M OV E to CCR

Operation: Source - CCR

Assembler

Move to Condition Codes

Syntax: MOVE < ea > ,CCR


M OVE to CC R

Description: The content of the source operand is moved to the condition codes. The sou rce operand is a word, but only the low order byte is used to update the cond it ion codes. The upper byte is ignored.


• I • I • I · • I N Set the same as bit 3 of the source operand. Z Set the same as bit 2 of the sou rce operand. V Set the same as bit 1 of the source operand. C Set the same as bit 0 of the source operand. X Set the same as bit 4 of the sou rce operand.

Instruction Format: 15 14 13 12 11 10 9 a 7 6 5

Instruction Fields:

4 3 2

Effective Address

Mode Register

o

Effective Address f ield - Specif ies the locat ion of the source operand. On ly data address ing modes are al lowed as shown:



An - - (xxx).L 1 1 1 001




(d16,An) 1 01 reg. number:An (d1 6,PC) 1 1 1 010

(da,An,Xn) 1 1 0 reg. number:An (da,PC,Xn) 1 1 1 011


([bd,An,Xnj,od) 1 1 0 reg. number:An ([bd,PC,Xnj,od) 1 1 1 011

([bd,Anj,Xn,od) 1 10 reg. number:An ([bd,PC],Xn,od) 1 1 1 01 1

Note: MOVE to CCR is a word operat ion. ANDI , ORI , and EORI to CCR are byte operations.

8-1 05

•

•

M OVE from SR

Move from the Status Register (Privileged Instruction)

M OVE from SR

Operation: I f supervisor state

Assembler

then SR --+ Desti nation e lse TRAP

Syntax: MOVE SR, < ea >


Description: The content of the status reg ister is moved to the destination location. The operand size is a word.


Instruction Format: 15 14 13 12 1 1 10 9 B 7 6

Instruction Fields:

5 4 3 2

Effective Address

Mode Register

o

Effective Address field - Specifies the dest ination location. Only data alterable addressing modes are a l lowed as shown:


On 000 reg. number:On (xxx)W 1 1 1 000

An - - (xxx).L 1 1 1 001





(dB,An,Xn) 1 10 reg. number:An (dB,PC,Xn) - -




Note: Use the MOVE from GGR instruct ion to access on ly the condition codes.

8-1 06

M OVE to SR

Move to the Status Register (Privileged Instruction)

Operation: If supervisor state then Source - S R else TRAP

Assembler Syntax: MOVE < ea > ,SR


M OVE to S R

Description: The content of the source operand is moved to the status register. The source operand is a word and all bits of the status reg ister are affected.

Condition Codes: Set accord ing to the source operand.

Instruction Format: 15 14 13 12 1 1 10 9 s 7 6

Instruction Fields:

5 4 3 2

Effective Address

Mode Register

o

Effect ive Address f ield - Specif ies the locat ion of the source operand. Only data address ing modes are al lowed as shown:



An - - (xxx).L 1 1 1 001





(dS,An,Xn) 1 1 0 reg. number:An (ds,PC,Xn) 1 1 1 01 1

(bd,An,Xn) 1 1 0 reg. number:An (bd,PC,Xn) 1 1 1 01 1

([bd,An,Xnl,od) 1 1 0 reg. number:An ([bd,PC,Xnl,od) 1 1 1 0 1 1

([bd,Anl,Xn,od) 1 1 0 reg. number:An ([bd,PC),Xn,od) 1 1 1 01 1

8-1 07

•

•

M OVE USP

Move User Stack Pointer (Privileged Instruction)

M OVE USP

Operation:

Assembler Syntax:

Attributes:

I f su pervisor state then USP - An or An - USP else TRAP

MOVE USP,An Move An,USP

Size = (Long)

Description: The contents of the user stack poi nter are transferred to or from the specif ied address reg ister.


Instruction Format: 15 14 13 12 1 1 10 9 8 7 6 5

Instruction Fields: dr f ield - Specif ies the d i rect ion of transfer:

O-transfer the address reg ister to the USP. 1 -transfer the USP to the address reg ister.

4 3 2 0

o dr I Register

Reg ister f ield - Specif ies the address reg ister to or from which the user stack poi nter is to be transferred .

8-108

M OVEC Move Control Register (Privileged Instruction)

Operation:

Assembler Syntax:

Attributes:

If su pervisor state then Rc - Rn or Rn - Rc else TRAP

MOVEC RC, Rn MOVEC Rn,Rc

Size = (Long)

,M OVEC

Description: Copy the contents of the specified control reg ister (Rc) t o the specif ied general reg ister or copy the contents of the spec ified general reg i ster to the spec if ied control reg ister. This is always a 32-bit transfer even though the control reg ister may be i mplemented with fewer bits. U n i mplemented bits are read as zeros.


Instruction Format:

Instruction Fields: dr f ield - Specif ies the d i rect ion of the transfer:

O-control reg ister to general register. 1 -general reg ister to control reg ister.

AID field - Specif ies the type of general reg ister: O-data reg ister. 1 -address reg ister.

Register f ield - Specif ies the reg ister number. Control Register f ield - Specifies the control reg ister.

Hex Control Register 000 Source Fu nction Code (SFC) register.

001 Dest i nation Function Code (DFC) reg ister. 002 Cache Control Reg ister (CACR). 800 User Stack Pointer (USP). 801 Vector Base Reg ister (VBR). 802 Cache Address Reg ister (CAAR). 803 Master Stack Pointer (MSP). 804 I nterrupt Stack Poi nter ( ISP).

A l l other codes cause an i l legal i nstruct ion except ion.

B-1 09

•

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M OV E M Move Multiple Registers M OVEM

Operation:

Assembler Syntax:

Attributes:

Registers -- Dest i nation Source -- Registers

MOVEM reg ister l ist, < ea > MOVEM < ea > , register l i st

Size = (Word, Long)

Description: Selected reg isters are t ransferred to or from consecutive memory locat ions start ing at the locat ion spec if ied by the effective address. A reg ister is t ransferred i f the bit correspond ing to that reg ister is set i n the mask f ield. The i nstruct ion selects how much of each reg ister is transferred; either the ent i re long word can be moved or just the low order word. I n the case of a word transfer to the reg isters, each word is s ign-extended to 32 bits ( inc lud ing data reg isters) and the resu l t ing long word loaded i nto the associated reg ister.

MOVEM al lows three forms of address modes: the control modes, the predecrement mode, or the posti ncrement mode. I f the effective address is in one of the control modes, the reg isters are transferred start i ng at the specif ied address and up through h igher addresses. The order o f transfer is from data reg ister 0 to data reg ister 7, then from address reg ister 0 to address reg ister 7.

I f the effective address is the predecrement mode, only a reg ister to memory operat ion is a l lowed. The reg isters are stored start ing at the spec if ied address minus the operand length (2 or 4) and down through lower addresses. The order of stor ing is from address reg ister 7 to address reg ister 0, then from data reg ister 7 to data reg ister O. The decremented address reg ister is updated to contai n the address of the last word stored.

If the effective address is the post i ncrement mode, only a memory to reg ister operat ion is al lowed. The reg isters are loaded start ing at the specif ied address and up through h igher addresses. The order of load ing is the same as for the control mode addressing . The i ncremented address reg ister is updated to conta in the add ress of the last word loaded p lus the operand length (2 or 4).

Condition Codes: N ot affected .


Effective Address o

Mode Register

- Conti nued -

8-1 1 0

M OV E M Move Multiple Registers M OVEM

Instruction Fields: dr f ield - Specif ies the d i rect ion of the transfer:

O-reg ister to memory. 1 - memory to reg ister.

Sz f ie ld - Specif ies the s ize of the reg isters being transferred: O-word transfer. 1 - long transfer.

Effective Address field - Specif ies the memory address to or from which the reg isters are to be moved. For reg ister to memory transfers, on ly control alterable addreSSing modes or the predecrement address ing mode are a l lowed as shown:


On - - (xxx).W 1 1 1 000

An - - (xxx).l 1 1 1 001


(An) + 0 1 1 -


(d1 6,An) 101 reg. number:An (d1 6, PC) - -





For memory to reg ister transfers, on ly contro l addressing modes or the posti ncrement addreSS ing mode are a l lowed as shown:


On - - (xxx).W 1 1 1 000

An - - (xxx).l 1 1 1 001



- (An) - -




([bd,An,Xn),od) 1 1 0 reg. number:An ([bd,PC,Xn),od) 1 1 1 0 1 1

([bd,An),Xn,od) 1 1 0 reg. number:An ([bd,PC),Xn,od) 1 1 1 0 1 1

Register L ist Mask f ield - Specif ies which reg isters are to be transferred. The low order bit corresponds to the f i rst reg ister to be transferred; the h igh bit corresponds to the last reg ister to be transferred. Thus, both for control modes and for the post i ncrement mode addresses, the mask correspondence is

1 5 1 4 1 3 12 11 1 0 9 a 7 6 5 4 3 2 1 0 I A7 I A6 I A5 I A4 I A3 I A2 I A1 AO 07 D6 05 04 I 03 I 02 I 01 I DO I 8-1 1 1

•

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M OVEM Move Multiple Registers M OV E M

whi le for the predecrement mode add resses, the mask correspondence is

1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 I 00 I 01 I 02 I 03 I 04 I 05 I os I 07 I AO I A1 I A2 I A3 I A4 I A5 I A6 I A7 I Note: An extra read bus cyc le occu rs for memory operands. This accesses an operand at

one address h igher than the last reg ister image requ i red .

8·1 1 2

M OVEP Move Peripheral Data

Operation:

Assembler Syntax:

Attributes:

Sou rce - Dest i nation

MOVEP DX,(d,Ay) MOVEP (d,Ay)Dx

Size = (Word, Long)

M OVEP

Description: Data is t ransferred between a data reg ister and alternate bytes of memory, start ing at the locat ion specif ied and i ncrementing by two. The h igh order byte of the data reg ister is transferred f i rst and the low order byte is t ransferred last. The memory address is specif ied us ing the address reg ister i nd i rect p lus 1 6-bit d isp lacement address ing mode. This instruction is designed to work with 8-bit peripherals on a 1 6-bit data bus. If the address is even, all the transfers are made on the high order half of the data bus; if the address is odd, all the t ransfers are made on the low order half of the data bus. On an 8- or 32-bit bus, the i nstruct ion st i l l accesses every other byte.

Example: Long transfer to/from an even address.

Byte organ izat ion in reg ister

31 24 23 16 1 5 8 7

Hi·Order M id·Upper Mid·Lower Low·Order

Byte organ izat ion i n memory (low add ress at top)

1 5

Hi·Order

Mid·Upper

Mid-Lower

Low-Order

8 7

Example: Word transfer to/from an odd address.

Byte organ izat ion in reg ister

31 24 23 16 1 5

H i-Order

o

8 7

Low-Order

Byte organ izat ion i n memory (low address at top)

1 5 8 7

B-1 1 3

o

Hi-Order

Low-Order

o

o

- Cont i nued -

•

II

M OVEP Move Peripheral Data M OVEP



o

Instruction Fields:

Data

Register Op·Mode

Displacement

2 Address

Register

o

Data Register f ield - Specif ies the data reg ister to or from which the data is to be t ransferred.

Op-Mode f ield - Specifies the d i rection and s ize of the operat ion: 1 00-transfer word from memory to reg ister. 101 -transfer long from memory to reg ister. 1 1 0-transfer word from reg ister to memory. 1 1 1 -transfer long from reg ister to memory.

Address Register f ield - Specif ies the address reg ister which is used in the address reg ister ind i rect plus displacement addressing mode.

Displacement f ield - Specif ies the displacement which is used in calculat ing the operand address.

8-1 1 4

M OVEQ Move Quick

Operation: Immed iate Data - Dest ination

Assembler Syntax: M OVEO # < data > ,Dn


M OVEQ

Description: M ove immediate data to a data reg ister. The data is contai ned i n an B-bit field w i th in the operat ion word. The data is S ign-extended to a long operand and a l l 32 bits are transferred to the data register.


/ - 1 * 1 * 1 0 0 1 N Set if the resu l t is negat ive. Cleared otherwise. Z Set if the resu l t is zero. Cleared otherwise. V A lways c leared. C Always c leared. X Not affected.

Instruction Format: 15 14 13 12 1 1 10 9 8 7 6 5 4 3 2 0 I 0 I 1 I 1 I 1 I Register 0 I Data

Instruction Fields: Register f ield - Specif ies the data reg ister to be loaded. Data f ield - B bits of data which are s ign extended to a long operand.

8-1 1 5

II

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M OVES Move Address Space (Privi leged Instruction)

Operation:

Assembler Syntax:

Attributes:

If su pervisor state then Rn - Dest i nation [DFC) or Source [SFC) - Rn else TRAP

MOVES Rn, < ea > MOVES < ea > ,Rn


M OVES

Description: Move the byte, word, or long operand from the specif ied general reg ister to a locat ion with in the address space specif ied by the desti nation fu nction code (DFC) reg ister. Or, move the byte, word, or long operand from a locat ion with in the address space spec if ied by the source function code (SFC) reg ister to the specif ied general reg ister.

I f the dest i nation is a data reg ister, the source operand replaces the corresponding low-order b i ts of that data reg ister. I f the dest i nation is an address reg ister, the source operand is s ign-extended to 32 bits and then loaded i nto that add ress reg ister.


Instruction Format: 15 14 13 12 1 1 10 9 8 7 6 5 4 3 2 0 0 o I 0 I 0 1 1 1 0 Size

AID Register dr 0 0 0 o 1 0 o 1 Instruction Fields:

Size f ield - Specifies the s ize of the operat ion: OO-byte operat ion. 01 -word operat ion. 1 0- long operation.

Effective Address

Mode I Register

0 1 0 1 0 1 0 1 0

Effective Address f ield - Specif ies the sou rce or dest i nation locat ion with in the alternate address space. On ly alterable memory addressing modes are al lowed as shown:

- Cont i nued -

B-1 1 6

M OVES Move Address Space (Privileged Instruction)

MOVES


On - - (xxx)W

An - - (xxx).L

(An) 010 reg. number:An # < data >



(d1 6,An) 101 reg. number:An (d16, PC)

(da,An,Xn) 1 10 reg. number:An (da,PC,Xn)

(bd,An,Xn) 1 10 reg. number:An (bd,PC,Xn)

([bd,An,Xn),od) 1 10 reg. number:An ([bd,PC,Xn),od)

([bd,An),Xn,od) 1 10 reg. number:An ([bd,PC),Xn,od)

AID f ield - Specif ies the type of general reg ister: O-data reg ister. 1 -address reg ister.

Reg ister f ield - Specif ies the reg ister number. dr f ield - Specifies the d i rect ion of the transfer:

O-from < ea > to general reg ister. 1 -from general reg ister to < ea > .

MOVES.x An(An) + or

MOVES.x An, - (An)

1 1 1 000

1 1 1 001 - -

- -

- -

- -

- -

- -

where An is the same add ress reg ister for both sou rce and dest i nation and is an u ndefined operat ion. The value stored in memory is u ndefined.

NOTE On the MC6801 0 and MC68020 implementat ions, the value stored is the increment or the decrement value of An. This i mplementation may not appear on future devices.

8-1 1 7

II

II

M U LS Signed Multiply

Operation: Source- Dest ination - Dest i nation

Assembler Syntax:

MULS.w < ea > ,Dn MULS. L < ea > ,D I M U LS. L < ea > ,Dh:D I


1 6 x 1 6 - 32 32 x 32 - 32 32 x 32 - 64

M U LS

Description: M u lt ip ly two s igned operands yielding a s igned resu lt. The operat ion is performed us ing s igned arithmetic.

The i nstruct ion has a word form and a long form. For the word form, the mu lt ip l ier and mult ipl icand are both word operands and the resu l t is long word operand. A reg ister operand i s taken f rom the low order word, the upper word is unused. A l l 32 bits of the product are saved i n the dest i nation data reg ister.

For the long form, the mult ip l ier and mu lt ipl icand are both long word operands and the resu lt is either a long word or a quad word. The long word resu l t is the low order 32 bits of the quad word resu lt .


1 - 1 - 1 * 1 * 1 0

N Set if the resu l t is negat ive. Cleared otherw ise. Z Set if the resu l t is zero. Cleared otherwise. V Set if overflow. Cleared otherw ise. C Always c leared. X Not affected.

Note: Overflow (V = 1 ) can occur on ly in the case of mu lt i p ly ing 32-bit operands to yield a 32-bit result . Overflow occurs if the h igh-order 32 bits of the quad word product are not the sign-extension of the low order 32 bits.

Instruction Format (word form): 15 1 4 1 3 12 11 10 9 8 7 6 5 4 3 2 0

Instruction Fields:

Register Effective Address

On Mode Register

Register f ield - Specif ies one of the data reg isters. This f ield a lways specifies the dest i nation.

Effective Address f ield - Specif ies the source operand. Only data addressing modes are al lowed as shown:

B-1 1 8

M U LS Signed Multiply M U LS



An - - (xxx).L 1 1 1 001




(d1 6,An) 101 reg. number:An (d16,PC) 1 1 1 010



([bd,An,Xnj,od) 1 1 0 reg. number:An ([bd,PC,Xnj,od) 1 1 1 01 1

([bd,Anj,Xn,od) 1 1 0 reg. number:An ([bd,PGj,Xn,od) 1 1 1 0 1 1

Instruction Format ( long form): 15 1 4 1 3 12 1 1 10 9 a 7 6 5 4 3 2 o



0 Register

1 Sz 0 0 0 0 o I 0 I 0 Register

01 Oh

Instruction Fields: Effect ive Address f ield - Specifies the sou rce operand. Only data addressing




An - - (xxx).L 1 1 1 001




(d16,An) 1 01 reg. number:An (d1 6, PC) 1 1 1 010



([bd,An,Xnj,od) 1 10 reg. number:An ([bd,PC,Xnj,od) 1 1 1 01 1

([bd,Anj,Xn,od) 1 10 reg. number:An ([bd,PGj,Xn,od) 1 1 1 01 1

Reg ister 01 field - Specif ies a data reg ister for the dest i nation operand. The 32-bit mult i pl icand comes from this reg ister, and the low order 32 bits of the product is loaded into this register.

Sz f ield - Selects a 32- or 64-bit product resu lt. 0-32-bit product to be returned to Reg ister 01 . 1 -64-bit product to be retu rned to Oh:OI .

Register Oh f ie ld - I f Sz is 1 , spec if ies the data reg ister i nto which the h igh order 32 bits of the product is loaded. If Oh = 01 and Sz is 1 , the resu lts of the operat ion are u ndefined. Otherwise, th is f ield is unused.

8-1 1 9

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M U L U Unsigned Multiply

Operation: Source* Dest i nation -- Dest i nation

Assembler Syntax:

M U LU.w < ea > ,Dn MULU.L < ea > ,01 MU LU. L < ea > , Dh:DI


1 6 x 1 6 -- 32 32 x 32 -- 32 32 x 32 -- 64

M U LU

Description: M u lt iply two uns igned operands y ie ld ing a u nsigned resu lt. The operat ion is performed us ing uns ig ned arithmetic.

The i nstruct ion has a word form and a long form. For the word form, the mul t ipl ier and mu lt ipl icand are both word operands and the result is a long word operand. A reg ister operand is taken from the low order word, the upper word is unused. A l l 32 bits of the product are saved i n the dest ination data reg ister.

For the long form, the mul t ip l ier and mult ip l icand are both long word operands and the resu lt is either a long word or a quad word. The long word result is the low order 32 bits of the quad word result .


1 - 1 * 1 * 1 * 1 0

N Set i f the resu l t is negat ive. Cleared otherw ise. Z Set if the resu l t is zero. Cleared otherw ise. V Set if overflow. Cleared otherw ise. C Always c leared. X Not affected.

Note: Overflow (V = 1) can occur on ly i n the case of mult ip ly ing 32-bit operands to yield a 32-bit resu lt. Overflow occurs if the h igh-order 32 bits of the quad word product are non-zero.

Instruction Format (word form): 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0

Instruction Fields:

Register Effective Address

Dn Mode Register

Register f ield - Specif ies one of the data reg isters. This f ield always specif ies the desti nat ion.

Effective Address f ield - Specif ies the source operand. On ly data address ing modes are al lowed as shown:

B-1 20

M U LU Unsigned Multiply M U LU



An - - (xxx).L 1 1 1 001





(ds,An,Xn) 1 1 0 reg. number:An (dS,PC,Xn) 1 1 1 0 1 1



([bd,Anl,Xn,od) 1 10 reg. number:An ([bd,PCJ,Xn,od) 1 1 1 0 1 1

Instruction Format ( long form): 15 1 4 1 3 12 11 10 9 s 7 6 5 4 3 2 o



0 Register

0 Sz 0 0 0 0 0 1 0 I 0 Register

01 Oh

Instruction Fields: Effective Address f ield - Specif ies the source operand. On ly data addressing




An - - (xxx).L 1 1 1 001




(d1 6,An) 101 reg. number:An (d16,PC) 1 1 1 010

(ds,An,Xn) 1 1 0 reg. number:An (ds,PC,Xn) 1 1 1 01 1



([bd,Anl,Xn,od) 1 10 reg. number:An ([bd,PCJ,Xn,od) 1 1 1 01 1

Register 01 f ie ld - Specif ies a data reg ister for the dest i nation operand. The 32-bit mu l t ip l icand comes from this reg ister, and the low order 32 bits of the product are loaded i nto th is reg ister.

Sz f ield - Selects a 32- or 64-bit product resu lt. 0-32-bit product to be returned to Reg ister 01. 1 -64-bit product to be retu rned to Oh:OI .

Reg ister Oh f ield - I f Sz is 1 , spec ifies the data reg ister i nto which the h igh order 32 bits of the product are loaded. I f Oh = 01 and Sz is 1 , the resu lts of the operat ion are u ndefi ned. Otherw ise, th is field is unused.

8-1 21

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N BC D Negate Decimal with Extend

Operation: 0 - Dest i nation1 Q - X - Desti nation

Assembler Syntax: N BCD < ea >


N BC D

Description: The operand addressed as the dest i nation and the extend bit are subt racted from zero. The operat ion is performed us ing decimal arithmetic. The resu l t is saved in the dest i nation locat ion. Th is i nstruction produces the tens complement of the desti nation if the extend bit is c lear, the n ines complement if the extend bit is set. Th is is a byte operat ion only.


1 * l u l * l u * 1 N Undefi ned. Z Cleared if the resu lt is non-zero. Unchanged otherwise. V U ndefi ned. C Set if a borrow (decimal) was generated. Cleared otherw ise. X Set the same as the carry bit.

NOTE Normally the Z cond it ion code bit is set via programming before the start of an operation. This a l lows successfu l tests for zero results upon completion of mult iple precision operat ions.


Instruction Fields:

Effective Address

Mode Register

Effective Address f ield - Specifies the destination operand. On ly data alterable address ing modes are al lowed as shown:

8-1 22

N BC D Negate Decimal with Extend N BC D



An - - (xxx).L 1 1 1 001







([bd,An,Xnl,od) 1 1 0 reg. number:An ([bd,PC,Xnl,od) - -

([bd,Anl,Xn,od) 1 1 0 reg. number:An ([bd,PCJ,Xn,od) - -

a

B·1 23

•

N EG Negate

Operation: 0 - Dest i nation - Dest i nation

Assembler Syntax: N EG < ea >

Attributes: Size = (Byte, Word , Long)

N EG

Description: The operand addressed as the dest i nation is subtracted from zero. The resu l t is stored in the dest i nation location. The size of the operat ion may be spec if ied to be byte, word, or long.


* 1 * 1 * 1 * 1 *

N Set if the resu l t is negative. Cleared otherw ise. Z Set if the resu l t is zero. Cleared otherwise. V Set if an overflow is generated. Cleared otherwise. C Cleared if the resu l t is zero. Set otherwise. X Set the same as the carry bit .

Instruction Format: 15 1 4 13 12 11 10 9 s 7 6 5 4 3 2

Effective Address

Instruction Fields: Size f ield - Specif ies the size of the operat ion.

OO- byte operat ion. 01 -word operat ion. 10- long operat ion.

Mode Register

o

Effective Address f ield - Specif ies the dest i nation operand. On ly data alterable addressing modes are al lowed as shown:



An - - (xxx).L 1 1 1 001









B-1 24

N EGX Negate with Extend

Operation: 0 - (Desti nation) - X - Dest i nation

Assembler Syntax: N EGX < ea >


N EGX

Description: The operand addressed as the dest i nation and the extend bit are subtracted from zero. The resu lt is stored i n the dest i nation locat ion. The size of the operation may be spec if ied to be byte, word, or long.

Condition Codes: x N z V c * I * I * I * I * I N Set if the resu l t is negat ive. Cleared otherwise. Z Cleared if the resu l t is non-zero. Unchanged otherw ise. V Set if an overflow is generated. Cleared otherwise. C Set if a borrow is generated. Cleared otherwise. X Set the same as the carry bit .

NOTE Normal ly the Z condit ion code bit is set via programming before the start of an operation. This a l lows successfu l tests for zero resu lts upon completion of mu l t ip le-prec is ion operat ions.


Instruction Fields:

Effective Address

Mode Register

Size f ield - Specif ies the size of the operation. OO-byte operat ion. 01 -word operation. 1 0- long operat ion.

B Effective Address f ield - Specif ies the desti nation operand. Only data alterable ad-dress ing modes are a l lowed as shown:

B-1 25

N EGX Negate with Extend N EGX _



An - - (xxx).L 1 1 1 001





(dS,An,Xn) 1 1 0 reg. number:An (ds,PC,Xn) - -




•

8-1 26

N O P

Operation: None

Assembler Syntax: NOP


No Operation N O P

Description: No operation occurs. The processor state, other than the program counter, is u naffected. Execut ion cont i nues with the i nstruction fol lowing the NOP i nstruct ion. The NOP i nstruction does not complete execution unt i l a l l pending bus cyc les are completed. This a l lows synchron izat ion of the p ipe l i ne to be accompl ished, and prevents i nstruction overlap.


Instruction Format: 15 14 1 3 12 11 10 9 8 7 6 5 4 3

9-1 27

2 1 0

•

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N OT Logical Complement

Operation: - Dest i nation - Dest i nation

Assembler Syntax: NOT < ea >


N OT

Description: The ones complements of the dest ination operand is taken and the resu l t is stored i n the dest i nation locat ion. The s ize of the operat ion may be specified to be byte, word, or long.


1 - 1 * 1 * 1 0 0 /

N Set if the resu l t is negat ive. Cleared otherw ise. Z Set if the resu lt is zero. Cleared otherwise. V Always c leared. C Always c leared. X Not affected.

Instruction Format: 15 1 4 1 3 1 2 1 1 10 9 s 7 6 5 4 3 2

Effective Address

Instruction Fields:

Mode Register

Size f ield - Specifies the s ize of the operation. OO- byte operat ion. 01 -word operat ion. 10- long operat ion.

o

Effective Address f ield - Specif ies the dest i nation operand. Only data alterable address ing modes are al lowed as shown:



An - - (xxx).l 1 1 1 001

(An) 010 reg. number:An #< data> - -(An) + 0 1 1 reg. number:An



(dS,An,Xn) 1 10 reg. number:An (dS,PC,Xn) - -




B-1 28

O R

Operation:

Assembler Syntax:

Attributes:

Inclusive OR Logical

Source v Dest i nation - Dest i nation

OR < ea > ,Dn OR Dn, < ea >


O R

Description: I nc lusive OR the source operand to the dest i nation operand and store the resu l t in the dest ination locat ion. The s ize of the operat ion may be specif ied to be byte, word, or long. The contents of an address reg ister may not be used as an operand.


1 - 1 * 1 * 1 0 0

N Set if the most s ign i f icant bit of the resu l t is set. Cleared otherwise. Z Set if the resu l t is zero. Cleared otherw ise. V Always cleared. C Always cleared. X Not affected.


Register Op·Mode

Instruction Fields:

Effective Address

Mode Register

Reg ister f ie ld - Specif ies any of the eight data reg isters. Op-Mode f ie ld -

Byte Word Long Operation 000 001 0 10 « ea > )v( < On » - < On > 1 00 1 01 1 1 0 « Dn » v« ea » - < ea >

Effective Address f ie ld -I f the locat ion spec i f ied is a sou rce operand then only data addressing modes are a l lowed as shown:

B-1 29

•

•

O R Inclusive OR Logical O R



An - - (xxx).L 1 1 1 001

(An) 010 reg. number:An # < data> 1 1 1 1 00




(da,An,Xn) 1 10 reg. number:An (da,PC,Xn) 1 1 1 01 1




I f the location specif ied is a dest i nation operand then on ly memory alterable address ing modes are al lowed as shown:


On - - (xxx).w 1 1 1 000

An - - (xxx).L 1 1 1 001









Notes: 1 . I f the desti nation is a data reg ister, then it cannot be specif ied by us ing the dest i nation < ea > mode, but must use the dest ination Dn mode instead.

2. ORI is used when the source is immediate data. Most assemblers automat ica l ly make th is d istinction .

8-1 30

O R I Inclusive OR Immediate

Operation: Immediate Data v Dest i nation - Dest i nation

Assembler Syntax: ORI # < data > , < ea >


O R I

Description: I nc lus ive OR the immediate data to the dest i nation operand and store the resu l t in the dest i nation locat ion. The s ize of the operat ion may be specif ied to be byte, word, or long. The s ize of the immediate data matches the operation s ize.


1 - 1 * 1 * 1 0 0 1 N Set if the most s ign if icant bit of the resu l t is set. Cleared otherw ise. Z Set if the resu l t is zero. Cleared otherw ise. V A lways c leared. C Always c leared. X Not affected.

I nstruction Format: 15 1 4 13 1 2 11 10 9 8 7 6 5 4 3 2 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Size ,

Word Data

Long Data

Instruction Fields: Size f ield - Specif ies the s ize of the operat ion.

�O- byte operat ion. 01 -word operat ion. 10- long operat ion.

Effective Address

Mode I Register

Byte Data

Effective Address f ield - Specif ies the dest i nation operand. Only data alterable addressing modes are al lowed as shown:

B-1 31

•

•

O RI Inclusive O R Immediate O R I



An - - (xxx).L 1 1 1 001





(dS,An,Xn) 1 10 reg. number:An (ds,PC,Xn) - -



([bd,Anj,Xn,od) 1 1 0 reg. number:An ([bd,PC),Xn,od) - -

Immediate f ield - (Data immediately fol lowing the i nstruct ion): If s ize = 00, then the data is the low order byte of the immediate word. If s ize = 01 , then the data is the ent ire immediate word. If s ize = 1 0, then the data is the next two immediate words.

8·1 32

O RI to CCR

Inclusive OR Immediate to Condition Codes

Operation: Sou rce v CCR -+ CCR

Assembler Syntax: ORI # < data > ,CCR


O RI to CC R

Description: I nc lus ive OR the immediate operand with the condition codes and store the resu l t in the low-order byte of the status register.

Condition Codes: x N z V c * 1 * 1 * 1 * 1 * 1

N Set if bit 3 of immediate operand is one. U nchanged otherwise. Z Set if bit 2 of immediate operand is one. U nchanged otherwise. V Set if bit 1 of immediate operand is one. U nchanged otherwise. C Set if bit 0 of immediate operand is one. U nchanged otherwise. X Set if bit 4 of immediate operand is one. U nchanged otherwise.

Instruction Format: 6 5 4 3 2

B-1 33

..

•

O RI to S R

Inclusive O R Immediate to the Status Register (Privileged Instruction)

Operation: If supervisor state

Assembler

then Source v SR - SR else TRAP

Syntax: ORI # < data > ,SR


O RI to S R

Description: I nc lus ive OR the immediate operand with the contents of the status reg ister and store the resu l t in the status register. A l l bits of the status reg ister are affected.

Condition Codes: x N z V c * 1 * 1 * 1 * 1 * 1 N Set if b it 3 of immediate operand is one. U nchanged otherwise. Z Set if b it 2 of immediate operand is one. U nchanged otherwise. V Set if b it 1 of immediate operand is one. Unchanged otherwise. C Set if b it 0 of immediate operand is one. Unchanged otherw ise. X Set if b it 4 of immediate operand is one. Unchanged otherw ise.

Instruction Format: 1 5 1 4 1 3 1 2 1 1 10 9 8 7 6 5 4 3 2 1 0

I 0 0 0 I 0 I 0 I 0 I 0 I 0 I 0 I 1 1 I 1 I 1 I 1 0 o I Word Data (16 Bits)

8·1 34

PAC K Pack PAC K

Operation: Source (Unpacked BCD) + adjustment - Dest i nation (Packed BCD)

Assembler Syntax:

Attributes:

PACK - (Ax), - (Ay),# < adjustment > PACK DX,Dy,# < adjustment >

U ns ized

Description: The low four bits of each of two bytes are adj usted and packed i nto a s ingle byte.

When both operands are data registers, the adjustment is added to the value contained in the source reg ister. Bits [1 1 :8] and [3:0] of the i ntermediate resu l t are concatenated and placed i n bits [7:0] of the dest i nation register. The remainder of the dest i nation reg ister is unaffected.

Source: 1 5 14

Ox I x I x 13 12 1 1 10

Add Adjustment Word:

9 8 c I d

7 6 5 4 3 2 x I x I x I x I e I f I 9

o

h I 15 14 13 12 1 1 10 9 8 7 6 5 4 3 2 0

16·Bit Extension

Resu l t ing in : 1 5 14 13 1 2 1 1 10 9 8 7 6 5 4 3 2 1 0 I x' I x' I x' I x' I a' I b' I c' d' I x' I x' I x' I x' I e' I f' g' h' I

Dest i nation: 15 1 4 13 1 2 11 10 9

OY I U I U I U l u u l u l u 8 7 6 5 4 3 2 1 0 u I a' I b' I c' I d' I e' I f' g' h' I

When the addressing mode specified is predecrement, two bytes from the source are fetched, adjusted, and concatenated. The extension word is added to the concatenated bytes. Bits [3:0] of each byte are extracted. These eight bits are concatenated to form a new byte which is then written to the destination .

Sou rce: 7 6 5 4 3 2 o

Concatenated Word: 1 5 14 13 12 11 10 9 8

B-1 35

7 6 5 4 3 2 0

•

•

PAC K Pack PAC K

Add Adjustment Word: 1 5 1 4 1 3 1 2 1 1 10 9 8 7 6 5 4 3 2 0

16-Bit Extension

Destination: 7 6 5 4 3 2 1 0

(Ay) I a' I b' I c' I d' I e' I I' I g' I h'


Instruction Format: 1 5 1 4 1 3 1 2 1 1 10 9 8 7 6 5 4 3 2 0

Register Register

Dy/Ay Dx/Ax

Adjustment

Instruction Fields: Register Dy/Ay field - Specifies the desti nation reg ister.

If RIM = 0, specifies a data reg ister. If RIM = 1 , specifies an address reg ister for the predecrement addressing mode.

RIM field - Specifies the operand addressing mode. 0-The operat ion is data reg ister to data reg ister. 1 -The operat ion is memory to memory.

Register DxlAx f ield - Specifies the source register. If RIM = 0, specifies a data register. If RIM = 1 , specifies an address reg ister for the predecrement addressing mode.

Adjustment f ield - Immediate data word which is added to the source operand. Appropriate constants can be used to trans late from ASCI I or EBCDIC to BCD .

B·1 36

P EA Push Effective Address

Operation: SP - 4 - SP; EA - (SP)

Assembler Syntax: PEA < ea >


P EA

Description: The effective address is computed and pushed onto the stack. A long word address is pushed onto the stack.


Instruction Format: 5

Instruction Fields:

4 3 2

Effective Address

Mode Register

o

Effective Address f ield - Specif ies the address to be pushed onto the stack. On ly control addressing modes are a l lowed as shown:


On - - (xxx).w 1 1 1 000

An - - (xxx).L 1 1 1 001


(An) + - -

- (An) - -

(d16,An) 1 01 reg. number:An (d1 6,PC) 1 1 1 010



([bd,An,Xnj,od) 1 10 reg. number:An ([bd,PC,Xnj,od) 1 1 1 0 1 1

([bd,Anj,Xn,od) 1 10 reg. number:An ([bd,PC),Xn,od) 1 1 1 0 1 1

8-1 37

•

•

R ESET

Operation: I f supervisor state

Reset External Devices (Privileged Instruction)

then Assert RESET Line else TRAP

Assembler Syntax: RESET


RESET

Description: The reset l ine is asserted, causing a l l external devices to be reset. The pro· cessor state, other than the program counter, is u naffected and execut ion conti nues with the next i nstruct ion.


Instruction Format: 1 5 1 4 1 3

o I 1 0

1 2 1 1 1 0 9 8 7 6 5

8·1 38

4 3 2

o I 0

1 0

o I 0

RO L RO R

Operation:

Assembler Syntax:

Attributes:

Rotate (Without Extend)

Desti nation Rotated by < cou nt > - Desti nation

ROd DX,Dy ROd # < data > , Dy ROd < ea > where d i s d i rection, L or R


RO L RO R

Description: Rotate the bits of the operand in the d i rection (L or R) specified. The extend bit is not i nc luded in the rotat ion. The rotate count for the rotat ion of a reg ister may be specif ied in two different ways: 1 . Immediate - the rotate count is specified in the instruct ion (rotate range, 1 -8). 2. Reg ister - the rotate count is contai ned in a data reg ister specif ied in the i nstruc

tion. The size of the operation may be specif ied to be byte, word, or long. The content of memory may be rotated by one bit only and the operand size is restricted to a word.

For ROL, the operand is rotated left; the number of positions rotated is the rotate count. Bits rotated out of the h igh order bit go to both the carry bit and back into the low order bit. The extend bit is not modif ied or used.

ROL: � •• ---+--�r------o

-pe-

r-a-nd

-----'� For ROR, the operand is rotated right; the number of positions rotated is the rotate count. Bits sh ifted out of the low order bit go to both the carry bit and back into h igh order bit . The extend bit is not modified or used.

ROR: �r------o

-pe-

r-a-nd------�---+--�.�

- Continued -

B-1 39

•

•

RO L RO R


1 - 1 * 1 * 1 0 * 1

Rotate (Without Extend)

RO L RO R

N Set if the most s ign i f icant bit of the resu l t is set. Cleared otherw ise. Z Set if the resu l t is zero. Cleared otherw ise. V A lways c leared. C Set accord ing to the last bit rotated out of the operand. Cleared for a rotate

count of zero. X Not affected.

Instruction Format (Register Rotate): 15 1 4 13 1 2 1 1 10 9 8 7 6 5 4 3 2 0

Rotatel

Register

Instruction Fields (Register Rotate): Rotate/Reg ister field -

Register

If i/r = O, the rotate count is specified in th is field. The values 0, 1 -7 represent a range of 8, 1 to 7 respectively.

If i/r = 1 , the rotate count (modu lo 64) is contai ned in the data reg ister specified in th is f ield.

dr f ield - Specif ies the d i rection of the rotate: O-rotate r ight. 1 -rotate left.

Size f ield - Specif ies the size of the operat ion: OO- byte operat ion. 01 -word operation. 1 0- long operat ion.

i/r field -If i/r = 0, specif ies immediate rotate count. If i/r = 1 , specif ies reg ister rotate count.

Reg ister f ield - Specif ies a data reg ister whose content is to be rotated .

Instruction Format (Memory Rotate):

8-1 40

5 4 3 2 Effective Address

Mode Register

o

- Continued -

ROL RO R Rotate (without Extend)

Instruction Fields (Memory Rotate): dr f ield - Specifies the d i rect ion of the rotate:

O-rotate right. 1 -rotate left.

RO L RO R

Effective Address field - Specif ies the operand to be rotated. Only memory alterable addressing modes are a l lowed as shown:


On - - (xxx).w 1 1 1 000

An - - (xxx).L 1 1 1 001

(An) 010 reg. number:An #I < data> - -(An) + 01 1 reg. number:An


(d16,An) 1 01 reg. number:An (d1 6, PC) - -(dS,An,Xn) 1 1 0 reg. number:An (ds,PC,Xn) - -(bd,An,Xn) 1 10 reg. number:An (bd,PC,Xn) - -

«bd,An,Xn),od) 1 1 0 reg. number:An ([bd,PC,Xn),od) - -«bd,An),Xn,od) 1 10 reg. number:An ([bd,PC),Xn,od) - -

8·1 41

•

•

ROXL ROXR

Operation:

Assembler Syntax:

Attributes:

Rotate with Extend

Dest i nation Rotated with X by < count > - Dest i nation

ROXd DX,Dy ROXd # < data > ,Dy ROXd < ea >


ROXL ROXR

Description: Rotate the bits of the dest i nation operand i n the d i rection spec if ied. The extend bit (X) is i nc luded in the rotation. The rotate count for the rotat ion of a reg ister may be specif ied in two different ways: 1 . Immediate - the rotate count is specif ied i n the i nstruction (rotate range, 1 -8). 2. Reg ister - the rotate count (modu lo 64) is contained in a data reg ister specif ied i n

the i nstruction. The s ize of the operation may be specif ied to be byte, word, or long. The content of memory may be rotated one bit on ly and the operand s ize is restricted to a word.

For ROXL, the operand is rotated left; the number of posit ions rotated is the rotate count. Bits rotated out of the h igh order bit go to both the carry and extend bits; the previous value of the extend bit is rotated into the low order bit.

ROXL: C �1.�-+l--�=======o=p=er=a=n=d======�I.�-4� For ROXR, the operand is rotated r ight; the number of pos it ions sh ifted is the rotate count. Bits rotated out of the low order bit go to both the carry and extend bits; the previous val ue of the extend bit is rotated into the h igh order bit.

ROXR: �--��I�-_-_-_-_-_o=p=er=a=nd======r-�l�-.�� Condition Codes:

x N z V c 1 · 1 · 1 · 1 0 · 1

N Set if the most S ign i f icant bit of the resu l t is set. Cleared otherw ise. Z Set if the resu l t is zero. C leared otherwise. V A lways cleared. C Set accord ing to the last bit rotated out of the operand. Set to the value of the

extend bit for a rotate count of zero. X Set accord ing to the last bit rotated out of the operand. Unaffected for a

rotate count of zero.

B-1 42

ROXL ROXR Rotate with Extend

Instruction Format (Register Rotate): 15 14 13 12 1 1 10 9 8 7 6 5 4 3 2 0

Rotatel

Register

Instruction Fields (Register Rotate): Count/Register f ield -

Register

ROXL ROXR

I f i/r = 0, the rotate count is specif ied in th is f ield. The values 0, 1 ·7 represent a range of 8, 1 to 7 respectively.

I f i/r = 1 , the rotate count (modu lo 64) is contained in the data reg ister spec ified i n th is f ield.

d r f ield - Specif ies the d i rect ion of the rotate: O-rotate r ight. 1 - rotate left.

S ize f ield - Specifies the s ize of the operat ion: OO-byte operat ion. 01 -word operation. 10- long operat ion.

i/r f ield -I f i/r = 0, specifies i mmediate rotate count. I f i/r = 1 , specifies reg ister rotate count.

Register field - Specifies a data reg ister whose content is to be rotated.

Instruction Format (Memory Rotate):

Instruction Fields (Memory Rotate):

5 4 3 2 0

Effective Address

Mode Register

dr f ield - Specif ies the d i rection of the rotate: O- rotate r ight. 1 -rotate left.

Effective Address field - Specif ies the operand to be rotated. On ly memory alterable addressing modes are a l lowed as shown:

8·1 43

•

•

ROXL ROXR

Addr. Mode

Dn

An

(An)

(An) +

- (An)

(d16,An)

(dB,An,Xn)

(bd,An,Xn)

([bd,An,Xnj,od)

([bd,Anj,Xn,od)

Mode

-

-

010

01 1

1 00

1 01

1 1 0

1 10

1 10

1 10

Rotate with Extend

Register Addr. Mode

- (xxx).w

- (xxx).L

reg. number:An " < data>

reg. number:An

reg. number:An

reg. number:An (d16,PC)

reg. number:An (dB,PC,Xn)


reg. number:An ([bd,PC,Xnj,od)

reg. number:An ([bd,PCj,Xn,od)

8·1 44

Mode

1 1 1

1 1 1 -

-

-

-

-

-

ROXL ROXR

Register

000

001 -

-

-

-

-

-

RT D Return and Deallocate Parameters

Operation: (SP) - PC; SP + 4 + d - SP

Assembler Syntax: RTD # < displacemen t >

Attributes: U ns ized

RT D

Description: The program counter is pu l led from the stack. The previous program counter value is lost. After the program counter is read from the stack, the d isplacement va lue (16 bits) is S ign-extended to 32 bits and added to the stack poi nter.



I 0 I 1 I 0 I 0 I 1 I 1 I Instruction Field:

9 8 7

1 0 I 0 I Displacement

6 5

1 I 1

4 I 1

3 2 0

Disp lacement f ield - Specif ies the twos complement i nteger which is to be s ignextended and added to the stack pai nter.

8-1 45

II

RTE Return from Exception (Privileged Instruction) RTE

Operation: I f supervisor state then (SP) -+ SR; SP + 2 -+ SP; (SP) -+ PC; SP + 4 -+ SP;

restore state and dea l locate stack according to (SP)

e lse TRAP

Assembler Syntax: RTE


Description: The processor state information in the except ion stack frame on top of the stack is loaded into the processor. The stack format field in the format/offset word is examined to determine how much information must be restored.

Condition Codes: Set accord ing to the content of the word on the stack.

Instruction Format: 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 0 I 0 I 1 I 0 I 0 I 1 I 1 I 1 I 0 0 I 1 I 1 I 1 I 0 0 I 1 I 1

Format/Offset Word ( in stack frame): 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 0

Format 0 0 Vector Offset

Instruction Fields: Format field - This 4-bit f ield def ines the amount of i nformat ion to be restored.

OOOO-Short Format, on ly four words are to be removed f rom the top of the stack. The status reg ister and program counter are loaded from the stack f rame.

0001 -Throwaway Format, four words are removed from the top of stack. On ly the status reg ister is loaded, after which, the processor beg ins executing the RTE from the top of the active system stack. This format is used to mark the bottom of the i nterrupt stack.

001 0 - l nstruction Error Format, six words are removed from the top of the stack. The f i rst four words are used as in the Short Format and the remain ing two words are thrown away.

1 000- M C68010 Long Format, the M C68020 takes a format error exception. 1 001 -Coprocessor M id-I nstruction Format, 1 0 words are removed from the top

of stack. Resumes coprocessor i nstruction execution. 1 01 0- M C68020 Short Format, 16 words are removed from the top of the

stack. Resumes i nstruction execution. 101 1 - MC68020 Long Format, 46 words are removed from the top of the stack.

Resumes instruction execution. Any others - the processor takes a format error exception.

8-1 46

RTM Return from Module

Operation: Reload Saved Module State from Stack

Assembler Syntax: RTM Rn


RTM

Description: A previously saved modu le state is reloaded from the top of stack. After the module state is retrieved from the top of the stack, the cal ler's stack pOinter is i ncremented by the argument count value i n the module state.


Instruction Format: 15 14 13 12 1 1 10 9 I 0 I 0 I 0 I 0 I 0 I 1 I 1

Instruction Fields:

8 7 6 5

o 4 3 2 0

o l OlA I Register

D/A f ield - Specifies whether the module data pointer is i n a data or an address reg ister. O-the reg ister is a data reg ister. 1 -the reg ister is an address reg ister.

Reg ister field - Specifies the reg ister number for the modu le data area poi nter which is to be restored from the saved modu le state. I f the reg ister specif ied is A7 (SP), the updated va lue of the reg ister reflects the stack poi nter operat ions, and the saved modu le data area pointer is lost.

8-1 47

•

•

RT R Return and Restore Condition Codes

Operation: (SP) - CCR; SP + 2 - SP; (SP) - PC; SP + 4 - SP

Assembler Syntax: RTR


RT R

Description: The cond it ion codes and program counter are pu l led from the stack. The previous cond it ion codes and program counter are lost. The supervisor port ion of the status reg ister is u naffected.



o I 1 0 0

1 1 1 0 9 8

o 7 6 5 4 3 2 o

I 1

8-1 48

RTS Return from Subroutine

Operation: (SP) -+ PC; SP + 4 -+ SP

Assembler Syntax: RTS


Description: The program counter is lost.

counter


Instruction Format: 1 5 1 4 1 3 1 2 1 1 1 0 9

0 I 1 I 0 0 I 1 I 1 I 1

i s pu l led from the stack. The

8 7 6 5 4 3 2

I 0 0 I 1 I 1 I 1 0 I 1 I

8·1 49

RTS

previous program

0

0 I 1

•

II

SBCD

Operation:

Assembler Syntax:

Attributes:

SBC D Subtract Decimal with Extend

Dest ination1 0 - Sou rce1 0 - X - Dest i nation

S8CD DX,Dy S8CD - (Ax), - (Ay)

Size = (8yte)

Description: Subtract the source operand from the dest i nation operand with the extend bit and store the resu l t in the dest i nation location. The subtract ion is performed using deci mal arithmetic. The operands may be addressed in two d i fferent ways: 1 . Data reg ister to data reg ister: The operands are contai ned in the data reg isters

specif ied in the i nstruct ion. 2. Memory to memory: The operands are addressed with the predecrement address

ing mode us ing the address reg isters specif ied in the i nstruct ion. This operation is a byte operation on ly.


1 * l u l * l u * 1 N U ndef ined. Z Cleared if the resu l t is non-zero. Unchanged otherw ise. V U ndef ined. C Set i f a borrow (dec i mal) is generated. Cleared otherwise. X Set the same as the carry bit.

NOTE Normal ly the Z cond it ion code bit is set v ia programming before the start of an operat ion. Th is a l lows successfu l tests for zero resu lts upon complet ion of mu l t ip le-precision operat ions.

Instruction Format:

Instruction Fields:

1 1 1 0 9

Register

Oy/Ay

4 3 2

Register DylAy f ield - Specif ies the dest i nation reg ister. I f RIM = 0, specif ies a data reg ister.

Register

Ox/Ax

o

If RIM = 1 , specif ies an address reg ister for the predecrement addressing mode. RIM f ie ld - Specif ies the operand addressing mode:

0-The operation is data reg ister to data reg ister. 1 -The operation is memory to memory.

Reg ister Ox/Ax f ield - Specif ies the source reg ister: If RIM = 0, specif ies a data reg ister. If RIM = 1 , specif ies an address reg ister for the predecrement addressing mode.

8-1 50

See Set According to Condition

Operation: If Cond it ion True

Assembler

then 1 s - Dest i nation else Os - Desti nation

Syntax: Scc < ea >


See

Description: The specif ied cond it ion code is tested; i f the cond it ion is t rue, the byte specif ied by the effective address is set to TRUE (al l ones), otherwise that byte is set to FALSE (al l zeroes). "cc" may specify the fol lowing cond it ions:

CC carry clear 0100 C CS carry set 0101 C EQ equal 01 1 1 Z F never true 0001 0 GE greater or equal 1 100 N.V + N.ij"

GT greater than 1 1 10 N.V.Z + N.V.Z HI high 0010 C'-Z LE less or equal 1 1 1 1 Z + N .V + N.V


Instruction Format:

Instruction Fields:

1 1 1 0 9

Condition

a

LS LT MI NE PL T VC VS

low or same 001 1 less than 1 101 minus 101 1 not equal 01 10 plus 1010 always true 0000 overflow clear 1000 overflow set 1001

5 4 3 2

Effective Address

Mode Register

o

Condit ion f ie ld - One of s ixteen cond it ions d iscussed i n description.

C + Z N.V + N.V

N Z N 1

V

V

Effective Address f ie ld - Specifies the locat ion i n which the true/false byte is to be stored. Only data alterable addressing modes are al lowed as shown:


On 000 reg. number:On (xxx)W 1 1 1 000

An - - (xxx).L 1 1 1 001




(d16,An) 101 reg. number:An (d1 6, PC) - -





Note: 1 . An arithmet ic one and zero resu l t may be generated by fol lowing the Scc i nstruct ion with a N EG i nstruct ion.

B-1 51

•

•

STO P Load Status Register and Stop

(Privileged Instruction)

Operation: If supervisor state

Assembler

then Immediate Data - SR; STOP else TRAP

Syntax: STOP # < data >

Attributes: Unsized

STO P

Description: The immediate operand is moved i nto the entire status register; the prog ram counter is advanced to point to the next instruction and the processor stops fetch ing and execut ing i nstructions. Execution of instructions resumes when a t race, interrupt, or reset except ion occurs. A t race except ion w i l l occur if the t race state is on when the STOP instruction beg ins execution. If an interru pt request is asserted with a priority h igher than the priority level set by the immediate data, an interru pt except ion occurs, otherwise, the interrupt request has no effect. If the bit of the immed iate data corresponding to the S-bit is off, execution of the instruction w i l l cause a privi lege violation. External reset w i l l a lways in itiate reset except ion processing.

Condition Codes: Set accord ing to the immediate operand.

Instruction Format: 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3

I 0 I 1 I 0 I 0 I 1 I 1 I 1 0 I 0 I 1 I 1 I 1 I 0

Immediate Data

Instruction Fields:

2 0

I 0 I 1 0 I Immediate field - Specifies the data to be loaded into the status reg ister .

8-1 52

SU B

Operation:

Assembler Syntax:

Attributes:

Subtract Binary

Dest i nation - Source -- Dest i nation

SUB < ea > ,Dn SUB Dn, < ea >


SU B

Description: Subtract the sou rce operand from the dest i nation operand and store the resu lt in the dest i nation. The s ize of the operation may be spec ified to be byte, word, or long. The mode of the i nstruct ion ind icates which operand is the source and which is the dest inat ion as wel l as the operand s ize.


1 * 1 * 1 * 1 * * 1 N Set if the resu l t is negat ive. Cleared otherwise. Z Set if the resu l t is zero. Cleared otherwise. V Set if an overflow is generated. Cleared otherw ise. C Set if a borrow is generated. Cleared otherwise. X Set the same as the carry bit.


Effective Address Register Op·Mode

Mode

Instruction Fields: Register f ield - Specif ies any of the eight data reg isters. Op-Mode f ield -

Byte Word Long Operation 000 001 010 < Dn > - < ea > -- < Dn > 1 00 1 01 1 1 0 < ea > - < Dn > -- < ea >

Effective Address field - Determi nes addressing mode:

Register

If the location specif ied is a source operand, then a l l addressing modes are a l lowed as shown:

B-1 53

•

•

SU B Subtract Binary SU B



An * 001 reg. number:An (xxx).L 1 1 1 001

(An) 010 reg. number:An #< data> 1 1 1 100



(d16,An) 101 reg. number:An (d1 6, PC) 1 1 1 010

(ds,An,Xn) 1 10 reg. number:An (dS,PC,Xn) 1 1 1 0 1 1




* For byte size operation, address register d i rect is not a llowed.

If the location specified is a destination operand, then only alterable memory addressing modes are al lowed as shown:


On - - (xxx).W 1 1 1 000

An - - (xxx).L 1 1 1 001









Notes: 1 . If the dest ination is a data reg ister, then it cannot be specif ied by using the destination < ea > mode, but must use the destination On mode instead.

2. SUBA is used when the dest ination is an address register. SUBI and SUBQ are used when the source is immediate data. Most assemblers automatical ly make th is disti nction .

B·1 54

SU BA Subtract Address

Operation: Dest i nation - Source - Desti nation

Assembler Syntax: SUBA < ea > ,An


SU BA

Description: Subtract the sou rce operand from the dest ination address reg ister and store the resu l t in the address reg ister. The s ize of the operat ion may be specif ied to be word or long. Word s ize source operands are sign extended to 32 bit quant it ies before the operat ion is done.


Instruction Format: 15 14 13 12 1 1 10 9 a 7

Register Op·Mode

Instruction Fields:

6 5 4 3 2

Effective Address

Mode Register

o

Register f ie ld - Specif ies any of the e ight address reg isters. Th is is a lways the dest i nation.

Op-Mode field - Specif ies the s ize of the operat ion: 01 1 -Word operation. The source operand is s ign-extended to a long operand

and the operat ion is performed on the address reg ister using al l 32 bits. 1 1 1 - Long operat ions.

Effective Address field - Specif ies the source operand. Al l addressing modes are al lowed as shown:







(d16,An) 1 01 reg. number:An (d1 6, PC) 1 1 1 010





B-1 55

•

•

SU B I Subtract Immediate

Operation: Desti nation - Immed iate Data - Dest ination

Assembler Syntax: SUBI # < data > , < ea >


SU BI

Description: Subtract the immediate data from the destination operand and store the resu lt i n the dest ination locat ion. The s ize of the operation may be spec if ied to be byte, word, or long. The s ize of the i mmediate data matches the operat ion s ize.


· 1 · 1 · 1 · 1 · 1 N Set if the resu l t is negative. Cleared otherw ise. Z Set i f the resu l t is zero. Cleared otherwise. V Set if an overflow is generated. Cleared otherwise. C Set if a borrow is generated. Cleared otherw ise. X Set the same as the carry bit.

Instruction Format: 15 14 13 12 1 1 10 9 8 7 6 5 4 3 2 0 0 1 0 1 0 1 0 1 0 1 1 1 0 1 0 Size 1

Word Data

Long Data

Instruction Fields: Size f ield - Specif ies the s ize of the operat ion.

OO-byte operation. 01 -word operat ion. 1 0- long operat ion.

Eflecllve Address

Mode 1 Register

Byte Data

Effective Address f ield - Specifies the destination operand. Only data alterable addressing modes are al lowed as shown:

B-1 56

SU B I Subtract Immediate SU BI



An - - (xxx).L 1 1 1 001




(d1 6,An) 101 reg. number:An (d16, PC) - -





I mmediate f ield - (Data immediately fol lowing the instruct ion) I f s ize = 00, then the data is the low order byte of the immediate word. I f s ize = 01 , then the data is the entire i mmediate word. I f s ize = 1 0, then the data is the next two immediate words.

8-1 57

II

•

SU BQ Subtract Quick

Operation: Dest ination - I m mediate Data -+ Destination

Assembler Syntax: SUBQ # < data > , < ea >


SU BQ

Description: Subtract the immed iate data from the dest ination operand. The data range is from 1 ·8. The s ize of the operation may be specif ied to be byte, word, or long. Word and long operations are also a l lowed on the address reg isters and the condition codes are not affected. When subtract ing from address reg isters, the ent ire dest i na· t ion address reg ister is used, regard less of the operat ion s ize.


* 1 * 1 * 1 * 1 * 1 N Set if the resu l t is negat ive. Cleared otherw ise. Z Set if the resu l t is zero. Cleared otherwise. V Set if an overflow is generated. Cleared otherwise. C Set if a borrow is generated. C leared otherw ise. X Set the same as the carry bit.

Data

Instruction Fields:

Effective Address

Mode Register

Data field - Three bits of immediate data, 0, 1 ·7 represent ing a range of 8, 1 to 7 respectively.

Size f ield - Specif ies the s ize of the operat ion: OO- byte operation. 01 -word operation. 1 0- long operat ion.

Effective Address field - Specif ies the dest i nation location. Only a lterable address ing modes are al lowed as shown:

B·1 58

SU BQ Subtract Quick SU BQ



A n * 001 reg. number:An (xxx).L 1 1 1 001




(d16,An) 1 01 reg. number:An (d16, PC) - -





* Word and long only.

•

8·1 59

•

SU BX

Operation:

Assembler Syntax:

Attributes:

Subtract with Extend SU BX

Dest i nation - Source - X -- Dest i nation

SUBX DX, Dy SUBX - (Ax), - (Ay)


Description: Subtract the source operand from the dest i nation operand along with the extend bit and store the resu l t i n the dest ination locat ion. The operands may be ad-dressed in two d ifferent ways:

.

1 . Data reg ister to data reg ister: The operands are contained i n data reg isters specif ied i n the i nstruction.

2. Memory to memory. The operands are contai ned in memory and addressed with the predecrement address ing mode us ing the address reg isters spec if ied in the i nstruct ion.

The s ize of the operand may be specif ied to be byte, word, or long.


· 1 · 1 · 1 · 1 · 1 N Set if the resu l t is negat ive. Cleared otherwise. Z Cleared if the resu l t is non-zero. Unchanged otherwise. V Set if an overflow is generated. Cleared otherwise. C Set if a carry is generated. Cleared otherwise. X Set the same as the carry bit.

NOTE Normal ly the Z cond it ion code bit is set via programming before the start of an operat ion. This a l lows successfu l tests for zero resu lts upon completion of mu l t ip le-precision operat ions.


Instruction Fields:

Register

Oy/Ay

Reg ister Dy/Ay f ield - Specif ies the desti nation reg ister: If RIM = 0, specif ies a data reg ister.

Register

Ox/Ax

I f RIM = 1 , specif ies an address reg ister for the predecrement addressing mode. Size f ield - Specif ies the s ize of the operat ion:


B-160

SU BX Subtract with Extend

RIM f ield - Specif ies the operand addressing mode: 0-The operation is data reg ister to data reg ister. 1 -The operation is memory to memory.

Reg ister Ox/Ax f ield - Specif ies the source reg ister: If RIM = 0, spec if ies a data reg ister.

SU BX

if RIM = 1 , specif ies an address reg ister for the predecrement addressing mode .

8-161

•

•

SWAP Swap Register Halves

Operation: Register [31 : 1 6] - Regi ster [1 5:0]

Assembler Syntax: SWAP On


Description: Exchange the 1 6·bit halves of a data reg ister.


1 - 1 * 1 * 1 0 1 0 1

SWAP

N Set if the most s ign i f icant bit of the 32·bit resu l t is set. Cleared otherw ise. Z Set if the 32·bit resu l t is zero. Cleared otherwise. V Always c leared. C Always c leared. X Not affected.

Instruction Format: 15 1 4 13 1 2 1 1 10 9 6 I 0 I 1 I 0 I 0 I 1 I 0 I 0 I 0

Instruction Fields:

7 6

o I 1

5 4

o I 0

Register f ield - Specif ies the data reg ister to swap .

8·1 62

3 2 0

o I Register

TAS Test and Set an Operand TAS

Operation: Dest i nation Tested -+ Cond it ion Codes; 1 -+ bit 7 of Destination

Assembler Syntax: T AS < ea >


Description: Test and set the byte operand addressed by the effective address f ield. The current value of the operand is tested and N and Z are set accord ing ly. The h igh order b i t of the operand is set. The operat ion is indiv is ib le (us ing a read-modify-write memory cyc le) to a l low synchron ization of several processors.


1 - 1 * 1 * 1 0 1 0 1 N Set if the most s ign if icant bit of the operand was set. Cleared otherwise. Z Set if the operand was zero. Cleared otherwise. V A lways c leared. C Always c leared. X Not affected.

Instruction Format: 15 14 13 12 1 1 10 9 e 7 6

Instruction Fields:

5 4 3 2

Effective Address

Mode Register

o

Effective Address f ield - Specif ies the locat ion of the tested operand. Only data alterable address ing modes are al lowed as shown:



An - - (xxx).L 1 1 1 001

(An) 010 reg. number:An # < data > - -(An) + 0 1 1 reg. number:An


(d16,An) 1 01 reg. number:An (d16,PC) - -(de,An,Xn) 1 10 reg. number:An (de,PC,Xn) - -(bd,An,Xn) 1 1 0 reg. number:An (bd,PC,Xn) - -



B-1 63

•

•

T RAP Trap

Operation: sSP - 2 -- SSP; Format/Offset -- (SSP); SSP - 4 -- SSP; PC -- (SSP); SSP - 2 -- SSP; SR -- (SSP); Vector Address -- PC

Assembler Syntax: TRAP # < vector >

Attributes: Unsized

TRAP

Description: The processor in i t iates exception proceSS i ng . The vector number is generated to reference the TRAP i nstruct ion exception vector speci fied by the low order four bits of the i nstruction. Sixteen TRAP i nstruction vectors (0- 1 5) are avai lable.


Instruction Format: 15 14 13 12 1 1 10 9 8

Instruction Fields:

7 6

o I 1

5 4

o I 0

3 2 o

Vector

Vector f ield - Specif ies which t rap vector conta ins the new program cou nter to be loaded .

8-164

T RAPcc Trap o n Condition TRAPcc

Operation:

Assembler Syntax:

Attributes:

If cc then TRAP

TRAPcc TRAPcc.W # < data > TRAPcc. L # < data >

Unsized or Size = (Word, Long)

Description: If the selected cond it ion is t rue, the processor in i t iates exception processi ng. The vector number is generated to reference the TRAPcc exception vector. The stacked program counter points to the next i nstruct ion. If the selected condit ion is not t rue, no operat ion is performed, and execution continues wi th the next i nstruct ion in sequence. The immediate data operand(s) is placed i n the next word(s) fol lowing the operation word and is (are) avai lable for user def in it ion for use with in the t rap handler. "cc" may specify the fol lowing conditions.

CC carry clear 0100 C LS low or same 001 1 C + Z CS carry set 0101 C LT less than 1 1 01 N .Y+ N.V EQ equal 01 1 1 Z MI minus 1011 N F never true 0001 0 NE not equal 01 1 0 Z GE greater or equal 1 1 00 N.V + N.Y PL plus 1010 Jq GT greater than 1 1 10 N.V.Z+ N.\i.Z T always true 0000 1 H I high 0010 �:Z VC overflow clear 1 000 Y LE less or equal 1 1 1 1 Z + N.Y + N.V VS overflow set 1 001 V



o I 1 I 0 I 1 I Condition I 1 I 1 I 1 I 1 I 1 I Op-Mode

Optional Word

or Long Word

Instruction Fields: Cond it ion field - One of s ixteen conditions discussed previous ly. Op-Mode field - Selects the i nstruct ion form.

01O-l nstruction is fol lowed by one operand word. 01 1 - l nstruction is fol lowed by two operands words. 1 00-l nstruction has no fol lowing operand words.

8-1 65

•

•

T RAPV

Operation: If V then TRAP

Assembler Syntax: TRAPV


Trap on Overflow T RAPV

Description: I f the overflow condit ion is set, the processor in i t iates except ion processing. The vector nu mber is generated to reference the TRAPV exception vector. If the overflow condit ion is c lear, no operat ion is performed and execution cont inues with the next i nstruction in sequence.


Instruction Format: 1 5 1 4

o 1

1 3 1 2

o 0

1 1 10 9 8 7 6 5 4 3 2 0

8-1 66

TST Test an Operand

Operation: Desti nation Tested -+ Condition Codes

Assembler Syntax: TST < ea >


TST

Description: Compare the operand with zero. No resu lts are saved; however, the condit ion codes are set accord ing to resu lts of the test. The size of the operat ion may be spec ified to be byte, word , or long.


1 - 1 * 1 * 1 0 0 1 N Set if the operand is negat ive. Cleared otherw ise. Z Set if the operand is zero. Cleared otherw ise. V Always cleared. C Always cleared. X Not affected.

Instruction Format: 15 14 13 12 11 10 9 s 7 6 5 4 3 2

Effective Address

Instruction Fields: Size f ield - Specifies the s ize of the operation:

OO- byte operation. 01 -word operat ion. 1 0- long operat ion.

Mode Register

o

Effective Address f ield - Specifies the dest i nation operand. If the operat ion s ize is word or long, a l l addressing modes are a l lowed. If the operat ion s ize is byte, only data address ing modes are a l lowed as shown:



An - - (xxx).l 1 1 1 001 (An) 010 reg. number:An # < data > - -





(bd,An,Xn) 1 1 0 reg. number:An (bd,PC,Xn) 1 1 1 011

([bd,An,XnJ,od) 1 1 0 reg. number:An ([bd,PC,XnJ,od) 1 1 1 01 1

([bd,AnJ,Xn,od) 1 10 reg. number:An ([bd,PCJ,Xn,od) 1 1 1 0 1 1

B-1 67

•

•

U N L K Unlink

Operation: An - SP; (SP) - An; SP + 4 -- SP

Assembler Syntax: U N LK An

Attributes: Unsized

U N L K

Description: The stack pointer is loaded from the specified address register. The address reg ister is then loaded with the long word pu l led from the top of the stack.



Instruction Fields:

8 7 6 5 4 3

1 I 1

2 0

Register

Register f ield - Specif ies the address reg ister through which the un l i nking is to be done.

8-1 68

U N P K Unpack BCD U N P K

Operation: Source (Packed BCD) + adjustment -- Destination (Unpacked BCD)

Assembler Syntax:

Attributes:

UN PACK - (Ax), - (Ay),# < adjustment > U N PK DX,DY,# < adjustment >

Unsized

Description: I n the u npack operat ion, two BCD d ig its with in the byte source operand are separated i nto two bytes with the BCD d ig i t resid ing in the lower n ibble and 0 in the upper n ibble. The adjustment is then added to this u npacked value without affect ing the cond it ion codes.

When both operands are data reg isters, the source reg ister contents are unpacked, the extension word is added, and the result is p laced in the desti nation reg ister. The h igh word of the dest i nation reg ister is u naffected.

Source: 15 14 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 0

Ox I u I u I u I u u I u I u I u I a I b I c I d I e I f I 9 I h

I ntermediate Expansion: 1 5 1 4 1 3 1 2 1 1 10 9 8 7 6 5 4 3 2 0

I 0 I 0 I 0 I 0 I a I b I c I d I 0 I 0 I 0 0 e I f I 9 I h Add Adjustment Word:

1 5 1 4 1 3 1 2 1 1 10 9 8 7 6 5 4 3 2 0

16·Bit Extension

Dest i nation: 15 14 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 0

Oy I v I v I v I v I a' I b' I c' I d' I w I w w I w I e' I f' g' I h' When the address ing mode spec ified is predecrement, two BCD dig its are extracted from a byte at the source address. After adding the extension word, two bytes are then written to the desti nation address.

Source: 7 6 5 4 3 2 1 0

a I b I c I d I e I f I 9 I h

(Ax)

- Conti nued -

B-1 69

•

•

U N P K

I ntermediate Expansion: 1 5 1 4 1 3 1 2 1 1 10

I 0 I 0 I 0 I 0 I a I b

Add Adj ustment Word : 1 5 1 4 1 3 1 2 1 1 10

Dest i nation: 7

Unpack BCD

9 8 7

I c I d 0

9 8 7 "16·Bit Extension

6 5 4

6 5

I 0 I 0

6

3 2

5

4 3

0 e

4 3

o

I v : 1 : 1 : 1 : 1 � I � I : I (Ay) w "


Instruction Format:

U N P K

2 0

I f I g I h

2 0

15 14 1 3 12 1 1 10 9 8 7 6 5 4 3 2 0

Instruction Fields:

Register

Dy/Ay

Register DylAy field - Specif ies the dest ination reg ister. I f RIM = 0, specif ies a data reg ister.

Register Dx/Ax

I f RIM = 1 , spec ifies an address reg ister for the predecrement addressing mode. RIM f ield - Specifies the operand addressing mode.

0-The operat ion is data reg ister to data reg ister. 1 -The operat ion is memory to memory.

Reg ister DxlAx f ield - Specif ies the data reg ister. I f RIM = 0, specifies a data reg ister. I f RIM = 1 , specifies an address reg ister for the predecrement addressing mode.

Adjustment field - I m mediate data word which is added to the source operand. Appropriate constants can be used to trans late from BCD to ASCI I or EBCDIC .

B-1 70

APPEN DIX C I NSTRUCTION FORMAT SU M MARY

This appendix provides a summary of the primary words in each instruct ion of the i nstruct ion set. The complete i nstruction def in i t ion consists of the primary words fol lowed by the addressing mode operands such as immediate data fields, d isplacements, and index operands. Table C-1 is an operat ion code (opcode) map which i l l ustrates how bits 15 through 12 are used to specify the operat ions. The fi rst sect ion g roups the standard i nstruct ions accord i ng to the opcode map. Disti nctions are made as to processor model su pport. Later processors support all earl ier model i nstructions and addressing modes. The next section documents coprocessor i nstruct ion forms. The last shows coprocessor pri mit ives which themselves are not i nstructions but are command formats used across the coprocessor i nterface.

Table C·1 . Operation Code Map

Bits 15 through 12 Operation

()()()() Bit Manipulation/MOVEP/ lmmediate 0001 Move Byte 0010 Move Long 001 1 Move Word 0100 M iscellaneous 0101 AOOO/ SUBO/ Scc/OBccITRAPcc 0 1 1 0 Bcc/ BSR/BRA 01 1 1 MOVEO 1000 OR/OIV /SBCO 1 001 SUB/SUBX 1010 (Unassigned, Reserved) 101 1 CMP/EOR 1 100 ANO/MULI ABCO/ EXG 1 101 AOO/AOOX 1 1 10 Shift/Rotate/Bit Field 1 1 1 1 Coprocessor Interface

C-1

•

•

Table C·2. Effective Addressing Mode Categories

Address Modes Mode Register Data Memory

Data Register Direct 000 reg. no. X -

Address Register Direct 001 reg. no. - -

Address Register Indirect 010 reg. no. X X Address Register Indirect

with Postincrement 0 1 l reg. no. X X Address Register Indirect

with Predecrement 100 reg. no. X X Address Register Indirect

with Displacement 101 reg. no X X Address Register Indirect with

Index IS-Bit Displacement! 1 10 reg. no. X X Address Register Indirect with

I ndex I Base Displacementl 1 1 0 reg. no. X X Memory Indirect Post-Indexed 1 10 reg. no. X X Memory Indirect Pre- Indexed 1 1 0 reg. no. X X Absolute Short 1 1 1 000 X X Absolute Long 1 1 1 001 X X Program Counter Indirect

with Displacement 1 1 1 101 X X Program Counter Indirect with

Index IS-Bit Displacement! 1 1 1 01 1 X X Program Counter Indi rect with

Index I Base Displacementl 1 1 1 01 1 X X PC Memory Indirect

Post-Indexed 1 1 1 01 1 X X PC Memory Indirect

Pre-Indexed 1 1 1 01 1 X X Immediate 1 1 1 100 X X

Table C·3. Conditional Tests

Mnemonic

T * F* H I LS

CCIHSI CSI LOI

NE EO VC VS PL MI GE LT GT LE

• = Boolean AND + = Boolean OR

Condition

True False High

Low or Same Carry Clear Carry Set Not Equal

Equal Overflow Clear Overflow Set

Plus Minus

Greater or Equal Less Than

Greater Than Less or Equal

N = Boolean NOT N

Encoding

0000 0001 0010 0011 0100 0101 0 1 10 01 1 1 1000 1001 1010 1011 1 100 1 101 1 1 10 1 1 1 1

* Not available for the Bee and cpBcc instructions

C·2

Control Alterable - X - X X X

- X

- X

X X

X X

X X X X X X X X X X

X -

X -

X -

X -

X -

- -

Test 1 0

C·Z C + Z

C C Z Z V V N N

N . V + N.V N·V + N·V

N .V .Z+ N .V.7 Z + N.V + N.V

Assembler Syntax

On An

IAnl

IAnl +

- IAnl

I d16,Anl

Ids,An,Xnl

Ibd,An,Xnl ( [bd,An I ,Xn ,odl l [bd ,An,XnJ ,odl

Ixxxl .W Ixxxl . L

Id16,PCI

Ids ,PC ,Xnl

Ibd,PC,Xnl

l [ bd, PCI ,Xn ,odl

l [ bd,PC,XnJ ,odl # < data >

STANDARD INSTRUCTIONS

OR Immediate

15 14 13 12 1 1 10 9 8 7 6

Size field: 00 = byte 01 = word 10 = long

OR Immediate to CCR

15 1 4 1 3 1 2 11 10 9 8 7 6

OR Immediate to S R

5

5

4 3 2

Effective Address

Mode Register

4 3 2

o

o

1 5 14 1 3 12 1 1 10 9 8 7 6 5 4 3 2 1 0

CMP2 (MC68020)

1 5 14 1 3 1 2 1 1 10 9

0 0 I 0 I 0 0 Size

AID Register 0 0 1 0 Size field: 00 = byte 01 = word 1 0 = long

CHK2 (MC68020)

Dynamic Bit

15 1 4 13 1 2 11 10 9

0 0 I 0 I 0 0 Size

AID Register 1 o 1 0 Size field: 00 = byte 01 = word 10 = long

15 14 13 12 11 10 9

Data

Register

Type field: 00 = TST 10 = CLR 01 = CHG 1 1 = SET

C-3

Word Data

8 7 6 5

0 1 1

0 0 0 0

8 7 6 5

0 1 1

0 0 0 0

8 7 6 5

o I 0

4 3 2 o

Effective Address

Mode 1 Register 1 0 1 0 1 0 1 0 1 0

4 3 2 o

Effective Address

Mode I Register 1 0 1 0 1 0 1 0 1 0

4 3 2

Effective Address

Mode Register

o •

MOVEP

15 14 13 12 1 1 1 0 9 8 7 6 5 4 3 2 0

Data Address

Register Op-Mode

Register

Op-Mode field: 100 = transfer word from memory to register 101 = transfer long from memory to register 1 10 = transfer word from reg ister to memory 1 1 1 = transfer long from register to memory

AND Immediate

1 5 1 4 1 3 1 2 1 1 10 9 8 7 6 5 4 3 2 0

Effective Address

Mode Register


AND Immediate to CCR

1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0

I 0 I 0 I 0 I 0 I 0 I 0 I 1 I 0 I 0 0 0 0

0 0 0 0 0 0 0 0 Byte Data

AND Immediate to SR

1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 0

0 0 0 0 0 0 0 0 0 0

Word Data

SUB Immediate

1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 0

Effective Address

Mode Register

Size field: 00 = byte 01 = word 1 0 = long

ADD Immediate

1 2 1 1 1 0 9 8 7 6 5 4 3 2 0

Effective Address

• Mode Register


C-4

RTM (MC68020)

1 5 1 4 1 3

0 0 0

1 2 1 1 1 0 9

CALLM (MC68020)

15 1 4 13 12 1 1 10 9

0 0 0 0 0 1 1

0 0 0 0 0 0 0

CAS (MC68020)

15 14 13 12 1 1 10 9

0 0 0 0 1 Size

0 0 0 0 0 o I 0


CAS2 (MC68020) 15 14 1 3 1 2 1 1 10 9

0 o I 0 I 0 1 Size

D/A1 Register 1 0 o I 0

D/A2 Register 2 0 o I 0

8 7 6

8 7 6

0 1 1 1

0

8 7 6

0 1 1 1 1

Du

8 7 6

o J 1 .1 1

Du1

Du2

Size field: 01 = byte 1 0 = word 1 1 = long

Static Bit

EOR Immediate

15 1 4 1 3 12 11 10 9

0 0 0 0 1

0 0 0 0 0

Type field: 00 = TST 1 0 = CLR 01 = CHG 11 = SET

1 5 1 4 1 3 1 2 1 1

0 0

0 0

1 0 9


C-5

8 7 6

o 1 Type

8 7 6

I I

I I

5

o

5

5

0

5

1

0

0

5

4 3 2 0

o I D/A I Register

4 3 2 o

Effective Address

Mode I Register

Argument Count

4 3 2 o

Effective Address

Mode I Register

I 0 I 0 I Dc

4 3 2 o

1 1 1 I 0 I 0

0 0 Dc1

0 0 Dc2

4 3 2 o

Effective Address

Mode I Register

Bit Number

5 4 3 2

Effective Address

Mode Register

o •

EOR Immediate to CCR

15 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0

0 0 I 0 I 0 I 1 I 0 I 1 I 0 I 0 0 1 I 1 I 1 0 0

0 0 0 0 0 0 0 0 Byte Data

EOR Immediate to SR

1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 1 I 1 I 1 0 0

Word Data

CMP Immediate

1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 0

Effective Address

Mode Register


MOVES (MC68010)

1 5 1 4 1 3 1 2 1 1 10 9 8 7 6 5 4 3 2 0

0 o I 0 I 0 1 1 0 Size

Effective Address 1

Mode 1 Register

AID Register dr 0 0 0 o 1 0 0 1 0 1 0 1 0 1 0 1 0 dr field: 0 = EA to register

1 = register to EA

MOVE Byte

1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 0

Destination Source


Note register and mode locations

MOVEA Long

1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 0

• Destination Source

Register Mode Register

C-6

MOVE Long

1 5 1 4 1 3 1 2 1 1 10 9 8 7 6 5 4 3 2 0

Destination Source



MOVEA Word

1 5 1 4 1 3 1 2 1 1 10 9 8 7 6 5 4 3 2 0

Destination Source


MOVE Word

1 5 1 4 1 3 1 2 1 1 10 9 8 7 6 5 4 3 2 0

Destination Source



N EGX

1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 0

Effective Address

Mode Register

Size field: 00 = byte 01 = wore( 10 = long

MOVE from SR

1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 0

Effective Address

Mode Register

CHK

1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 0

Data Effective Address


Size field: 1 0 = Longword (MC68020) • 1 1 = Word

C-7

LEA

1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 0

Address Effective Address


CLR

1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 0

Effective Address

Mode Register


MOVE from CCR (MC6801 0)

1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 0

Effective Address

Mode Register

NEG

1 5 1 4 1 3 1 2 1 1 10 9 8 7 6 5 4 3 2 0

Effective Address

Mode Register


MOVE to CCR

15 14 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 0

Effective Address

Mode Register

NOT

1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 0

Effective Address

Mode Register


• MOVE to SR

1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 0

Effective Address

Mode Register

c·a

N BCD

1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 0

Effective Address

Mode Register

LINK Long (MC68020)

1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 0

o 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 Data 0 0 0 0 0 0 0

Register

High-Order Displacement

Low-Order Displacement

SWAP

1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 0

I I I I I I I I I I I I I I Data 0 0 0 0 0 0 0 0 0 0

Register

BKPT (MC6801 0)

1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 0

0 1 0 0 1 0 0 0 0 I 1 0 0 I 1 Vector

PEA

5 4 3 2 0

Effective Address

Mode Register

EXT/EXTB (EXTB-MC68020)

1 5 1 4 1 3 1 2 1 1 10 9 8 7 6 5 4 3 2 0

I I I I I I I I I I I I Data 0 0 0 0 0 Type 0 0 0

Register

Type Field: 01 0 = Extend Word 0 1 1 = Extend Long 1 1 1 = Extend Byte Long - (MC68020)

MOVEM Registers to EA • 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 0

Effective Address

Mode Register

Sz field: 0 = word transfer 1 = long transfer

C-g

•

TST

1 5 1 4 1 3 1 2 1 1

Size field: 00 = byte 01 = word

TAS

1 5 1 4 1 3 1 2

I LLEGAL

15 14 1 3 1 2

0 1 1 0 I- 0

M U LS/MULU Long (MC68020)

1 5 1 4 1 3 1 2

0 1 I 0 I 0

0 DI

Type Field: 0 = MULU 1 = MULS

DIVS/DIVU Long (MC68020) DIVUUDIVSL (MC68020)

1 1

1 1

1 1

1 1

1

Type

1 0 9 8 7 6 5 4 3 2

Effective Address

Mode Register

1 0 = long

1 0

1 0

0 1

10

1

Size

9 8 7 6 5 4 3 2

Effective Address

Mode Register

9 8 7 6 5 4 3 2 1

1 0 I 1 I 1 I 1 1 I 1 I 1 0

9 8 7 6 5 4 3 2

Effective Address 0 0 0 0

Mode I Register

0 0 ' 0 0 0 1 0 1 Dh

Size Field: 0 = Longword Product 1 = Quadword Product

15 14 13 12 1 1 10 9 8 7 6 5 4 3 2

0 1 I 0 I 0 Dq

Type Field: 0 = DIVU 1 = DIVS

MOVEM EA to Registers

0 1 1

Type Size

Effective Address 0 0 0 1

Mode 1 Register

0 0 0 0 o 1 0 1 0 1 Dr

Size Field: 0 = Longword Dividend 1 = Quadword Dividend

5 4 3 2

Effective Address

Mode Register

Sz field: 0 = word transfer 1 = long transfer

C-1 0

0

0

0

0

0

o

o

TRAP

15 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 0

o I 1 I 0 0 1 I 1 I 1 o I 0 1 I 0 0 Vector

LINK Word

1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 0

I I I 0 I 1 1 I 1 1 I I 0 I 1 I I I I Address 0 1 0 1 0 0 1 0

Register

U N LK

1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 0

I 0 I I 0 I 0 I I I I 0 I 0 I I 0 I I I Address

Register

MOVE to USP

1 5 1 4 1 3 1 2 1 1 10 9 8 7 6 5 4 3 2 0

I 0 I I 0 I 0 1 1 I I I 0 I 0 1 1 I I 0 I Address 1 1 0

Register

MOVE from USP

15 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 0

I 0 I I I I I 1 1 I I I I I 1 1 I Address 0 0 0 0 0

Register

RESET

1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0

0 1 I o I 0 1 I 1 I 1 o I 0 I 1 I 1 I 1 I 0 · 0 0 I 0

NOP

1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0

0 1 0 0 1 I 1 1 I 0 0 I 1 I 1 I 1 0 0 0 I 1 •

C-1 1

•

STOP

1 5 1 4 1 3 1 2 1 1 10 9 8

0 1 0 0 I 1 1 I 1 0

RTE

15 14 13 12 1 1 10 9 8

0 I 1 0 I 0 I 1 I 1 I 1 0

RTD (MC6801 0)

1 5 1 4 1 3 1 2 1 1 10 9 8

I 0 1 I 0 I 0 I 1 I 1 I 1 I 0

RTS

1 5 1 4 1 3 1 2 1 1 10 9 8

0 1 I 0 0 1 I 1 I 1 0

TRAPV

1 5 1 4 1 3 1 2 1 1 10 9 8

0 I 1 0 I 0 I 1 1 I 1 I 0

RTR

15 1 4 1 3 1 2 1 1 10 9 8

0 I 1 0 I 0 I 1 I 1 I 1 I 0

MOVEC (MC6801 0)

dr field: 0 = control register to general register 1 = general reg ister to control register

Control Register field: $000 = SFC $001 = DFC $002 = CACR (MC68020) $8oo = USP

C-1 2

7 6 5 4 3 2 0

I 0 I 1 I 1 1 I 0 0 I 1 0 I

7 6 5 4 3 2 0

I 0 I 1 I 1 I 1 I 0 0 I 1 I 1

7 6 5 4 3 2 0

I 0 I 1 I 1 I 1 I 0 I 1 I 0 I 0

7 6 5 4 3 2 1 0

I 0 I 1 I 1 I 1 0 I 1 0 I 1

7 6 5 4 3 2 0 I 0 I 1 I 1 1 0 I 1 I 0

7 6 5 4 3 2 0

I 0 I 1 I 1 I 1 I 0 ! 1 I 1

$801 = VBR $802 = CAAR (MC68020) $803 = MSP (MC68020) $804 = ISP (MC68020)

JSR

1 5 1 4 1 3 1 2 1 1 10 9 8 7 6 5 4 3 2 0

Effective Address

Mode Register

JMP

1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 0

Effective Address

Mode Register

ADDQ

1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 0

Effective Address Data

Mode Register

Data field: Three bits of immediate data, 0, 1·7 representing a range of 8, 1 to 7 respectively.


See

1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 5 4 3 2 0

Effective Address Condition

Mode Register

OSee

1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 0

I I I I I I I I I I Data 0 0 Condition 0 0

Register

TRAPee (MC68020)

1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 0

0 0 Condition Mode

Operand

Mode Field: 010 = Word Operand 0 1 1 = Longword Operand 1 00 = No Operand •

C-1 3

SUBQ

Bee

BRA

BSR

MOVEQ

OR

•

1 1 1 0 9 5 4 3 2

Effective Address Data

Mode Register

Data field: Three bits of Immediate data, 0, 1-7 representing a range of 8, 1 to 7 respectively.


15 14 13 12 1 1 1 0 9 8 7 6 5 4 3 2

o I 1 I 1 I o I Condition I 8-Blt Displacement

16-Blt Displacement If 8-Blt Displacement = $00

32-Bit Displacement if 8-Blt Dlplacement = $FF

15 1 4 13 1 2 1 1 1 0 9 8 7 6 5 4 3 2

o I 1 I 1 I 0 1 0 1 0 1 0 1 0 1 8-Blt Displacement

16-Bit Displacement if 8-Bit Displacement = $00

32-Bit Displacement If 8-Blt Displacement = $FF

15 14 1 3 12 11 10 9 8 7 6 5 4 3 2

o I 1 I 1 I o I o I 0 I 0 I 1 I 8-Bit Displacement

16-Bit Displacement if 8-Bit Displacement = $00

32-Bit Displacement if 8-Bit Displacement = $FF

15 1 4 13 12 1 1 1 0

Data

Register

9 8 7 6 5 4

Data

Data field: Data is sign extended to a long operand and al l 32 bits are transferred to the data register.

1 1 1 0 9 8 7 6 5 4

3 2

3 2


Op-Mode field: Byte Word 000 001 1 00 101

Register Op-Mode

Long 010 1 1 0

Operation « ea » v« Dn » - < Dn > « Dn» v« ea » - < ea>

C-1 4

Mode Register

o

o

o

o

o

o

DIVUlDIVS Word

1 4 12 11 1 0 9 7 5 4 3 2


SBCD

Type field: 0 = DIVU

1 5 1 4 1 3 12

Register

1 = DIVS

1 1 1 0 9

Destination

Register*

RIM field: 0 = data register to data register 1 = memory to memory

* If RIM = 0, specifies a data register

Mode

8 7 6 5 4 3

If RIM = 1 , specifies an address register for the predecrement addressing mode.

PACK (MC68020)

1 5 1 4 1 3 1 2 1 1 1 0 9

Destination

Register*

8 7 6

16-9it Extension: Adjustment

RIM field: 0 = data reg ister to data register 1 = memory to memory

* If RIM = 0, specifies a data reg ister

5 4 3


U N PK (MC68020)

SUB

1 5 1 4 1 3 1 2 1 1 10 9

Destination

Register*

RIM field: 0 = data register to data register 1 = memory to memory

* If RIM = 0, specifies a data register

4 3


1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3

2

2

2

2

Register

Source

Register*

Source

Register*

Source

Register*


Register Op·Mode

Mode Register

Op-Mode field: Byte Word Long Operation 000 001 010 « Dn» - « ea » - < Dn > 100 1 01 1 10 « ea » - « Dn » - < ea >

C-1 5

0

0

o

o

0

•

SUBA

1 5 1 4 1 3 1 2 1 1 10 9 8 7 6 5 4 3 2 0


Register Op-Mode

Mode Register

Op-Mode field: Word Long Operation 0 1 1 1 1 1 « An » - « ea » - < A n >

SUBX

15 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 0

Destination Source

Register* Register"

Size field: 00 = byte 01 = word 1 0 = long RIM field: 0 = data register to data register 1 = memory to memory * If RIM = 0, specifies a data register

I f RIM = 1 , specifies an address register for the predecrement addressing mode_

CMP

1 1 1 0 9 8 7 6 5 4 3 2 0


Register Op-Mode

Mode Register

Op-Mode field: Byte Word Long Operation 000 001 010 « Dn » - « ea »

CMPA

1 1 1 0 9 8 7 6 5 4 3 2 0


Register Op-Mode

Mode Register

Op-Mode field: Word Long Operation 0 1 1 1 1 1 « An » - « ea »

EOR

1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 0


Register Op-Mode

Mode Register

Op-Mode field: Byte Word Long Operation

• 1 00 1 01 1 10 « ea » e « Dn » - < ea >

C-1 6

CMPM

1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 0

Destination Source

Register Register


AND

1 1 1 0 9 8 7 6 5 4 3 2 0 Data Effective Address

Register Op·Mode

Mode Register

Op·Mode field: Byte Word Long Operation 000 001 010 « ea » A« Dn» - < On > 1 00 1 01 1 10 « Dn» A« ea » - < ea >

MULU Word M U LS Word

1 5 1 4 1 3 1 2 1 1 10 9 8 7 6 5 4 3 2 0



Type field: 0 = MULU 1 = MULS

ABCD

1 5 1 4 1 3 1 2 1 1 10 9 8 7 6 5 4 3 2 0

Destination Source

Register* Register'

RIM field: 0 = data register to data register 1 = memory to memory * If RIM = 0, specifies a data register

I f RIM = 1 , specifies an address register for the predecrement addressing mode.

EXG Data Registers

1 5 1 4 1 3 1 2 1 1 10 9 8 7 6 5 4 3 2 0

Data Data

Register Register

EXG Address Registers

1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 0 • Address Address

Register Register

C·1 7

•

EXG Data Register and Address Register

1 5 1 4 1 3 1 2 1 1 1 0 9 7 4 3 2

Data Address

Register Register

ADD

15 1 4 1 3 1 2 1 1 10 9 8 7 6 5 4 3 2


Register Op-Mode

Mode Register

Op-Mode field: Byte Word Long Operation 000 001 010 « ea » + « Dn» - < Dn > 1 00 101 1 1 0 « Dn » + « ea» - < ea >

ADDA

1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2

Address Effective Address

ADDX

Register Op-Mode

Mode

Op-Mode field: Word Long Operation 01 1 1 1 1 « ea » + « An » - < An >

1 5 1 4 1 3 1 2 1 1 10 9

Destination Register*


8 7 6 5

RIM field: 0 = data register to data register 1 = memory to memory * If RIM = 0, specifies a data register

4 3


SHI FT/ROTATE - Register

15 1 4 13 12 1 1 1 0

Countl

Register

9 8 7

Count/Register field: If i/r field = 0, specifies shift count

6 5

If i/r field = 1 , specifies a data register that contains the shift count

dr field: 0 = right 1 = left Size field: 00 = byte 01 = word 10 = long i/r field: 0 = immediate shift count 1 = register shift count Type field: 00 = arithmetic shift 10 = rotate with extend

01 = logical shift 1 1 = rotate

C·1 8

4 3

2

2

Register

Source Register'

Data

Register

0

0

0

o

o

SHIFT/ROTATE - Memory

1 5 14 13 1 2 1 1 1 0 9 8 7 6 5 4 3 2

Effective Address

Mode Register

Type field: 00 = arithmetic shift 01 = logical shift 10 = rotate with extend 11 = rotate dr field: 0 = right 1 = left

Bit Field (MC68020)

1 5 14 13 12 1 1 1 0 9

1 1 I 1 I 0

0 Register

Type Field: 000 = BFTST 001 = BFEXTU 010 = BFCHG 0 1 1 = BFEXTS

1 Type

Do

1 00 = BFCLR 1 01 = BFFFO 1 1 0 = BFSET 1 1 1 = BFINS

8 7 6

I 1 I 1

Offset

Register Field Is 000 for BFTST, BFCHG, BFCLR, and BFSET Do field: 0 = Offset Is Immediate 1 = Offset Is Data Register Ow field: O = Wldth is Immediate 1 = Width Is Data Register

C-1 9

5 4 3 2

Effective Addres

Mode I Register

Ow I Width

o

o

•

/'

•

COPROCESSOR INSTRUCTIONS

cpGEN (MC68020)

1 5 14 13 12 1 1 10 9 8 7 6 5 4 3 2 o Cp-Id I I I I Effective Address o 0 0 II------:-:-:----r-----::---:-:---I

Mode I Register

Coprocessor Dependent Command Word

cpScc (MC68020)

1 5 14 13 12 1 1 10 9 8 7 6 5 4 3 2 o Effective Address 1 1 1 1 Cp-Id 0 0 1

Mode 1 Register

0 0 0 0 0 1 0 1 0 0 0 0 Coprocessor Condition

cpDBcc (MC68020)

15 14 13 12 1 1 10 9 8 7 6 5 4 3 2 o 1 1 1 1 1 1 1 1 Cp-Id 1 0 1 0 1 1 I o I 0 I 1 I Register

0 I 0 I 0 I 0 I 0 I 0 I o I 0 I 0 I 0 I Coprocessor Condition

Displacement

cpTRAPcc (MC68020)

15 1 4 13 12 1 1 10 9 8 7 6 5 4 3 2 o 1 1 1 1 1 1 1 1 Cp-Id 1 0 1 0 1 1 1 1 I 1 I 1 I Mode

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Coprocessor Condition Operand

Mode field: 010 = Word Operand 01 1 = Longword Operand 100 = No Displacement

cpBcc (MC68020)

1 5 14 13 12 1 1 10 9 5 4 3 2 o Cp-Id Coprocessor Condition

Displacement

Size field: 0 = Word Displacement 1 = Longword Displacement

C·20

cpSAVE (MC68020)

1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 0

Effective Address Cp-Id

Mode Register

cpRESTORE (MC68020)

1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 0

Effective Address Cp-Id

Mode Register

•

C-21

COPROCESSOR PRIMITIVES (MC68020)

BUSY

1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0

I 1 I PC I 1 I o I 0 I 1 I o I o I 0 0 I 0 0 I 0 I 0 0 0 I TRANSFER M U LTIPLE COPROCESSOR REGISTERS

1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 0

I CA I PC I dr I 0 I 0 I o I o I 1 I Length

TRANSFER STATUS REGISTER AND SCAN PC

1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 I CA I PC I dr I 0 0 0 1 I SP I 0 0 I 0 I 0 I 0 I 0 0 I 0

SUPERVISOR CH ECK

15 1 4 1 3 1 2 1 1 10 9 8 7 6 5 4 3 2 1 0

I 1 I PC I o I 0 I 0 I 1 o I o I 0 I 0 I 0 0 0 0 0 o I TAKE ADDRESS AND TRANSFER DATA

1 5 1 4 1 3 1 2 1 1 10 9 8 7 6 5 4 3 2 0 I CA I PC I dr I 0 I 0 I 1 I 0 1 I Length

TRANSFER M U LTIPLE MAI N PROCESSOR REGISTERS

1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0

I CA I PC I dr I 0 0 I 1 1 I 0 I 0 0 I 0 0 I 0 I 0 0 0

TRANSFER OPERATION WORD

1 5 1 4 1 3 1 2 1 1 10 9 8 7 6 5 4 3 2 1 0 I CA I PC I 0 0 0 1 I 1 I 1 0 I 0 I 0 0 0 0 0 0 I •

N U LL

1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 I CA I PC I 0 0 I 1 0 0 I IA I 0 I 0 I 0 0 I 0 I 0 I PF I TF I

C-22

EVALUATE AND TRANSFER EFFECTIVE ADDRESS

1 5 1 4 1 3 1 2 1 1 10 9 8 7 6 5 4 3 2 0 I CA I PC I 0 I 0 I 1 I 0 I 1 o I 0 I 0 I 0 I 0 I 0 I 0 I 0 o I TRANSFER SINGLE MAIN PROCESSOR REGISTER

15 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 0

I CA I PC I dr 0 I 1 I 1 I 0 I 0 I 0 0 I 0 0 l OlA I Register

TRANSFER MAIN PROCESSOR CONTROL REG ISTER

15 1 4 1 3 1 2 1 1 10 9 8 7 6 5 4 3 2 1 0

I CA I PC I dr 0 I 1 I 1 0 I 1 0 I 0 I 0 0 I 0 0 0 I 0

TRANSFER TO/FROM TOP OF STACK

1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 0 I CA I PC I DR I 1 1 I 1 I 0 Length

TRANSFER FROM INSTRUCTION STREAM

1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 0

I CA I PC I 0 I o I 1 I 1 I 1 I 1 I Length

EVALUATE EFFECTIVE ADDRESS AND TRANSFER DATA

1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 0

I CA I PC I dr I 1 I 0 Valid EA Length

TAKE PRE·INSTRUCTION EXCEPTION

1 5 1 4 1 3 1 2 1 1 10 9 8 7 6 5 4 3 2 0

I 0 I PC I 0 I 1 I 1 I 1 0 o I Vector Number

TAKE MID·INSTRUCTION EXCEPTION II 1 5 1 4 1 3 1 2 1 1 10 9 8 7 6 5 4 3 2 0 I 0 I PC I 0 I 1 I 1 I 1 0 I 1 I Vector Number

C·23

•

TAKE POST·INSTRUCTION EXCEPTION

15 1 4 13 1 2 1 1 10 9 8 7 6 5 4 3 2 0 I 0 I PC I 0 I 1 I 1 I 1 I 1 I 0 I Vector Number

WRITE TO PREVIOUSLY EVALUATED EFFECTIVE ADDRESS

15 14 13 12 11 10 I CA I PC I 1 I 0 0 0 9 8

o I 0

C-24

7 6 5 4 3 Length

2 o

APPENDIX D ADVANCED TOPICS

This appendix provides i nformation on the fol lowing advanced topics: Module Support Access Levels Extension Words CAS/CAS2 for Systems Programmers

0.1 MODULE SUPPORT

The MC68020 inc ludes support for modules with the cal l module (CALLM) and return from modu le (RTM) i nstruct ions. The CALLM i nstruct ion references a modu le descriptor. This descr iptor contains control i nformat ion for entry i nto the cal led modu le. The CALLM in· struction creates a modu le stack frame and stores the current modu le state in that frame and loads a new modu le state from the referenced descriptor. The RTM instruct ion recovers the previous modu le state from the stack f rame and returns to the ca l l i ng modu le.

The module i nterface fac i l itates finer resolution of access control by external hardware. Although the MC68020 does not i nterpret the access control i nformat ion, it does com· mun icate with external hardware when the access control is to be changed, and rel ies on the external hardware to verify that the changes are legal.

0.1 .1 Module Descriptor

Figure D·1 i l l ustrates the format of the modu le descriptor. The f i rst long word conta ins control information used during the execution of the CALLM i nstruction. The remain ing locations conta in data which may be loaded into processor reg isters by the CALLM i n· struction.

The Opt field specif ies how arguments are to be passed to the cal led module; the MC68020 recognizes only the options of 000 and 1 00, all others cause a format except ion. The 000 option ind icates that the cal led modu le expects to f ind arguments from the cal l · i ng modu le on the stack just below the module stack frame. I n cases where there is a change of stack pOinter dur ing the cal l , the MC68020 w i l l copy the arguments from the old stack to the new stack. The 1 00 option i nd icates that the cal led module w i l l access the arguments f rom the ca l l ing module through an i nd i rect pointer in the stack of the cal l i ng modu le. Hence, the arguments are not copied, but the MC68020 puts the val ue of the stack poi nter from the cal l i ng module in the modu le stack frame.

D·1

•

•

31 28 23 1 5 o Base -- Opt 1 Type I Access Level I ( Reserved, Must be Zero)

+ S04 Module Entry Word Pointer

+ S08 Module Data Area Pointer

+ SOC

+ S10

Additional User-Defined Information

Figure 0·1 . Module Descriptor Format

The Type field specifies the type of the descriptor; the MC68020 only recogn izes descriptors of type $00 and $01 , a l l others cause a format except ion. The $00 type descr iptor defines a modu le for which there is no change in access r ights, and the cal led modu le bui lds i ts stack frame on top of the stack used by the cal l i ng modu le. The $01 type descr iptor defines a modu le for which there may be a change In access r ights, such a cal led modu le may have a separate stack area from that of the cal l i ng modu le.

The access level field is used on ly with the type $01 descr iptor, and is passed to external hardware to change the access control.

The modu le entry word pointer specif ies the entry address of the cal led modu le, The f i rst word at the entry address (see F igure D-2) specifies the reg ister to be saved in the module stack frame and then loaded with the module descr iptor data area pointer; the f i rst i nstruction of the module starts with the next word. The module descriptor data area pointer field conta ins the address of the cal led modu le data area.

If the access change requ i res a change of stack pointer, the old va lue is saved in the modu le stack frame, and the new value is taken from the module descr iptor stack pointer f ie ld , Any further i nformation in the modu le descr iptor is user def i ned.

14 13 1 2 Register

Figure 0·2. Module Entry Word

Al l module descriptor types $1 0·$1 F are reserved for user def i n i t ion and cause a format error exception, This provides the user with a means of disab l i ng any module by setti ng a s ing le bit i n its descr iptor, w ithout loss of any descriptor i nformation.

If the cal led modu le does not wish the module data area poi nter to be loaded i nto a reg ister, the modu le entry word can select reg ister A7, and the loaded value w i l l be overwritten with the correct stack poi nter value after the modu le stack frame is created and f i l led.

D-2

0.1 .2 Module Stack Frame

Figure D-3 i l l ustrates the format of the module stack frame. Th is frame is constructed by the CALLM i nstruction, and is removed by the RTM i nstruct ion. The f i rst and second long words conta in control i nformat ion passed by the CALLM i nstruct ion to the RTM i nstruct ion. The module descriptor poi nter conta ins the address of the descriptor used dur ing the modu le cal l . A l l other locations contai n i nformat ion to be restored on return to the cal l i ng modu le.

15 12 7 o S p ..... Opt Type Saved Access Level

0 I o I 0 o I o I o I o I 0 Condition Codes 0 I o I 0 o I o I o I o I 0 Argument Count

(Reservedl + $08

Module Descriptor Pointer

+ SOC Saved Program Counter

+ $10 Saved Module Data Area Pointer

+ $14 Saved S tack Pointer

+ $1 8

Arguments (Optional)

Figure 0·3. Module Call Stack Frame

The program counter is the saved address of the i nstruction fol lowing the CALLM i nstruction. The Opt and Type f ields spec ify the argument options and type of module stack frame, and are copied to the frame from the module descr iptor by the CALLM i nstruct ion; the RTM i nstruction w i l l cause a format error if the Opt and Type f ields do not have recogn izable val ues. The access level is the saved access control i nformation, which is saved from external hardware by the CALLM i nstruction and restored by the RTM i nstruction. The argument count f ield is set by the CALLM i nstruction, and is used by the RTM i nstruction to remove arguments from the stack of the cal l ing modu le. The contents of the CCR are saved by the CALLM i nstruction and restored by the RTM i nstruction. The saved stack poi nter f ield conta ins the value of the stack pOi nter when the CALLM i nstruction started execution, and that value is restored by RTM. The saved modu le data poi nter f ield contains the saved value of the modu le data area pointer reg ister from the ca l l ing module.

0.2 ACCESS LEVELS

The MC68020 module mechanism supports a f iner level of access control beyond the d ist inction between user and supervisor modes. The modu le mechanism al lows a modu le with l i m ited access r ights to call a module with g reater access r ights. With the help of external hardware, the processor can verify that an i ncrease i n access r ights is al lowable, or can detect attempts by a modu le to gain access r ights to which i t is not entit led.

D-3

•

•

Type $01 modu le descr iptors and module stack frames i nd icate a request to change access levels. Whi le processing a type $01 descr iptor or frame, the CALLM and RTM i nstructions commun icate with external access control hardware via accesses i n the CPU space. For these accesses, address bits [ 19: 1 6] equal 0001 . F igure 0-4 shows the address map for these CPU space accesses. If the processor receives a bus error on any of these CPU space accesses dur ing the execution of a CALLM or RTM i nstruct ion, the processor w i l l take a format error except ion.

$00 $04 $08 soc $40 $44 $48 $4C $50 $54 $58 $5C

31 23 o CAL (Unused, Reserved)

STATUS (Unused, Reserved) IAL (Unused, Reserved) DAL (Unused, Reserved)

Function Code 0 Descriptor Address Function Code 1 Descriptor Address ( User Data) Function Code 2 Descriptor Address (User Program) Function Code 3 Descriptor Address Function Code 4 Descriptor Address ( Supervisor Data) Function Code 5 Descriptor Address ( Supervisor Program) Function Code 6 Descriptor Address Function Code 7 Descriptor Address (CPU Space)

Figure 0-4_ Access Level Control Bus Registers

The current access level reg ister (CAL) conta ins the access level r ights of the currently execut ing modu le. The i ncrease access level reg ister ( IAL) is the reg ister through which the processor requests i ncreased access r ights. The decrease access level reg ister (OAL) is the reg ister through which the processor requests decreased access r ights. The formats of these three reg isters are u ndef ined to the main processor, but the main processor assumes that i nformat ion read f rom the modu le descri ptor stack frame, or the current access level reg ister can be mean ingfu l ly written to the i ncrease access level reg ister or the decrease access level reg ister. The access status reg ister a l lows the processor to query the external hardware as to the legal ity of i ntended access level transitions. Table 0-1 l ists the val id values of the access status reg ister.

Table 0-1 _ Access Status Register Codes

Value Validity Processor Action

00 Invalid Format Error 01 Valid No Change in Access Rights

02-03 Valid Change Access Rights with no Change of Stack Pointer 04-07 Valid Change Access Rights and Change Stack Pointer Other Undefined Undefined !Take Format Error Exception)

The processor uses the descriptor address reg isters dur ing the CALLM i nstruction to communicate the address of the type $01 descriptor. This a l lows external hardware to verify that the address is a va l id address for a type $01 descr iptor. This prevents a module from creating a type $01 descr iptor to surreptit iously i ncrease its access r ights .

0-4

0.2.1 Module Call

The CALLM i nstruct ion is used to make the modu le cal l . For the type $00 modu le descrip· tor, the processor s imply creates and f i l l s the modu le stack frame at the top of the act ive system stack. The condit ion codes of the cal l i ng module are saved in the CCR field of the frame. I f Opt is equal to 000 (arguments passed on the stack) in the module descri ptor, the MC68020 does not save the stack pointer or load a new stack poi nter value. The processor uses the module entry word to save and load the module data area pointer reg ister, and then beg ins execut ion of the cal led modu le .

For the type $01 modu le descriptor the processor must f i rst obtain the current access level from external hardware. It also verif ies that the ca l l i ng modu le has the right to read f rom the area poi nted to by the current va lue of the stack pointer by read ing from that address. It then passes the descriptor address and i ncrease access level to external hardware for val idation, and then reads the access status. I f external hardware determi nes that the change in access rights should not be granted, the access status is zero, and the processor takes a format error except ion. No visible processor reg isters are changed, nor should the current access level enforced by external hardware be changed. I f external hardware determ i nes that a change should be granted, the external hardware changes its access level , and the processor proceeds. I f the access status register i nd icates that a change i n the stack poi nter is requ i red, the stack poi nter is saved internal ly, a new va lue is loaded from the module descriptor, and arguments are copied from the cal l i ng stack to the new stack. F ina l ly, the modu le stack frame is created and f i l led on the top of the current stack. The condit ion codes of the cal l i ng module are saved i n the CCR f ie ld of the frame. Execution of the cal l ed module then beg ins as with a type $00 descriptor.

0.2_2 Module Return

The RTM i nstruct ion is used to return from a modu le. For the type $00 module stack f rame, the processor reloads the condit ion codes, the program counter, and the module data area pOinter reg ister from the frame. The frame is removed from the top of the stack, the argument count is added to the stack pointer, and execution returns to the cal l i ng modu le.

For the type $01 module stack frame, the processor reads the access level , condition codes, program counter, saved module data area poi nter, and saved stack pointer from the modu le stack f rame. The access level is written to the decrease access level reg ister for val idation by external hardware, the processor then reads the access status to check the val idation. I f the external hardware determi nes that the change in access rights should not be granted, the access status is zero, and the processor takes a format error exception. No v is ib le processor reg isters are changed, nor should the current access level which is enforced by external hardware be changed. I f the external hardware determ ines that the change in access rights should be granted, the external hardware changes its access leve l , the values read from the modu le stack frame are loaded i nto the corresponding processor registers, the argument count is added to the new stack pointer value, and execut ion returns to the cal l i ng modu le.

I f the cal led module does not wish the saved modu le data pointer to be loaded into a reg ister, the RTM i nstruction word can select reg ister A7, and the loaded value w i l l be overwritten with the correct stack pointer value after the module stack frame is dea l located.

0-5

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•

D.3 EXTENSION WORDS

I f it is desi red to write programs that can be transported from one member of the M68000 processor Fami ly to another, certai n restr ict ions may have to be observed. F i rst of a l l , each new member of the Fami ly is a lways upward object code compatib le with earl ier members, with some extensions to the architecture. Thus, t ransport ing appl ications code from an early mach i ne to a new one is stra ightforward, s ince no changes are necessary. Secondly, a l l processors fu l ly decode a l l 65,536 possi ble operat ion words and i n it iate except ion processing i f an opcode is encou ntered that is not i mplemented by a g iven processor. Thus, if code written for a new member of the Fami ly is executed on an earlier machi ne, new i nstruct ions for the new processor w i l l be 'trapped out' by the earl ier processor and can be emu lated with run-time support software on the o lder system. However, only the f i rst word for an i nstruct ion is checked for legal i ty; any exten· s ion words ind icated necessary by the f i rst word are assumed to be val id and are not checked.

The extension words are of concern when us ing certain addressing modes of the MC68020. Specif ical ly, the address reg ister memory ind i rect with i ndex, and program counter relat ive ind i rect with i ndex addressing modes are extensions of the corresponding addressing modes of the MC68000, MC68008, MC6801 0, and MC68012. The extension words of these effective addressing modes are shown i n F igure 0-5. As can be seen from th is f igure, the MC68020 address reg ister ind i rect with i ndex, with a scal ing mu lt ip l ier of one (Scale = 00) encod ing, is equ ivalent to the MC68000, et. aI . , encod ing so that upward compat ibi l i ty is mai ntained. However, i f any other encoding for the MC68020 is used, downward compat ib i l i ty of the i nstruct ion is lost and special precautions must be taken s i nce these extension words are not checked for val id ity on the older processors. The fol lowing two examples i l l ustrate why these precautions must be observed to i nsure downward compat ib i l ity.

Example 1 . MC68020 Address Register Indirect with Index versus M68000 Address Register Indirect with Index

MC68000 Program Assembly Language

Source Code MOVE.L OFFSET(AO,00. L), 01

Object Code 2230 08XX

MC66020 Program

MOVE.L (OFFSET,AO,OO.L * 4),01

2230 OCXX

As can be seen from the object code, only one bit (bit 1 0 of the extension word) is d if· ferent i n the two i nstruct ions, yet the source effective address values are qu i te d i fferent. I f the MC68020 code were executed on an MC68000, the processor would i nterpret the code as though i t were the MC68000 code and the wrong data would be fetched, but no exception wou ld occur.

Example 2. MC68020 Address Register Indirect with Index/Indirect versus MC68000 Address Register Indirect with Index

MC68000 Program

Assembly Language Source Code MOVE.L OFFSET(AO,00.L), 01

Object Code 3230 08XX

0·6

MC68020 Program

MOVE.L ([OFFSET,AO,OO. L * 4]),01

3230 0021 XXXX

A comparison of the object code i n th is example shows a more volat i le situation that w i l l occur i f the MC68020 code is executed on a n MC68000. I n t h i s case, the MC68000 w i l l ig nore bits 8-1 0 of the f i rst extension word and interpret the i nstruct ion as "MOVE.L $21 (AO,DO.L), D1" , and then erroneously use the second extension word as the f i rst word of the next i nstruction. Thus, the processor w i l l get 'out of sync' with the i ntended i nstruction stream and u npred ictable resu lts w i l l occu r. Eventual ly, the processor may encounter an i l legal i nstruction and t rap to the operating system, but i ncorrect execution may have occurred, with no i nd icat ion that the MC68020 extended addressing mode was at fau lt.

I f i t is des i red to protect against the above s ituations, the user might precede any prog ram that ut i l izes the advanced features of the MC68020 with the "TRAPF" i nstruction. This i nstruction performs no operation on the MC68020, but w i l l cause an i l l egal i nstruct ion except ion on the MC68000, MC68008, MC6801 0, or MC68012; thus prevent i ng the prog ram from execut ing on the o lder processors.

MC68020, Brief Format

1 5 14 13 1 2 1 1 1 0 9 8 7 6 5 4 3 2 o I D/A I Register IW/L I Scale I 0 I Displacement

MC68020, Full Format

1 5 14 13 1 2 1 1 10 9 8 7 6 5 4 3 2 o D/A I Register IW/ L I Scale I 1 I BS 1 IS 1 BD S IZE 1 0 1 I l l S

Base Displacement 10, 1 , or 2 Wordsl Outer D isplacement 10, 1, or 2 Wordsl

Figure 0·5. Indexed/Indirect Addressing Mode Extension Words

The fields used in Figure D-5 are as follows:

Mode

Register D/A

W/L

Scale

B S

Addressing Mode

Index Register Number Index Register Type:

0 = Dn 1 = An

Word/Long Word Index Size: 0= Sign Extended Word 1 = Long Word

Scale Factor: 00 = 1 01 = 2 1 0 = 4 1 1 = 8

Base Suppress: 0= Base Register Added 1 = Base Register Suppressed

Mode

I S

BD SIZE

I l l S

D-7

Addressing Mode

Index Suppress: 0 = Evaluate and Add Index Operand 1 = Suppress Index Operand

Base Displacement Size: 00 = Reserved 01 = Null Displacement 1 0 = Word Displacement 1 1 = Long Displacement

Index/ lndirect Selection: Indirect and I ndexing Operand Determined in Conjunction with Bit 6, Index Suppress

•

Index/ IS Indirect Operation

0 000 No Memory Indication 0 001 Ind i rect After Indexing with Nu l l Displacement 0 010 I ndirect After I ndexing with Word Displacement 0 01 1 Indi rect After Indexing with Long Displacement 0 100 Reserved 0 101 Indirect Before Indexing with Nul l Displacement 0 1 10 Indirect Before Indexing with Word Displacement 0 1 1 1 Indi rect Before Indexing with Long Displacement 1 000 No Memory Indication 1 001 Memory Indi rect with Nul l Displacement 1 010 Memory Indi rect with Word Displacement 1 01 1 Memory Indi rect with Long Displacement 1 . 100- 1 1 1 Reserved

0.4 CAS/CAS2 FOR SYSTEMS PROG RAMM ERS

The CAS instruction al lows secure updating of system cou nters, h istory information, and g loba l ly shared pointers. Secu rity is provided in s ing le processor systems, mult itasking environments, and i n mu lt iprocessor environments. In a s ing le processor system, the non-interruptable update operat ion provides security in an i nterrupt driven environment; wh i le in a m u lt iprocessor environment, the indivisible bus cyc le operation provides the security mechanism. For example, suppose location SYS_CNTR contains a count of the number of ti mes a part icular operat ion has been done, and that this operation may be done by any process or any processor in the system. Then the fol lowing sequence guarantees that SYS_CNTR is correctly incremented.

MOVE.w MOVE.w AOOQ.w CAS.w

B N E

SYS_C NTR, OO 00, 01 # 1 , 0 1 00,01 ,SYS_CNTR

I N C_LOOP

get the old value of the counter make a copy of it and i ncrement it i f counter value is sti l l the same,

u pdate it i f not, try again

The CAS and CAS2 instructions together a l low safe operat ions in manipu lation of system queues. I f a queue can be managed last- i n-fi rst-out, only a S ing le locat ion H EAD need be contro l led. I f the queue is empty, H EAD contains the N ULL poi nter (0). The fol lowing sequence i l l ustrates the code for insertion and deletion from such a queue. F igures D-6 and D-7 i l l ustrate the insertion and deletion, respectively.

D-8

SINSERT

SI LOOP MOVE.L MOVE.L MOVE.L CAS.L

B N E

Before Inserting a n Element:

Entry

+ Next

New

After Inserting an Element:

SDELETE

SDLOOP

SDEM PTY

Entry

+ Next

LEA MOVE. L TST.L B EQ LEA MOVE.L CAS2.L

B N E

Before Deleting a n Element:

H EAD,DO DO,(N EXT,A1) A 1 , D 1 DO, D 1 , H EAD

S I LOOP

al locate new entry, addr i n A 1 move head pOinter value to DO establ ish fwd l ink in new entry move new entry ptr value to 01 if we sti l l point to top of stack,

u pdate the head ptr if not, try again

J1 EntryFV ' " + Next

Head '-__ --'-----'

Entry

+ Next

Entry Entry

+ Next + Next

Figure 0·6. Linked List Insertion

H EAD,AO (AO),DO DO SDEM PTY (N EXT, DO),A1 (A1),D1 00: 01 , 0 1 :01 ,(AO):(A 1 )

SDLOOP

load addr of head ptr i nto AO move value of head ptr i nto DO check for n u l l head ptr if em pty, nothing to delete load addr of fwd l ink i nto A1 put fwd l ink value i n 01 i f st i l l po int to entry to be deleted,

then u pdate head and fwd ptrs i f not, try again successful deletion, addr of deleted

entry in DO (may be nU l l)

J1 Entry� Entry� • • •

+ Next + Next

Head '--------'-----' '--------'-----'

Entry

+ Next

After Deleting an Element:

Entry Entry Entry

+ Next + Next + Next

Head

Figure 0·7. Linked List Deletion

0-9

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•

The CAS2 instruct ion may be used to maintain a f i rst-in-fi rst-out doubly l i nked l i st safely. Such a l inked l ist needs two control led locations, LIST_PUT and LIST_G ET, which point to the last element i nserted in the l i st and the next to be removed, respect ively. I f the l i st is empty, both poi nters are N U LL (0). The fol lowing sequence i l l ustrates the i nsertion and deletion operat ions in such a l inked l i st. F igures 0-8 and 0-9 i l l ustrate the i nsert ion and delet ion from a doubly l i n ked l ist.

DI NSERT

O I LOOP

O IEMPTY

OIOO N E

LEA LEA MOVE. L MOVE. L TST. L B EQ MOVE. L CLR.L MOVE.L LEA CAS2.L

B N E B RA MOVE.L MOVE.L CAS2.L

B N E

Before Inserting New Entry:

Entry

Entry

+ Last + Next

LIST _PUT,AO LlST_G ET,A1 A2,02 (AO),OO DO O IEMPTY 00,(N EXT,A2) 01 01 ,(LAST,A2) (LAST,00),A1 00: 01 , 02: 00,(AO):(A 1 )

OI LOOP DlOONE 00,(N EXT,A2) 00,(LAST,A2) 00:00,02: 02,(AO):(A 1 )

O I LOOP

(al locate new l ist entry, load addr into A2)

load addr of head ptr i nto AO load addr of tai l ptr into A1 load new entry ptr i nto 02 load ptr to head entry i nto DO is head ptr n u l l (0 entries i n l ist)? if so, we need only to establ ish ptrs put head ptr i nto fwd ptr of new entry put n u l l ptr value i n 01 put n u l l ptr i n bkwd ptr of new entry load bkwd ptr of old head entry i nto A 1 if we st i l l point to old head entry,

u pdate poi nters i f not, try again

put nul l ptr i n fwd ptr of new entry put n u l l ptr in bkwd ptr of new entry if we sti l l have no entries, set both

poi nters to this entry if not, try agai n successfu l l ist entry i nsertion

Entry

Entry

Figure 0-8_ Doubly Linked List Insertion

0-1 0

OOELETE LEA LIST _PUT,AO get addr of head ptr in AO LEA LlST_G ET,A1 get addr of tai l ptr in A1

OOLOOP MOVE. L (A1 ),01 move tai l p t r i nto 01 B EQ OOOO N E i f n o l ist, qu i t MOVE.L (LAST, 01) ,02 put bkwd ptr i n 02 B EQ OOEM PTY if only one element, u pdate ptrs LEA (N EXT,02),A2 put addr of fwd ptr in A2 CLR.L DO put n u l l ptr val ue in DO CAS2.L 01 :01 , 02: 00,(A 1 ):(A2) if both ptrs st i l l point to this entry,

u pdate them B N E OOLOOP if not, try agai n BRA OOOO N E

OOEM PTY CAS2. L 01 : 01 , 02: 02:(A 1 ):(AO) if sti l l f i rst entry, set head and t ial ptrs to n u l l

B N E OOLOOP if not, try agai n OOOONE successfu l entry deletion, addr of

deleted entry i n 01 (may be n U l l)

Before Deleting Entry:

Entry

After Deleting Entry:

Entry

Deleted Entry

Figure D·9.Doubly Linked List Deletion

D.5 A PROG RAMMER'S VIEW OF THE MC68020 ADDRESSING MODES

Extensions to the i ndexed addressing modes, i nc luding i nd i rection along with the sup· port of fu l l 32·bit d isplacements, provide the MC68020 programmer with addressing capabi l ity new to the M68000 Fam i ly.

The purpose of the fol lowing paragraphs is to i nd icate the new techniques avai lable and to summarize them from a programmer's point of view. These techn iques w i l l be cal led "generic" addressing modes s ince they may or may not relate d i rect ly to a u n ique effec· t ive address mode as defined by the MC68020 arch i tecture.

D.5.1 New Addressing Capabilities

The suppression of the base address reg ister in the MC68020 i ndexed addressing mode al lows the use of any i ndex reg ister to be used in p lace of the base reg ister. Since any of

0·1 1

III

•

the data reg isters can be i ndex reg isters, the new forms (On) and (disp,Dn) are obta i ned. These could be cal led Data Register I nd i rect but its probably better to th ink in terms of (Rn) and (d isp,Rn) as just Reg ister I nd i rect where any data or address reg ister is a l lowed. Remember that whenever an i ndex reg ister appears (X n), its s ize may be spec if ied to be a s ign-extended word or a long word.

Since d isplacements may be a fu l l 32 bits, they may represent absol ute addresses or the resu l t of express ions which conta in absol ute addresses. This a l lows the general Register Ind i rect form above to become (addr, Rn), and with the base not suppressed we get (addr,An,Rn). Thus, an absolute address may be d i rect ly i ndexed by one or two reg isters.

Scal ing provides for an optional sh ift ing of an i ndex reg ister to the left by zero, one, two, or three bits before being used in the effective address calculation. This is equ ivalent to mu lt i plying the reg ister by one, two, four, or eight, which al lows d i rect subscript ing i nto an array of components of that size by an arithmet ic value resid ing in any of the 16 indexable reg isters. Scal ing , combined with the appropriate new modes derived above, al lows new modes. Arrayed structures may be addressed absolutely and then subscri pted, Le., (addr, Rn* scale). Optional ly, an address reg ister may contain a dynamic d isp lacement value s i nce it may be i nc luded in the address calcu lation (addr,An, Rn* scale). Other variat ions can be generated by assuming an address reg ister points d i rectly to the arrayed item with (An, Rn* scale) or that an address reg ister with d isp lacement (Le., a base address) points to the arrayed item (disp,An,Rn* scale).

Yet another featu re of the i ndex ing mode on the MC68020 is memory ind i rect ion. This a l lows a long word pointer i n memory to be fetched and used to point to the data operand. Any of the modes mentioned earl ier can be used to address the memory pointer. I n addit ion, when both reg isters are suppressed, the displacement acts as an absol ute address. Hence, absolute address ing can be used to access the memory pointer as wel l .

Once the memory pointer is fetched i t can optiona l ly have yet another constant d isp lacement added to it before it is used to access the f inal data operand. This second d isplacement is cal led the Outer Displacement. Thus the memory pointer may itself be t reated as a base address.

When memory i nd i rection is being used, the i ndex reg ister may be ut i l ized in one of three ways. It may be suppressed, used to access the memory pointer (before the ind i rect ion, or pre ind i rect), or used to access the final data operand (after the ind i rect ion, or posti nd i rect). This last case causes the i ndex reg ister to be added to the fetched poi nter from memory (and opt ional ly the Outer Disp lacement i f present). S i nce i ndex reg isters on the MC68020 can be scaled, subscript ing also may be employed on the data operand that the fetched memory poi nter accesses. However, when the i ndex reg ister is used to access the f inal data operand i t is not avai lable to address the memory poi nter. That is, i ndexing is not a l lowed both before and after ind i rect ion; rather i t is on ly a l lowed before or after i nd i rect ion.

0.5_2 A General Addressing Mode Summary

Some of the generic address ing modes mentioned in the previous paragraphs do not actual ly ex ist as d ist inct basic MC68020 effective address modes s i nce they either rely on a

0-1 2

spec if ic combi nation of opt ions i n the i ndex ing mode, or may be derived from two d i fferent nat ive MC68020 modes. For example, the generic mode cal led Register I nd i rect (Rn) wou ld assemble to the basic mode Address Reg ister I nd i rect if the reg ister was an address reg ister, or to the Reg ister Ind i rect with I ndex with address reg ister suppression i f Rn was a data reg ister. Another case is (disp,An) which depends on the s ize of the d isplacement. I f the disp lacement fits wi th in 1 6 bits, then the nat ive Address Reg ister I nd i rect with Displacement (d1 6,An) w i l l be used, otherwise the Address Reg ister I nd i rect with I ndex w i l l be used s i nce on ly it can su pport a larger d isplacement.

On the other hand, two or more of the modes mentioned may assemble i nto the very same nat ive effective address option. For i nstance, an absolute address with a reg ister i ndex (addr,Rn) and a base address with a large d isp lacement (d isp, Rn) are both two ways of looking at the same th ing - a reg ister with a 32-bit d isplacement. They both assemble i nto the very same object code.

An assembler makes the necessary dist i nct ions and chooses which basic address ing mode to use; a lways p ick ing the more eff ic ient one i f more than one is appl icable. Normal ly, the programmer need not be concerned about these dec isions, so it is usefu l to summarize the addressing modes avai lable to a programmer without regard to the nat ive MC68020 effective addressing mode actual ly imp lemented on ch ip.

The 'generic' address ing modes d iscussed be low are defined i n normal programming terms which should not be d i rect ly related to any specif ic bas ic modes as provided by the MC68020 arch itecture, even though some w i l l have obvious counterparts. F i rst, some terms commonly used by programmers are def ined here as to their exact meani ng.

poi nter

base

i ndex

d isp

subscript

re lative

addr

psaddr

Long word va lue in a reg ister or in memory which represents an add ress.

A pointer combi ned with a d isp lacement to represent an address.

A constant or variable value which the programmer uses to add a bias i nto an effective address calcu lation. As a constant, the i ndex ends up treated as a displacement. A variable i ndex is always represented by a reg ister contai n i ng the value.

Displacement, a constant i ndex.

The use of any of the data or address reg isters as a variable i ndex subscript i nto arrays of items 1 , 2, 4, or 8 bytes i n s ize.

An address based with the Program Cou nter. This makes the reference code posi t ion i ndependent and the operand accessed is in Program Space. A l l others but psaddr (below) fal l i nto Data Space.

An absolute address.

An absolute address in Program Space. A l l others but relative fal l i nto Data Space.

D-1 3

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•

Secondly, the generic modes are summarized as fol lows:

Immediate Data - #data

Register Di rect Rn

Scann i ng Modes (An) +

- (An)

Absolute Address - (addr) (psaddr,ZPC)

Reg ister Pointer

I ndex ing

Subscripting

(Rn) (d isp,Rn)

(An ,Rn) (d isp,An, Rn)

(addr,Rn) (addr,An,Rn)

(An, Rn * scale) (disp,An ,Rn * sca le)

(addr,Rn* scale) (addr,An ,Rn* scale)

Program Relative - (d isp,PC) (d isp,PC,Rn) (d isp,PC,Rn * scale)

0-1 4

The data is a constant i n the instruct ion stream.

The contents of a reg ister is specif ied.

Address reg ister poi nter automat ical ly i ncremented after use. Address reg ister poi nter automat ical ly decremented before use.

Absolute address in data space. Absolute address in program space.

Register as a pOi nter. Register as a poi nter and constant i ndex (or base address.)

Register pointer with variable index. Reg ister poi nter with constant and variable i ndex (or a base address with a variable i ndex). Absolute address with variable i ndex. Absolute address with 2 variable i ndexes.

Address reg ister pOinter subscri pt. Address reg ister pOi nter subscript with constant d isplacement (or base address with subscript). Absolute address with subscri pt. Abso lu te address s u bscr ipt w i t h variable i ndex.

Simple re lative. Relat ive with variable i ndex. Relat ive with subscri pt.

Memory Poi nter ([* modes])

([* modej,d isp)

([* * modesj, Rn) ([* * modesj,disp,Rn)

M e mory poi nter d i rect ly to data operand. Memory pointer as base with d isp lace· ment to data operand. Memory poi nter with variable i ndex. Memory pointer with constant and variable i ndex.

([* * modesj ,Rn * scale) Memory poi nter subscri pted. ([* * modesj,disp,Rn * scale)Memory pOinter subscri pted with cons

tant i ndex.

* -al lowed modes are any of the above from absolute address through program relat ive. * * -al lowed modes are as fol lows:

addr Absol ute address in data space. psaddr,ZPC Absol ute address in program space. An Reg ister poi nter. d isp,An Register pOinter with constant displacement (or base address). addr,An Absolute address with s ing le variable index. d isp,PC Simple program relat ive.

0-1 510·16

--

APPEN DIX E MC68020 EXTENSIONS TO M68000 FAM I LY

This Append ix summarizes the extensions to the M6BOOO Fami ly i mplemented by the MC6B020 microprocessor.

NOTE In the fol lowing descript ion, the notation " MC6BOOO" inc l udes the MC6BOOO and the MC6BOOB together, and " MC6B010" inc ludes the MC6B010 and MC6B012 together, except where specif ical ly mentioned.

E laborat ion on MC6BOOO and MC6B010 d ifferences may be found in the M68000 Programmer's Reference Manual.

Data Bus Size (Bits) MC6B020 . . . . . . . . . . . . . . . . . B, 1 6, 32 MC6BOOO/MC6B010 . . . . . . . . . 1 6 MC6BOOB . . . . . . . . . . . . . . . . . B

Address Bus Size (Bits) MC6B020 . . . . . . . . . . . . . . . . . 32 MC6B01 2 . . . . . . . . . . . . . . . . . 30 (plus A31 ) MC6BOOO/MC6B01 0 . . . . . . . . . 24 MC6BOOB . . . . . . . . . . . . . . . . . 20

I nstruction Cache MC6B020 . . . . . . . . . . . . . . . . . 1 2B Words MC6B010 . . . . . . . . . . . . . . . . . Provides Loop Mode (3 Words)

V i rtual Memory/Machine MC6B020/MC6B010 . . . . . . . . . Provides Bus Error Detect ion, RTE Recovery

Coprocessor I nterface MC6B020 . . . . . . . . . . . . . . . . . In M icrocode MC6BOOO/MC6B010 . . . . . . . . . Emulated in Software

Processor S ignals and P in ASSignments Detai led in each specif ic data sheet.

I nstruction Execution Time Detai led i n each spec if ic data sheet.

E-1 •

II

Word/Long Word Data Al ignment MC68020 . . . . . . . . . . . . . . . . . Only I nstruct ions M ust be Word A l igned MC68000/MC68010 . . . . . . . . . Word/Long Word Data, I nstructions, and Stack

Must be Word Al igned

Control Reg isters MC68020 . . . . . . . . . . . . . . . . . SFC, DFC, VBR, CACR, CAAR MC68010 . . . . . . . . . . . . . . . . . SFC, DFC, VBR MC68000 . . . . . . . . . . . . . . . . . N one

Stack Pointers MC68020 . . . . . . . . . . . . . . . . . USP, SSP (MSP, ISP) MC68000/MC68010 . . . . . . . . . USP, SSP

Status Register MC68020 . . . . . . . . . . . . . . . . . TOIT1 , S, M, 10/ 1 1 /12, X/NIl/V/C MC68000/MC6801 0 . . . . . . . . . T, S, 1011 1 112, X/NIZlV/C

Function Code/Address Space MC68020/MC6801 0 . . . . . . . . . FCO·FC2 = 7 is CPU Space MC68000 . . . . . . . . . . . . . . . . . FCO·FC2 = 7 is I nterru pt Acknowledge, Only

I ndivisible Bus Cyc les MC68020 . . . . . . . . . . . . . . . . . Use RMC Signal MC68000/MC68010 . . . . . . . . . Use AS Signal (MC6801 2 Also Uses RMC)

Exception Vectors Detai led in each specif ic data sheet.

Stack Frames MC68020 . . . . . . . . . . . . . . . . . Su pports Formats $0, $1 , $2, $9, $A, $B MC68010 . . . . . . . . . . . . . . . . . Su pports Formats $0, $8 MC68000 . . . . . . . . . . . . . . . . . Supports Original Set

Addressing M odes MC68020 extensions: memory ind i rect addressing modes, scaled index, and larger d isplacements. Deta i ls are found in each spec if ic data sheet.

MC68020 I nstruct ion Set Extensions Bcc . . . . . . . . . . . . . . . . . . . . . . Supports 32·Bit Displacements BFxxxx . . . . . . . . . . . . . . . . . . . Bit Field I nstructions (BFCHG, BFCLR,

BFEXTS, BFEXTU, BFEXTS, BFFFO, BFI NS, BFSET, BFTST)

BKPT . . . . . . . . . . . . . . . . . . . . New I nstruction Functional ity BRA . . . . . . . . . . . . . . . . . . . . . Supports 32·Bit Disp lacements BSR . . . . . . . . . . . . . . . . . . . . . Supports 32·Bit Disp lacements CALLM . . . . . . . . . . . . . . . . . . . New I nstruction CAS, CAS2 . . . . . . . . . . . . . . . . New I nstruction CHK . . . . . . . . . . . . . . . . . . . . . Supports 32·Bit Operands CHK2 . . . . . . . . . . . . . . . . . . . . New I nstruction

E·2

CMPI . . . . . . . . . . . . . . . . . . . . Supports Program Counter Relative Addressing M odes

C M P2 . . . . . . . . . . . . . . . . . . . . New Instruction cp . . . . . . . . . . . . . . . . . . . . . . . Coprocessor I nstruct ions DIVS/DIVU . . . . . . . . . . . . . . . . Supports 32-Bit and 64-Bit Operands EXTB . . . . . . . . . . . . . . . . . . . . Supports 8-B it Extend to 32 Bits LI N K . . . . . . . . . . . . . . . . . . . . . Supports 32-Bit D isplacement M OVEC . . . . . . . . . . . . . . . . . . Supports New Control Reg isters M U LS/M ULU . . . . . . . . . . . . . . Supports 32-Bit Operands PACK . . . . . . . . . . . . . . . . . . . . New I nstruction RTM . . . . . . . . . . . . . . . . . . . . . New I nstruct ion TST . . . . . . . . . . . . . . . . . . . . . . Supports Program Counter Relative Addressing

Modes TRAPcc . . . . . . . . . . . . . . . . . . New Instruction U N PK . . . . . . . . . . . . . . . . . . . . New Instruction

A17717-1 4/85

II E-3/E-4

CLK 50 52 53 5 1 S4 55

� ;:<--.J'-='�� .... AO-A31 K

FCO-FC2 K 51ZE K EC5 �@ +(i2� GP �

� �

OC5

(6a)-+ -� f.,.� f-\ Kel..

A5

�� 14 1 3 � F-<� � k!� @r f+-

05 , � 1--_ - @ � Vg I--A/Vii j 46 J � H�

05ACKO , j 05ACKI

00-031

� 311 I ..... k§) j 1+ � �

'- .... ... 27 �

OBEN � .J. BEAA

745' � � I+- \ �

HALT \ All

Asynchronous

I+-� \. .I Inputs .� 47a -@ +-NOTE: Timing measurements are referenced to and from a low voltage of 0.8 volt and a high voltage of 2.0 volts. unless otherwise noted. The voltage swing through this range should start outside and pass through the range such that the rise or fall will be linear between 0.8 volt and 2.0 volts.

Figure 1 0-5. Read Cycle Timing Diagram

Foldout 1

NOTE:

so S 1 S2 S3 S4 S5

'" G5-r:::'f----Ir--.L-.f1�� AO-A31 ) l

FCO-FC2 ___ �J)Hf--:--+---+----+-�f---''f"l,----0VI+*-+--+-+t

�� r,oa)-.I/,..-4--+------4----4---4---OCS I ' 1'-

1+ 1i)��--� 14l------l� �)AS --+--.:.-�""',

� (9)r-�+----+-1 .-"'8""'a ---I'll OS -+---+"'::'::;";""+---h., 10-----+----.1

�-..."....--I'I I---{�)..--�j\.. -+ @ 1+t---<t22 }------i� � I+- � , 'C & f+- C0 II�---R/W

��---+----�I�l---�+--� OSACKO I 1\ I -----' e 1'---...... -----I-.j.r-€-""28.t-�-'

I I , Ir---OSACK 1 -@::: I

---' � 55 _ C\ f*-----+-+---+--' '-. � C�)�� 00-031 ---++---t �

OBEN � ..- -+1'-�-=26�----+ .... 1---{--t�""'5--/:· -S-ee----.J Note 5 ��r----4----_+�� ---4+---��,�/__

-. � I+-BERR __ � \ � � ��-�---

HALT --------------------��,

- � Timing measurements are referenced to and from a low voltage of 0.8 volt and a high voltage of 2.0 volts, unless otherwise noted. The voltage swing through this range should start outside and pass through the range such that the rise or fall will be linear between 0.8 volt and 2.0 volts.

Figure 1 0·6. Write Cycle Timing Diagram

Foldout 2

ClK

AO-A3l

DO-D3l

FCO-FC2

SIZO-SIZl

ECS (2) ocs

AS

DS

R/W

' DBEN

DSACKO

DSACKl

BR

BG 39

BGACK

NOTE: Timing measurements are referenced to and from a low voltage of 0.8 volt and a high voltage of 2.0 volts, unless otherwise noted. The voltage swing through this range should start outside and pass through the range such that the rise or fall will be linear between 0.8 volt and 2.0 volts.

Figure 1 0-7_ Bus Arbitration Timing Diagram

Foldout 3

MC68020 32-Bit Microprocessor User's Manual

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