MBIST maths

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Cost and Benet Models for Logic and Memory BIST

Juin-Ming Lu and Cheng-Wen WuLab. for Reliable Computing (LARC)Department of Electrical Engineering

National Tsing Hua UniversityHsinchu, Taiwan 30013

ROC

Abstract

We present cost and benet models and analyze the eco-nomics effects of built-in self-test (BIST) for logic and mem-ory cores. In our cost and benet models for BIST, we takeinto consideration the design verication time and test de-velopment time associated with testability. Experimental re-sults for logic BIST and memory BIST examples show that a threshold volume exists when BIST is protable for thelogic core under considerationit is not recommended for a higher volume. However, BIST is a good choice for mem-ory cores in general.

1. Introduction

Built-in self-test (BIST) is receiving growing attentionwith the advent of core-based system-on-chip (SOC) de-sign, which is a natural sequel of deep-submicron VLSItechnology. When cores from different vendors are inte-grated together on the system chip, the difculty level of chip testing rapidly multiplies. Among the most appar-ent issues are core isolation, core access, system diagno-sis, test reuse, test compaction, tester qualication, intel-lectual property (IP) protection, etc. For all these issues,BIST is a potentially good solution, if used properly. How-ever, we do care about hardware overhead (area, pin, etc.),performance penalty, and extra design effort that may beassociated with BIST. An economics (i.e., costs and ben-ets) analysis tool for weighing the costs and benets of BIST (and other design-for-testability methodologies) isdenitely helpful for the project managers and designers(see, e.g., [1, 2, 3, 4, 5, 6]).

We analyze the economics effects of BIST for logicand memory cores in this paper. BIST is a relatively ma-ture DFT methodology, but techniques used in logic BIST(LBIST) may be quite different from those used in mem-ory BIST (MBIST). LBIST is normally based on pseudo-

random pattern generator and signature analyzer techniqueswith scan paths [7]. MBIST, on the other hand, is normallybased on the march algorithms [8, 9].

In this paper we propose economics models for estimat-ing both the costs and benets associated with LBIST andMBIST. We have performed experiments on these models,and the results show that a threshold volume exists whenLBIST is protable for the case we studied, i.e., it is notrecommended for a volume higher than the threshold. How-ever, MBIST is shown to be a good choice in general, exceptwhen the volume is low.

2. Models for LBIST

We consider recurring and nonrecurring costs and bene-ts for LBIST. In our model, the cost associated with LBISTmainly comes from area overhead. In return, reduced testertime and development time (i.e., time-to-market) representthe recurring and nonrecurring benets, respectively.

2.1. Benet due to Early Market Entry

Conventionally, DFT has been considered to lengthentime-to-market, since extra design effort is required. How-ever, we have observed that the product development cyclemay actually be shortened if proper DFT methodology isadopted, saving verication and debugging time (mainly inthe prototyping stage) [5, 6].

We divide the product development cycle into threestages: the design stage, test development stage, and ver-ication stage. Our development time model (

) thus is

(1)

where

is the design time,

is the test developmenttime, and

is the verication (including prototyping)time. When LBIST is adopted in a design, the developmenttime

.


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Our design time model is

(2)

where is the gate count,

is the average numberof engineers,

is the designer skill level, is the de-sign reusability factor, and is its complexity. The twovariables, , and , are normalized between 0 and 1. Theamount

is measured in number of gates designed perday. With LBIST, is assumed to remain unchanged. Also,

is expected to increase when LBIST is adopted, i.e.,

(3)

where

represents the area overhead of LBIST,which will be discussed later. The complexity parameter, ,can be estimated from the complexity of the functionalityand specication (e.g., timing and power specications andsilicon budget) of the target circuit. When adding LBIST to

the design, the relation between

and

is modeled as

(4)

To calculate

, we use

and

in Eq. (2). Weadopt the test generation time model in [10], i.e., our testdevelopment time model is

(5)

where

is a constant factor that relates the test generationtime to the IC gate count . When adding LBIST to thedesign, the test development time

is modeled as

(6)

where the factor 590 represents the test length reductionratio due to LBIST, and will be explained later. Here weassume that the test development time is in proportion tothe test length. The verication time includes the time fordesign verication, design debugging, and prototyping (in-cluding engineering runs). Our verication time model is

(7)

where

is the part of the verication time that is indepen-dent of circuit testability, while

is testability dependent.

Again, the number 590 represents the saving factor in ver-ication time due to the improvement in circuit controllabil-ity and observability. Our model for

is therefore

(8)

After calculating

,

, and

,

is ob-tained and the amount of time saved by LBIST is

(9)

which is used in the market life cycle model for estimatingthe revenue gain. Figure 1 [5, 6] shows a market windowwith three periods: the growth period, maturity period, anddecline period. Early to the market results in extra revenueas represented by the shaded region in the gure.

Revenue

TimeTTMgrow TTMmatu TTMdeclTime saving

TTMrev_DFT

TTMrev

Figure 1. The Market Life Cycle Model.The revenue of a product with a delay in time-to-market

is

(10)

The overall revenue from the product with an early time-to-market (due to LBIST) can be estimated as [6]

(11)

where

is the market growth period,

isthe market maturity period,

is the market declineperiod, and

is the maximal revenue per month atthe maturity period without DFT. Therefore, the benet canbe estimated as

(12)

2.2. Man-Power Benet due to Shortened Develop-ment Time

The benet for product development man-power is

(13)

where

is the average number of engineers and

is the average cost of an engineer per day. Note howeverthat

is not necessarily positive.


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2.3. Cost due to Area Overhead

The LBIST area overhead ranges from 4% to 15% inmost cases [10]. Our model for the core area with LBIST is

(14)

where is the area overhead. As to the yield af-fected by the area overhead, we adopt the Poisson yieldmodel [11]:

(15)

where

is the defect density. The cost per die due to thearea overhead is modeled as [10]

(16)

where

is the production volume,

is the cost perwafer,

is the radius of the wafer, and

is theutilization ratio of the wafer. A typical value for

is90%.

2.4. Benet due to Reduced Testing Cost

BIST reduces off-chip communication, so the externaltester can be greatly simplied. The testing cost savingsthus can be translated to the tester cost:

(17)

where

is the price of the external logic tester to accessthe chip without LBIST,

is the price of the testerto access LBIST,

is the annual depreciation rate of the tester,

is the number of seconds in one year(i.e., 31,536,000),

is the tester time for the core withoutLBIST, and

is the tester time for the core with LBIST.With LBIST, the pin count seems to increase. However,

using self test, the pin and frequency requirement of thetester actually is greatly reduced, i.e.,

(18)

where

is the tester frequency factor,

is thenumber of pins for the simple inexpensive tester to accessLBIST (typically ranging from three to ve if the core istested entirely by LBIST), and is the pin count of the corewithout LBIST. Note that LBIST also can reduce test lengthin most cases, as compared with functional or even sequen-tial ATPG patterns. According to our testability experimentwhich will be discussed later, adding LBIST causes a re-duction of

in test length, i.e.,

(19)

In summary, the total benet for using LBIST is

(20)

3. Models for MBIST

For MBIST, we will also consider costs due to extra de-sign effort and area overhead, and benet due to reducedtesting cost.

3.1. Cost due to Extra Development Effort

Our model for the extra development cost in terms of man-power is

(21)

where

is the average number of extra engineers forMBIST,

is the average cost of engineer per day, and

is the development time associated with MBIST.

3.2. Cost due to Area Overhead

Our model for the MBIST overhead is [9]

(22)

where is the memory capacity. We use the sameyield model as shown in Eq. (15). The silicon cost due toarea overhead is

(23)

3.3. Benet due to Reduced Testing Cost

MBIST reduces the time that memory testers have to beused [9]. Therefore, similar to Eq. (17), the benet that wegain from this is

(24)

where

and

represent the amount of time thememory tester and logic tester are used for the chip withMBIST, respectively;

is the price of a memory tester;

is the price of a logic tester to access the MBISTcircuit. Similarly to Eq. (18), the relation between

and

is

(25)


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where

is the number of pins for the logic tester toaccess the memory core with MBIST (it normally rangesfrom 4 to 10, and the default is 8 [9]). Also, we assume

and

.In summary, the total benet from MBIST is

(26)

0 5 10 15 20 25 30 35 400

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Vector length

F C

alpha=1

alpha=0.1

alpha=0.01

Figure 2. Fault coverage (FC) vs. test lengthfor various

values.

4. Testability Analysis

Figure 2 shows the relation between fault coverage ( )and test length (number of vectors, ) [6, 12], which can bemodeled by

(27)

where

is the factor representing the growth rate of FC.We have experimented the model using ISCAS89 bench-mark circuits [13], and the results are listed in Fig. 3.

The testability improvement ratio,

, varies from oneto about one thousand. The weighted arithmetic mean of

is calculated as follows:

(28)

where is the number of nets in a circuit, e.g., for s1488, . According to the result, adding LBIST causesa reduction in test length and testing time by a factor of

590, as has been shown previously. Note that the value590 was obtained empirically from the benchmark circuits.For practical applications, a better result can be obtained bylooking at the specic class of circuits under consideration.

5. LBIST Case

We use the chip reported in [14] as a case for our LBISTmodel evaluation. The costs and benets associated with

Figure 3. Testability improvement ratios.

LBIST are calculated using our models and are shown inFig. 4.

When the production volume is low (less than 4M),the overall economics effect is dominated by nonrecurringterms, i.e., labor and time-to-market. For higher

values(above 4M), the effect of recurring costs dominates.

-

-

-

-

-

-

Figure 4. Analysis results of the LBIST case.

6. MBIST Case

We use the design reported in [9] as a case for ourMBIST model evaluation. The testing benet is high dueto expensive memory testers and a signicant reduction inmemory tester time. As a result, MBIST is benecial formedium- to high-volume products, as shown in Fig. 5.


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-

-

-

-

-

-

Figure 5. Analysis results of the MBIST case.

7. Conclusions

We have presented cost and benet models associatedwith BIST for logic and memory cores, and a novel ap-proach for testability estimation which is used in our mod-els. Two cases have been presented, one for LBIST and theother for MBIST. Experimental results show that LBIST ispreferred at lower production volume for the case we use,while MBIST is favorable at higher volume in general. Notethat the results shown are for the specic cases we haveexperimented. Different projects (and manufacturers) maylead to different results and conclusions due to variation inthe parameters.

We are currently modifying our Evaluation System forTEst Engineering Methodologies (ESTEEM) to incorporatethe BIST related models proposed here. Our system allowsuser modication of the default models in addition to theparameters, so customization for a specic product line caneasily be done.

The system is not meant to accurately predict the protthat a product may bring before it is actually manufactured(or even designed), because it is not possible. Rather, it isan aid for project leaders to allocate DFT budget as earlyas possible, to increase the possibility of product success.In some cases, however, the decision may not be economic,e.g., due to company policy or the lack of other solutions.

References

[1] P. Varma, A. Ambler, and K. Baker, An analysis of the economics of self-test, in Proc. Int. Test Conf.(ITC) , pp. 2030, 1984.

[2] B. Davis, The Economics of Automatic Testing . Lon-don: McGraw-Hill, second ed., 1994.

[3] C. Dislis, J. H. Dick, I. D. Dear, and A. P. Ambler,Test Economics and Design for Testability for Elec-tronic Circuits and Systems . Hemel Hempstead: EllisHorwood, 1995.

[4] J. M. Miranda, A BIST and boundary-scan eco-nomics framework, IEEE Design & Test of Comput-ers , vol. 14, pp. 1723, July-Sept. 1997.

[5] C.-W. Wu and C.-C. Wei, The economic models fora VLSI test strategy planning system, in Proc. SEMI-CON Taiwan 97, Test Seminar , (Taipei), pp. 8792,Sept. 1997.

[6] J.-D. Lin, J.-M. Lu, and C.-W. Wu, An improvedVLSI test economics analysis system, in Proc. 9thVLSI Design/CAD Symp. , (Nantou), pp. 149152,Aug. 1998.

[7] P. H. Bardell, W. H. McAnney, and J. Savir, Built-In

Test for VLSI . New York: John Wiley & Sons, 1987.[8] A. J. van de Goor, Testing Semiconductor Memories:

Theory and Practice . Chichester, England: John Wi-ley & Sons, 1991.

[9] C.-T. Huang, J.-R. Huang, C.-F. Wu, C.-W. Wu, andT.-Y. Chang, A programmable BIST core for em-bedded DRAM, IEEE Design & Test of Computers ,vol. 16, pp. 5970, Jan.-Mar. 1999.

[10] S. Wei, P. K. Nag, R. D. Blanton, A. Gattiker, andW. Maly, To DFT or not to DFT?, in Proc. Int. Test Conf. (ITC) , 1997.

[11] V. K. Kim, M. Tegethoff, and T. Chen, ASIC yield es-timation at early design cycle, in Proc. Int. Test Conf.(ITC) , pp. 590594, 1996.

[12] J.-D. Lin, An improved VLSI test economics anal-ysis system, master thesis, Department of ElectricalEngineerig, National Tsing Hua University, Hsinchu,Taiwan, June 1998.

[13] F. Brglez, D. Bryan, and K. Ko zmi nski, Combina-tional proles of sequential benchmark circuits, inProc. IEEE Int. Symp. Circuits and Systems (ISCAS) ,pp. 19291934, 1989.

[14] C.-H. Tsai, IEEE Std 1149.5 MTM-Bus Slave mod-ule chip design and its application to hierarchical sys-tem test, master thesis, Department of Electrical En-gineerig, National Tsing Hua University, Hsinchu,Taiwan, June 1996.

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