May 8, 2001 2

Undocumented UTMIUndocumented UTMI

Eric HuangEric Huang

and Ravikumar Govindaramanand Ravikumar GovindaramaninSilicon CorporationinSilicon Corporation

May 8, 2001 3

Typical USB 2.0 ApplicationTypical USB 2.0 Application

USB2.0USB2.0USB2.0USB2.0USB2 USB2 PHYPHY

(USB2.0 Transceiver (USB2.0 Transceiver Macrocell)Macrocell)

UDC20UDC20(USB2.0 Device Controller)(USB2.0 Device Controller)

ApplicationApplication(USB2.0 function)(USB2.0 function)

UTMIUTMI AIAI

May 8, 2001 4

FeaturesFeatures

UTMI RecapUTMI Recap

Peripheral onlyPeripheral only 8 or 16 bit interface8 or 16 bit interface HS, FS fallbackHS, FS fallback LS only in a separate implementationLS only in a separate implementation FS only in a separate implementationFS only in a separate implementation Vendor control and statusVendor control and status

May 8, 2001 5

UTM Block DiagramUTM Block Diagram

May 8, 2001 6

Hard to ImplementHard to Implement

Challenging to implement rx_valid deassertion Challenging to implement rx_valid deassertion when 8 bits of stuffed bits are received withwhen 8 bits of stuffed bits are received with8 bit interface8 bit interface

Challenging to implement tx_ready deassertion Challenging to implement tx_ready deassertion when 8 stuffed bits are transmittedwhen 8 stuffed bits are transmitted

A nightmare to implement optional 16 bit or 8 and A nightmare to implement optional 16 bit or 8 and 16 bit interface in one transceiver instantiation16 bit interface in one transceiver instantiation

tx_hold_register and rx_hold_register should be tx_hold_register and rx_hold_register should be renamed as tx_hold_buffer and rx_hold bufferrenamed as tx_hold_buffer and rx_hold buffer

May 8, 2001 7

Why 8 or 16 Bit Interface for UTMWhy 8 or 16 Bit Interface for UTM

16 bit interface16 bit interface– FPGA application developmentFPGA application development– Battery powered or bus-powered devicesBattery powered or bus-powered devices

8 bit interface8 bit interface– Reduces package pricing by saving pinsReduces package pricing by saving pins– ASIC/FPGA application developmentASIC/FPGA application development

May 8, 2001 8

Turn Around Time BottleneckTurn Around Time Bottleneck

HS turn around time 192 bit times (24 clocks inHS turn around time 192 bit times (24 clocks in8 bit interface and 12 clocks in 16 bit interface)8 bit interface and 12 clocks in 16 bit interface)

UTM may end up in consuming 103 bit times UTM may end up in consuming 103 bit times maximum in 8 bit interfacemaximum in 8 bit interface

Assuming(may not be possible) 16 bit interface also Assuming(may not be possible) 16 bit interface also consumes same bit duration (we have only 5/11 consumes same bit duration (we have only 5/11 UTMI clock periods for UDC and application)UTMI clock periods for UDC and application)

It is preferred to support both 8 and 16 bit interface It is preferred to support both 8 and 16 bit interface in the same implementationin the same implementation

May 8, 2001 9

Turn Around Time BottleneckTurn Around Time Bottleneck

16 bit interface allows 5 clock cycles for both 16 bit interface allows 5 clock cycles for both UDC20 and applicationUDC20 and application– This will force usb 2.0 application to use the same This will force usb 2.0 application to use the same

UTMI clockUTMI clock– Huge buffers(RAM) are needed for every endpoint Huge buffers(RAM) are needed for every endpoint

depending on implementation.depending on implementation. Example Cypress USB 2.0 solution or inSilicon USB2.0Example Cypress USB 2.0 solution or inSilicon USB2.0

AHB solution.AHB solution. 8 bit interface allows 11 clock cycles8 bit interface allows 11 clock cycles

– Efficient trade off can be made between huge buffers Efficient trade off can be made between huge buffers or lower application operating clock frequencyor lower application operating clock frequency

ContinuedContinued

May 8, 2001 10

Problems EncounteredProblems Encountered

1000 PPM clock tolerance tests1000 PPM clock tolerance tests– Simulation should be done with higher timescale Simulation should be done with higher timescale

resolution. resolution. Example in fs(femto is 10Example in fs(femto is 10-15-15 seconds) otherwise tests fail seconds) otherwise tests fail

Check your results in different waveform viewersCheck your results in different waveform viewers Example Undertow waveform viewer gave wrong information Example Undertow waveform viewer gave wrong information

in showing clocksin showing clocks

May 8, 2001 11

Why Not LS and FS Only in the Same ImplementationWhy Not LS and FS Only in the Same Implementation

USB 2.0 does not allow LS device to act as aUSB 2.0 does not allow LS device to act as aHS deviceHS device

USB 2.0 host needs to support HS, FS, and LSUSB 2.0 host needs to support HS, FS, and LS Vendors no need to maintain 1.1 transceiversVendors no need to maintain 1.1 transceivers

and UDCsand UDCs

May 8, 2001 12

Why Not HUBs and HOSTs?Why Not HUBs and HOSTs?

USB 2.0 hub needs hub controllerUSB 2.0 hub needs hub controller HUB repeaters need elasticity buffer and DLLHUB repeaters need elasticity buffer and DLL HUB repeaters demand a serial interfaceHUB repeaters demand a serial interface

at 480 Mhzat 480 Mhz UTMI can be used for EHCI (host) applicationUTMI can be used for EHCI (host) application

with additional signalswith additional signals Additional host signals have been kept proprietaryAdditional host signals have been kept proprietary

inSilicon USB2 PHYinSilicon USB2 PHYFeaturesFeaturesSupportedSupported

11 UTMI compliant (100%)UTMI compliant (100%)

22 HS and FS fallback 16 bit unidirectionalHS and FS fallback 16 bit unidirectional

33 HS and FS fallback 8 bit unidirectionalHS and FS fallback 8 bit unidirectional

44 FS only 16 bit unidirectionalFS only 16 bit unidirectional

55 FS only 8 bit unidirectionalFS only 8 bit unidirectional

66 LS only 16 bit unidirectionalLS only 16 bit unidirectional

77 LS only 8 bit unidirectionalLS only 8 bit unidirectional

88 HS and FS fallback 16 bit bidirectionalHS and FS fallback 16 bit bidirectional

99 HS and FS fallback 8 bit bidirectionalHS and FS fallback 8 bit bidirectional

1010 FS only 16 bit bidirectionalFS only 16 bit bidirectional

1111 FS only 8 bit bidirectionalFS only 8 bit bidirectional

1212 LS only 16 bit bidirectionalLS only 16 bit bidirectional

1313 LS only 8 bit bidirectionalLS only 8 bit bidirectional

1414 EHCI compliantEHCI compliant

1515 USB 2.0 HUB supportUSB 2.0 HUB support

1616 SoftDisconnectSoftDisconnect

1717 Single chip USB 2.0 products.Single chip USB 2.0 products.

1818 Available in TSMC .18 Available in TSMC .18

1919 Crystal requirementCrystal requirement

2020 Crystal clock supportCrystal clock support

30 Mhz

48 Mhz

inSilicon inSilicon XtremeUTMI PHYXtremeUTMI PHYOne solution for all One solution for all

genericgenericUTMI PHYUTMI PHY

DiscreteDiscreteUTMIUTMIPHY 1PHY 1

ProprietarProprietary PHY 1y PHY 1

Discrete Discrete UTMI PHY 2UTMI PHY 2

IPIPUTMI PHYUTMI PHY11

IPIPUTMI PHYUTMI PHY22

XX

XX XX XX

XX XX XX XX

XX XX XX XX XX XX

XX XX XX XX XX XX

XX XX XX XX XX XX

XX XX XX XX XX XX

XX XX

XX XX XX XX

XX XX XX XX XX XX

XX XX XX XX XX XX

XX XX XX XX XX XX

XX XX XX XX XX XX

XX XX XX XX XX XX

XX XX XX XX XX XX

XX XX XX XX XX

XX XX XX

NANA NANA NANA NANA NDANDA NDANDA

NANA 30 Mhz30 Mhz 12 Mhz12 Mhz NANA NDANDA NDANDA

NANA XX XX 48 Mhz48 Mhz NDANDA NDANDA

May 8, 2001 14

USB OnTheGoUSB OnTheGo

UTMI support peripheral only implementationUTMI support peripheral only implementation Additional signals will be require for USB OnTheGo Additional signals will be require for USB OnTheGo

implementationsimplementations inSilicon Hard TSMC Phy and Developers Kit Phy inSilicon Hard TSMC Phy and Developers Kit Phy

will support OTG out-of-the-boxwill support OTG out-of-the-box

May 8, 2001 15

Questions and Comments

Questions and Comments