MAX78000 User Guide

MAX78000 User GuideMAX78000 User Guide UG7456; Rev 0; 7/2021
Abstract: This user guide provides application developers information on how to use the memory and peripherals of the MAX78000 microcontroller. Detailed information for all registers and fields in the device are covered. Guidance is given for managing all the peripherals, clocks, power and startup for the device family.
MAX78000 User Guide
MAX78000 User Guide
Table of Contents
1. Introduction ----------------------------------------------------------------------------------------------------------------------- 24 1.1 Related Documentation-------------------------------------------------------------------------------------------------------------------- 24 1.2 Document Conventions -------------------------------------------------------------------------------------------------------------------- 24
1.2.1 Number Notations ------------------------------------------------------------------------------------------------------------------ 24 1.2.2 Register and Field Access Definitions ------------------------------------------------------------------------------------------ 24 1.2.3 Register Lists -------------------------------------------------------------------------------------------------------------------------- 25 1.2.4 Register Detail Tables -------------------------------------------------------------------------------------------------------------- 25
2. Overview --------------------------------------------------------------------------------------------------------------------------- 26
3. Memory, Register Mapping, and Access ----------------------------------------------------------------------------------- 28
3.1 Memory, Register Mapping, and Access Overview --------------------------------------------------------------------------------- 28 3.2 Standard Memory Regions ---------------------------------------------------------------------------------------------------------------- 33
3.2.1 Code Space ---------------------------------------------------------------------------------------------------------------------------- 33 3.2.2 Internal Cache Memory ------------------------------------------------------------------------------------------------------------ 33 3.2.3 Information Block Flash Memory ----------------------------------------------------------------------------------------------- 33 3.2.4 SRAM Space --------------------------------------------------------------------------------------------------------------------------- 34 3.2.5 Peripheral Space --------------------------------------------------------------------------------------------------------------------- 35 3.2.6 AES Key and Working Space Memory ------------------------------------------------------------------------------------------ 35 3.2.7 System Area (Private Peripheral Bus) ------------------------------------------------------------------------------------------ 35
3.3 AHB Interfaces-------------------------------------------------------------------------------------------------------------------------------- 35 3.3.1 Arm Core AHB Interfaces ---------------------------------------------------------------------------------------------------------- 35 3.3.2 AHB Slaves ----------------------------------------------------------------------------------------------------------------------------- 36 3.3.3 AHB Slave Base Address Map ---------------------------------------------------------------------------------------------------- 36
3.4 Peripheral Register Map ------------------------------------------------------------------------------------------------------------------- 36 3.4.1 APB Peripheral Base Address Map ---------------------------------------------------------------------------------------------- 36
3.5 Error Correction Coding (ECC) Module ------------------------------------------------------------------------------------------------- 38 3.5.1 SRAM ----------------------------------------------------------------------------------------------------------------------------------- 38 3.5.2 Limitations----------------------------------------------------------------------------------------------------------------------------- 38
4. System, Power, Clocks, Reset ------------------------------------------------------------------------------------------------- 39
4.1 Oscillator Sources ---------------------------------------------------------------------------------------------------------------------------- 39 4.1.1 100MHz Internal Primary Oscillator (IPO) ------------------------------------------------------------------------------------ 39 4.1.2 60MHz Internal Secondary Oscillator (ISO) ----------------------------------------------------------------------------------- 39 4.1.3 8kHz-30kHz Internal Nano-Ring Oscillator (INRO) -------------------------------------------------------------------------- 39 4.1.4 7.3728MHz Internal Baud Rate Oscillator (IBRO) --------------------------------------------------------------------------- 40 4.1.5 32.768kHz External Real-Time Clock Oscillator (ERTCO) ------------------------------------------------------------------ 40
4.2 System Oscillator (SYS_OSC) -------------------------------------------------------------------------------------------------------------- 40 4.2.1 System Oscillator Selection ------------------------------------------------------------------------------------------------------- 40 4.2.2 System Clock (SYS_CLK) ------------------------------------------------------------------------------------------------------------ 41
4.3 Operating Modes ---------------------------------------------------------------------------------------------------------------------------- 43
4.3.1 ACTIVE Mode ------------------------------------------------------------------------------------------------------------------------- 43 4.3.2 Low-Power Modes ------------------------------------------------------------------------------------------------------------------ 43
4.4 Wake-Up Sources for Each Operating Mode ----------------------------------------------------------------------------------------- 55 4.5 Device Resets --------------------------------------------------------------------------------------------------------------------------------- 55
4.5.1 Peripheral Reset --------------------------------------------------------------------------------------------------------------------- 56 4.5.2 Soft Reset ------------------------------------------------------------------------------------------------------------------------------ 56 4.5.3 System Reset ------------------------------------------------------------------------------------------------------------------------- 56 4.5.4 Power-On Reset ---------------------------------------------------------------------------------------------------------------------- 57
4.6 Unified Internal Cache Controllers ------------------------------------------------------------------------------------------------------ 57 4.6.1 Enabling the Internal Cache Controllers --------------------------------------------------------------------------------------- 57 4.6.2 Disabling the ICC --------------------------------------------------------------------------------------------------------------------- 57 4.6.3 Invalidating the ICC Cache and Tag RAM -------------------------------------------------------------------------------------- 57 4.6.4 Flushing the ICC ---------------------------------------------------------------------------------------------------------------------- 57 4.6.5 Internal Cache Control Registers (ICC) ----------------------------------------------------------------------------------------- 57 4.6.6 ICC0 Register Details ---------------------------------------------------------------------------------------------------------------- 58
4.7 RAM Memory Management -------------------------------------------------------------------------------------------------------------- 59 4.7.1 On-Chip Cache Management ----------------------------------------------------------------------------------------------------- 59 4.7.2 RAM Zeroization --------------------------------------------------------------------------------------------------------------------- 59
4.8 Miscellaneous Control Registers (MCR) ----------------------------------------------------------------------------------------------- 60 4.8.1 Miscellaneous Control Register Details ---------------------------------------------------------------------------------------- 60
4.9 Single Inductor Multiple Output Power Supply (SIMO) ---------------------------------------------------------------------------- 63 4.9.1 Power Supply Monitor ------------------------------------------------------------------------------------------------------------- 63 4.9.2 Single Inductor Multiple Output Registers (SIMO) ------------------------------------------------------------------------- 64 4.9.3 Single Inductor Multiple Output (SIMO) Registers Details --------------------------------------------------------------- 64
4.10 Low-Power General Control Registers (LPGCR) ---------------------------------------------------------------------------------- 68 4.10.1 Low-Power General Control Registers Details ------------------------------------------------------------------------------- 69
4.11 Power Sequencer Registers (PWRSEQ) --------------------------------------------------------------------------------------------- 70 4.11.1 Power Sequencer Register Details ---------------------------------------------------------------------------------------------- 71
4.12 Trim System Initialization Registers (TRIMSIR) ---------------------------------------------------------------------------------- 77 4.12.1 TRIM System Initialization Register Details ----------------------------------------------------------------------------------- 78
4.13 Global Control Registers (GCR) ------------------------------------------------------------------------------------------------------- 80 4.13.1 Global Control Register Details (GCR) ------------------------------------------------------------------------------------------ 80
4.14 System Initialization Registers (SIR) ------------------------------------------------------------------------------------------------ 98 4.14.1 System Initialization Register Details------------------------------------------------------------------------------------------- 98
4.15 Function Control Registers (FCR) ---------------------------------------------------------------------------------------------------- 99 4.15.1 Function Control Register Details --------------------------------------------------------------------------------------------- 100
4.16 General Control Function Registers (GCFR) ------------------------------------------------------------------------------------- 103 4.16.1 General Control Function Register Details ---------------------------------------------------------------------------------- 103
5. Interrupts and Exceptions --------------------------------------------------------------------------------------------------- 105
5.1 CM4 Interrupt and Exception Features ---------------------------------------------------------------------------------------------- 105 5.2 CM4 Interrupt Vector Table ------------------------------------------------------------------------------------------------------------- 105 5.3 RV32 Interrupt Vector Table ------------------------------------------------------------------------------------------------------------ 107
6. General-Purpose I/O and Alternate Function Pins (GPIO) ----------------------------------------------------------- 109
6.1 Instances ------------------------------------------------------------------------------------------------------------------------------------- 109 6.2 Configuration ------------------------------------------------------------------------------------------------------------------------------- 110
MAX78000 User Guide
Maxim Integrated Page 4 of 414
6.2.1 Power-On-Reset Configuration ------------------------------------------------------------------------------------------------ 110 6.2.2 Serial Wire Debug Configuration ---------------------------------------------------------------------------------------------- 110 6.2.3 Pin Function Configuration ----------------------------------------------------------------------------------------------------- 111 6.2.4 Input Mode Configuration ------------------------------------------------------------------------------------------------------ 111 6.2.5 Output Mode Configuration ---------------------------------------------------------------------------------------------------- 111
6.3 Reference Tables --------------------------------------------------------------------------------------------------------------------------- 112 6.4 Usage ----------------------------------------------------------------------------------------------------------------------------------------- 113
6.4.1 Reset State -------------------------------------------------------------------------------------------------------------------------- 113 6.4.2 Input Mode Configuration ------------------------------------------------------------------------------------------------------ 113 6.4.3 Output Mode Configuration ---------------------------------------------------------------------------------------------------- 114 6.4.4 Alternate Function Configuration --------------------------------------------------------------------------------------------- 114
6.5 Configuring GPIO (External) Interrupts ---------------------------------------------------------------------------------------------- 114 6.5.1 GPIO Interrupt Handling --------------------------------------------------------------------------------------------------------- 115 6.5.2 Using GPIO for Wake Up from Low-Power Modes ----------------------------------------------------------------------- 115
6.6 Registers ------------------------------------------------------------------------------------------------------------------------------------- 116 6.6.1 Register Details -------------------------------------------------------------------------------------------------------------------- 117
7. Flash Controller (FLC) --------------------------------------------------------------------------------------------------------- 125
7.1 Instances ------------------------------------------------------------------------------------------------------------------------------------- 125 7.2 Usage ----------------------------------------------------------------------------------------------------------------------------------------- 125
7.2.1 Clock Configuration --------------------------------------------------------------------------------------------------------------- 125 7.2.2 Lock Protection -------------------------------------------------------------------------------------------------------------------- 126 7.2.3 Flash Write Width ----------------------------------------------------------------------------------------------------------------- 126 7.2.4 Flash Write -------------------------------------------------------------------------------------------------------------------------- 126 7.2.5 Page Erase --------------------------------------------------------------------------------------------------------------------------- 126 7.2.6 Mass Erase -------------------------------------------------------------------------------------------------------------------------- 127
8. Debug Access Port (DAP) ----------------------------------------------------------------------------------------------------- 133
8.1 Instances ------------------------------------------------------------------------------------------------------------------------------------- 133 8.2 Access Control ------------------------------------------------------------------------------------------------------------------------------ 133
8.2.1 Factory Disabled DAP ------------------------------------------------------------------------------------------------------------- 133 8.2.2 Software Accessible DAP -------------------------------------------------------------------------------------------------------- 133
8.3 Pin Configuration -------------------------------------------------------------------------------------------------------------------------- 133
9.1 Instances ------------------------------------------------------------------------------------------------------------------------------------- 134 9.2 Multiprocessor Communications ------------------------------------------------------------------------------------------------------ 134
9.2.1 Reset ---------------------------------------------------------------------------------------------------------------------------------- 134 9.2.2 CM4 Semaphore Interrupt Generation -------------------------------------------------------------------------------------- 134 9.2.3 RV32 Semaphore Interrupt Generation ------------------------------------------------------------------------------------- 134
10. Standard DMA (DMA) ---------------------------------------------------------------------------------------------------- 140 10.1 Instances --------------------------------------------------------------------------------------------------------------------------------- 140 10.2 DMA Channel Operation (DMA_CH)---------------------------------------------------------------------------------------------- 140
MAX78000 User Guide
10.2.1 Channel Arbitration and DMA Bursts ---------------------------------------------------------------------------------------- 140 10.2.2 Source and Destination Addressing ------------------------------------------------------------------------------------------ 141 10.2.3 Data Movement from Source to DMA --------------------------------------------------------------------------------------- 142 10.2.4 Data Movement from DMA to Destination -------------------------------------------------------------------------------- 142
10.3 Usage ------------------------------------------------------------------------------------------------------------------------------------- 144 10.4 Count-To-Zero (CTZ) Condition ----------------------------------------------------------------------------------------------------- 144 10.5 Chaining Buffers ----------------------------------------------------------------------------------------------------------------------- 145 10.6 DMA Interrupts ------------------------------------------------------------------------------------------------------------------------- 147 10.7 Channel Timeout Detect ------------------------------------------------------------------------------------------------------------- 147 10.8 Memory-to-Memory DMA ---------------------------------------------------------------------------------------------------------- 148 10.9 Registers --------------------------------------------------------------------------------------------------------------------------------- 148
10.9.1 Register Details -------------------------------------------------------------------------------------------------------------------- 148 10.10 DMA Channel Registers -------------------------------------------------------------------------------------------------------------- 149
10.10.1 DMA Channel Register Details --------------------------------------------------------------------------------------------- 149 11. Analog to Digital Converter (ADC) and Comparators (LPCMP) ------------------------------------------------- 155
11.1 Features ---------------------------------------------------------------------------------------------------------------------------------- 155 11.2 Instances --------------------------------------------------------------------------------------------------------------------------------- 155 11.3 Architecture ----------------------------------------------------------------------------------------------------------------------------- 156 11.4 Clock Configuration ------------------------------------------------------------------------------------------------------------------- 157 11.5 Power-Up Sequence------------------------------------------------------------------------------------------------------------------- 158 11.6 Conversion ------------------------------------------------------------------------------------------------------------------------------- 158
11.6.1 Data Conversion Output Alignment ------------------------------------------------------------------------------------------ 158 11.6.2 Data Conversion Value Equations --------------------------------------------------------------------------------------------- 159
11.7 Reference Scaling and Input Scaling ---------------------------------------------------------------------------------------------- 159 11.7.1 AIN0 – AIN7 Scale Limitations -------------------------------------------------------------------------------------------------- 160 11.7.2 Scale Limitations for All Other Input Channels ---------------------------------------------------------------------------- 160
11.8 Data Limits and Out of Range Interrupts ---------------------------------------------------------------------------------------- 160 11.9 Power-Down Sequence--------------------------------------------------------------------------------------------------------------- 162 11.10 Comparator Operation --------------------------------------------------------------------------------------------------------------- 162
11.10.1 Comparator 0 Usage ---------------------------------------------------------------------------------------------------------- 162 11.10.2 Low-Power Comparators 1, 2, and 3 Usage ---------------------------------------------------------------------------- 162 11.10.3 Using Comparator 0 as a Wake-Up Source ----------------------------------------------------------------------------- 163 11.10.4 Using Low-Power Comparators 1, 2, and 3 as a Wake-Up Source ----------------------------------------------- 163
11.11 ADC Registers --------------------------------------------------------------------------------------------------------------------------- 163 11.11.1 ADC Register Details ---------------------------------------------------------------------------------------------------------- 163
11.12 Low-Power Comparator Registers ------------------------------------------------------------------------------------------------ 167 11.12.1 Low-Power Comparator Register Details ------------------------------------------------------------------------------- 168
12. Universal Asynchronous Receiver/Transmitter (UART) ---------------------------------------------------------- 169
12.1 Instances --------------------------------------------------------------------------------------------------------------------------------- 170 12.2 DMA --------------------------------------------------------------------------------------------------------------------------------------- 171 12.3 UART Frame ----------------------------------------------------------------------------------------------------------------------------- 171 12.4 FIFOs -------------------------------------------------------------------------------------------------------------------------------------- 171
MAX78000 User Guide
12.4.1 Transmit FIFO Operation -------------------------------------------------------------------------------------------------------- 171 12.4.2 Receive FIFO Operation ---------------------------------------------------------------------------------------------------------- 172 12.4.3 Flushing ------------------------------------------------------------------------------------------------------------------------------ 172
12.5 Interrupt Events ------------------------------------------------------------------------------------------------------------------------ 172 12.5.1 Frame Error ------------------------------------------------------------------------------------------------------------------------- 172 12.5.2 Parity Error -------------------------------------------------------------------------------------------------------------------------- 173 12.5.3 CTS Signal Change ----------------------------------------------------------------------------------------------------------------- 173 12.5.4 Overrun ------------------------------------------------------------------------------------------------------------------------------ 174 12.5.5 Receive FIFO Threshold ---------------------------------------------------------------------------------------------------------- 174 12.5.6 Transmit FIFO Half-Empty ------------------------------------------------------------------------------------------------------- 174
12.6 LPUART Wakeup Events ------------------------------------------------------------------------------------------------------------- 174 12.6.1 Receive FIFO Threshold ---------------------------------------------------------------------------------------------------------- 174 12.6.2 Receive FIFO Full ------------------------------------------------------------------------------------------------------------------- 174 12.6.3 Receive Not Empty ---------------------------------------------------------------------------------------------------------------- 174
12.7 Inactive State --------------------------------------------------------------------------------------------------------------------------- 174 12.8 Receive Sampling ---------------------------------------------------------------------------------------------------------------------- 175 12.9 Baud Rate Generation ---------------------------------------------------------------------------------------------------------------- 175
12.9.1 UART Clock Sources --------------------------------------------------------------------------------------------------------------- 175 12.9.2 LPUART Clock Sources ------------------------------------------------------------------------------------------------------------ 176 12.9.3 Baud Rate Calculation ------------------------------------------------------------------------------------------------------------ 176 12.9.4 Low-Power Mode Operation of LPUARTs for 9600 Baud and Below ------------------------------------------------ 176
12.10 Hardware Flow Control -------------------------------------------------------------------------------------------------------------- 177 12.10.1 Automated HFC ---------------------------------------------------------------------------------------------------------------- 178 12.10.2 Application Controlled HFC ------------------------------------------------------------------------------------------------- 179
12.11 Registers --------------------------------------------------------------------------------------------------------------------------------- 180 12.11.1 Register Details ---------------------------------------------------------------------------------------------------------------- 180
13. Serial Peripheral Interface (SPI) ---------------------------------------------------------------------------------------- 187 13.1 Instances --------------------------------------------------------------------------------------------------------------------------------- 188 13.2 Format ------------------------------------------------------------------------------------------------------------------------------------ 189
13.2.1 Four-Wire SPI ----------------------------------------------------------------------------------------------------------------------- 189 13.2.2 Three-Wire SPI --------------------------------------------------------------------------------------------------------------------- 190
13.3 Pin Configuration ---------------------------------------------------------------------------------------------------------------------- 191 13.3.1 SPI Alternate Function Mapping ----------------------------------------------------------------------------------------------- 191 13.3.2 Four-wire Format Configuration ---------------------------------------------------------------------------------------------- 191 13.3.3 Three-Wire Format Configuration -------------------------------------------------------------------------------------------- 191 13.3.4 Dual-Mode Format Configuration -------------------------------------------------------------------------------------------- 192 13.3.5 Quad-Mode Format Pin Configuration -------------------------------------------------------------------------------------- 192
13.4 Clock Configuration ------------------------------------------------------------------------------------------------------------------- 192 13.4.1 Serial Clock -------------------------------------------------------------------------------------------------------------------------- 192 13.4.2 Peripheral Clock -------------------------------------------------------------------------------------------------------------------- 192 13.4.3 Master Mode Serial Clock Generation --------------------------------------------------------------------------------------- 193 13.4.4 Clock Phase and Polarity Control ---------------------------------------------------------------------------------------------- 193 13.4.5 Transmit and Receive FIFOs ---------------------------------------------------------------------------------------------------- 194 13.4.6 Interrupts and Wakeups --------------------------------------------------------------------------------------------------------- 194
13.5 Registers --------------------------------------------------------------------------------------------------------------------------------- 195 13.5.1 Register Details -------------------------------------------------------------------------------------------------------------------- 196
14. I2C Master/Slave Serial Communications Peripheral (I2C) ------------------------------------------------------- 205
MAX78000 User Guide
14.1 I2C Master/Slave Features ----------------------------------------------------------------------------------------------------------- 205 14.2 Instances --------------------------------------------------------------------------------------------------------------------------------- 205 14.3 I2C Overview ---------------------------------------------------------------------------------------------------------------------------- 206
14.3.1 I2C Bus Terminology -------------------------------------------------------------------------------------------------------------- 206 14.3.2 I2C Transfer Protocol Operation ----------------------------------------------------------------------------------------------- 206 14.3.3 START and STOP Conditions ---------------------------------------------------------------------------------------------------- 206 14.3.4 Master Operation ----------------------------------------------------------------------------------------------------------------- 206 14.3.5 Acknowledge and Not Acknowledge ----------------------------------------------------------------------------------------- 206 14.3.6 Bit Transfer Process --------------------------------------------------------------------------------------------------------------- 207
14.4 Configuration and Usage ------------------------------------------------------------------------------------------------------------ 208 14.4.1 SCL and SDA Bus Drivers --------------------------------------------------------------------------------------------------------- 208 14.4.2 SCL Clock Configurations -------------------------------------------------------------------------------------------------------- 208 14.4.3 SCL Clock Generation for Standard, Fast and Fast-Plus Modes ------------------------------------------------------- 208 14.4.4 SCL Clock Generation for Hs-Mode ------------------------------------------------------------------------------------------- 209 14.4.5 Addressing --------------------------------------------------------------------------------------------------------------------------- 210 14.4.6 Master Mode Operation--------------------------------------------------------------------------------------------------------- 210 14.4.7 Slave Mode Operation ----------------------------------------------------------------------------------------------------------- 213 14.4.8 Interrupt Sources ------------------------------------------------------------------------------------------------------------------ 218 14.4.9 Transmit FIFO and Receive FIFO ----------------------------------------------------------------------------------------------- 219 14.4.10 Transmit FIFO Preloading --------------------------------------------------------------------------------------------------- 220 14.4.11 Interactive Receive Mode (IRXM) ----------------------------------------------------------------------------------------- 221 14.4.12 Clock Stretching ---------------------------------------------------------------------------------------------------------------- 222 14.4.13 Bus Timeout -------------------------------------------------------------------------------------------------------------------- 222 14.4.14 DMA Control -------------------------------------------------------------------------------------------------------------------- 223
15. Inter-IC Interface (I2S) ---------------------------------------------------------------------------------------------------- 239
15.1 Instances --------------------------------------------------------------------------------------------------------------------------------- 239 15.1.1 I2S Bus Lines and Definitions --------------------------------------------------------------------------------------------------- 239
15.2 Details ------------------------------------------------------------------------------------------------------------------------------------ 240 15.3 Master and Slave Mode Configuration ------------------------------------------------------------------------------------------ 241 15.4 Clocking ---------------------------------------------------------------------------------------------------------------------------------- 241
15.4.1 BCLK Generation for Master Mode ------------------------------------------------------------------------------------------- 242 15.4.2 LRCLK Period Calculation -------------------------------------------------------------------------------------------------------- 242
15.5 Data Formatting ----------------------------------------------------------------------------------------------------------------------- 243 15.5.1 Sample Size-------------------------------------------------------------------------------------------------------------------------- 243 15.5.2 Word Select Polarity -------------------------------------------------------------------------------------------------------------- 243 15.5.3 First Bit Location Control -------------------------------------------------------------------------------------------------------- 243 15.5.4 Sample Adjustment --------------------------------------------------------------------------------------------------------------- 244 15.5.5 Stereo/Mono Configuration ---------------------------------------------------------------------------------------------------- 245
15.6 Transmit and Receive FIFOs--------------------------------------------------------------------------------------------------------- 246 15.6.1 FIFO Data Width ------------------------------------------------------------------------------------------------------------------- 246 15.6.2 Transmit FIFO ----------------------------------------------------------------------------------------------------------------------- 246 15.6.3 Receive FIFO ------------------------------------------------------------------------------------------------------------------------ 246 15.6.4 FIFO Word Control ---------------------------------------------------------------------------------------------------------------- 246 15.6.5 FIFO Data Alignment -------------------------------------------------------------------------------------------------------------- 247 15.6.6 Typical Audio Configurations --------------------------------------------------------------------------------------------------- 248
15.7 Interrupt Events ------------------------------------------------------------------------------------------------------------------------ 248
15.7.1 Receive FIFO Overrun ------------------------------------------------------------------------------------------------------------ 249 15.7.2 Receive FIFO Threshold ---------------------------------------------------------------------------------------------------------- 249 15.7.3 Transmit FIFO Half-Empty ------------------------------------------------------------------------------------------------------- 249 15.7.4 Transmit FIFO One Entry Remaining ----------------------------------------------------------------------------------------- 249
15.8 Direct Memory Access ---------------------------------------------------------------------------------------------------------------- 249 15.9 Block Operation ------------------------------------------------------------------------------------------------------------------------ 250 15.10 Registers --------------------------------------------------------------------------------------------------------------------------------- 250
15.10.1 Register Details ---------------------------------------------------------------------------------------------------------------- 250 16. Camera Interface (CAMERAIF) ----------------------------------------------------------------------------------------- 255
16.1 Instances --------------------------------------------------------------------------------------------------------------------------------- 255 16.2 Capture Modes ------------------------------------------------------------------------------------------------------------------------- 256
16.2.1 Single Image Capture ------------------------------------------------------------------------------------------------------------- 256 16.2.2 Continuous Capture -------------------------------------------------------------------------------------------------------------- 256
16.3 Timing Modes -------------------------------------------------------------------------------------------------------------------------- 256 16.3.1 Horizontal and Vertical Synchronization Timing Mode ----------------------------------------------------------------- 256 16.3.2 Data Stream Timing Mode ------------------------------------------------------------------------------------------------------ 256
16.4 Data Width ------------------------------------------------------------------------------------------------------------------------------ 256 16.4.1 8-Bit Width -------------------------------------------------------------------------------------------------------------------------- 256 16.4.2 10 and 12-bit Width -------------------------------------------------------------------------------------------------------------- 257
16.5 Data FIFO -------------------------------------------------------------------------------------------------------------------------------- 258 16.6 Usage ------------------------------------------------------------------------------------------------------------------------------------- 258
16.6.1 DMA ----------------------------------------------------------------------------------------------------------------------------------- 258 16.6.2 Interrupts ---------------------------------------------------------------------------------------------------------------------------- 259
16.7 Camera Registers ---------------------------------------------------------------------------------------------------------------------- 259 16.7.1 Parallel Camera Register Details ---------------------------------------------------------------------------------------------- 259
17. 1-Wire Master (OWM) --------------------------------------------------------------------------------------------------- 264 17.1 1-Wire Master Features ------------------------------------------------------------------------------------------------------------- 264 17.2 1-Wire Pins and Configuration ----------------------------------------------------------------------------------------------------- 265
17.2.1 1-Wire I/O (OWM_IO) ------------------------------------------------------------------------------------------------------------ 265 17.2.2 Pullup Enable (OWM_PE) ------------------------------------------------------------------------------------------------------- 265 17.2.3 Clock Configuration --------------------------------------------------------------------------------------------------------------- 265
17.3 1-Wire Protocol ------------------------------------------------------------------------------------------------------------------------ 265 17.3.1 Networking Layers ---------------------------------------------------------------------------------------------------------------- 265 17.3.2 Read ROM Command ------------------------------------------------------------------------------------------------------------ 270 17.3.3 Skip ROM and Overdrive Skip ROM Commands -------------------------------------------------------------------------- 271 17.3.4 Match ROM and Overdrive Match ROM Commands -------------------------------------------------------------------- 271 17.3.5 Search ROM Command ---------------------------------------------------------------------------------------------------------- 271 17.3.6 Search ROM Accelerator Operation ------------------------------------------------------------------------------------------ 272 17.3.7 Resume Communication Command ------------------------------------------------------------------------------------------ 272
17.4 1-Wire Operation ---------------------------------------------------------------------------------------------------------------------- 273 17.4.1 Resetting the OWM --------------------------------------------------------------------------------------------------------------- 273
17.5 1-Wire Data Reads -------------------------------------------------------------------------------------------------------------------- 273 17.5.1 Reading a Single Bit Value from the 1-Wire Bus -------------------------------------------------------------------------- 273 17.5.2 Reading an 8-Bit Value from the 1-Wire Bus ------------------------------------------------------------------------------- 274
17.6 Registers --------------------------------------------------------------------------------------------------------------------------------- 274
MAX78000 User Guide
17.6.1 Register Details -------------------------------------------------------------------------------------------------------------------- 274 18. Real-Time Clock (RTC) ---------------------------------------------------------------------------------------------------- 279
18.1 Overview --------------------------------------------------------------------------------------------------------------------------------- 279 18.2 Instances --------------------------------------------------------------------------------------------------------------------------------- 280 18.3 Register Access Control -------------------------------------------------------------------------------------------------------------- 280
18.3.1 RTC_SEC and RTC_SSEC Read Access Control ------------------------------------------------------------------------------ 280 18.3.2 RTC Write Access Control ------------------------------------------------------------------------------------------------------- 281
18.4 RTC Alarm Functions ------------------------------------------------------------------------------------------------------------------ 281 18.4.1 Time-of-Day Alarm ---------------------------------------------------------------------------------------------------------------- 281 18.4.2 Sub-Second Alarm ----------------------------------------------------------------------------------------------------------------- 281 18.4.3 RTC Interrupt and Wakeup Configuration ---------------------------------------------------------------------------------- 282 18.4.4 Square Wave Output ------------------------------------------------------------------------------------------------------------- 283
18.5 RTC Calibration ------------------------------------------------------------------------------------------------------------------------- 283 18.6 Registers --------------------------------------------------------------------------------------------------------------------------------- 285
18.6.1 Register Details -------------------------------------------------------------------------------------------------------------------- 285 19. Timers (TMR/LPTMR) ----------------------------------------------------------------------------------------------------- 290
19.1 Instances --------------------------------------------------------------------------------------------------------------------------------- 291 19.2 Basic Timer Operation ---------------------------------------------------------------------------------------------------------------- 291 19.3 32-Bit Single / 32-Bit Cascade / Dual 16-Bit ------------------------------------------------------------------------------------ 292 19.4 Timer Clock Sources ------------------------------------------------------------------------------------------------------------------- 292 19.5 Timer Pin Functionality --------------------------------------------------------------------------------------------------------------- 293 19.6 Wake-Up Events ----------------------------------------------------------------------------------------------------------------------- 295 19.7 Operating Modes ---------------------------------------------------------------------------------------------------------------------- 296
19.7.1 One-Shot Mode (0) --------------------------------------------------------------------------------------------------------------- 298 19.7.2 Continuous Mode (1) ------------------------------------------------------------------------------------------------------------- 300 19.7.3 Counter Mode (2) ----------------------------------------------------------------------------------------------------------------- 302 19.7.4 PWM Mode (3) --------------------------------------------------------------------------------------------------------------------- 304 19.7.5 Capture Mode (4) ----------------------------------------------------------------------------------------------------------------- 305 19.7.6 Compare Mode (5) ---------------------------------------------------------------------------------------------------------------- 308 19.7.7 Gated Mode (6) -------------------------------------------------------------------------------------------------------------------- 310 19.7.8 Capture/Compare Mode (7) ---------------------------------------------------------------------------------------------------- 312 19.7.9 Dual Edge Capture Mode (8) --------------------------------------------------------------------------------------------------- 314 19.7.10 Inactive Gated Mode (14) --------------------------------------------------------------------------------------------------- 314
20. Wake-Up Timer (WUT) --------------------------------------------------------------------------------------------------- 323
20.1 Basic Operation ------------------------------------------------------------------------------------------------------------------------ 323 20.2 One-Shot Mode (0) -------------------------------------------------------------------------------------------------------------------- 324
20.2.1 One-Shot Mode Timer Period -------------------------------------------------------------------------------------------------- 324 20.2.2 One-Shot Mode Configuration ------------------------------------------------------------------------------------------------- 325
20.3 Continuous Mode (1) ----------------------------------------------------------------------------------------------------------------- 325 20.3.1 Continuous Mode Timer Period ----------------------------------------------------------------------------------------------- 326 20.3.2 Continuous Mode Configuration ---------------------------------------------------------------------------------------------- 326
20.4 Registers --------------------------------------------------------------------------------------------------------------------------------- 326
MAX78000 User Guide
20.4.1 Register Details -------------------------------------------------------------------------------------------------------------------- 327 21. Watchdog Timer (WDT) -------------------------------------------------------------------------------------------------- 329
21.1 Instances -------------------------------------------------------------------------------------------------------------------------------- 330 21.2 Usage ------------------------------------------------------------------------------------------------------------------------------------- 330
21.2.1 Using the WDT as a Long-Interval Timer ------------------------------------------------------------------------------------ 331 21.2.2 Using the WDT as a Long-Interval Wake-Up Timer ----------------------------------------------------------------------- 331
21.3 WDT Feed Sequence ------------------------------------------------------------------------------------------------------------------ 331 21.4 WDT Events ----------------------------------------------------------------------------------------------------------------------------- 332
21.4.1 WDT Early Reset ------------------------------------------------------------------------------------------------------------------- 332 21.4.2 WDT Early Interrupt -------------------------------------------------------------------------------------------------------------- 333 21.4.3 WDT Late Reset -------------------------------------------------------------------------------------------------------------------- 333 21.4.4 WDT Late Interrupt --------------------------------------------------------------------------------------------------------------- 334
21.5 Initializing the WDT ------------------------------------------------------------------------------------------------------------------- 335 21.6 Resets ------------------------------------------------------------------------------------------------------------------------------------- 335 21.7 Registers --------------------------------------------------------------------------------------------------------------------------------- 335
21.7.1 Register Details -------------------------------------------------------------------------------------------------------------------- 336 22. Pulse Train Engine (PT) --------------------------------------------------------------------------------------------------- 340
22.1 Instances --------------------------------------------------------------------------------------------------------------------------------- 340 22.2 Features ---------------------------------------------------------------------------------------------------------------------------------- 340 22.3 Engine ------------------------------------------------------------------------------------------------------------------------------------ 340
22.3.1 Pulse Train Output Modes ------------------------------------------------------------------------------------------------------ 340 22.4 Enabling and Disabling a Pulse Train Output ---------------------------------------------------------------------------------- 342 22.5 Atomic Pulse Train Output Enable and Disable -------------------------------------------------------------------------------- 342
22.5.1 Pulse Train Atomic Enable ------------------------------------------------------------------------------------------------------ 342 22.5.2 Pulse Train Atomic Disable ------------------------------------------------------------------------------------------------------ 342
22.6 Halt and Disable ----------------------------------------------------------------------------------------------------------------------- 343 22.7 Interrupts -------------------------------------------------------------------------------------------------------------------------------- 343 22.8 Registers --------------------------------------------------------------------------------------------------------------------------------- 343
22.8.1 Register Details -------------------------------------------------------------------------------------------------------------------- 344 23. Cyclic Redundancy Check (CRC) ---------------------------------------------------------------------------------------- 351
23.1 Instances --------------------------------------------------------------------------------------------------------------------------------- 351 23.2 Usage ------------------------------------------------------------------------------------------------------------------------------------- 351 23.3 Polynomial Generation --------------------------------------------------------------------------------------------------------------- 352 23.4 Calculations Using Software -------------------------------------------------------------------------------------------------------- 352 23.5 Calculations Using DMA ------------------------------------------------------------------------------------------------------------- 353 23.6 Registers --------------------------------------------------------------------------------------------------------------------------------- 354
23.6.1 Register Details -------------------------------------------------------------------------------------------------------------------- 354 24. Advanced Encryption Standard (AES) -------------------------------------------------------------------------------- 357
24.1 Instances --------------------------------------------------------------------------------------------------------------------------------- 357 24.2 Encryption of 128-Bit Blocks of Data Using FIFO ------------------------------------------------------------------------------ 357 24.3 Encryption of 128-Bit Blocks Using DMA ---------------------------------------------------------------------------------------- 357
MAX78000 User Guide
24.4 Encryption of Blocks Less Than 128-Bits ----------------------------------------------------------------------------------------- 359 24.5 Decryption ------------------------------------------------------------------------------------------------------------------------------- 359 24.6 Interrupt Events ------------------------------------------------------------------------------------------------------------------------ 359
24.6.1 Data Output FIFO Overrun ------------------------------------------------------------------------------------------------------ 360 24.6.2 Key Zero ------------------------------------------------------------------------------------------------------------------------------ 360 24.6.3 Key Change -------------------------------------------------------------------------------------------------------------------------- 360 24.6.4 Calculation Done ------------------------------------------------------------------------------------------------------------------ 360
25. TRNG Engine ---------------------------------------------------------------------------------------------------------------- 363
26. Bootloader ------------------------------------------------------------------------------------------------------------------ 365 26.1 Instances --------------------------------------------------------------------------------------------------------------------------------- 365 26.2 Bootloader Operating States ------------------------------------------------------------------------------------------------------- 366
26.2.1 UNLOCKED -------------------------------------------------------------------------------------------------------------------------- 366 26.2.2 LOCKED ------------------------------------------------------------------------------------------------------------------------------- 366 26.2.3 PERMLOCKED ----------------------------------------------------------------------------------------------------------------------- 366 26.2.4 CHALLENGE (Secure Bootloader Only) --------------------------------------------------------------------------------------- 367 26.2.5 APPVERIFY (Secure Bootloader only) ---------------------------------------------------------------------------------------- 367
26.3 Creating the Motorola SREC File--------------------------------------------------------------------------------------------------- 368 26.4 Bootloader Activation ---------------------------------------------------------------------------------------------------------------- 368 26.5 Bootloader------------------------------------------------------------------------------------------------------------------------------- 368 26.6 Secure Bootloader --------------------------------------------------------------------------------------------------------------------- 369
26.7 Command Protocol -------------------------------------------------------------------------------------------------------------------- 370 26.8 General Commands ------------------------------------------------------------------------------------------------------------------- 371
26.8.1 General Command Details ------------------------------------------------------------------------------------------------------ 371 26.9 Secure Commands --------------------------------------------------------------------------------------------------------------------- 375
26.9.1 Secure Command Details -------------------------------------------------------------------------------------------------------- 375 26.10 Challenge/Response Commands -------------------------------------------------------------------------------------------------- 377
26.10.1 Challenge/Response Command Details --------------------------------------------------------------------------------- 377 27. Convolutional Neural Network (CNN) -------------------------------------------------------------------------------- 378
27.1 Overview --------------------------------------------------------------------------------------------------------------------------------- 378 27.2 Instances --------------------------------------------------------------------------------------------------------------------------------- 381
27.2.1 Block Diagram ---------------------------------------------------------------------------------------------------------------------- 381 27.3 Memory Configuration --------------------------------------------------------------------------------------------------------------- 382
27.3.1 CNNx16_n TRAM Details -------------------------------------------------------------------------------------------------------- 383 27.3.2 CNNx16_n MRAM Details ------------------------------------------------------------------------------------------------------- 385
27.4 CNN Global Registers (CNN) -------------------------------------------------------------------------------------------------------- 387 27.4.1 Global CNN Register Details ---------------------------------------------------------------------------------------------------- 387
27.5 CNNx16 Processor Array (CNNx16_n) Registers ------------------------------------------------------------------------------- 391
MAX78000 User Guide
27.5.1 CNNx16_n Instances and Base Offset Addresses ------------------------------------------------------------------------- 391 27.5.2 CNN Per x16 Processor Register Details ------------------------------------------------------------------------------------- 392
28. Revision History ------------------------------------------------------------------------------------------------------------ 414
List of Figures
Figure 2-1: MAX78000 Block Diagram ....................................................................................................................................... 27 Figure 3-1: CM4 Code Memory Mapping .................................................................................................................................. 29 Figure 3-2: RISC-V IBUS Code Memory Mapping ....................................................................................................................... 30 Figure 3-3: CM4 Peripheral and Data Memory Mapping........................................................................................................... 31 Figure 3-4: RV32 Peripheral and Data Memory Mapping .......................................................................................................... 32 Figure 3-5: Unique Serial Number Format ................................................................................................................................. 33 Figure 4-1: MAX78000 Clock Block Diagram .............................................................................................................................. 42 Figure 4-2: SLEEP Mode Clock Control ....................................................................................................................................... 44 Figure 4-3: LPM Clock and State Retention Diagram ................................................................................................................. 46 Figure 4-4: UPM Clock and State Retention Block Diagram ...................................................................................................... 48 Figure 4-5: STANDBY Mode Clock and State Retention Block Diagram ..................................................................................... 50 Figure 4-6: BACKUP Mode Clock and State Retention Block Diagram ....................................................................................... 52 Figure 4-7: PDM Clock and State Retention Block Diagram....................................................................................................... 54 Figure 10-1: DMA Block-Chaining Flowchart ........................................................................................................................... 146 Figure 11-1: Analog to Digital Converter Block Diagram ......................................................................................................... 156 Figure 11-2: ADC Limit Engine ................................................................................................................................................. 161 Figure 12-1: UART Block Diagram ............................................................................................................................................ 170 Figure 12-2: UART Frame Structure ......................................................................................................................................... 171 Figure 12-3: UART Interrupt Functional Diagram .................................................................................................................... 172 Figure 12-4: Oversampling Example ........................................................................................................................................ 175 Figure 12-5: UART Baud Rate Generation ............................................................................................................................... 175 Figure 12-6: LPUART Timing Generation ................................................................................................................................. 176 Figure 12-7: Hardware Flow Control Physical Connection ...................................................................................................... 178 Figure 12-8: Hardware Flow Control Signaling for Transmitting to an External Receiver ....................................................... 179 Figure 13-1: SPI Block Diagram ................................................................................................................................................ 188 Figure 13-2: 4-Wire SPI Connection Diagram .......................................................................................................................... 190 Figure 13-3: Generic 3-Wire SPI Master to Slave Connection ................................................................................................. 191 Figure 13-4: Dual Mode SPI Connection Diagram .................................................................................................................... 192 Figure 13-5: SCK Clock Rate Control ........................................................................................................................................ 193 Figure 13-6: SPI Clock Polarity ................................................................................................................................................. 194 Figure 14-1: I2C Write Data Transfer ........................................................................................................................................ 207 Figure 14-2: I2C SCL Timing for Standard, Fast and Fast-Plus Modes ...................................................................................... 208 Figure 15-1: I2S Master Mode, Full Duplex Connection ........................................................................................................... 240 Figure 15-2: I2S Slave Mode ..................................................................................................................................................... 241 Figure 15-3: Audio Interface I2S Signal Diagram ...................................................................................................................... 241 Figure 15-4: Audio Mode with Inverted Word Select Polarity ................................................................................................. 243 Figure 15-5: Audio Master Mode Left-Justified First Bit Location ........................................................................................... 244 Figure 15-6: MSB Adjustment when Sample Size is Less Than Bits Per Word ......................................................................... 244 Figure 15-7: LSB Adjustment when Sample Size is Less Than Bits Per Word ........................................................................... 245 Figure 15-8: I2S Mono Left Mode ............................................................................................................................................. 245 Figure 15-9: I2S Mono Right Mode ........................................................................................................................................... 246 Figure 16-1: Horizontal and Vertical Synchronization Timing Mode with 8-Bit Data Width ................................................... 257 Figure 16-2: Data Stream Timing Mode with 8-Bit Data Width ............................................................................................... 257 Figure 16-3: 10 or 12-bit PCIF_VSYNC/PCIF_HSYNC ................................................................................................................ 258 Figure 17-1: 1-Wire Signal Interface ........................................................................................................................................ 266 Figure 17-2: 1-Wire Reset Pulse ............................................................................................................................................... 267 Figure 17-3: 1-Wire Write Time Slot ........................................................................................................................................ 268 Figure 17-4: 1-Wire Read Time Slot ......................................................................................................................................... 268
MAX78000 User Guide
Figure 17-5: 1-Wire ROM ID Fields .......................................................................................................................................... 270 Figure 18-1: MAX78000 RTC Block Diagram (12-bit Sub-Second Counter) ............................................................................. 279 Figure 18-2: RTC Interrupt/Wakeup Diagram Wake-Up Function ........................................................................................... 282 Figure 18-3: Internal Implementation of 4kHz Digital Trim ..................................................................................................... 284 Figure 19-1: MAX78000 TimerA Output Functionality, Modes 0/1/3/5 .................................................................................. 294 Figure 19-2: MAX78000 TimerA Input Functionality, Modes 2/4/6/7/8/14 ............................................................................ 295 Figure 19-3: Timer I/O Signal Naming Conventions ................................................................................................................. 296 Figure 19-4: One-Shot Mode Diagram ..................................................................................................................................... 299 Figure 19-5: Continuous Mode Diagram .................................................................................................................................. 301 Figure 19-6: Counter Mode Diagram ....................................................................................................................................... 303 Figure 19-7: Capture Mode Diagram ....................................................................................................................................... 307 Figure 19-8: Compare Mode Diagram ..................................................................................................................................... 309 Figure 19-9: Gated Mode Diagram .......................................................................................................................................... 311 Figure 19-10: Capture/Compare Mode Diagram ..................................................................................................................... 313 Figure 20-1: One-Shot Mode Diagram ..................................................................................................................................... 324 Figure 20-2: Continuous Mode Diagram .................................................................................................................................. 325 Figure 21-1: Windowed Watchdog Timer Block Diagram ........................................................................................................ 330 Figure 21-2: WDT Early Interrupt and Reset Event Sequencing Details .................................................................................. 333 Figure 21-3: WDT Late Interrupt and Reset Event Sequencing Details.................................................................................... 334 Figure 26-1: MAX78000 Combined Bootloader Flow .............................................................................................................. 369 Figure 27-1: CNN Overview...................................................................................................................................................... 380 Figure 27-2: CNNx16_n Processor Quadrant Block Diagram ................................................................................................... 381 Figure 27-3: CNN Global and Quad CNNx16n Processor Array APB Memory Map ................................................................. 382
MAX78000 User Guide
List of Tables
Table 1-1: Field Access Definitions ............................................................................................................................................ 24 Table 1-2: Example Registers ..................................................................................................................................................... 25 Table 1-3: Example Name 0 Register ......................................................................................................................................... 25 Table 3-1: System SRAM Configuration ..................................................................................................................................... 34 Table 3-2: AHB Slave Base Address Map ................................................................................................................................... 36 Table 3-3: APB Peripheral Base Address Map............................................................................................................................ 36 Table 4-1: Available System Oscillators ..................................................................................................................................... 40 Table 4-2: Reset Sources and Effect on Oscillator and System Clock ........................................................................................ 41 Table 4-3 System RAM Retention in BACKUP Mode .................................................................................................................. 51 Table 4-4: Wake-Up Sources for Each Operating Mode in the MAX78000 ............................................................................... 55 Table 4-5: Reset and Low-Power Mode Effects ......................................................................................................................... 56 Table 4-6: Instruction Cache Controller Register Summary ....................................................................................................... 58 Table 4-7: ICC0 Cache Information Register .............................................................................................................................. 58 Table 4-8: ICC0 Memory Size Register ....................................................................................................................................... 58 Table 4-9: ICC0 Cache Control Register ..................................................................................................................................... 58 Table 4-10: ICC0 Invalidate Register .......................................................................................................................................... 59 Table 4-11: Miscellaneous Control Register Summary .............................................................................................................. 60 Table 4-12: Error Correction Coding Enable Register ................................................................................................................ 60 Table 4-13: IPO Manual Register ............................................................................................................................................... 60 Table 4-14: Output Enable Register ........................................................................................................................................... 61 Table 4-15: Comparator 0 Control Register ............................................................................................................................... 61 Table 4-16: Miscellaneous Control Register .............................................................................................................................. 62 Table 4-17: GPIO3 Pin Control Register ..................................................................................................................................... 62 Table 4-18: SIMO Power Supply Device Pin Connectivity .......................................................................................................... 63 Table 4-19: SIMO Controller Register Summary ........................................................................................................................ 64 Table 4-20: SIMO Buck Voltage Regulator A Control Register ................................................................................................... 64 Table 4-21: SIMO Buck Voltage Regulator B Control Register ................................................................................................... 65 Table 4-22: SIMO Buck Voltage Regulator C Control Register ................................................................................................... 65 Table 4-23: SIMO High Side FET Peak Current VREGO_A VREGO_B Register ..................................................................................... 66 Table 4-24: SIMO High Side FET Peak Current VREGO_C Register ................................................................................................. 66 Table 4-25: SIMO Maximum High Side FET Time On Register ................................................................................................... 66 Table 4-26: SIMO Buck Cycle Count VREGO_A Register ................................................................................................................. 67 Table 4-27: SIMO Buck Cycle Count VREGO_B Register ................................................................................................................. 67 Table 4-28: SIMO Buck Cycle Count VREGO_C Register ................................................................................................................. 67 Table 4-29: SIMO Buck Cycle Count Alert VREGO_A Register ........................................................................................................ 67 Table 4-30: SIMO Buck Cycle Count Alert VREGO_B Register ........................................................................................................ 67 Table 4-31: SIMO Buck Cycle Count Alert VREGO_C Register ........................................................................................................ 67 Table 4-32: SIMO Buck Regulator Output Ready Register ......................................................................................................... 67 Table 4-33: SIMO Zero Cross Calibration VREGO_A Register ......................................................................................................... 68 Table 4-34: SIMO Zero Cross Calibration VREGO_B Register ......................................................................................................... 68 Table 4-35: SIMO Zero Cross Calibration VREGO_C Register ......................................................................................................... 68 Table 4-36 Low-Power Control Register Summary .................................................................................................................... 69 Table 4-37: Reset Control Register ............................................................................................................................................ 69 Table 4-38: Clock Disable Register ............................................................................................................................................. 69 Table 4-39: Power Sequencer Register Summary ...................................................................................................................... 70 Table 4-40: Low Power Control Register ................................................................................................................................... 71 Table 4-41: GPIO0 Low Power Wakeup Status Flags ................................................................................................................. 72 Table 4-42: GPIO0 Low Power Wakeup Enable Registers .......................................................................................................... 72 Table 4-43: GPIO1 Low Power Wakeup Status Flags ................................................................................................................. 73 Table 4-44: GPIO1 Low Power Wakeup Enable Registers .......................................................................................................... 73
MAX78000 User Guide
Table 4-45: GPIO2 Low Power Wakeup Status Flags ................................................................................................................. 73 Table 4-46: GPIO2 Low Power Wakeup Enable Registers .......................................................................................................... 73 Table 4-47: GPIO3 Low Power Wakeup Status Flags ................................................................................................................. 74 Table 4-48: GPIO3 Low Power Wakeup Enable Registers .......................................................................................................... 74 Table 4-49: Low Power Peripheral Wakeup Status Flags ........................................................................................................... 74 Table 4-50: Low Power Peripheral Wakeup Enable Registers ................................................................................................... 75 Table 4-51: Low Power General Purpose 0 Register .................................................................................................................. 77 Table 4-52: Low Power General Purpose 1 Register .................................................................................................................. 77 Table 4-53: Trim System Initialization Register Summary ......................................................................................................... 77 Table 4-54: RTC Trim System Initialization Register .................................................................................................................. 78 Table 4-55: SIMO Trim System Initialization Register ................................................................................................................ 78 Table 4-56: IPO Low Trim System Initialization Register ........................................................................................................... 78 Table 4-57: Control Trim System Initialization Register ............................................................................................................. 79 Table 4-58: INRO Trim System Initialization Register ................................................................................................................ 79 Table 4-59: Global Control Register Summary ........................................................................................................................... 80 Table 4-60: System Control Register .......................................................................................................................................... 80 Table 4-61: Reset Register 0 ...................................................................................................................................................... 82 Table 4-62: Clock Control Register ............................................................................................................................................. 85 Table 4-63: Power Management Register ................................................................................................................................. 87 Table 4-64: Peripheral Clock Divisor Register ............................................................................................................................ 88 Table 4-65: Peripheral Clock Disable Register 0 ........................................................................................................................ 89 Table 4-66: Memory Clock Control Register .............................................................................................................................. 91 Table 4-67: Memory Zeroize Control Register ........................................................................................................................... 91 Table 4-68: System Status Flag Register .................................................................................................................................... 92 Table 4-69: Reset Register 1 ...................................................................................................................................................... 92 Table 4-70: Peripheral Clock Disable Register 1 ........................................................................................................................ 94 Table 4-71: Event Enable Register ............................................................................................................................................. 95 Table 4-72: Revision Register ..................................................................................................................................................... 96 Table 4-73: System Status Interrupt Enable Register ................................................................................................................ 96 Table 4-74: Error Correction Coding Error Register ................................................................................................................... 96 Table 4-75: Error Correction Coding Correctable Error Detected Register ............................................................................... 96 Table 4-76: Error Correction Coding Interrupt Enable Register ................................................................................................. 96 Table 4-77: Error Correction Coding Error Address Register ..................................................................................................... 97 Table 4-78: General Purpose 0 Register .................................................................................................................................... 98 Table 4-79: System Initialization Register Summary.................................................................................................................. 98 Table 4-80: System Initialization Status Register ....................................................................................................................... 98 Table 4-81: System Initialization Address Error Register .....................................................................................

MAX78000 User Guide

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