Mass test and calibration of SAMPA

Lund Team: Jonathan Adolfsson Ulf Mjörnmark Anders Oskarsson David Silvermyr Lennart Österman + GBT/TRORC experts (Torsten Alt) and Experts involved in SAMPA-FEC and MuCh work

Outline: • Experience from first 700 SAMPA MPW2 (manual test) • The robotic test station • Plan

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700 v2 SAMPAS have been tested in a systematic way by operator • Same equipment as for SAMPA characterization • PCCA test card with socket (from ALICE Muon Chambers) • Readout with ALTERA development board • Testpulsing by remote control function generator (Tektronix AFG3000)

Operation at full speed (not fully TPC-adapted yet): • 320MHz readout, • 10 MHz sampling • 11 Elinks

Large scale experience from early-on testing • Time estimates • Yield indication • Root Software for analysis • Scripts for pulser control • Socket reliability

Overview: Experience with SAMPA testing so far

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ALTERA development board

Setup for SAMPA characterization and test of 700 SAMPAs

Inside of socket Pitch 0.65 372 spring loaded pins

PCCA socket version to be used in mass testing

SAMPA

SAMPA test board with socket

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Fab Tests DC measure DC voltages and currents Tests built into SAMPA JTAG test – checks most digital IO Memory test checks all memory cells DFT test checks ~25000 flip flops Pedestals by filters BC2 and BC3 (amplifier faults are giving zero ped.) Data integrity same checks as in final data taking External testpulses pulse every second channel. Bondwire and BGA substrate input. crosstalk Calibration Taking calibration data for each channel ADC test Noise Gain calibration risetime-falltime

Test procedure in final testing

odd-even effect on v2

Problem in the high end

Better in the middle

Worse again at the low end

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ADC test Testpulse arbitrary time relative to sampling clock

Populate whole ADC range Very large number of pulses

Shall be smooth - not like below

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Affected by finite ADC resolution and ADC problem Spread partly due to ADC problem - Hope to be better on v3/v4

Noise test

Will be done with TPC det cap (18 pF) and series resistor (100Ω) in final mass test. Can also choose MuCh parameters

Gain calibration example (one channel)

70 fC signal in 1 TimeBin = 100 ns Γ(4)-fit with fixed τ (170 ns)

Amplitude = Max – Baseline used in later slides

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Testpulser synchronized with sampling clock. Delay adjusted to capture peak max.

Can also be done with Muon amplifier settings

0

10

20 30 40 50

60

70

80 90

100

1000 testpulses per amplitude . Numbers refer to the injected amount of fC.

ADC bit error

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Distribution of max values

Calibration results for each chip and for individual channels

Fit par 1 = slope

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All 32 channels at the same time

Slope parameter all channels, for 198 chips

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Slope parameters for 603 SAMPAS for which the Gain calibration was run

Sigma 0.9% Most within +/- 0.2 i.e. +/-2.2%

Includes some long term variation

Some systematics underneath to take away

Gain calibration: Fit slope

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all channels on ca 700 chips over 3 months

+/- 1%

Have to correct for long term effects +/- 1% within reach after correction

Gain calibration: Slope vs chip number

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pulse

Delay in ns

1 20000

2 23510

3 27020

4 30530

5 34040

6 37550

7 41060

8 44570

9 48080

10 51590

1 event is a pulse train of 10 pulses of same amplitude Triggered by synchronized trigger pulse. 1000 events gives 1000 pulses on each 10ns sample

Steps 10ns longer than multiple of 100ns

Risetime, Falltime

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Can also be done with Muon analog settings

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Γ(4)-fit

Fake 100MHz sampling by phase shift in 10ns steps

High resolution pulse sampling

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Time sweep of pulse train

10MHz sampling, 100 microsecs full sweep Induce opposite charge

IMPORTANT. No manual handling of individual chips Manual tray handling. For SAMPA - full table 756 chips. Reload every 16 hours. 17

Robotic production testing in clean room (ISO7) • automatic mass testing was done for 80000 ALTRO and 80000 PASA • CHIP handling – chip sorting - database procedures will be re-used • New test card and readout

PASA/ALTRO robotic test setup

Robotic testing

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• Use socket PCCA which has all signals pulled out to a connector • Read out with VLDB board • VLDB: GBT +SCA + optics as on FEC backend • Datataking identical to FEC. Should take data after very small FW modifications • PCCA needs no modification (just some passive components to leave out) • Connect PCCA and VLDB with an interface card • Fast signals from VLDB to/from PCCA on mHDMI cables – flexible routing • Slow signals and DC: plug in with board to board connector. • Connect to pin headers on PCCA for DC measurements and programmable

configurations by flat cables. • Protoyping of intermediate card cheap and quick.

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PCCA socket All signals to back contact

VLDB • GBTX + GBT-SCA + Optics • Same as FEC backend • Sends data to T-RORC • Fast signals on mHDMI cables

Intermediate card

• Transfer fast signals GBTx

• ADC for DC measurements

• Configuration from SCA (DC levels for strapping)

• Level translation (a few)

Taking data shall be the same as on FEC Firmware for readout exists Firmware for built-in tests to be done

New readout schematic for robotic testing

Database

Linux DAQ

T-RORC

Comp controlled Function generators Tec. AFG3000 series

ethernet

windows

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vldb

PCCA

vldb vldb vldb

PCCA PCCA PCCA

Setup

Pneumatic movement for fixed forces

Robot arm

PCCA

socket

Lennart Österman

Tested the chip contacting in automatic handling. Works at 80N force (8 Kg weight)

Wagon sliding on ball bearings on 12mm rods (commercial product)

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Positioning guide

Need to know chip position better than 100um

Mechanics

Side view:

Top view:

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Capacity with 4 independent stations (one robot serving) • 5 minutes per chip including movement • 12 chips tested per hour per station • 48 chips in total per hour • 960 chips tested per 20hr day For TPC 20 000 SAMPAS including spares needed Test 30 000 in three lots of 10 000 each Fab plan 2018: Lot 1: 10000 SAMPA to Lund Oct 1 - ship from Lund Oct 29 Lot 2: 10000 SAMPA to Lund Oct 30 - ship from Lund Nov 29 Lot 3: 10000 SAMPA to Lund Nov 30 - ship from Lund Dec 29 This will be doable with margins. 10 days per lot. Pending decision about early start with extra wafers from v3/v4 Hope to run some thousand chips in the spring to settle on acceptance criteria

Planning

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First version (to be re-discussed after v3/v4 performance is available): Likely to have large scale experience (>1000 chips) before final production • Power consumption: nominal ± 20% (will be split up in power domains) • Peaking time: ± 10% • Input Charge to ADC code calibration ± 2% • Noise < 1 LSB for TPC settings • Pedestals < 100 for TPC settings • Crosstalk < 1%

• Built-in tests passed • Data integrity (checked by real datataking procedures) • No dead channels

• To be defined: ADC test acceptance criteria. We have no direct access to the

ADC input.

Acceptance criteria (TPC)

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Some options to consider for SAMPA muon testing

1. Use TPC test as it is but with Muon analog settings. 2. Use your own readout with dual SAMPA (one position socketed) or PCCA. Include Built in tests and DC measurements in your system 3. We make new intermediate card which allows switching between. TPC and Muon DAQ Run DFT and built in tests and DC tests from TPC system. And take data with muon setting. 4. Use your own readout with dual SAMPA (one position socketed) for normal datataking We run DFT and DC tests one day with TPC setup and the next day we run the muon datataking tests tests in your own system. How often to switch we will have to see.

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Backup slides

Effective Yield ≈ 505/694 = 72% Need to order and test substantial surplus

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Score after 700 tested MPW2 SAMPA

judgement # of chips

Fraction comment

Fully OK 252 36%

OK with corrective ref voltage

253 36% Considered good

Dead channel (ped zero) 60 9% Some may be due to ADC problem

Dead channel (no signal) 8 1% Bondwire ?

Memory error 48 7%

DFT failed 48 7%

Sync 9 1% May be readout

Inoperable 16 2% 5 shorted

Not fully digested 6 1%