Marvell - Storage - 88SE9215 Datasheet · 2017-04-17 · 88SE9215 R1.1 One-Lane PCIe 2.0 to...

Doc No. MV-S108451-U0 Rev. D

December 5, 2018

Document Classification: PublicMarvell. Moving Forward Faster

88SE9215 R1.1One-Lane PCIe 2.0 to Four-Port 6 Gbps SATA I/O ControllerDatasheet

88SE9215 R1.1 One-Lane PCIe 2.0 to Four-Port 6 Gbps SATA I/O ControllerDatasheet

This Document And The Information Furnished In This Document Are Provided "As Is" Without Any Warranty. Marvell Expressly Disclaims And Makes No Warranties Or Guarantees, Whether Express, Oral, Implied, Statutory, Arising By Operation Of Law, Or As A Result Of Usage Of Trade, Course Of Dealing, Or Course Of Performance, Including The Implied Warranties Of Merchantability And Fitness For Particular Purpose And Non-infringement.

This document, including any software or firmware included or referenced in this document is owned by Marvell. The information furnished in this document is provided for reference purposes only for use with Marvell products. It is the user's own responsibility to design or build products with the information. Marvell products are not authorized for use as critical components in medical devices, military systems, life or critical support devices, or related systems. Marvell is not liable, in whole or in part, and the user shall indemnify and hold Marvell harmless for any claim, damage, or other liability related to any such use of Marvell products. Marvell and the Marvell logo are registered trademarks of Marvell. For a more complete listing of Marvell trademarks, visit www.marvell.com.

Copyright © 2018. Marvell International Ltd. All rights reserved.

For more information, visit our website at: www.marvell.com

iiCopyright © 2018 Marvell Doc No. MV-S108451-U0 Rev. DDecember 5, 2018 Document Classification: Public

http://www.marvell.com


Ordering Information

iiiCopyright © 2018 Marvell Doc No. MV-S108451-U0 Rev. DDecember 5, 2018 Document Classification: Public

ORDERING INFORMATION

Ordering Part Numbers and Package MarkingsThe following figure shows the ordering part numbering scheme for the 88SE9215 part. For complete ordering information, contact your Marvell FAE or sales representative.Sample Ordering Part Number

The standard ordering part numbers for the respective solutions are indicated in the following table.

The next figure shows a typical Marvell package marking.88SE9215 Package Marking and Pin 1 Location

Note: The above drawing is not drawn to scale. The location of markings is approximate. Add-on marks are not represented. Flip chips vary widely in their markings and flip chip examples are not shown here. For flip chips, the markings may be omitted per customer requirement.

Ordering Part Numbers

Part Number Description

88SE9215A1-NAA2C000 76-pin QFN 9 mm × 9 mm, One-Lane PCIe 2.0 to four-port 6 Gbps SATA Controller.

88SE9215A1-NAA2I000 76-pin Industrial Grade QFN 9 mm × 9 mm, One-Lane PCIe 2.0 to four-port 6 Gbps SATA Controller.

Part Number

Product RevisionCustom Code

Custom Code(optional )

88XXXXX - XX - XXX - C000 - XXXX

Temperature CodeC = CommercialI = Industrial

Environmental Code + = RoHS 0/6–= RoHS 5/61 = RoHS 6/62 = Green)

Package Code3-character

alphabetic code such as BCC, TEH

Custom Code

Extended Part Number

YYWW xx@Country of Origin

Part number, package code, environmental code eXXXXX = Part number AAA = Package codee = Environmental code (+ = RoHS 0/6, no code = RoHS 5/6, 1 = RoHS 6/6, 2 = Green)

Country of origin(contained in the mold ID ormarked as the last line onthe package)

Pin 1 location

Marvell Logo

Lot Number88XXXXX-AAAe

Date code, custom code, assembly plant codeYYWW = Date code (YY = year, WW = Work Week)xx = Custom code or die revision@ = Assembly plant code

88SE9215 R1.1 One-Lane PCIe 2.0 to Four-Port 6 Gbps SATA I/O Controller Datasheet

THIS PAGE LEFT INTENTIONALLY BLANK

ivCopyright © 2018 Marvell Doc No. MV-S108451-U0 Rev. DDecember 5, 2018 Document Classification: Public

Change History

vCopyright © 2018 Marvell Doc No. MV-S108451-U0 Rev. DDecember 5, 2018 Document Classification: Public

CHANGE HISTORY

The following table identifies the document change history for Rev. D.

Document Changes *

* The type of change is categorized as: Parameter, Revision, or Update. A Parameter change is a change to a spec value, a Revision change is one that originates from the chip Revision Notice, and an Update change includes all other document updates.

Location Type Description Date

Global Update Removed “Confidential” from footer and watermark. December 13, 2016

Page 7-3 Update Corrected Temperature settings in 7.2, Recommended Operating Conditions.

November 15, 2018

88SE9215 R1.1 One-Lane PCIe 2.0 to Four-Port 6 Gbps SATA I/O ControllerDatasheet


viCopyright © 2018 Marvell Doc No. MV-S108451-U0 Rev. DDecember 5, 2018 Document Classification: Public

Contents

CONTENTS

1 OVERVIEW ........................................................................................................................................................ 1-1

2 FEATURES ........................................................................................................................................................ 2-12.1 GENERAL .................................................................................................................................................. 2-22.2 PCIE ......................................................................................................................................................... 2-32.3 SATA CONTROLLER .................................................................................................................................. 2-42.4 SPI INTERFACE CONTROLLER .................................................................................................................... 2-52.5 PERIPHERAL INTERFACE CONTROLLER ....................................................................................................... 2-6

3 PACKAGE ......................................................................................................................................................... 3-13.1 PIN DIAGRAM ............................................................................................................................................ 3-23.2 MECHANICAL DIMENSIONS ......................................................................................................................... 3-33.3 SIGNAL DESCRIPTIONS ............................................................................................................................... 3-5

3.3.1 Signal Descriptions Overview ................................................................................................... 3-53.3.2 Pin Type Definitions .................................................................................................................. 3-53.3.3 Signal Descriptions ................................................................................................................... 3-6

4 LAYOUT GUIDELINES ...................................................................................................................................... 4-14.1 LAYOUT GUIDELINES OVERVIEW ................................................................................................................. 4-24.2 BOARD SCHEMATIC EXAMPLE .................................................................................................................... 4-34.3 LAYER STACK-UP ...................................................................................................................................... 4-4

4.3.1 Layer Stack-Up Overview ......................................................................................................... 4-44.3.2 Layer 1–Topside, Parts, Slow and High Speed Signal Routes, and Power Routes .................. 4-44.3.3 Layer 2–Solid Ground Plane ..................................................................................................... 4-44.3.4 Layer 3–Power Plane ................................................................................................................ 4-44.3.5 Layer 4–Bottom Layer, Slow and High-Speed Signal Routes, and Power Routes ................... 4-4

4.4 POWER SUPPLY ........................................................................................................................................ 4-54.4.1 Power Supply Overview ............................................................................................................ 4-54.4.2 VDD Power (1.0V) ..................................................................................................................... 4-54.4.3 Analog Power Supply (1.8V) ..................................................................................................... 4-54.4.4 Bias Current Resistor (RSET) ................................................................................................... 4-6

4.5 PCB TRACE ROUTING ............................................................................................................................... 4-74.6 RECOMMENDED LAYOUT ............................................................................................................................ 4-8

5 ELECTRICAL SPECIFICATIONS ...................................................................................................................... 5-15.1 ABSOLUTE MAXIMUM RATINGS ................................................................................................................... 5-25.2 RECOMMENDED OPERATING CONDITIONS ................................................................................................... 5-35.3 POWER REQUIREMENTS ............................................................................................................................. 5-45.4 DC ELECTRICAL CHARACTERISTICS ............................................................................................................ 5-55.5 THERMAL DATA ......................................................................................................................................... 5-6

viiCopyright © 2018 Marvell Doc No. MV-S108451-U0 Rev. DDecember 5, 2018 Document Classification: Public

88SE9215 One-Lane PCIe 2.0 to Four-Port 6 Gbps SATA I/O ControllerDatasheet


viiiCopyright © 2018 Marvell Doc No. MV-S108451-U0 Rev. DDecember 5, 2018 Document Classification: Public

1-1Copyright © 2018 Marvell Doc No. MV-S108451-U0 Rev. DDecember 5, 2018 Document Classification: Public

Overview

1 OVERVIEW

The 88SE9215 is a four-port, 3 Gbps or 6 Gbps SATA Host Bus Adapter that provides a one-lane PCIe 2.0 interface and SATA controller functions. The 88SE9215 supplies four 6 Gbps SATA ports.

The 88SE9215 supports devices compliant with the Serial ATA International Organization: Serial ATA Revision 3.1 specification. Figure 1-1 shows the system block diagram.Figure 1-1 SE9215 Architecture

PCIe 2.0 x1 EndPoint Controller

(5 Gbps x 1)

Function 0 BAR Interface

Peripheral Interface Controller

(SPI / GPIO)

Internal Bus and Bus Arbiter

Serial ATA 4-port AHCIController

(1.5, 3 or 6 Gbps)


Features

2 FEATURES

This chapter contains the following information:

General PCIe SATA Controller SPI Interface Controller Peripheral Interface Controller


2-2 GeneralCopyright © 2018 Marvell Doc No. MV-S108451-U0 Rev. DDecember 5, 2018 Document Classification: Public

2.1 General 55 nm CMOS process, 1.0V digital core, 1.8V analog, and 3.3V I/O power supplies. Reference clock frequency of 25 MHz, provided by an external clock source or generated by

an external crystal oscillator.

Features

PCIe 2-3Copyright © 2018 Marvell Doc No. MV-S108451-U0 Rev. DDecember 5, 2018 Document Classification: Public

2.2 PCIe PCIe 2.0 endpoint device. Compliant with PCIe 2.0 specifications. Supports communication speed of 2.5 Gbps and 5 Gbps. Supports AHCI programming interface registers for the SATA controller. Supports aggressive power management. Supports error reporting, recovery and correction. Supports Message Signaled Interrupt (MSI).


2-4 SATA ControllerCopyright © 2018 Marvell Doc No. MV-S108451-U0 Rev. DDecember 5, 2018 Document Classification: Public

2.3 SATA Controller Compliant with Serial ATA Specification 3.1. Supports communication speeds of 6 Gbps, 3 Gbps, and 1.5 Gbps. Supports programmable transmitter signal levels. Supports Gen 1i, Gen 1x, Gen 2i, Gen 2m, Gen 2x, and Gen 3i. Supports four SATA ports. Supports AHCI 1.0 programming interface. Supports Native Command Queuing (NCQ). Supports Port Multiplier FIS based switching or command based switching. Supports Partial and Slumber Power Management states. Supports Staggered Spin-up.

Features

SPI Interface Controller 2-5Copyright © 2018 Marvell Doc No. MV-S108451-U0 Rev. DDecember 5, 2018 Document Classification: Public

2.4 SPI Interface Controller A four-pin interface provides read and write access to an external SPI flash or SPI ROM

device. Vendor specific information stored in the external device is read by the controller during the

chip power-up. PCI BootROMs of PCIe function 0 can also be stored in the external SPI device and read

through the Expansion ROM BAR and the SPI interface controller.


2-6 Peripheral Interface ControllerCopyright © 2018 Marvell Doc No. MV-S108451-U0 Rev. DDecember 5, 2018 Document Classification: Public

2.5 Peripheral Interface Controller Eight General Purpose I/O (GPIO) ports. Each of the GPIO pins can be assigned to act as a general input or output pin. Each of the GPIO inputs can be programmed to generate an edge-sensitive or a

level-sensitive maskable interrupt. Each of the GPIO outputs can be programmed for a connected LED to blink at a user-defined

fixed rate. The default rate is 100 ms.


Package

3 PACKAGE


Pin Diagram Mechanical Dimensions Signal Descriptions


3-2 Pin DiagramCopyright © 2018 Marvell Doc No. MV-S108451-U0 Rev. DDecember 5, 2018 Document Classification: Public

3.1 Pin DiagramThe 76-pin QFN pin diagram is illustrated in Figure 3-1.Figure 3-1 SE9215 Pin Diagram

Note: The center area beneath the chip is the Exposed Die Pad (Epad). When designing the PCB, create a solder pad for the Epad and connect the Epad to ground.

SPI_

DO

GPIO7

VDD

TXP_

3VS

SR

XP_2

RXP

_3R

XN_3

TXN_

3

VAA2

_2TX

N_2

GPI

O3

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

RXN

_2

SPI_

CS

SPI_

CLK

VDD

IOS

PI_D

I

VAA2

_3

TXP_

2VSS

RXN_1VAA2_1

RXP_188SE9215

WAKE_NCLKN

VDDPERST_N

TST2

GPIO1

GPIO0TST0

TST5TST4

61626364656667686970717273747576

585960

CLKP

TST6GPIO6

VDD

VDDIOTST3

TST1

GPIO2

TP

VDDN/CTXP_0

N/C

TXN_0

RXN_0RXP_0

TXN_1

VDDTESTMODEGPIO5GPIO4

VDD

VAA2_0

20

383736353433323130292827262524232221

N/C

N/C

VSS

VDD

XTLN

_OSC

40 3957 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41

N/C

VSS

PRXP

0

N/C

ISET

VAA1

AVD

D0

PTXP

0

XTLO

UT

N/C

PTXN

0

PRXN

0

N/C

N/C

TXP_1

Package

Mechanical Dimensions 3-3Copyright © 2018 Marvell Doc No. MV-S108451-U0 Rev. DDecember 5, 2018 Document Classification: Public

3.2 Mechanical DimensionsThe package mechanical drawing is shown in Figure 3-2.Figure 3-2 Package Mechanical Diagram


3-4 Mechanical DimensionsCopyright © 2018 Marvell Doc No. MV-S108451-U0 Rev. DDecember 5, 2018 Document Classification: Public

The package mechanical dimensions are shown in Figure .Figure 3-3 Package Mechanical Dimensions

Package

Signal Descriptions 3-5Copyright © 2018 Marvell Doc No. MV-S108451-U0 Rev. DDecember 5, 2018 Document Classification: Public

3.3 Signal DescriptionsThis section contains the following information:

Signal Descriptions Overview Pin Type Definitions Signal Descriptions

3.3.1 Signal Descriptions OverviewThis section contains the pin types and signal descriptions for the 88SE9215 package.

3.3.2 Pin Type DefinitionsPin type definitions are shown in Table 3-1. Table 3-1 Pin Type Definitions

Pin Type Definition

I/O Input and Output

I Input Only

O Output Only

A Analog

PU Internal Pull-Up when Input

PD Internal Pull-Down when Input

OD Open-Drain Pad

Ground Ground

Power Power


3-6 Signal DescriptionsCopyright © 2018 Marvell Doc No. MV-S108451-U0 Rev. DDecember 5, 2018 Document Classification: Public

3.3.3 Signal DescriptionsThis section outlines the 88SE9215 pin descriptions. All signals ending with the letter N indicate an active-low signal.

Table 3-2 PCIe Interface Signals

Signal Name Signal Number Type Description

PERST_N 61 I, PU PCI Platform Reset.Active low, indicates when the applied power is within the specified tolerance and stable.

WAKE_N 60 O, OD PCI Wake-Up.An open-drain, active low signal that is driven low by a PCIe function to reactivate the PCIe Link hierarchy’s main power rails and reference clocks.+Note: For applications that support a wake-up function, connect this pin to the WAKE# signal of a PCIe card slot or system board. Connect an external pull-up resistor from the PCIe card slot or system board to the 3.3V auxiliary supply. For applications that do not support a wake-up function, keep the WAKE_N pin on the 88SE9215 open.

CLKPCLKN

5859

I, A PCIe Reference Clock of 100 MHz.

PRXP0PRXN0

5554

I, A PCIe differential signals to the controller’s receiver.

PTXP0PTXN0

5251

O, A PCIe differential signals from the controller’s transmitter.

Package


Table 3-3 Serial ATA Interface Signals


TXN_0TXP_0TXN_1TXP_1TXN_2TXP_2TXN_3TXP_3

33342728121367

O, A Serial ATA Transmitter Differential Outputs.

RXN_0RXP_0RXN_1RXP_1RXN_2RXP_2RXN_3RXP_3

3130252410943

I, A Serial ATA Receiver Differential Inputs.

Table 3-4 Reference Signals


ISET 42 I/O, A Reference Current for Crystal Oscillator and PLL.This pin has to be connected to an external 6.04 kΩ 1% resistor to Ground.

XTLOUT 41 O, A Crystal Output.

XTLIN_OSC 40 I, A Reference Clock Input.This signal can be from an oscillator, or connected to a crystal with the XTLOUT pin. The clock frequency must be 25 MHz ± 80 ppm.

Table 3-5 General Purpose I/O Signals


GPIO0GPIO1GPIO2GPIO3GPIO5GPIO4GPIO6GPIO7

6369701821207576

I/O, PU General Purpose I/O.



Table 3-6 SPI Flash Interface Signals


SPI_CLK 17 O SPI Interface Clock.

SPI_DI 15 I, PU Serial Data In.Connect to the serial flash device’s serial data output (DO).

SPI_CS 14 O SPI Interface Chip Select.

SPI_DO 2 O Serial Data Out.Connect to the serial flash device’s serial data input (DI).

Table 3-7 Test Mode Interface Signals


TP 38 I/O, A Analog Test Point for PCIe PHY, SATA PHY, crystal oscillator, and PLL.

TST0 64 I/O Test Pin 0.

TST1 65 I/O Test Pin 1.

TST2 66 I/O Test Pin 2.This pin is reserved for chip test purposes only. Keep floating.





TESTMODE 22 I, PD Test Mode.Enables chip test modes.

Table 3-8 Power and Ground Pins

Signal Name Signal Number Type DescriptionVAA2_0VAA2_1VAA2_2VAA2_3

3226115

Power Analog Power.1.8V analog power supply for SATA PHY.

VAA1 39 Power Analog Power.1.8V analog power for crystal oscillator, reference current generator, and PLL.

Package


AVDD0 53 Power Analog Power.1.8V analog power supply for PCIe PHY.

VDDIO 16, 68 Power I/O Power.3.3V analog power supply for digital I/Os.

VDD 1, 19, 23, 36, 44, 62, 71

Power 1.0V Core Digital Power.

VSS 8, 29, 45, 56 Power Ground.The main ground is the exposed die-pad (ePad) on the bottom side of the package.

Table 3-9 No Connect Signals


N/C 35, 37, 43, 57 N/A No Connect.

Table 3-8 Power and Ground Pins (continued)



Layout Guidelines

4 LAYOUT GUIDELINES

The chapter contains the following information:

Layout Guidelines Overview Board Schematic Example Layer Stack-Up Power Supply PCB Trace Routing Recommended Layout

Refer to Chapter 3, Package, for package information.


4-2 Layout Guidelines OverviewCopyright © 2018 Marvell Doc No. MV-S108451-U0 Rev. DDecember 5, 2018 Document Classification: Public

4.1 Layout Guidelines OverviewThis chapter describes the system recommendations from the Marvell Semiconductor design and application engineers who work with the 88SE9215. This chapter is written for those who are designing schematics and printed circuit boards for an 88SE9215-based system. Whenever possible, the PCB designer should try to follow the suggestions provided in this chapter.Note: The information in this chapter is intended only to provide guidelines, and is not meant to restrict the customer from exercising discretion in implementing board designs. In cases where it is deemed necessary to deviate from the guidelines, Marvell recommends that customers consult with the Marvell FAEs to ensure that the performance of the Marvell product is not compromised.

Layout Guidelines

Board Schematic Example 4-3Copyright © 2018 Marvell Doc No. MV-S108451-U0 Rev. DDecember 5, 2018 Document Classification: Public

4.2 Board Schematic ExampleThe board schematic consists of the major interfaces of the 88SE9215 including SATA and PCIe. Figure 4-1 shows an example of board schematic.Figure 4-1 SE9215 Example Board Schematic

Note: This diagram is for reference only. Contact your Marvell field applications engineer for the latest schematics.

S_TX

P0S0

_TXP

S0_T

XN

S0_R

XP

S_TX

N0

S_R

XN0

S_R

XP0

S0_R

XN

S1_T

XPS1

_TXN

S1_R

XP

S_TX

N1

S_R

XN1

S_R

XP1

S1_R

XNS_

TXN

0

TEST

MO

DE

S_R

XN0

S_R

XP0

S_TX

P1

VDD

_10

VDD

_10

VAA1

PRX_0PPRX_0N

XTLI

VDD_10

PER

ST_N

AVDD0

PTX_0NPTX_0P

S_TX

P0

S_R

XP1

GN

D

VAA2

_0

S_TX

N1

VAA2

_1

GND

S_R

XN1

ISET

GN

D

S_TX

P1

S2_T

XPS2

_TXN

S2_R

XP

S_TX

N2

S_R

XN2

S_R

XP2

S2_R

XN

S_TX

P2

S3_T

XPS3

_TXN

S3_R

XP

S_TX

N3

S_R

XN3

S_R

XP3

S3_R

XN

S_TX

P3

XTLOUT

PTX_

0P

XTLI

PCLK

P

PCLK

N

GPI

O2

GPI

O1

GPI

O4

VDD

_10

VDD

_10

VDD

IO

VDD

IO

PTX_

0N

XTLO

UT

XTLO

UT

SPI_

CLK

SPI_

CS

SPI_

DO

SPI_

DI

GPI

O1

GPI

O2

GPI

O3

GPI

O4

GPIO3

SPI_

CS

SPI_

CLK

SPI_

DO

VDD_10

S_TXN2VAA2_2

S_RXN2

GND

S_TXN3

S_RXN3S_RXP3

VDD_10

S_TXP3

S_TXP2

VAA2_3

VDDIO

SPI_

DI

S_RXP2

HSI

N

PCIE

_AU

X3

PRX_

0P

WAK

E_N

PRX_

0NH

SIP

PCLK

P

PER

ST_N

PCLK

N

PRSN

T#

3V3

1V8

1V8

VCC

IN

1V8

1V8

VAA2

_0

VAA2

_1

VAA2

_2

VAA2

_3

VAA1

AVD

D0

VDD

_10a

VDD

_10

3V3

3V3

3V3

VCC

INVC

CIN

SATA Interface

PCIE Interface

(Contact Marvell for SPI AVL)

LEDs for SATA activity

VDD_10a is 1V power

C631000pF

C631000pF

C58.01uF

C58.01uF

KE

YS3

S-AT

AK

EY

S3S-

ATA

1 2 3 4 5 6 78 9

C73.1uFC73.1uF

C62.01uF

C62.01uF

C6

.01u

FC

6.0

1uF

R8

100R

R8

100R

C281000pF

C281000pF

C16

.01u

FC

16.0

1uF

C57.1uFC57.1uF

ACT_

S1G

reen

ACT_

S1G

reen

R3

NA_

100-

1%R

0402

R3

NA_

100-

1%R

0402

C72.1uFC72.1uF

C292.2uF

C292.2uF

C71.1uFC71.1uF

C2

.01u

FC

2.0

1uF

C382.2uF

C382.2uF

R12

R08

05

0R±1

%R

12

R08

05

0R±1

%

C61.1uFC61.1uF

C5

.01u

FC

5.0

1uF

C15

.01u

FC

15.0

1uF

C562.2uF

C562.2uF

C27.01uF

C27.01uF

C602.2uF

C602.2uF

C411000pF

C411000pF

Y125M

Hz

Y125M

Hz

12

C36.01uF

C36.01uF

FB6

FB04

02

80oh

m_7

00m

aFB

6

FB04

02

80oh

m_7

00m

a

FB4

FB04

02

80oh

m_7

00m

aFB

4

FB04

02

80oh

m_7

00m

a

C30.1uFC30.1uF

88SE

9215

U1

88SE

9215

U1

WAK

E_N

60C

LKN

59C

LKP

58

N/C_3 57VSS_4 56PRXP0 55PRXN0 54AVDD0 53PTXP0 52PTXN0 51N/C_8 50N/C_7 49N/C_6 48N/C_5 47N/C_4 46VSS_3 45VDD_5 44N/C_9 43ISET 42XTLOUT 41

PER

ST_N

61VD

D_6

62G

PIO

063

TST0

64TS

T165

TST2

66TS

T367

VDD

IO_2

68G

PIO

169

GPI

O2

70VD

D_7

71TS

T472

TST5

73TS

T674

GPI

O6

75G

PIO

776

VDD_11 SPI_DO2 RXP_33 RXN_34 VAA2_35 TXN_36 TXP_37 VSS_18 RXP_29 RXN_210 VAA2_211 TXN_212 TXP_213 SPI_CS14 SPI_DI15 VDDIO_116 SPI_CLK17 GPIO318 VDD_219 XTLIN_OSC 40VAA1 39

TP38

N/C

_237

VDD

_436

N/C

_135

GPI

O5

21TE

STM

OD

E22

VDD

_323

RXP

_124

RXN

_125

VAA2

_126

TXN

_127

TXP_

128

VSS_

229

RXP

_030

RXN

_031

VAA2

_032

TXN

_033

TXP_

034

GPI

O4

20EP

AD77

U2

4Mb

SPI F

LASH

SOIC

8-50

-212

W25

X40B

VSSI

G

U2

4Mb

SPI F

LASH

SOIC

8-50

-212

W25

X40B

VSSI

G

CS

1

SO2

WP

3

SI5

SCLK

6H

OLD

7VC

C8

Gnd

4

C14

.01u

FC

14.0

1uF

PCIE 1x

TOP

BOT

gold finger

P1

PCIE 1x

TOP

BOT

gold finger

P1 +12V

_1B1

+12V

_2B2

RSV

D1

B3G

ND

1B4

SMC

LKB5

SMD

ATB6

GN

D2

B73V

3_1

B8TR

STn

B93.

3VAu

xB1

0W

AKE#

B11

RSV

D2

B12

GN

D3

B13

HSO

p(R

X)B1

4H

SOn(

RX)

B15

GN

D4

B16

PRSN

T#2

B17

GN

D5

B18

PRSN

T#1

A1+1

2V_3

A2+1

2V_4

A3G

ND

6A4

TCK

A5TD

IA6

TDO

A7TM

SA8

3V3_

2A9

3V3_

3A1

0PW

RG

DA1

1

GN

D7

A12

REF

CLK

+A1

3R

EFC

LK-

A14

GN

D8

A15

HSI

p(TX

)A1

6H

SIn(

TX)

A17

GN

D9

A18

C252.2uF

C252.2uF

R7

100R

R7

100R

ACT_

S3

Gre

en ACT_

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C04

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R1

R06

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0310

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FB2

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m_7

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00m

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C70.1uFC70.1uF

C9

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C9

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C39.1uFC39.1uF

C47.1uFC47.1uF

C52.1uFC52.1uF

C8

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C342.2uF

C342.2uF

C64

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C64

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C54.01uF

C54.01uF

C371000pF

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ATA

1 2 3 4 5 6 78 9

C31.01uF

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C462.2uF

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C50.01uF

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C40.01uF

C40.01uF

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C48.01uF

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C3

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3.0

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C591000pF

C591000pF

C321000pF

C321000pF

C74.1uFC74.1uF


4-4 Layer Stack-UpCopyright © 2018 Marvell Doc No. MV-S108451-U0 Rev. DDecember 5, 2018 Document Classification: Public

4.3 Layer Stack-UpThis section contains the following information:

Layer Stack-Up Overview Layer 1–Topside, Parts, Slow and High Speed Signal Routes, and Power Routes Layer 2–Solid Ground Plane Layer 3–Power Plane Layer 4–Bottom Layer, Slow and High-Speed Signal Routes, and Power Routes

4.3.1 Layer Stack-Up OverviewThe following layer stack up is recommended:

Layer 1–Topside, Parts, Slow and High Speed Signal Routes, and Power Routes Layer 2–Solid Ground Plane Layer 3–Power Plane Layer 4–Bottom Layer, Slow and High-Speed Signal Routes, and Power Routes

5 mil traces and 5 mil spacing are the recommended minimum requirements.

4.3.2 Layer 1–Topside, Parts, Slow and High Speed Signal Routes, and Power RoutesAll active parts are to be placed on the topside. Some of the differential pairs for SATA and PCIe are routed on the top layer, differential 100 ohm impedance needs to be maintained for those high speed signals.

4.3.3 Layer 2–Solid Ground PlaneA solid ground plane should be located directly below the top layer of the PCB. This layer should be a minimum distance below the top layer in order to reduce the amount of crosstalk and EMI. There should be no cutouts in the ground plane. Use of 1 ounce copper is recommended.

4.3.4 Layer 3–Power PlaneUse solid planes on layer 3 to supply power to the ICs on the PCB. Avoid narrow traces and necks on this plane.

4.3.5 Layer 4–Bottom Layer, Slow and High-Speed Signal Routes, and Power RoutesSome of the differential pairs for SATA and PCIe are routed on the top layer, differential 100Ω impedance needs to be maintained for those high speed signals. The high speed signals have the return current on the third layer, which is the power plane. Make sure there is no cut-out under the signal path.

Layout Guidelines

Power Supply 4-5Copyright © 2018 Marvell Doc No. MV-S108451-U0 Rev. DDecember 5, 2018 Document Classification: Public

4.4 Power SupplyThis section contains the following information:

Power Supply Overview VDD Power (1.0V) Analog Power Supply (1.8V) Bias Current Resistor (RSET)

4.4.1 Power Supply OverviewThe 88SE9215 operates using the following power supplies:

VDD Power (1.0V) for the digital core Analog Power Supply (1.8V)

4.4.2 VDD Power (1.0V)All digital power pins (VDD pins) must be connected directly to a VDD plane in the power layer with short and wide traces to minimize digital power-trace inductances.

Use vias close to the VDD pins to connect to this plane and avoid using the traces on the top layer. Marvell recommends placing capacitors around the three sides of the PCB near VDD pins with the following dimensions:

1 µF (1 capacitor) 0.1 µF (2 capacitors) 2.2 µF (1 ceramic capacitor)

The 2.2 µF ceramic decoupling capacitor is needed to filter the lower frequency power-supply noise.

To reduce system noise, the use of high-frequency surface-mount monolithic ceramic bypass capacitors should be placed as close as possible to the channel VDD pins. At least one decoupling capacitor should be placed on each side of the IC package.

Short and wide copper traces should be used to minimize parasitic inductances. Low-value capacitors (1,000–10,000 pF) are preferable over higher values because they are more effective at higher frequencies.

4.4.3 Analog Power Supply (1.8V)The PCIe analog supply provides power for the PCIe link’s high speed serial signals. To ensure high speed link operation, use a series of bypass capacitors for the supplies. A typical capacitor value combination is 1 µF, 0.1µF, and 2.2 µF.


4-6 Power SupplyCopyright © 2018 Marvell Doc No. MV-S108451-U0 Rev. DDecember 5, 2018 Document Classification: Public

4.4.4 Bias Current Resistor (RSET)Connect a 6.04KΩ (1%) resistor between the ISET pin and the adjacent top ground plane. This resistor should lie as close as possible to the ISET pin.

Layout Guidelines

PCB Trace Routing 4-7Copyright © 2018 Marvell Doc No. MV-S108451-U0 Rev. DDecember 5, 2018 Document Classification: Public

4.5 PCB Trace RoutingThe stack-up parameters for the reference board are shown in Table 4-1. Table 4-1 PCB Board Stack-up Parameters

Layer Layer Description

Copper Weight (oz)

Target Impedance(±10%)

1 Signal 0.5 50

2 GND 1 N/A

3 Power 1 N/A

4 Signal 0.5 50


4-8 Recommended LayoutCopyright © 2018 Marvell Doc No. MV-S108451-U0 Rev. DDecember 5, 2018 Document Classification: Public

4.6 Recommended LayoutSolid ground planes are recommended. However, special care should be taken when routing VAA and VSS pins.

The following general tips describe what should be considered when determining your stack-up and board routing. These tips are not meant to substitute for consulting with a signal-integrity expert or doing your own simulations. Note: Specific numbers or rules-of-thumb are not used here because they might not be applicable in every situation.

Do not split ground planes. Keep good spacing between possible sensitive analog circuitry on your board and the digital signals to sufficiently isolate noise. A solid ground plane is necessary to provide a good return path for routing layers. Try to provide at least one ground plane adjacent to all routing layers (see Figure 4-2).

Keep trace layers as close as possible to the adjacent ground or power planes. This helps minimize crosstalk and improve noise control on the planes.

Figure 4-2 Trace Has At Least One Solid Plane For Return Path

When routing adjacent to only a power plane, do not cross splits. Route traces only over the power plane that supplies both the driver and the load. Otherwise, provide a decoupling capacitor near the trace at the end that is not supplied by the adjacent power plane.

Critical signals should avoid running parallel and close to or directly over a gap.This would change the impedance of the trace.

Separate analog powers onto opposing planes.This helps minimize the coupling area that an analog plane has with an adjacent digital plane.

For dual strip-line routing, traces should only cross at 90 degrees.Avoid more than two routing layers in a row to minimize tandem crosstalk and to better control impedance.

Planes should be evenly distributed in order to minimize warping. Calculating or modeling impedance should be made prior to routing.

This helps ensure that a reasonable trace thickness is used and that the desired board thickness is available. Consult with your board fabricator for accurate impedance.

GND

V2

V1

Layout Guidelines

Recommended Layout 4-9Copyright © 2018 Marvell Doc No. MV-S108451-U0 Rev. DDecember 5, 2018 Document Classification: Public

Allow good separation between fast signals to avoid crosstalk. Crosstalk increases as the parallel traces get longer.

When packages become smaller, route traces over a split power planeSmaller packages force vias to become smaller, thereby reducing board thickness and layer counts, which might create the need to route traces over a split power plane. Some alternatives to provide return path for these signals are listed below. Caution must be used when applying these techniques. Digital traces should not cross over analog planes, and vice-versa. All of these rules must be followed closely to prevent noise contamination problems that might arise due to routing over the wrong plane. By tightly controlling the return path, control noise on the power and ground planes can be controlled. Place a ground layer close enough to the split power plane in order to couple enough to

provide buried capacitance, such as SIG-PWR-GND (see Figure 4-3). Return signals that encounter splits in this situation simply jumps to the ground plane, over the split, and back to the other power plane. Buried capacitance provides the benefit of adding low inductance decoupling to your board. Your fabricator may charge for a special license fee and special materials. To determine the amount of capacitance your planes provide, use the following equation:

Where ER is the dielectric coefficient, L • W represents the area of copper, and H is the separation between planes.

Provide return-path capacitors that connect to both power planes and jumps the split. Place them close to the traces so that there is one capacitor for every four or five traces. The capacitors would then provide the return path (see Figure 4-4).

Allow only static or slow signals on layers where they are adjacent to split planes.

Figure 4-3 shows the ground layer close to the split power plane.Figure 4-3 Close Power and Ground Planes Provide Coupling For Good Return Path

Figure 4-4 shows the thermal ground plane in relation to the return-path capacitor.Figure 4-4 Suggested Thermal Ground Plane On Opposite Side of Chip

C 1.249 10 13–• Er• L• W H⁄•=

V2 PLANE

GND PLANE

V1 PLANEH

V1

V2


Electrical Specifications

5 ELECTRICAL SPECIFICATIONS


Absolute Maximum Ratings Recommended Operating Conditions Power Requirements DC Electrical Characteristics Thermal Data


5-2 Absolute Maximum RatingsCopyright © 2018 Marvell Doc No. MV-S108451-U0 Rev. DDecember 5, 2018 Document Classification: Public

5.1 Absolute Maximum RatingsTable 5-1 defines the absolute maximum ratings for the 88SE9215. Table 5-1 Absolute Maximum Ratings*

* Estimated values are provided until characterization is complete.

Parameter Symbol Minimum Maximum Units

Absolute Analog Power for PCIe PHY AVDD0abs -0.5 1.98 V

Absolute Analog Power for Crystal Oscillator and PLL VAA1abs -0.5 1.98 V

Absolute Analog Power for SATA PHY VAA2_0abs -0.5 1.98 V

Absolute Analog Power for SATA PHY VAA2_1abs -0.5 1.98 V

Absolute Digital Core Power VDDabs -0.5 1.10 V

Absolute Digital I/O Power VDDIOabs -0.5 3.63 V


Recommended Operating Conditions 5-3Copyright © 2018 Marvell Doc No. MV-S108451-U0 Rev. DDecember 5, 2018 Document Classification: Public

5.2 Recommended Operating ConditionsTable 5-2 defines the recommended operating conditions for the 88SE9215. Table 5-2 Recommended Operating Conditions*


Parameter Symbol Minimum Type Maximum Units

Analog Power for PCIe PHY AVDD0op 1.71 1.8 1.89 V

Analog Power for Crystal Oscillator and PLL VAA1op 1.71 1.8 1.89 V

Analog Power for SATA PHY VAA2_0op 1.71 1.8 1.89 V

Analog Power for SATA PHY VAA2_1op 1.71 1.8 1.89 V

Digital Core Power VDDop 0.95 1.0 1.05 V

Digital I/O Power VDDIOop 3.135 3.3 3.465 V

Internal Bias Reference ISETop 5.738 6.04 6.342 KΩ

Ambient Operating Temperature, Commercial

N/A 0 N/A 70 °C

Ambient Operating Temperature, Industrial N/A -40 N/A 85 °C

Junction Operating Temperature, Commercial

N/A 0 N/A 125 °C

Junction Operating Temperature, Industrial N/A -40 N/A 125 °C


5-4 Power RequirementsCopyright © 2018 Marvell Doc No. MV-S108451-U0 Rev. DDecember 5, 2018 Document Classification: Public

5.3 Power RequirementsTable 5-3 defines the power requirements for the 88SE9215. Table 5-3 Power Requirements*


Parameter Symbol Maximum Units

Analog Power for PCIe PHY Transmitter IAVDD0 55 mA

Analog Power for Crystal Oscillator and PLL IVAA1 10 mA

Analog Power for SATA PHY IVAA2_0 70 mA

Analog Power for SATA PHY IVAA2_1 70 mA

Digital Core Power IVDD 1500 mA

Digital I/O Power (3.3V)†

† The digital I/O power supply can be either 3.3V or 1.8V.

IVDDIO 50 mA


DC Electrical Characteristics 5-5Copyright © 2018 Marvell Doc No. MV-S108451-U0 Rev. DDecember 5, 2018 Document Classification: Public

5.4 DC Electrical CharacteristicsTable 5-4 defines the DC electrical characteristics for the 88SE9215. Table 5-4 DC Electrical Characteristics*


Parameter Symbol Test Condition Minimum Maximum Units

Input Low Level Voltage VIL N/A -0.4 0.25 × VDDIO V

Input High Level Voltage VIH N/A 0.8 x VDDIO

5.5 V

Output Low Level Current IOL VPAD = 0.4V 5 N/A mA

Output High Level Current IOH VPAD = VDDIO – 0.4V 5 N/A mA

Pull Up Strength IPU VPAD = 0.5 x VDDIO 10 N/A µA

Pull Down Strength IPD VPAD = 0.5 x VDDIO 10 N/A µA

Input Leakage Current ILK 0 < VPAD < VDDIO N/A 10 µA

Input Capacitance CIN 0 < VPAD < 5.5V N/A 5 pF


5-6 Thermal DataCopyright © 2018 Marvell Doc No. MV-S108451-U0 Rev. DDecember 5, 2018 Document Classification: Public

5.5 Thermal DataIt is recommended to read application note AN-63 Thermal Management for Selected Marvell® Products (Document Number MV-S300281-00) and the ThetaJC, ThetaJA, and Temperature Calculations White Paper, available from Marvell, before designing a system. These documents describe the basic understanding of thermal management of integrated circuits (ICs) and guidelines to ensure optimal operating conditions for Marvell products.

Table 5-5 shows the values for the package thermal parameters for the 76-lead Quad Flat Non-Lead package (QFN 76) mounted on a 4-layer PCB. The simulation was performed according to JEDEC standards.

Note: In addition to the airflow requirement, a heat sink is required to assist the thermal dissipation.

Table 5-5 Thermal Data for 76-pin QFN Package

Parameter DefinitionAirflow Value

0 m/s 1 m/s 2 m/s 3 m/s

θJA Thermal resistance: junction to ambient

25.00 C/W 23.90 C/W 22.80 C/W 22.20 C/W

θJC Thermal resistance: junction to case 10.10 C/W N/A N/A N/A

θJB Thermal resistance: junction to board 14.40 C/W N/A N/A N/A

ΨJB Thermal characterization parameter: junction to bottom surface center of the package.

14.30 C/W 14.20 C/W 14.10 C/W 14.00 C/W

ψJT Thermal characterization parameter: junction to top center

0.20 C/W 0.39 C/W 0.49 C/W 0.57 C/W

Marvell Semiconductor, Inc.5488 Marvell Lane

Santa Clara, CA 95054, USA

Tel: 1.408.222.2500Fax: 1.408.752.9028

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