UW-Madison Computer Sciences Vertical Research Group © 2010

A Unified Model for Timing Speculation: Evaluating the Impact of Technology Scaling, CMOS

Design Style, and Fault Recovery Mechanism

Marc de KruijfShuou Nomura

Karu Sankaralingam

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From Hard to Harder

45nm & beyond90nm

180nm

360nm

720nm

1500um

4000um

10000nm

Hard Harder

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What is the Problem?

Non-ideal transistor scaling Transistor wear-out Process, voltage, and temperature (PVT) variations Errors due to particle interference Noise coupling & crosstalk

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What is the Problem?

DMR

Timing s

peculati

on

RMT

HW checkpoints

TMRECC

Watchdog

DynamicverificationMulti-core

Coherence &

consistency

On-chip netw

ork

Out-of-order

Branchprediction

Performance Toolbox Reliability Toolbox

NEED HIGH-LEVEL ANALYSIS TOOLS

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Our Contribution

Also….

Q. What is the impact of technology scaling? A. Further benefits are small to none.

Q. What is the impact of CMOS design style? A. Very low power designs benefit most.

Q. What is the impact of the fault recovery mechanism?A. Fine-grained recovery is key to high efficiencies.

A model for timing speculation• Unifies hardware + system• Small set of high-level inputs

processordesigner

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Outline

Timing Speculation

Model Overview Hardware Efficiency Model System Recovery Model

Results

Conclusion

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Timing Speculation

…clock

circuit delay

clock period ( = 1/frequency )

Timing failure!variations

OK!

slower clock

detect &recover

…

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Outline

Timing Speculation

Model Overview Hardware Efficiency Model System Recovery Model

Results

Conclusion

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Model Overview

Error rate Error rateError rate

Tim

e

Hardware Efficiency System RecoveryOverall EfficiencyEn

ergy

Ener

gy

Model Inputs1. A hardware path delay distribution2. Effect of variations on path delay as N(μ,σ)3. The time between recovery checkpoints4. The time to restore a checkpoint

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Hardware Efficiency Model#

Path

s

Path delay

Err

or p

rob.

Clock period

Error rate

Ener

gy

Input 1: Path delay distributionInput 2: Path delay variation (σ)

Err

or p

rob.

Clock period

Cloc

k pe

riod

Error prob.

Ener

gy

Error prob.

… …e.g.

frequencyscaling

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System Recovery Model

System Recovery Model Inputs1. The time between recovery checkpoints (cycles)2. The time to restore a checkpoint (restore)

overhead(rate) = failures(rate) x waste(rate) + restore( )

Error rate

Tim

e

(applies to all backward error recovery systems)

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Outline

Timing Speculation

Model Overview Hardware Efficiency Model System Recovery Model

Results

Conclusion

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Results

High Performance CMOSLow Power CMOS

Ultra-low Power CMOS

RazorReunionPaceline

11nm45nm

Is the model useful?What can we learn?

CMOS Design StyleTechnology

NodeRecoverySystem

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Results

Error rate Error rate Error rate

Tim

e

Hardware Efficiency System Recovery Overall Efficiency

Ener

gy

Ener

gy

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Hardware Model Inputs

1. Path delay distribution Application: H.264 decoding Hardware: OpenRISC processor

2. Effect of process variations as N(μ,σ) using ITRS data High Performance CMOS

45nm σ = 0.046μ 11nm σ = 0.051μ

Low Power CMOS 45nm σ = 0.029μ 11nm σ = 0.042μ

Ultra-low Power CMOS 45nm σ = 0.196μ

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Hardware Efficiency

Error rate

Ener

gy

Results forHigh Performance CMOS

EDP Energy = Power x Time

EDP = Power x Time2

Nor

mal

ized

EDP

Error rate

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Recovery Model Inputs

1. The time between recovery checkpoints &2. The time to restore a checkpoint

Razor Latch-level detection + pipeline rollback 1 cycle checkpoint size & 5 cycle recovery cost

Reunion DMR detection + checkpoint 100 cycle checkpoint size & 100 cycle recovery cost

Paceline DMR detection + checkpoint + flush 100 cycle checkpoint size & 1000 cycle recovery cost

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System Recovery

Error rate

Tim

e

Nor

mal

ized

Tim

e

Error rate

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Overall Efficiency

Error rateED

P

1. High Performance CMOS

2. Low Power CMOS

3. Ultra-low Power CMOS

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Nor

mal

ized

EDP

Overall Efficiency

High Performance CMOS

23% PEAK, 8-15% TYPICALError rate

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Overall Efficiency

Low Power CMOS

18% PEAK, 5-10% TYPICAL

Error rate

Nor

mal

ized

EDP

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Nor

mal

ized

EDP

Overall Efficiency

Ultra-low Power CMOS

47% PEAK, 20-30% TYPICALError rate

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Outline

Timing Speculation

Model Overview Hardware Efficiency Model System Recovery Model

Results

Conclusion

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Conclusions A High-level Model

Results Efficiency gains improve only minimally with scaling Ultra-low power (sub-threshold) CMOS benefits most Fine-grained recovery is key

Future Work Incorporate more sources of variation A tool for processor designers?

Under development at http://www.cs.wisc.edu/vertical

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Timing s

peculati

onMulti-core

Coherence &

consistency

On-chip netw

ork

Out-of-order

Branchprediction

Questions?

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?

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Timing Speculation

ManufacturingProcess

Runtime Application

Source of Timing Variation

Speed BinningOnline Timing AnalysisTiming Speculation

Figure adapted from Greskamp et al., Paceline: [...]. In PACT ’07.

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expected # cycles executed upon failure

System Recovery Model

System Recovery Model Inputs1. The time between recovery checkpoints (cycles)2. The time to restore a checkpoint (restore)

expected # failures before success

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Overall Inputs1. Path delay distribution

Application: H.264 decoding Hardware: OpenRISC processor

2. Effect of process variations on path delay as N(μ,σ) using ITRS data High Performance CMOS @45nm σ = 0.046μ Low Power CMOS @45nm σ = 0.029μ Ultra-low Power CMOS @45nm σ = 0.196μ

3. The time between recovery checkpoints &4. The time to restore a checkpoint

Razor – Latch-level detection + pipeline rollback (1 & 5 cycles) Reunion – DMR detection + checkpoint (100 & 100 cycles) Paceline – DMR detection + checkpoint + flush (100 & 1000 cycles)