Manufacturing Process -II

EE141© Digital Integrated Circuits2nd Manufacturing1

ManufacturingManufacturingProcess -IIProcess -II

Dr. Shiyan HuOffice: EERC 518

Adapted and modified from Digital Integrated Circuits: A Design Perspective by Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic.

EE4271EE4271VLSI DesignVLSI Design


ChallengeChallenge

Illumination source

Mask

Objective Lens

Aperture

Wafer

193nm

45nm


Mask v.s. PrintingMask v.s. Printing0.25µ 0.18µ

0.13µ 90-nm 65-nm

Layout

What you design is NOT what you get!


MotivationMotivation Chip design cannot be fabricated

Gap– Lithography technology: 193nm wavelength – VLSI technology: 45nm features

Lithography induced variations– Impact on timing and power

Even for 180nm technology, variations up to 20x in leakage power and 30% in frequency were reported.

Technology nodeTechnology node 130nm130nm 90nm90nm 65nm65nm 45n45nmm

Gate length (nm)Gate length (nm)Tolerable variation Tolerable variation

(nm)(nm)

90905.35.3

53533.753.75

35352.52.5

282822

Wavelength (nm)Wavelength (nm) 248248 193193 193193 193193


Gap: Lithography Tech. v.s. VLSI Tech.Gap: Lithography Tech. v.s. VLSI Tech.

193nm 28nm, tolerable distortion: 2nm

Increasing gap Printability problem (and

thus variations) more severe!


Design RulesDesign Rules


Design RulesDesign Rules

Interface between designer and process engineer

Guidelines for constructing process masks Unit dimension: Minimum line width

scalable design rules: lambda parameter absolute dimensions (micron rules)


Lambda RuleLambda Rule Every distance in layout rules is specified by lambda Given a process, lambda is set to a specific value.

Process technology is defined using minimum line width. 0.25um technology means minimum line width is 0.25um. Lambda=minimum line width/2.

For a 0.25um process, lambda=0.125um In practice, scaling is often not linear. Industry usually uses micron rule and lambda rule is used only for

prediction/estimation of the impact of technology scaling to a design.


Layers in 0.25 Layers in 0.25 m CMOS processm CMOS process


Intra-Layer Design RulesIntra-Layer Design Rules

Metal2 4

3

10

90

Well

Active3

3

Polysilicon2

2

Different PotentialSame Potential

Metal1 3

32

Contactor Via

Select2

or6

2Hole

Rules are used to mitigate fabrication error


Transistor LayoutTransistor Layout

1

2

5

3

Tran

sist

or


Layout EditorLayout Editor


Design Rule CheckerDesign Rule Checker

poly_not_fet to all_diff minimum spacing = 0.14 um.


Some PackagesSome Packages


Wire Bonding (not printed)Wire Bonding (not printed)

Lead Frame

Substrate

Die

Pad

Wire Bonding Bond wire


Imprinted Tape-Automated BondingImprinted Tape-Automated Bonding

(a) Polymer Tape with imprinted

(b) Die attachment using solder bumps.

wiring pattern.

Substrate

Die

Solder BumpFilm + Pattern

Sprockethole

Polymer film

Leadframe

Testpads

Disadvantage: Must place I/O pins at the specific locations (i.e., around the boundary on the die).


Flip-Chip BondingFlip-Chip Bonding

Flip-Chip places connection across the chip rather than around boundary. The bond wire is replaced with solder bump

balls directly placed on the die surface Chip is flipped upside down Carefully align to package Heat to melt solder bump balls

Manufacturing Process -II

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