Madhav Rao September 21 Self-assembled structures for 3D integration Madhav Rao (ECE) The University...

Madhav Rao September 21

Self-assembled structures for 3D integration

Madhav Rao (ECE)

The University of Alabama

Research Professors – Dr. John C Lusth (CS)

Dr. Susan L Burkett (ECE)

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http://www.ua.edu/


Outline

•Motivation

Dr. Gracias Research Group self assembly work in Johns Hopkins University.

•Bridging study to date

Controlling gap size and metal thickness

•Initial Work On chip 3D structures developed in our lab.

•Dip soldering study

Controlling dip time and dip temperature

•Future Work

Self assembled structures for 3D integration

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Introduction

Source: M. Rao, J. C. Lusth, S. L. Burkett, “Self-assembly solder process to form three-dimensional structures on silicon”, J. Vac. Sci. Technol. B, Vol. 27, No. 1, January 2009.

2D patterns Anchored 3D structures

Fig 1: Images showing 3D structures formed from 2D metal patterns

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Earlier work: Dr. Gracias Research Group

Source: Timothy G. Leong, Paul A. Lester, Travis L. Koh, Emma K. Call, and, David H. Gracias, “Surface Tension-Driven Self-Folding Polyhedra”, Langmuir 2007 23 (17), 8747-8751: Supporting information electronic files, ACS Copyrights.

Aqueo

us H

CL solu

tion

Self assembled structure

Self Assembly movie

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Source: Timothy G. Leong,, Paul A. Lester, Travis L. Koh, Emma K. Call, and, David H. Gracias, “Surface Tension-Driven Self-Folding Polyhedra”, Langmuir 2007 23 (17), 8747-8751: Supporting information electronic files, ACS Copyrights.

Snapshots of the video

Free floating 3D structures

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Principle of Surface Tension: Solder Self Assembly

•Surface tension principles

•Surface area minimization drives the assembly process.

Fig 2: Schematic representation of solder-driven self assembly: before solder reflow.Fig 2: Schematic representation of solder-driven self assembly: after solder reflow.

Image redrawn from: K. Harsh, Y.C. Lee, “Modelling for solder self-assembled MEMS, in: Proceedings of the SPIE”, San Jose, CA, 24–30 January 1998, pp. 177–184.

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Initial work: Process flow

Conventional metal patterning and dip soldering process

Fig 3: Process flow diagram.

SiO2 etched windowChromium adhesive layer depositionGold seed layer deposition

Develop ResistSpin Resist2.5 µm Nickel electroplating

2 µm Copper electroplatingResist strip; Seed layer and adhesive layer etching

Resist around patterned structures

Dip soldering at 65 ºCResist and sacrificial layer removalAuto folded structures, after solder reflow


3-D micro-scale Polyhedron

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Initial work: Self assembly solder process to form 3D structures

Cube

Square Pyramid Truncated Pyramid

Pyramid

Truncated Square Pyramid

Fig 4: Self Assembled 3D shapes


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Fig 5: Images showing structures: after Ni–Cu electroplating (column 1), after Cr–Au etch (column 2), after solder reflow (column 3), and representative failures (column 4)


Focusing on failures

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Maximum yield: 50 %

Fig 6: Yield as a function of polyhedron type.

Solder Self Assembled Polyhedra Yield


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Motivation

Can we control the solder deposition process to improve the yield ?

Thickness

Roughness

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Dip soldering process

Dip Temperatur

e

Flux Temperatur

e

Solder alloys

Blanket samples:100 nm thick Cu on 1cm2

SiO2.

Patterned samples:90 µm to 800 µm wide, 400 µm long and 100 nm thick Cu patterns

on SiO2 substrate.

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Solder alloys

Trade names

StoichiometryM.P. in C⁰

Internal Designation

LMA117 44.7Bi-22.6Pb-8.3Sn-5.3Cd-19.1In 47 SA47

LOW203 52.5Bi-32Pb-15.5Sn 95 SA95

LMA281 58Bi-42Sn 138 SA138

INDALLOY241 95.5Sn-3.8Ag-0.7Cu 217 SA217

Table 1: Different solders used

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Solder roughness and thickness measurement

•Roughness

Solder deposited samples were scanned by Dektak Profilometer .

Sample Type Scan Length Scan samplesNo. of readings on each sample Replicates

Blanket samples 2 mm 1000 3 7Patterned samples 100 µm 1000 3 7

x : mean

y-x : deviation from mean

L : Total scan points (1000)

Table 2: Profilometer parameters used.

14/50Source: R. A. Sprague, Applied Optics 11, 2811 (1972).

•Thickness

Viewing vertical cross sections in Scanning Electron Microscope (SEM)


Blanket samples: Low Dipping temperature roughness data

Fig 8: Roughness of dip-soldering at low dipping temperatures of solder alloys

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Blanket samples: High Dipping temperature roughness data

Fig 9: Roughness of dip-soldering at high dipping temperatures of solder alloys with flux maintained at room temperature

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Fig 10: Thickness of dip-soldering at low dipping temperatures of solder alloys

Blanket samples: Low dipping temperature thickness data

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Blanket samples: High dipping temperature thickness data

Fig 11: Thickness of dip-soldering at high dipping temperatures of solder alloys with flux maintained at room temperature

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Interfacial structure formed on Cu thin film due to SA217 soldering shows two layers of intermetallic compounds such as Cu3Sn and Cu6Sn5 at high temperatures[1,2].

Cu6Sn5 grows into a solder and forms a structure known as scallop morphology [1,2].

Source[1] I. Dutta, B. S. Majumdar, D. Pan, W. S. Horton, W. Wright and Z. X. Wang. Development of a novel adaptive lead-free solder containing reinforcements displaying the shape-memory effect. J Electron Mater 33(4), pp. 258-70. 2004.[2] I. Dutta, D. Pan, S. Ma, B. S. Majumdar and S. Harris. Role of shape-memory alloy reinforcements on strain evolution in lead-free solder joints. J Electron Mater 35(10), pp. 1902-13. 2006.

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Fig 11: Thickness of dip-soldering at high dipping temperatures of solder alloys with flux maintained at room temperature

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Blanket samples: Experimental analysis

Trend of decreased roughness and thickness is observed as dip-temperature increases. Better uniformity at higher temperature is achieved except for SA217 alloy.

At the higher dipping temperatures, the highest melting point solder results in a significantly thicker layer than the other solders.

Low melting point alloy shows less variation in thickness and roughness. This suggests better uniformity when using low melting-point alloy.

Preheating flux improves uniformity for temperatures only near the melting-point of alloy.

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Pattern designations

Linkers

Dividers

Bars

Source: M. Rao, J. C. Lusth, S. L. Burkett, “Analysis of a dip-solder process for self assembly”, J. Vac. Sci. Technol. B, Vol. 29, No. 4, August, 2011, available online.

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Processing Conditions

Solders Dip Time

Dip Temperature(Relative to

M.P)

Pattern NamesAverage

Yield in %

Standard Error in

%

SA47 90 seconds 50 C

Bars 89.37 4.530Linkers 90.09 6.787

Dividers 97.16 0.565

SA95 2 seconds 50 C

Bars 98.79 0.909Linkers 91.59 0.476


SA138 2 seconds 40 C

Bars 85.95 3.188Linkers 89.84 5.714


Dip soldering process for three different solder alloys

Table 3: Dip soldering process and wetting yield for copper metal patterns


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Wetting yield: Analysis

Blanket samples did not require significant dipping time.

We suspect: •The lowest melting point alloy needs to overcome the resistance provided by the high density of non-wetting regions around the metal pads.

•The higher melting point alloy provided the necessary thermal energy to wet the patterns.

•The adhesion strength of solder on Cu thin film depends on Sn content [3].

SA47 required 90 seconds of dip-time for complete coverage.

[3] Z. Mei, F. Hua, J. Glazer and C. C. Key. Low temperature soldering. Presented at Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium. 1997, Available: http://dx.doi.org/10.1109/IEMT.1997.626966.

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Fig 12: Thickness of pattern dip-soldering

Thickness measurement of solder alloys on patterned samples


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Roughness measurement of solder alloys on patterned samples

Fig 13: Roughness of pattern dip-soldering


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Fig 14: Improvement in solder folding yield due to change in process.

Analysis of dip-soldering process

Improved Yield

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Parameters Initial Work Refined Process

Solder Alloy Used SA47 SA47

Dip Temperature 65°C 97°C

Dip Time 5 seconds 90 seconds

Metal Stack Cr-Au-Ni-Cu Ti-Cu

Sacrificial Layer SiO2 type Plasma Enhanced

Chemical Vapor oxideElectron beam

evaporated oxide

Table 4: Processing parameters used in different SBSA* fabrication procedures.

*Keyword: SBSA Solder based self assembly

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Solder Bridging studies

Dip soldering

Bridging

Folding

Fig 15: Illustration showing different stages in SBSA process.

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Can we control the solder bridging process to improve the folding yield ?

Metal Thickness

Gap Size

Solder Bridging variables

Solder Coverage

Fig 16: Schematic showing Gap size between the metal entities and Metal thickness of copper metal to be soldered.

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Solder Coverage: Types of Soldering

Fig 17: Illustration showing different types of soldering. a) Face soldering and b) Edge soldering.

a) Face soldering b) Edge soldering

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Bridging yield: Face soldering

Fig 18: Face solder bridging yield of 2D template of a) Truncated Square Pyramid and b) Box, by varying gap-size and metal thickness.

a) b)

4.9 µm thick.4.9 µm thick.

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Fig 19: a) SEM image and b) bridging yield varying gap-size of 2D template of Edge soldered box.

a) b)

Bridging yield: Edge soldering of Box

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Face soldering: Folding yield of various 3D structures

Fig 20: Face soldering yield of various 3D structures


Edge soldering: Folding yield of various 3D structures

Fig 21: Edge soldering yield of various 3D structures


Folding yield due to different soldering types

Fig 22: Folding yield due to different types of soldering using 7.5 µm gap size between metal faces.


Analysis on bridging to date

Increased metal thickness influences bridging and folding yield.

We suspect: High Face area deters the success of folding.

Low gap size favors bridging and folding yield.

Higher hinge (solder) volume is required for successful folding.

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Wet Grinding

Observe solder nature inside the 3D structures.

•Bench Top Struers DAP-V Single platen laboratory polisher / grinder

•Platen speed used: 300 rpm

•Silicon carbide paper mounted on plate.

•Water lubricant is used while grinding.

Fig 23: Image captured from Struers website, showing the bench top grinding tool [4].

Source: http://www.struers.com/

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Grinding on 3D structures

Fig 24: Cross sectional SEM images due to different types of soldering.

a) Face soldered b) Edge soldered

Solde

r bum

p

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Dr. Burkett’s and AFRL vision: 3D integration circuit layout

Image redrawn from: Y. Liu, Development of 3D VLSI integration technology using copper-plated through silicon vias, copper post assembly, and fluid cooling. PhD thesis, University of Arkansas, United States, 2009.

Tin layerFig 25: Conceptual schematic of assembled system.

Keyword: TSV Through Silicon Via

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Yangs Work: 3D integration using Copper Posts

Fig 26: SEM image of Compliant Copper posts, captured from [5].

[5] Image captured from: Y. Liu, Development of 3D VLSI integration technology using copper-plated through silicon vias, copper post assembly, and fluid cooling. PhD thesis, University of Arkansas, United States, 2009.

Copper posts arrays

•Fixed dimensions: 100 µm tall, 50 µm in diameter

•Needs additional tin layer

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3D integration circuit layout

Fig 27: Conceptual schematic of assembled system using SBSA posts.

Keyword: TSV Through Silicon Via

Image redrawn using SBSA structures from: Y. Liu, Development of 3D VLSI integration technology using copper-plated through silicon vias, copper post assembly, and fluid cooling. PhD thesis, University of Arkansas, United States, 2009.

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Future experiments: Interconnection study

Fig 28: Illustration showing two SBSA structures interconnected via buried conducting channel.

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Future experiments: Challenges in Interconnection study

Dielectric and sacrificial layer dilemma.

Compatibility question on overall SBSA process flow.

Continuity testing between two or more SBSA posts.

Mask design for the work.

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Future experiments: Bridging and Folding studies

Fig 29: CAD design for future work: top to bottom indicates study on no. of faces, face-length and solder-coverage respectively.

Face length

Solder coverage

No of Faces

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Conclusions

•Prototype SBSA were fabricated.

•Solder wetting study: roughness and thickness was completed.

•Solder bridging studies: certain parameters were studied.

To be completed:

•Solder bridging study

•SBSA posts with Simulated TSV.

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Journal Articles

• M. Rao, J. C. Lusth, and S. L. Burkett, Analysis of a dip-solder process for self assembly, J. Vac. Sci. Technol. B 29(4), pp.042003-042003-9, 2011, available online.

• M. Rao, J. C. Lusth, and S. L. Burkett, Self-assembly solder process to form three dimensional structures, J. Vac. Sci. Technol. B 27(1), pp.76-80, 2009.

• M. Rao, J. C. Lusth, and S. L. Burkett, A study of solder bridging for the purpose of assembling three dimensional structures (in preparation), to be submitted to J. Vac. Sci. Technol. B.

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Conference proceedings and presentations•M. Rao, J. C. Lusth, and S. L. Burkett, Analysis of a dip-solder process for self assembly, 57th Symposium of the American Vacuum Society on October 21, 2010.

•M. Rao, B. Ajilore, M. Westberry, A. Gilbert, S. Troy, J. Headley, and K. Ricks, A system engineering approach to develop a lunar based robot, NASA, Kennedy space centre, Lunar regolith excavation challenge, May 25-28, 2010.

•M. Rao, J. C. Lusth, and S. L. Burkett, Towards the formation of millimeter wave antenna using a self assembly process, MINT Research Review, UA, July 2009.

•H. Taylor, M. Rao, and S. L. Burkett, Terahertz Antenna Simulation, in Undergraduate Research Conference, UA, April 2009.

•M. Rao, J. C. Lusth, and S. L. Burkett, Towards the formation of Terahertz antenna using solder self assembly method, Graduate Research Conference, UA, March 2009.

•M. Rao, J. C. Lusth, S. L. Burkett, and Y. K. Hong, Magnetic dot polarity switching via current generated magnetic fields, AVS Poster session, October 2008.

•M. Rao, J. C. Lusth, and S. L. Burkett, Magnetic dot polarity switching via current generated magnetic fields, MINT Research review and workshop, UA, October 2008.

•M. Rao, J. C. Lusth, and S. L. Burkett, Towards the setting of logical inputs in a magnetic edge driven computational device, MINT Research Seminar, UA, January 2008.

•M. Rao, J. C. Lusth, S. L. Burkett, and J. Shultz, Logic gates using Magnetic Dots, in the 14th Semiconducting and Insulating Materials Conference, UARK, June 2007.

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Acknowledgments

•College of Engineering, UA

•CAF facilities, UA.

•Research was sponsored by the Army Research Laboratory and was accomplished under Cooperative Agreement Number W911NF-10-2-0093.

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Other major references

•A. Kamto, Y. Liu, L. Schaper, and S. L. Burkett. Reliability study of through-silicon via (tsv) copper filled interconnects. Thin solid films, 518(5), 2009.

•D. H. Gracias, V. Kavthekar, J. C. Love, K. E. Paul, and G. M. Whitesides. Fabrication of micrometer-scale, patterned polyhedra by self-assembly. Advanced Materials, 14(3), 2002.

Questions, Comments and Suggestions !!



Difference: Heating flux and flux at room temperature for blanket samples

Fig 7: Roughness of dip-soldering at low dipping temperatures of SA95 solder alloy


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Miscellaneous


Face soldering: Folding yield of various 3D structures

Fig 20: Face soldering yield of various 3D structures

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Edge soldering: Folding yield of various 3D structures

Fig 21: Edge soldering yield of various 3D structures

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Folding yield due to different soldering types

Fig 22: Folding yield due to different types of soldering using 7.5 µm gap size between metal faces.

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Pattern Types Total entities for measuring yieldBar 12

Linkers 90Dividers 88

Table 4: No of entities used in finding wetting yield for different pattern types.

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2D precursors of Polyhedra

DimensionsBase

length (µm)

Side Length

(µm)

Linear length (µm)

FaceArea(µm2)

Angle (in °)

Truncated Square Pyramid

300 173.2 150 32000 60

Square Pyramid 300 346.4 300 45000 60Pyramid 300 300 259.8 39000 60

Truncated Pyramid 300 173.2 150 32000 60Box 300 300 300 90000 90

Spiral 300 720 705 105800 78Closed Box 300 300 300 90000 90

Inverted Square Pyramid 300 346.4 300 142000 120

Table 5: Dimensions of 2D precursors of different polyhedra attempted.

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Solder alloy

Roughness of solder deposited at room

temperature Flux at dipping Temperature of 50C

Roughness of solder deposited using heated

Flux at dipping Temperature of 10C

SA47 1.04173 2.22595

SA95 1.17765 2.86413

SA138 4.50911 7.08632

SA217 1.15816 6.21877

Solder alloy

Thickness of solder deposited at room

temperature Flux at dipping Temperature of 50C

Thickness of solder deposited using heated

Flux at dipping Temperature of 10C

SA47 8.61713 9.95467

SA95 21.06667 284.15

SA138 46.228 605.16667

SA217 177.42067 931.9

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Fig: Wetting yield vs number of dips for three solder alloys.


Fig: Wetting degradation for the number of dips in the flux for copper patterns


a) Successful solder coating on copper patterns b) Failure of solder coating on copper patterns


Stylus Profilometer

Contact mode, stylus running along the sample generates analog signal, via inertial force due to stylus vertical movement. Analog signal is then converted to Digital and printed in the screen.

Image captured from: Beckman institute of the California institute of Technology

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E beam evaporator

This is a typical physical vapor deposition (PVD) process that is also performed in a vacuum chamber. A high dc voltage is applied to a tungsten filament that causes electrons to be discharged. The stream of electrons emitted excites the targeted solid and turns it into vapor, which travels to the substrate. As they reach the surface, they condense and form a thin film coating.

Image captured from: http://wwwold.ece.utep.edu/research/webedl/cdte/Fabrication/index.htm

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Closed box Inverted square pyramid Square pyramid

Truncated square pyramid Truncated pyramid Regular Pyramid

Spiral Box

Madhav Rao September 21 Self-assembled structures for 3D integration Madhav Rao (ECE) The University...

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