M-TECH 4th SEM PRESENTATION
-
Upload
subhajit-shaw -
Category
Documents
-
view
194 -
download
4
Transcript of M-TECH 4th SEM PRESENTATION
Slide 1
A presentation on Design of OPAMP Based R-2R Ladder Type 4-bit Digital to Analog Converter (DAC) Using 90nm CMOS Technology
Submitted by Under the guidance of Subhajit Shaw Mr. Soumen Pal
M.TECH in Micro Electronics & VLSI Designs
NARULA INSTITUTE OF TECHNOLOGY
UNIVERSITY Roll No: 12710414002.
UNIVERSITY Registration No: 141270410002 of 2014-2015.
113/06/2016Narula Institute of Technology
113/06/2016
ContentsINTRODUCTION
TWO STAGE CMOS OP-AMP
GIVEN SPECIFICATIONS OF OP-AMP
DESIGN PARAMETERS OF OP-AMPSPICE CIRCUIT DIAGRAM OF CMOS OP-AMP(Using T-SPICE Tool)SIMULATED RESULTS OF CMOS OP-AMPR-2R LADDER DACSPECIFICATIONS OF R-2R LADDER DACSPICE CIRCUIT DIAGRAM OF R-2R LADDER DAC (Using T-SPICE Tool)SIMULATED RESULTS OF R-2R LADDER DAC
CONCLUSION
FURTHER ENHANCEMENT
REFFERENCES
213/06/2016Narula Institute of Technology
213/06/2016
IntroductionHigh resolution digital to analog converters (DACs) are highly demanded in todays wireless communication applications.The basic theory of the R-2R ladder network is that current flowing through any input resistor (2R) encounters two possible paths at the far end.The total resistances of both paths are the same (also 2R), so the incoming current splits equally along both paths. The R-2R resistor ladder network directly converts a parallel digital symbol/word into an analog voltage.The goal of this thesis is to design the R-2R Ladder type 4-bit digital to analog converter (DAC) using 90nm CMOS technology which is based on two stage CMOS Op-Amp. 13/06/20163Narula Institute of Technology
Two Stage CMOS Op-AmpThe two stage CMOS Op-amp is widely used because of its simple structure ,robustness and very high Gain.Current mirror are used extensively in CMOS Op-amp circuits both as active load elements and biasing circuits to get a high AC voltage gain.Designing of an Op-amp requires some predefined electrical specifications such as gain ,band width, slew rate, input common mode range and maximum output swing .Op-amp are designed to be operated with negative feedback connection to ensure the stability of the system.The basic structure of two stage CMOS op-amp is shown in the following diagram Which includes differential gain stage(First stage), output stage(Second stage), compensation circuit and biasing circuit.
413/06/2016Narula Institute of Technology
13/06/20164
Basic circuit diagram of two stage op-amp
513/06/2016Narula Institute of Technology
513/06/2016
Given design specifications
Electrical ParametersExpected valuesSupply voltage1VLoad Capacitance1 pFUnity gain frequency100MHzSlew rate10 volt/secInput Common mode range0.4voltOutput swing0.9 volt
613/06/2016Narula Institute of Technology
Design procedure of two stage op-amp
713/06/2016Narula Institute of Technology
Design procedure of two stage op-amp contd
813/06/2016Narula Institute of Technology
Design parameters of op-ampParameters Value Unit Cc 200fF CL1pF(W/L)1,29500/100 nm/ nm(W/L)3,42170/100 nm/ nm(W/L)5,8120/100 nm / nm(W/L)621400/100 nm/ nm(W/L)7480/100 nm / nm(W/L)9120/100nm/ nm
913/06/2016Narula Institute of Technology
Circuit diagram of two stage op-amp(Using T-SPICE Tool)
1013/06/2016Narula Institute of Technology
DC response of designed op-amp in non inverting mode
1113/06/2016Narula Institute of Technology
Transient response in non inverting mode
V(IN)
1213/06/2016Narula Institute of Technology
Transient response in non inverting mode
V(OUT)
1313/06/2016Narula Institute of Technology
AC response[Magnitude vs Frequency]
1413/06/2016Narula Institute of Technology
AC response[Phase vs Frequency]
1513/06/2016Narula Institute of Technology
What is a DAC?
DAC
100101
A digital to analog converter (DAC) is a device that converts digital numbers (binary) into an analog voltage or current output.
1613/06/2016Narula Institute of Technology
What is a DAC?Each sample is converted from binary to analog, between 0 and Vref for Unipolar, or Vref and Vref for Bipolar
101110011010011110000110010101000011001000010000
Digital Input SignalAnalog Output Signal
1713/06/2016Narula Institute of Technology
R-2R Ladder D/A Converter
The 4-bit R-2R ladder type DAC is the most popular DAC.It uses a ladder network containing series-parallel combinations of values R and 2R. It is easily scalable to any desired number of bits.Its uses only two values of resistors which make for easy and accurate fabrication and integration.Output impedance is equal to R, regardless of the number of bits, simplifying filtering and further analog signal processing circuit design.
13/06/201618Narula Institute of Technology
R-2R Ladder D/A Converter
04 bit converter000Each bit corresponds to a switch:
If the bit is high, the corresponding switch is connected to the inverting input of the op-amp.
If the bit is low, the corresponding switch is connected to ground.
Requires only two precision resistance value (R and 2R)1913/06/2016Narula Institute of Technology
R-2R Ladder Example
Convert 0001 to analog
2013/06/2016Narula Institute of Technology
R-2R Ladder ExampleConvert 0001 to analog
R2R
2113/06/2016Narula Institute of Technology
R-2R DAC SummaryConversion results for each bit
Digital bitAnalog Conversion
0001001001001000
for
Conversion equation for N-bit DAC
2213/06/2016Narula Institute of Technology
AdvantagesOnly two resistor valuesDoes not need as precision resistors as Binary weighted DACsCheap & Easy to manufactureFaster response time
DisadvantagesSlower conversion rate More confusing analysisR-2R DAC Summary2313/06/2016Narula Institute of Technology
23
13/06/2016
Specification of DACResolutionSpeedSettling timeLinearityReference voltage
2413/06/2016Narula Institute of Technology
Specification - Resolution25Resolution of a DAC is the change in output voltage for a change in the least significant bit (LSB) of the digital input.Resolution is specified in bits.Most DACs have a resolution of 8 to 16 bits
Example: A DAC with 10 bits has a resolution of
Higher resolution (more bits) = smoother output.
13/06/2016Narula Institute of Technology
Also called the conversion rate or sampling rate - rate at which the register value is updatedRate of conversion of a single digital input to its analog equivalentConversion Rate depends onclock speed of input signalsettling time of converterWhen the input changes rapidly, the DAC conversion speed must be high. Specification - Speed2613/06/2016Narula Institute of Technology
26
13/06/2016
The time required for the input signal voltage to settle to the expected output voltage (within +/- of VLSB).Ideally, an instantaneous change in analog voltage would occur when a new binary word enters into DACFast converters reduce slew time, but usually result in longer ring time. Specification Settling Time
tdelaytslewtring
2713/06/2016Narula Institute of Technology
27
13/06/2016
Specification LinearityLinearity(Ideal Case)
Digital InputPerfect Agreement Desired/Approximate OutputAnalog Output VoltageNON-Linearity(Real World)
Analog Output VoltageDigital Input
Desired OutputMiss-alignment
Approximate outputThe difference between the desired analog output and the actual output over the full range of expected values.Ideally, a DAC should produce a linear relationship between a digital input and the analog output, this is not always the case.2813/06/2016Narula Institute of Technology
28
13/06/2016
A specified voltage used to determine how each digital input will be assigned to each voltage division.Types:Non-multiplier DAC: Vref is fixed (specified by the manufacturer)Multiplier DAC: Vref is provided via an external sourceSpecification Reference VoltageFull Scale VoltageDefined as the output when digital input is all 1s.
2913/06/2016Narula Institute of Technology
29
13/06/2016
Circuit diagram of R-2R Ladder D/A Converter(Using T-SPICE Tool)
3013/06/2016Narula Institute of Technology
Output Waveform of D /A Converter
3113/06/2016Narula Institute of Technology
Comparison between Expected Output & Simulated OutputTable 1:- Performance summary
Sl.No.Input Pulse(Bit Value)Ideal Output(mV)Simulated Output(mV)100000.00.020001062.555.8030010125.0112.7940011187.5167.2450100250.0242.4460101312.5294.7970110375.0366.6880111437.5419.07
3213/06/2016Narula Institute of Technology
Comparison between Expected Output and Simulated OutputSl.No.Input Pulse(Bit Value)Ideal Output(mV)Simulated Output(mV)91000500.0489.16101001562.5547.73111010625.0602.18121011687.5672.34131100750.0730.66141101812.5770.87151110875.0802.23161111937.5821.78
3313/06/2016Narula Institute of Technology
Comparison between Expected Output and Simulated OutputTable 2:-Deviation among successive outputs
Sl.No.Expected Result(mV)Simulated Output(mV)162.556.99262.554.45362.575.20462.552.35562.571.89662.552.99762.569.49
3413/06/2016Narula Institute of Technology
Comparison between Expected Output and Simulated OutputSl.No.Expected Result(mV)Simulated Output(mV)862.558.57962.554.451062.570.161162.558.321262.540.211362.531.361462.519.55
3513/06/2016Narula Institute of Technology
Conclusion
In this work, a two stage op-amp has been designed using 90nm CMOS technology and a 4-bit R-2R ladder type digital to analog converter is also realised using designed Op-Amp. The simulation results confirm that the design procedure is suitable for op-amp based DAC design in 90nm CMOS technology. The designed DAC is simulated using TANNER Tool using 90nm CMOS technology. The simulation results shows that the deviations among successive outputs become more non-linear for higher order digital input bits as depicted in Table 2.
3613/06/2016Narula Institute of Technology
Future plan In this work 90nm CMOS technology has been used. Further reduction in MOSFET channel length can be done to ensure more integration. The design of DAC can be enhanced further, considering the specifications like resolution, offset error, Differential Non-Linearity (DNL) and Integral Non-Linearity (INL). In Communication System and signal processing purpose, A/D converter and D/A converter are inseparably used as a front end and rare end blocks respectively. The designed D/A converter can also be utilised to design A/D converter.
3713/06/2016Narula Institute of Technology
ReferencesPhillip E. Allen and Douglas R. Holberg, CMOS AnalogCircuit Design. Second Edition. Prentice-Hall, 2002.D. Johns, and K. Martin, Analog integrated circuit design," John Wiley & Sons, 1997,ISBN: 0-471-14448-7.Fateh Moulahcene, Nour-Eddine Bouguechal, Imad Benacer and Saleh Hanfoug, Design of CMOS Two-stage Operational Amplifier for ECG Monitoring System Using 90nm Technology, International Journal of Bio-Science and Bio-Technology Vol.6, No.5 (2014), pp.55-66.J. Huynh, B. Ngo, M. Pham, and L. He, Design of a 10 Bit TSMC 0.25m CMOS Digital to Analog Converter, 2005 IEEE, [email protected]. Baker, H. Li, and D. Boyce, CMOS - circuit design, layout, and simulation," IEEE Press, 1998, ISBN 0-7803-3416-7.
3813/06/2016Narula Institute of Technology
Amana Yadav , Design of Two-Stage CMOS Op-Amp and Analyze the Effect of Scaling, Vol. 2, Issue 5, September- October 2012, pp.647-654. Basanta Bhowmik, Manisha Pattanaik, Pankaj Srivastava, A Low Power Low Noise Two Stage CMOS Operational Amplifier for Biopotential Signal Acquisition System, ISSN 2250-2459, ISO 9001:2008 Certified Journal, Volume 3, Issue 4, April 2013, Website: www.ijetae.com.A Sowjanya , Implementation of 4-bit R-2R DAC on CADENCE Tools, ISSN: 2321-9939, Volume 4, Issue 1, IJEDR 2016.Ankit Upadhyay, Rajanikant M. Soni , 3-bit R-2R Digital to Analog Converter with Better INL & DNL , IJEAT Journal ,ISSN: 2249 8958, Volume-2, Issue-3, February 2013.Benjamin Jankunas , Design and Calibration of a 12- Bit Current-Steering Dac Using Data-Interleaving , Approved September 2014 by the Graduate Supervisory Cmmittee.References3913/06/2016Narula Institute of Technology
worlds fastest Digital to Analog Converter (DAC) from Tektronix Component Solutions.https://www.google.co.in/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&cad=rja&uact=8&ved=0ahUKEwjVlPOWxd7MAhWLQY8KHWT6A1oQFggcMAA&url=http%3A%2F%2Fume.gatech.edu%2Fmechatronics_course%2FDAC_S06.ppt&usg=AFQjCNFshvpTBjo_2PpiDda4yBOR7-fW9g&bvm=bv.122129774,d.c2IB. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill Higher Education, 2002 Mr. Soumen Pal, Ms. Pinky Ghosh, Design & simulation of two stage low power cmos op-amp in nm range,ICCACCS, pp-425-432, Springer, 2014.Etienne SICARD Professor, INSA-Dgei,Introducing 90 nm technology in Microwind3, Website: Etienne, sicardtdlinsa-toulouse. Fr .References4013/06/2016Narula Institute of Technology
Scott E. Thompson et al:A 90-nm Logic Technology Featuring Strained-Silicon,IEEE Transactions On Electron Devices, Vol. 51, No. 11, November 2004.Yoshihiro Takao, Satoshi Nakai and Naoto Horiguchi, Extended 90 nm CMOS Technology with High Manufacturability for High- Performance, Low-Power, RF/Analog Applications, Manuscript received December 9, 2002.Alexander gurney et al: ume.gatech.edu/mechatronics_course/DAC_F10. .pptx. References4113/06/2016Narula Institute of Technology
Questions
4213/06/2016Narula Institute of Technology
Thank you.4313/06/2016Narula Institute of Technology