LTM9011-14/LTM9010-14/LTM9009-14 (Rev D) · 2019-06-05 · LTM9011-14/ LTM9010-14/LTM9009-14 2 Rev...
Transcript of LTM9011-14/LTM9010-14/LTM9009-14 (Rev D) · 2019-06-05 · LTM9011-14/ LTM9010-14/LTM9009-14 2 Rev...
![Page 1: LTM9011-14/LTM9010-14/LTM9009-14 (Rev D) · 2019-06-05 · LTM9011-14/ LTM9010-14/LTM9009-14 2 Rev D For more information ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) PIN CONFIGURATION ORDER](https://reader030.fdocuments.us/reader030/viewer/2022041012/5ec00636c7bd0c67d4621658/html5/thumbnails/1.jpg)
1Rev D
LTM9011-14/LTM9010-14/LTM9009-14
For more information www.analog.comDocument Feedback
TYPICAL APPLICATION
FEATURES
APPLICATIONS
DESCRIPTION
14-Bit, 125Msps/105Msps/ 80Msps Low Power Octal ADCs
LTM9011-14, 125Msps, 2-Tone FFT, fIN = 70MHz and 75MHz
The LTM®9011-14/LTM9010-14/LTM9009-14 are 8-chan-nel, simultaneous sampling 14-bit A/D converters designed for digitizing high frequency, wide dynamic range signals. AC performance includes 73.1dB SNR and 88dB spurious free dynamic range (SFDR). Low power consumption per channel reduces heat in high channel count applications. Integrated bypass capacitance and flow-through pinout reduces overall board space requirements.
DC specs include ±1LSB INL (typ), ±0.3LSB DNL (typ) and no missing codes over temperature. The transition noise is a low 1.2LSBRMS.
The digital outputs are serial LVDS to minimize the num-ber of data lines. Each channel outputs two bits at a time (2-lane mode). At lower sampling rates there is a one bit per channel option (1-lane mode).
The ENC+ and ENC– inputs may be driven differentially or single-ended with a sine wave, PECL, LVDS, TTL, or CMOS inputs. An internal clock duty cycle stabilizer al-lows high performance at full speed for a wide range of clock duty cycles.
n 8-Channel Simultaneous Sampling ADCn 73.1dB SNRn 88dB SFDRn Low Power: 140mW/113mW/94mW per Channeln Single 1.8V Supplyn Serial LVDS Outputs: 1 or 2 Bits per Channeln Selectable Input Ranges: 1VP-P to 2VP-P n 800MHz Full Power Bandwidth S/Hn Shutdown and Nap Modesn Serial SPI Port for Configurationn Internal Bypass Capacitance, No External
Componentsn 140-Pin (11.25mm × 9mm) BGA Package
n Communicationsn Cellular Base Stationsn Software Defined Radiosn Portable Medical Imagingn Multichannel Data Acquisitionn Nondestructive Testing All registered trademarks and trademarks are the property of their respective owners.
FREQUENCY (MHz)0
–100–110–120
–70
–60
–80–90
AMPL
ITUD
E (d
BFS)
–50
–30
–40
–20
–10
0
10 20 30 40 50 60
9009101114 TA01b
DATASERIALIZER
ENCODEINPUT
SERIALIZEDLVDSOUTPUTS
1.8VVDD
1.8VOVDD
OUT1A
OUT1B
OUT2A
OUT2B
OUT8A
OUT8B
DATACLOCKOUT
FRAME
GNDGND9009101114 TA01
S/HCHANNEL 1
ANALOGINPUT
14-BITADC CORE
S/HCHANNEL 2
ANALOGINPUT
14-BITADC CORE
S/HCHANNEL 8
ANALOGINPUT
14-BITADC CORE
PLL
• • •
• • •
• • •
• • •
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LTM9011-14/LTM9010-14/LTM9009-14
2Rev D
For more information www.analog.com
ABSOLUTE MAXIMUM RATINGS(Notes 1, 2)
PIN CONFIGURATION
ORDER INFORMATIONLEAD FREE FINISH TRAY PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTM9011CY-14#PBF LTM9011CY-14#PBF LTM9011Y14 140-Lead (11.25mm × 9mm × 2.72mm) BGA 0°C to 70°C
LTM9011IY-14#PBF LTM9011IY-14#PBF LTM9011Y14 140-Lead (11.25mm × 9mm × 2.72mm) BGA –40°C to 85°C
LTM9010CY-14#PBF LTM9010CY-14#PBF LTM9010Y14 140-Lead (11.25mm × 9mm × 2.72mm) BGA 0°C to 70°C
LTM9010IY-14#PBF LTM9010IY-14#PBF LTM9010Y14 140-Lead (11.25mm × 9mm × 2.72mm) BGA –40°C to 85°C
LTM9009CY-14#PBF LTM9009CY-14#PBF LTM9009Y14 140-Lead (11.25mm × 9mm × 2.72mm) BGA 0°C to 70°C
LTM9009IY-14#PBF LTM9009IY-14#PBF LTM9009Y14 140-Lead (11.25mm × 9mm × 2.72mm) BGA –40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
Supply Voltages VDD, OVDD ................................................ –0.3V to 2VAnalog Input Voltage (AIN
+, AIN–,
PAR/SER, SENSE) (Note 3) .......... –0.3V to (VDD + 0.2V)Digital Input Voltage (ENC+, ENC–, CS,SDI, SCK) (Note 4) .................................... –0.3V to 3.9VSDO (Note 4) ............................................. –0.3V to 3.9VDigital Output Voltage ................ –0.3V to (OVDD + 0.3V)Operating Temperature Range LTM9011C, LTM9010C, LTM9009C ......... 0°C to 70°C LTM9011I, LTM9010I, LTM9009I .........–40°C to 85°CStorage Temperature Range .................. –55°C to 125°C
1
P
C
D
E
F
G
H
J
K
L
M
N
A
B
1098765432
BGA PACKAGE140-LEAD (11.25mm × 9.00mm × 2.72mm)
TJMAX = 150°C, θJA = 30°C/W, θJC = 25°C/W, θJB = 15°C/W, θJCbottom = 12°C/W
TOP VIEW
http://www.linear.com/product/LTM9011-14#orderinfo
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3Rev D
LTM9011-14/LTM9010-14/LTM9009-14
For more information www.analog.com
CONVERTER CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
PARAMETER CONDITIONS
LTM9011-14 LTM9010-14 LTM9009-14
UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX
Resolution (No Missing Codes) l 14 14 14 Bits
Integral Linearity Error Differential Analog Input (Note 6) l –4.1 ±1.2 4.1 –3.25 ±1 3.25 –2.75 ±1 2.75 LSB
Differential Linearity Error Differential Analog Input l –0.9 ±0.3 0.9 –0.8 ±0.3 0.8 –0.8 ±0.3 0.8 LSB
Offset Error (Note 7) l –12 ±3 12 –12 ±3 12 –12 ±3 12 mV
Gain Error Internal Reference External Reference
l
–2.6
–1.3 –1.3
0
–2.6
–1.3 –1.3
0
–2.6
–1.3 –1.3
0
%FS %FS
Offset Drift ±20 ±20 ±20 µV/°C
Full-Scale Drift Internal Reference External Reference
±35 ±25
±35 ±25
±35 ±25
ppm/°C ppm/°C
Gain Matching External Reference ±0.2 ±0.2 ±0.2 %FS
Offset Matching ±3 ±3 ±3 mV
Transition Noise External Reference 1.2 1.2 1.2 LSBRMS
ANALOG INPUT The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN Analog Input Range (AIN+ – AIN
–) 1.7V < VDD < 1.9V l 1 to 2 VP-P
VIN(CM) Analog Input Common Mode (AIN+ + AIN
–)/2 Differential Analog Input (Note 8) l VCM – 100mV VCM VCM + 100mV V
VSENSE External Voltage Reference Applied to SENSE External Reference Mode l 0.625 1.250 1.300 V
IINCM Analog Input Common Mode Current Per Pin, 125Msps Per Pin, 105Msps Per Pin, 80Msps
155 130 100
µA µA µA
IIN1 Analog Input Leakage Current 0 < AIN+, AIN
– < VDD, No Encode l –1 1 µA
IIN2 PAR/SER Input Leakage Current 0 < PAR/SER < VDD l –3 3 µA
IIN3 SENSE Input Leakage Current 0.625 < SENSE < 1.3V l –6 6 µA
tAP Sample-and-Hold Acquisition Delay Time 0 ns
tJITTER Sample-and-Hold Acquisition Delay Jitter 0.15 psRMS
CMRR Analog Input Common Mode Rejection Ratio 80 dB
BW-3B Full-Power Bandwidth Figure 6 Test Circuit 800 MHz
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LTM9011-14/LTM9010-14/LTM9009-14
4Rev D
For more information www.analog.com
DYNAMIC ACCURACY The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 5)
SYMBOL PARAMETER CONDITIONS
LTM9011-14 LTM9010-14 LTM9009-14
UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX
SNR Signal-to-Noise Ratio 5MHz Input 70MHz Input 140MHz Input
l
70.8
73.1 73
72.6
70.6
73 72.9 72.6
69.7
73 72.9 72.5
dBFS dBFS dBFS
SFDR Spurious Free Dynamic Range 2nd or 3rd Harmonic
5MHz Input 70MHz Input 140MHz Input
l
69
88 85 82
71
88 85 82
74
88 85 82
dBFS dBFS dBFS
Spurious Free Dynamic Range 4th Harmonic or Higher
5MHz Input 70MHz Input 140MHz Input
l
81
90 90 90
81
90 90 90
82
90 90 90
dBFS dBFS dBFS
S/(N+D) Signal-to-Noise Plus Distortion Ratio
5MHz Input 70MHz Input 140MHz Input
l
68.4
73 72.6 72
69.7
73 72.6 72
69.6
72.9 72.6 72
dBFS dBFS dBFS
Crosstalk, Near Channel 10MHz Input (Note 12) –90 –90 –90 dBc
Crosstalk, Far Channel 10MHz Input (Note 12) –105 –105 –105 dBc
INTERNAL REFERENCE CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 5)
PARAMETER CONDITIONS MIN TYP MAX UNITS
VCM Output Voltage IOUT = 0 0.5 • VDD – 25mV 0.5 • VDD 0.5 • VDD + 25mV V
VCM Output Temperature Drift ±25 ppm/°C
VCM Output Resistance –600µA < IOUT < 1mA 4 Ω
VREF Output Voltage IOUT = 0 1.225 1.250 1.275 V
VREF Output Temperature Drift ±25 ppm/°C
VREF Output Resistance –400µA < IOUT < 1mA 7 Ω
VREF Line Regulation 1.7V < VDD < 1.9V 0.6 mV/V
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5Rev D
LTM9011-14/LTM9010-14/LTM9009-14
For more information www.analog.com
DIGITAL INPUTS AND OUTPUTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
ENCODE INPUTS (ENC+, ENC– )
Differential Encode Mode (ENC– Not Tied to GND)
VID Differential Input Voltage (Note 8) l 0.2 V
VICM Common Mode Input Voltage Internally Set Externally Set (Note 8)
l
1.1
1.2 1.6
V V
VIN Input Voltage Range ENC+, ENC– to GND l 0.2 3.6 V
RIN Input Resistance (See Figure 10) 10 kΩ
CIN Input Capacitance 3.5 pF
Single-Ended Encode Mode (ENC– Tied to GND)
VIH High Level Input Voltage VDD = 1.8V l 1.2 V
VIL Low Level Input Voltage VDD = 1.8V l 0.6 V
VIN Input Voltage Range ENC+ to GND l 0 3.6 V
RIN Input Resistance (See Figure 11) 30 kΩ
CIN Input Capacitance 3.5 pF
DIGITAL INPUTS (CS, SDI, SCK in Serial or Parallel Programming Mode. SDO in Parallel Programming Mode)
VIH High Level Input Voltage VDD = 1.8V l 1.3 V
VIL Low Level Input Voltage VDD = 1.8V l 0.6 V
IIN Input Current VIN = 0V to 3.6V l –10 10 µA
CIN Input Capacitance 3 pF
SDO OUTPUT (Serial Programming Mode. Open-Drain Output. Requires 2kΩ Pull-Up Resistor if SDO Is Used)
ROL Logic Low Output Resistance to GND VDD = 1.8V, SDO = 0V 200 Ω
IOH Logic High Output Leakage Current SDO = 0V to 3.6V l –10 10 µA
COUT Output Capacitance 3 pF
DIGITAL DATA OUTPUTS
VOD Differential Output Voltage 100Ω Differential Load, 3.5mA Mode 100Ω Differential Load, 1.75mA Mode
l
l
247 125
350 175
454 250
mV mV
VOS Common Mode Output Voltage 100Ω Differential Load, 3.5mA Mode 100Ω Differential Load, 1.75mA Mode
l
l
1.125 1.125
1.250 1.250
1.375 1.375
V V
RTERM On-Chip Termination Resistance Termination Enabled, OVDD = 1.8V 100 Ω
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LTM9011-14/LTM9010-14/LTM9009-14
6Rev D
For more information www.analog.com
POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 9)
SYMBOL PARAMETER CONDITIONS
LTM9011-14 LTM9010-14 LTM9009-14
UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX
VDD Analog Supply Voltage (Note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V
OVDD Output Supply Voltage (Note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V
IVDD Analog Supply Current Sine Wave Input l 582 632 476 508 395 450 mA
IOVDD Digital Supply Current 2-Lane Mode, 1.75mA Mode 2-Lane Mode, 3.5mA Mode
l
l
54 98
62 108
52 96
62 106
50 94
58 104
mA mA
PDISS Power Dissipation 2-Lane Mode, 1.75mA Mode 2-Lane Mode, 3.5mA Mode
l
l
1145 1224
1249 1332
950 1030
1026 1105
801 880
914 997
mW mW
PSLEEP Sleep Mode Power 2 2 2 mW
PNAP Nap Mode Power 170 170 170 mW
PDIFFCLK Power Decrease With Single-Ended Encode Mode Enabled (No Decrease for Sleep Mode)
40 40 40 mW
TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER CONDITIONS
LTM9011-14 LTM9010-14 LTM9009-14
UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX
fS Sampling Frequency (Notes 10,11) l 5 125 5 105 5 80 MHz
tENCL ENC Low Time (Note 8) Duty Cycle Stabilizer Off Duty Cycle Stabilizer On
l
l
3.8 2
4 4
100 100
4.52 2
4.76 4.76
100 100
5.93 2
6.25 6.25
100 100
ns ns
tENCH ENC High Time (Note 8) Duty Cycle Stabilizer Off Duty Cycle Stabilizer On
l
l
3.8 2
4 4
100 100
4.52 2
4.76 4.76
100 100
5.93 2
6.25 6.25
100 100
ns ns
tAP Sample-and-Hold Acquisition Delay Time
0 0 0 ns
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Digital Data Outputs (RTERM = 100Ω Differential, CL = 2pF to GND on Each Output)
tSER Serial Data Bit Period 2-Lanes, 16-Bit Serialization 2-Lanes, 14-Bit Serialization 2-Lanes, 12-Bit Serialization 1-Lane, 16-Bit Serialization 1-Lane, 14-Bit Serialization 1-Lane, 12-Bit Serialization
1/(8 • fS) 1/(7 • fS) 1/(6 • fS) 1/(16 • fS) 1/(14 • fS) 1/(12 • fS)
s s s s s s
tFRAME FR to DCO Delay (Note 8) l 0.35 • tSER 0.5 • tSER 0.65 • tSER s
tDATA DATA to DCO Delay (Note 8) l 0.35 • tSER 0.5 • tSER 0.65 • tSER s
tPD Propagation Delay (Note 8) l 0.7n + 2 • tSER 1.1n + 2 • tSER 1.5n + 2 • tSER s
tR Output Rise Time Data, DCO, FR, 20% to 80% 0.17 ns
tF Output Fall Time Data, DCO, FR, 20% to 80% 0.17 ns
DCO Cycle-Cycle Jitter tSER = 1ns 60 psP-P
Pipeline Latency 6 Cycles
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7Rev D
LTM9011-14/LTM9010-14/LTM9009-14
For more information www.analog.com
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
SPI Port Timing (Note 8)
tSCK SCK Period Write Mode Read Back Mode, CSDO = 20pF, RPULLUP = 2k
l
l
40 250
ns ns
tS CS to SCK Setup Time l 5 ns
tH SCK to CS Setup Time l 5 ns
tDS SDI Setup Time l 5 ns
tDH SDI Hold Time l 5 ns
tDO SCK Falling to SDO Valid Read Back Mode, CSDO = 20pF, RPULLUP = 2k
l 125 ns
TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime.Note 2: All voltage values are with respect to GND (unless otherwise noted).Note 3: When these pin voltages are taken below GND or above VDD, they will be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND or above VDD without latchup.Note 4: When these pin voltages are taken below GND they will be clamped by internal diodes. When these pin voltages are taken above VDD they will not be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND without latchup.Note 5: VDD = OVDD = 1.8V, fSAMPLE = 125MHz (LTM9011), 105MHz (LTM9010), or 80MHz (LTM9009), 2-lane output mode, differential ENC+/ENC– = 2VP-P sine wave, input range = 2VP-P with differential drive, unless otherwise noted.Note 6: Integral nonlinearity is defined as the deviation of a code from a best fit straight line to the transfer curve. The deviation is measured from the center of the quantization band.
Note 7: Offset error is the offset voltage measured from –0.5 LSB when the output code flickers between 00 0000 0000 0000 and 11 1111 1111 1111 in 2’s complement output mode.Note 8: Guaranteed by design, not subject to test.Note 9: VDD = OVDD = 1.8V, fSAMPLE = 125MHz (LTM9011), 105MHz (LTM9010), or 80MHz (LTM9009), 2-lane output mode, differential ENC+/ENC– = 2VP-P sine wave, input range = 2VP-P with differential drive, unless otherwise noted. The supply current and power dissipation specifications are totals for the entire device, not per channel.Note 10: Recommended operating conditions.Note 11: The maximum sampling frequency depends on the speed grade of the part and also which serialization mode is used. The maximum serial data rate is 1000Mbps so tSER must be greater than or equal to 1ns.Note 12: Near-channel crosstalk refers to Ch. 1 to Ch.2, and Ch.7 to Ch.8. Far-channel crosstalk refers to Ch.1 to Ch.7, Ch.1 to Ch.8, Ch.2 to Ch.7, and Ch.2 to Ch.8.
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LTM9011-14/LTM9010-14/LTM9009-14
8Rev D
For more information www.analog.com
2-Lane Output Mode, 14-Bit Serialization
ANALOGINPUT
ENC–
ENC+
DCO–
DCO+
tAP
tENCH tENCL
tSER
tSER
tSERtPD
tDATAtFRAME
SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 SAMPLE N-3
N+1
N+2N
9009101114 TD02
D7 D5 D3 D1 D13 D11 D9 D7 D5 D3 D1 D13 D11 D9 D7 D5 D3 D1 D13 D11 D9OUT#A–
OUT#A+
FR–
FR+
D6 D4 D2 D0 D12 D10 D8 D6 D4 D2 D0 D12 D10 D8 D6 D4 D2 D0 D12 D10 D8OUT#B–
OUT#B+
NOTE THAT IN THIS MODE FR+/FR– HAS TWO TIMES THE PERIOD OF ENC+/ENC–
TIMING DIAGRAMS
2-Lane Output Mode, 16-Bit Serialization*
ANALOGINPUT
ENC–
ENC+
DCO–
DCO+
tAP
tENCH tENCL
tSER
tSER
tSERtPD
tDATAtFRAME
SAMPLE N-6
*SEE THE DIGITAL OUTPUTS SECTION
SAMPLE N-5 SAMPLE N-4
N+1N
9009101114 TD01
D5 D3 D1 0 D13 D11 D9 D7 D5 D3 D1 0 D13 D11 D9OUT#A–
OUT#A+
FR–
FR+
D4 D2 D0 0 D12 D10 D8 D6 D4 D2 D0 0 D12 D10 D8OUT#B–
OUT#B+
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9Rev D
LTM9011-14/LTM9010-14/LTM9009-14
For more information www.analog.com
TIMING DIAGRAMS
2-Lane Output Mode, 12-Bit Serialization
1-Lane Output Mode, 16-Bit Serialization
ANALOGINPUT
ENC–
ENC+
DCO–
DCO+
tAP
tENCH tENCL
tSER
tSER
tSERtPD
tDATAtFRAME
SAMPLE N-6 SAMPLE N-5 SAMPLE N-4
N+1N
9009101114 TD03
D9 D7 D5 D3 D13 D11 D9 D7 D5 D3 D13 D11 D9OUT#A–
OUT#A+
FR+
FR–
D8 D6 D4 D2 D12 D10 D8 D6 D4 D2 D12 D10 D8OUT#B–
OUT#B+
ANALOGINPUT
ENC–
ENC+
DCO–
DCO+
tAP
tENCH tENCL
tSERtPD
tDATAtFRAME
SAMPLE N-6 SAMPLE N-5 SAMPLE N-4
N+1N
tSER
tSER
9009101114 TD04
D1 D0 0 0 D13 D12 D11 D10 D12 D11 D10D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 D13OUT#A–
OUT#A+
FR–
FR+
OUT#B+, OUT#B– ARE DISABLED
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LTM9011-14/LTM9010-14/LTM9009-14
10Rev D
For more information www.analog.com
TIMING DIAGRAMS
1-Lane Output Mode, 14-Bit Serialization
ANALOGINPUT
ENC–
ENC+
DCO–
DCO+
tAP
tENCH tENCL
tSERtPD
tDATAtFRAME
SAMPLE N-6 SAMPLE N-5 SAMPLE N-4
N+1N
tSER
tSER
9009101114 TD06
D3 D2 D1 D0 D13 D12 D11 D10 D12 D11 D10D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D13OUT#A–
OUT#A+
FR–
FR+
OUT#B+, OUT#B– ARE DISABLED
1-Lane Output Mode, 12-Bit Serialization
ANALOGINPUT
ENC–
ENC+
DCO–
DCO+
tAP
tENCH tENCL
tSERtPD
tDATAtFRAME
SAMPLE N-6 SAMPLE N-5 SAMPLE N-4
N+1N
tSER
tSER
9009101114 TD07
D5 D4 D3 D2 D13 D12 D11 D10 D12 D11D9 D8 D7 D6 D5 D4 D3 D2 D13OUT#A–
OUT#A+
FR–
FR+
OUT#B+, OUT#B– ARE DISABLED
![Page 11: LTM9011-14/LTM9010-14/LTM9009-14 (Rev D) · 2019-06-05 · LTM9011-14/ LTM9010-14/LTM9009-14 2 Rev D For more information ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) PIN CONFIGURATION ORDER](https://reader030.fdocuments.us/reader030/viewer/2022041012/5ec00636c7bd0c67d4621658/html5/thumbnails/11.jpg)
11Rev D
LTM9011-14/LTM9010-14/LTM9009-14
For more information www.analog.com
A6
tS tDS
A5 A4 A3 A2 A1 A0 XX
D7 D6 D5 D4 D3 D2 D1 D0
XX XX XX XX XX XX XX
CS
SCK
SDI R/W
SDOHIGH IMPEDANCE
SPI Port Timing (Readback Mode)
SPI Port Timing (Write Mode)
tDH
tDO
tSCK tH
A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
9009101114 TD08
CS
SCK
SDI R/W
SDOHIGH IMPEDANCE
TIMING DIAGRAMS
![Page 12: LTM9011-14/LTM9010-14/LTM9009-14 (Rev D) · 2019-06-05 · LTM9011-14/ LTM9010-14/LTM9009-14 2 Rev D For more information ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) PIN CONFIGURATION ORDER](https://reader030.fdocuments.us/reader030/viewer/2022041012/5ec00636c7bd0c67d4621658/html5/thumbnails/12.jpg)
LTM9011-14/LTM9010-14/LTM9009-14
12Rev D
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
LTM9011-14: Integral Nonlinearity (INL)
LTM9011-14: Differential Nonlinearity (DNL)
LTM9011-14: 8k Point FFT, fIN = 5MHz, –1dBFS, 125Msps
OUTPUT CODE0
–2.0
–0.5
–1.0
–1.5
INL
ERRO
R (L
SB)
0
0.5
1.0
1.5
2.0
4096 8192 12288 16384
9009101114 G01OUTPUT CODE
0–1.0
–0.4
–0.2
–0.6
–0.8
DNL
ERRO
R (L
SB)
0
0.4
0.2
0.6
0.8
1.0
4096 8192 12288 16384
9009101114 G02FREQUENCY (MHz)
–100–110–120
–70
–60
–80–90
AMPL
ITUD
E (d
BFS)
–50
–30
–40
–20
–10
0
9009101114 G03
0 10 20 30 40 50 60
LTM9011-14: 8k Point FFT, fIN = 30MHz, –1dBFS, 125Msps
LTM9011-14: 8k Point FFT, fIN = 70MHz, –1dBFS, 125Msps
LTM9011-14: 8k Point FFT, fIN = 140MHz, –1dBFS, 125Msps
LTM9011-14: 8k Point 2-Tone FFT, fIN = 70MHz, 75MHz, –7dBFS per Tone, 125Msps
LTM9011-14: Shorted Input Histogram
FREQUENCY (MHz)0
–100–110–120
–70
–60
–80–90
AMPL
ITUD
E (d
BFS)
–50
–30
–40
–20
–10
0
9009101114 G04
10 20 30 40 50 60FREQUENCY (MHz)
0
–100–110–120
–70
–60
–80–90
AMPL
ITUD
E (d
BFS)
–50
–30
–40
–20
–10
0
10 20 30 40 50 60
9009101114 G05FREQUENCY (MHz)
0
–100–110–120
–70
–60
–80–90
AMPL
ITUD
E (d
BFS)
–50
–30
–40
–20
–10
0
10 20 30 40 50 60
9009101114 G06
FREQUENCY (MHz)0
–100–110–120
–70
–60
–80–90
AMPL
ITUD
E (d
BFS)
–50
–30
–40
–20
–10
0
10 20 30 40 50 60
9009101114 G07OUTPUT CODE
8178
1000
0
3000
2000
COUN
T
4000
5000
6000
8180 8182 8184 8186
9009101114 G08
![Page 13: LTM9011-14/LTM9010-14/LTM9009-14 (Rev D) · 2019-06-05 · LTM9011-14/ LTM9010-14/LTM9009-14 2 Rev D For more information ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) PIN CONFIGURATION ORDER](https://reader030.fdocuments.us/reader030/viewer/2022041012/5ec00636c7bd0c67d4621658/html5/thumbnails/13.jpg)
13Rev D
LTM9011-14/LTM9010-14/LTM9009-14
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
INPUT FREQUENCY (MHz)0
72
71
70
69
68
67
66
74
73
SNR
(dBF
S)
50 100 150 200 250 300 350
9009101114 G09
LTM9011-14: SNR vs Input Frequency, –1dBFS, 2V Range, 125Msps
LTM9011-14: SFDR vs Input Level, fIN = 70MHz, 2V Range, 125Msps
LTM9011-14: IVDD vs Sample Rate, 5MHz Sine Wave Input, –1dBFS
INPUT LEVEL (dBFS)–80
60
50
40
30
20
10
0
80
70
SFDR
(dBc
AND
dBF
S)
90
100
110
–70 –60 –50 –40 –30 –20 –10 0
9009101114 G11
dBFS
dBc
INPUT FREQUENCY (MHz)0
90
85
80
75
70
65
95
SFDR
(dBF
S)
50 100 150 200 250 300 350
9009101114 G10
LTM9011-14: SFDR vs Input Frequency, –1dBFS, 2V Range, 125Msps
IOVDD vs Sample Rate, 5MHz Sine Wave Input, –1dBFS
LTM9011-14: SNR vs SENSE, fIN = 5MHz, –1dBFS
SENSE PIN (V)0.6
71
68
69
70
67
66
72
73
74
SNR
(dBF
S)
0.7 0.8 0.9 1.1 1.2 1.31
9009101114 G15
SAMPLE RATE (Msps)
580
560
540
520
500
480
460
440
420
I VDD
(mA)
0 25 50 75 100 125
9009101114 G13
SAMPLE RATE (Msps)
100
80
60
40
20
0
I OVD
D (m
A)
0 25 50 75 100 125
9009101114 G14
1-LANE, 1.75mA
2-LANE, 3.5mA
2-LANE, 1.75mA
1-LANE, 3.5mA
INPUT LEVEL (dBFS)
60
50
40
30
20
10
0
80
70
SNR
(dBc
AND
dBF
S)
–60 –50 –40 –30 –20 –10 0
9009101114 G12
dBFS
dBc
LTM9011-14: SNR vs Input Level, fIN = 70MHz, 2V Range, 125Msps
![Page 14: LTM9011-14/LTM9010-14/LTM9009-14 (Rev D) · 2019-06-05 · LTM9011-14/ LTM9010-14/LTM9009-14 2 Rev D For more information ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) PIN CONFIGURATION ORDER](https://reader030.fdocuments.us/reader030/viewer/2022041012/5ec00636c7bd0c67d4621658/html5/thumbnails/14.jpg)
LTM9011-14/LTM9010-14/LTM9009-14
14Rev D
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
LTM9010-14: Integral Nonlinearity (INL)
LTM9010-14: Differential Nonlinearity (DNL)
LTM9010-14: 8k Point FFT, fIN = 5MHz, –1dBFS, 105Msps
OUTPUT CODE0
–2.0
–0.5
–1.0
–1.5
INL
ERRO
R (L
SB)
0
0.5
1.0
1.5
2.0
4096 8192 12288 16384
9009101114 G16OUTPUT CODE
0–1.0
–0.4
–0.2
–0.6
–0.8
DNL
ERRO
R (L
SB)
0
0.4
0.2
0.6
0.8
1.0
4096 8192 12288 16384
9009101114 G17FREQUENCY (MHz)
0
–100–110–120
–70
–60
–80–90
AMPL
ITUD
E (d
BFS)
–50
–30
–40
–20
–10
0
10 20 30 40 50
9009101114 G18
LTM9010-14: Shorted Input Histogram
OUTPUT CODE8195
1000
0
3000
2000
COUN
T
4000
5000
6000
8197 8199 8201 8203
9009101114 G23
LTM9010-14: 8k Point FFT, fIN = 70MHz, –1dBFS, 105Msps
LTM9010-14: 8k Point FFT, fIN = 140MHz, –1dBFS, 105Msps
FREQUENCY (MHz)0
–100–110–120
–70
–60
–80–90
AMPL
ITUD
E (d
BFS)
–50
–30
–40
–20
–10
0
10 20 30 40 50
9009101114 G20FREQUENCY (MHz)
0
–100–110–120
–70
–60
–80–90
AMPL
ITUD
E (d
BFS)
–50
–30
–40
–20
–10
0
10 20 30 40 50
9009101114 G21
LTM9010-14: 8k Point 2-Tone FFT, fIN = 70MHz, 75MHz, –7dBFS per Tone, 105Msps
FREQUENCY (MHz)0
–100–110–120
–70
–60
–80–90
AMPL
ITUD
E (d
BFS)
–50
–30
–40
–20
–10
0
10 20 30 40 50
9009101114 G22
LTM9010-14: 8k Point FFT, fIN = 30MHz, –1dBFS, 105Msps
FREQUENCY (MHz)0
–100–110–120
–70
–60
–80–90
AMPL
ITUD
E (d
BFS)
–50
–30
–40
–20
–10
0
10 20 30 40 50
9009101114 G19
![Page 15: LTM9011-14/LTM9010-14/LTM9009-14 (Rev D) · 2019-06-05 · LTM9011-14/ LTM9010-14/LTM9009-14 2 Rev D For more information ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) PIN CONFIGURATION ORDER](https://reader030.fdocuments.us/reader030/viewer/2022041012/5ec00636c7bd0c67d4621658/html5/thumbnails/15.jpg)
15Rev D
LTM9011-14/LTM9010-14/LTM9009-14
For more information www.analog.com
LTM9010-14: IVDD vs Sample Rate, 5MHz Sine Wave Input, –1dBFS
LTM9010-14: SFDR vs Input Level, fIN = 70MHz, 2V Range, 105Msps
TYPICAL PERFORMANCE CHARACTERISTICS
INPUT LEVEL (dBFS)–80
60
50
40
30
20
10
0
80
70
SFDR
(dBc
AND
dBF
S)
90
100
110
–70 –60 –50 –40 –30 –20 –10 0
9009101114 G26
dBFS
dBc
INPUT FREQUENCY (MHz)0
72
71
70
69
68
67
66
74
73
SNR
(dBF
S)
50 100 150 200 250 300 350
9009101114 G24INPUT FREQUENCY (MHz)
0
90
85
80
75
70
65
95
SFDR
(dBF
S)
50 100 150 200 250 300 350
9009101114 G25
LTM9010-14: SNR vs Input Frequency, –1dBFS, 2V Range, 105Msps
LTM9010-14: SFDR vs Input Frequency, –1dBFS, 2V Range, 105Msps
SAMPLE RATE (Msps)
460
440
420
400
380
360
340
320
I VDD
(mA)
0 25 50 75 100
9009101114 G27
LTM9010-14: SNR vs SENSE, fIN = 5MHz, –1dBFS
SENSE PIN (V)0.6
71
68
69
70
67
66
72
73
74
SNR
(dBF
S)
0.7 0.8 0.9 1.1 1.2 1.31
9009101114 G28
![Page 16: LTM9011-14/LTM9010-14/LTM9009-14 (Rev D) · 2019-06-05 · LTM9011-14/ LTM9010-14/LTM9009-14 2 Rev D For more information ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) PIN CONFIGURATION ORDER](https://reader030.fdocuments.us/reader030/viewer/2022041012/5ec00636c7bd0c67d4621658/html5/thumbnails/16.jpg)
LTM9011-14/LTM9010-14/LTM9009-14
16Rev D
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
LTM9009-14: 8k Point 2-Tone FFT, fIN = 70MHz, 75MHz, –7dBFS per Tone, 80Msps
LTM9009-14: Shorted Input Histogram
LTM9009-14: 8k Point FFT, fIN = 30MHz, –1dBFS, 80Msps
LTM9009-14: 8k Point FFT, fIN = 70MHz, –1dBFS, 80Msps
LTM9009-14: 8k Point FFT, fIN = 140MHz, –1dBFS, 80Msps
LTM9009-14: Integral Nonlinearity (INL)
LTM9009-14: Differential Nonlinearity (DNL)
LTM9009-14: 8k Point FFT, fIN = 5MHz, –1dBFS, 80Msps
OUTPUT CODE0
–1.0
–0.4
–0.2
–0.6
–0.8
DNL
ERRO
R (L
SB)
0
0.4
0.2
0.6
0.8
1.0
4096 8192 12288 16384
9009101114 G30FREQUENCY (MHz)
0
–100–110–120
–70
–60
–80–90
AMPL
ITUD
E (d
BFS)
–50
–30
–40
–20
–10
0
10 20 30 40
9009101114 G31
FREQUENCY (MHz)0
–100–110–120
–70
–60
–80–90
AMPL
ITUD
E (d
BFS)
–50
–30
–40
–20
–10
0
10 20 30 40
9009101114 G32FREQUENCY (MHz)
0
–100–110–120
–70
–60
–80–90
AMPL
ITUD
E (d
BFS)
–50
–30
–40
–20
–10
0
10 20 30 40
9009101114 G33FREQUENCY (MHz)
0
–100–110–120
–70
–60
–80–90
AMPL
ITUD
E (d
BFS)
–50
–30
–40
–20
–10
0
10 20 30 40
9009101114 G34
FREQUENCY (MHz)0
–100–110–120
–70
–60
–80–90
AMPL
ITUD
E (d
BFS)
–50
–30
–40
–20
–10
0
10 20 30 40
9009101114 G35OUTPUT CODE
8184
1000
0
3000
2000
COUN
T
4000
5000
6000
8186 8188 8190 8192
9009101114 G36
OUTPUT CODE0
–2.0
–0.5
–1.0
–1.5
INL
ERRO
R (L
SB)
0
0.5
1.0
1.5
2.0
4096 8192 12288 16384
9009101114 G29
![Page 17: LTM9011-14/LTM9010-14/LTM9009-14 (Rev D) · 2019-06-05 · LTM9011-14/ LTM9010-14/LTM9009-14 2 Rev D For more information ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) PIN CONFIGURATION ORDER](https://reader030.fdocuments.us/reader030/viewer/2022041012/5ec00636c7bd0c67d4621658/html5/thumbnails/17.jpg)
17Rev D
LTM9011-14/LTM9010-14/LTM9009-14
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
LTM9009-14: IVDD vs Sample Rate, 5MHz Sine Wave Input, –1dBFS
DCO Cycle-Cycle Jitter vs Serial Data Rate
LTM9009-14: SNR vs SENSE, fIN = 5MHz, –1dBFS
SENSE PIN (V)0.6
71
68
69
70
67
66
72
73
74
SNR
(dBF
S)
0.7 0.8 0.9 1.1 1.2 1.31
9009101114 G41
LTM9009-14: SFDR vs Input Level, fIN = 70MHz, 2V Range, 80Msps
INPUT LEVEL (dBFS)–80
60
50
40
30
20
10
0
80
70
SFDR
(dBc
AND
dBF
S)
90
100
110
–70 –60 –50 –40 –30 –20 –10 0
9009101114 G39
dBFS
dBc
INPUT FREQUENCY (MHz)0
90
85
80
75
70
65
95
SFDR
(dBF
S)
50 100 150 200 250 300 350
9009101114 G38
LTM9009-14: SFDR vs Input Frequency, –1dBFS, 2V Range, 80Msps
INPUT FREQUENCY (MHz)0
72
71
70
69
68
67
66
74
73
SNR
(dBF
S)
50 100 150 200 250 300 350
9009101114 G37
LTM9009-14: SNR vs Input Frequency, –1dBFS, 2V Range, 80Msps
SERIAL DATA RATE (Mbps)
350
300
250
200
150
100
50
0
PEAK
-TO-
PEAK
JIT
TER
(ps)
0 200 400 600 800 1000
9009101114 G42SAMPLE RATE (Msps)
380
360
340
320
300
280
I VDD
(mA)
0 20 40 60 80
9009101114 G40
![Page 18: LTM9011-14/LTM9010-14/LTM9009-14 (Rev D) · 2019-06-05 · LTM9011-14/ LTM9010-14/LTM9009-14 2 Rev D For more information ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) PIN CONFIGURATION ORDER](https://reader030.fdocuments.us/reader030/viewer/2022041012/5ec00636c7bd0c67d4621658/html5/thumbnails/18.jpg)
LTM9011-14/LTM9010-14/LTM9009-14
18Rev D
For more information www.analog.com
PIN FUNCTIONSAIN1
+ (B2): Channel 1 Positive Differential Analog Input.
AIN1– (B1): Channel 1 Negative Differential Analog Input.
VCM14 (B3): Common Mode Bias Output, Nominally Equal to VDD/2. VCM should be used to bias the common mode of the analog inputs of channels 1 and 4. VCM is internally bypassed to ground with a 0.1µF ceramic capacitor. No external capacitance is required.
AIN2+ (C2): Channel 2 Positive Differential Analog Input.
AIN2– (C1): Channel 2 Negative Differential Analog Input.
AIN3+ (E2): Channel 3 Positive Differential Analog Input.
AIN3– (E1): Channel 3 Negative Differential Analog Input.
VCM23 (F3): Common Mode Bias Output, Nominally Equal to VDD/2. VCM should be used to bias the common mode of the analog inputs of channels 2 and 3. VCM is internally bypassed to ground with a 0.1µF ceramic capacitor. No external capacitance is required.
AIN4+ (G2): Channel 4 Positive Differential Analog Input.
AIN4– (G1): Channel 4 Negative Differential Analog Input.
AIN5+ (H1): Channel 5 Positive Differential Analog Input.
AIN5– (H2): Channel 5 Negative Differential Analog Input.
VCM67 (J3): Common Mode Bias Output, Nominally Equal to VDD/2. VCM should be used to bias the common mode of the analog inputs of channels 6 and 7. VCM is internally bypassed to ground with a 0.1µF ceramic capacitor. No external capacitance is required.
AIN6+ (K1): Channel 6 Positive Differential Analog Input.
AIN6– (K2): Channel 6 Negative Differential Analog Input.
AIN7+ (M1): Channel 7 Positive Differential Analog Input.
AIN7– (M2): Channel 7 Negative Differential Analog Input.
VCM58 (N3): Common Mode Bias Output, Nominally Equal to VDD/2. VCM should be used to bias the common mode of the analog inputs of channels 5 and 8. VCM is internally bypassed to ground with a 0.1µF ceramic capacitor. No external capacitance is required.
AIN8+ (N1): Channel 8 Positive Differential Analog Input.
AIN8– (N2): Channel 8 Negative Differential Analog Input
VDD (D3, D4, E3, E4, K3, K4, L3, L4): 1.8V Analog Power Supply. VDD is internally bypassed to ground with 0.1μF ceramic capacitors.
ENC+ (P5): Encode Input. Conversion starts on the rising edge.
ENC– (P6): Encode Complement Input. Conversion starts on the falling edge.
CSA (L5): In serial programming mode, (PAR/SER = 0V), CSA is the serial interface chip select input for registers controlling channels 1, 4, 5 and 8. When CS is low, SCK is enabled for shifting data on SDI into the mode con-trol registers. In parallel programming mode (PAR/SER = VDD), CS selects 2-lane or 1-lane output mode. CS can be driven with 1.8V to 3.3V logic.
CSB (M5): In serial programming mode, (PAR/SER = 0V), CSB is the serial interface chip select input for registers controlling channels 2, 3, 6 and 7. When CS is low, SCK is enabled for shifting data on SDI into the mode con-trol registers. In parallel programming mode (PAR/SER = VDD), CS selects 2-lane or 1-lane output mode. CS can be driven with 1.8V to 3.3V logic.
SCK (L6): In serial programming mode, (PAR/SER = 0V), SCK is the serial interface clock input. In parallel pro-gramming mode (PAR/SER = VDD), SCK selects 3.5mA or 1.75mA LVDS output currents. SCK can be driven with 1.8V to 3.3V logic.
SDI (M6): In serial programming mode, (PAR/SER = 0V), SDI is the serial interface data Input. Data on SDI is clocked into the mode control registers on the rising edge of SCK. In parallel programming mode (PAR/SER = VDD), SDI can be used to power down the part. SDI can be driven with 1.8V to 3.3V logic.
GND (See Pin Configuration Table): ADC Power Ground. Use multiple vias close to pins.
![Page 19: LTM9011-14/LTM9010-14/LTM9009-14 (Rev D) · 2019-06-05 · LTM9011-14/ LTM9010-14/LTM9009-14 2 Rev D For more information ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) PIN CONFIGURATION ORDER](https://reader030.fdocuments.us/reader030/viewer/2022041012/5ec00636c7bd0c67d4621658/html5/thumbnails/19.jpg)
19Rev D
LTM9011-14/LTM9010-14/LTM9009-14
For more information www.analog.com
PIN FUNCTIONSOVDD (G9, G10): Output Driver Supply. OVDD is internally bypassed to ground with a 0.1µF ceramic capacitor.
SDOA (E6): In serial programming mode, (PAR/SER = 0V), SDOA is the optional serial interface data output for reg-isters controlling channels 1, 4, 5 and 8. Data on SDO is read back from the mode control registers and can be latched on the falling edge of SCK. SDO is an open-drain N-channel MOSFET output that requires an external 2k pull-up resistor from 1.8V to 3.3V. If read back from the mode control registers is not needed, the pull-up resis-tor is not necessary and SDO can be left unconnected. In parallel programming mode (PAR/SER = VDD), SDOA is an input that enables internal 100Ω termination resistors on the digital outputs of channels 1, 4, 5 and 8. When used as an input, SDO can be driven with 1.8V to 3.3V logic through a 1k series resistor.
SDOB (D6): Serial Data Output Pin for Channels 2, 3, 6 and 7. See description for SDOA.
PAR/SER (A7): Programming Mode Selection Pin. Connect to ground to enable the serial programming mode. CSA, CSB, SCK, SDI, SDOA and SDOB become a serial interface that control the A/D operating modes. Connect to VDD to enable parallel programming mode where CSA, CSB, SCK, SDI, SDOA and SDOB become parallel logic inputs that control a reduced set of the A/D operating modes. PAR/SER should be connected directly to ground or the VDD of the part and not be driven by a logic signal.
VREF (B6): Reference Voltage Output. VREF is internally bypassed to ground with a 1μF ceramic capacitor, nomi-nally 1.25V.
SENSE (C5): Reference Programming Pin. Connecting SENSE to VDD selects the internal reference and a ±1V input range. Connecting SENSE to ground selects the internal reference and a ±0.5V input range. An external reference between 0.625V and 1.3V applied to SENSE selects an input range of ±0.8 • VSENSE. SENSE is inter-nally bypassed to ground with a 0.1µF ceramic capacitor.
LVDS Outputs
All pins in this section are differential LVDS outputs. The output current level is programmable. There is an optional internal 100Ω termination resistor between the pins of each LVDS output pair.
OUT1A–/OUT1A+, OUT1B–/OUT1B+ (E7/E8, C8/D8):Serial Data Outputs for Channel 1. In 1-lane output mode only OUT1A–/OUT1A+ are used.
OUT2A–/OUT2A+, OUT2B–/OUT2B+ (B8/A8, D7/C7): Serial Data Outputs for Channel 2. In 1-lane output mode only OUT2A–/OUT2A+ are used.
OUT3A–/OUT3A+, OUT3B–/OUT3B+ (D10/D9, E10/E9): Serial Data Outputs for Channel 3. In 1-lane output mode only OUT3A–/OUT3A+ are used.
OUT4A–/OUT4A+, OUT4B–/OUT4B+ (C9/C10, F7/F8): Serial Data Outputs for Channel 4. In 1-lane output mode only OUT4A–/OUT4A+ are used.
OUT5A–/OUT5A+, OUT5B–/OUT5B+ (J8/J7, K8/K7): Serial Data Outputs for Channel 5. In 1-lane output mode only OUT5A–/OUT5A+ are used.
OUT6A–/OUT6A+, OUT6B–/OUT6B+ (K9/K10, L9/L10): Serial Data Outputs for Channel 6. In 1-lane output mode only OUT6A–/OUT6A+ are used.
OUT7A–/OUT7A+, OUT7B–/OUT7B+ (M7/L7, P8/N8): Serial Data Outputs for Channel 7. In 1-lane output mode only OUT7A–/OUT7A+ are used.
OUT8A–/OUT8A+, OUT8B–/OUT8B+ (L8/M8, M10/M9): Serial Data Outputs for Channel 8. In 1-lane output mode only OUT8A–/OUT8A+ are used.
FRA–/FRA+ (H7/H8): Frame Start Outputs for Channels 1, 4, 5 and 8.
FRB–/FRB+ (J9/J10): Frame Start Outputs for Channels 2, 3, 6 and 7.
DCOA–/DCOA+ (G8/G7): Data Clock Outputs for Channels 1, 4, 5 and 8.
DCOB–/DCOB+ (F10, F9): Data Clock Outputs for Chan-nels 2, 3, 6 and 7.
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LTM9011-14/LTM9010-14/LTM9009-14
20Rev D
For more information www.analog.com
1 2 3 4 5 6 7 8 9 10
A GND GND GND GND GND GND PAR/SER OUT2A+ GND GND
B AIN1– AIN1
+ VCM14 GND GND VREF GND OUT2A– GND GND
C AIN2– AIN2
+ GND GND SENSE GND OUT2B+ OUT1B– OUT4A– OUT4A+
D GND GND VDD VDD GND SDOB OUT2B– OUT1B+ OUT3A+ OUT3A–
E AIN3– AIN3
+ VDD VDD GND SDOA OUT1A– OUT1A+ OUT3B+ OUT3B–
F GND GND VCM23 GND GND GND OUT4B– OUT4B+ DCOB+ DCOB–
G AIN4– AIN4
+ GND GND GND GND DCOA+ DCOA– OVDD OVDD
H AIN5+ AIN5
– GND GND GND GND FRA– FRA+ GND GND
J GND GND VCM67 GND GND GND OUT5A+ OUT5A– FRB– FRB+
K AIN6+ AIN6
– VDD VDD GND GND OUT5B+ OUT5B– OUT6A– OUT6A+
L GND GND VDD VDD CSA SCK OUT7A+ OUT8A– OUT6B– OUT6B+
M AIN7+ AIN7
– GND GND CSB SDI OUT7A– OUT8A+ OUT8B+ OUT8B–
N AIN8+ AIN8
– VCM58 GND GND GND GND OUT7B+ GND GND
P GND GND GND GND ENC+ ENC– GND OUT7B– GND GND
Top View of BGA Package (Looking Through Component).
PIN CONFIGURATION TABLE
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21Rev D
LTM9011-14/LTM9010-14/LTM9009-14
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FUNCTIONAL BLOCK DIAGRAM
Figure 1. Figure 1. Functional Block Diagram
DIFFREFAMP
REFBUFFER
REFH REFLRANGESELECT
1.25VREFERENCE
GND
VDD/2
9009101114 F01
SENSE
VREFMODE
CONTROLREGISTERS
OVDD = 1.8VVDD = 1.8V
OUT1A+
OUT1A–
OUT1B+
OUT1B–S/H
CH 1ANALOG
INPUT
14-BITADC CORE
OUT2A+
OUT2A–
OUT2B+
OUT2B–S/H
CH 2ANALOG
INPUT
14-BITADC CORE
OUT3A+
OUT3A–
OUT3B+
OUT3B–S/H
CH 3ANALOG
INPUT
14-BITADC CORE
OUT4A+
OUT4A–
OUT4B+
OUT4B–S/H
CH 4ANALOG
INPUT
14-BITADC CORE
OUT5A+
OUT5A–
OUT5B+
OUT5B–S/H
CH 5ANALOG
INPUT
14-BITADC CORE
OUT6A+
OUT6A–
OUT6B+
OUT6B–S/H
CH 6ANALOG
INPUT
14-BITADC CORE
OUT7A+
OUT7A–
OUT7B+
OUT7B–S/H
CH 7ANALOG
INPUT
14-BITADC CORE
OUT8A+
OUT8A–
OUT8B+
OUT8B–S/H
CH 8ANALOG
INPUT
14-BITADC CORE
DCOA±DCOB±FRA±FRB±
ENC+
ENC–
SDOASDOBSDISCKCSACSBPAR/SER
VCM14 VCM58 VCM23 VCM67
PLL
DATASERIALIZER
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LTM9011-14/LTM9010-14/LTM9009-14
22Rev D
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APPLICATIONS INFORMATIONCONVERTER OPERATION
The LTM9011-14/LTM9010-14/LTM9009-14 are low power, 8-channel, 14-bit, 125Msps/105Msps/80Msps A/D converters that are powered by a single 1.8V supply. The analog inputs should be driven differentially. The encode input can be driven differentially for optimal jitter perfor-mance, or single-ended for lower power consumption. The digital outputs are serial LVDS to minimize the num-ber of data lines. Each channel outputs two bits at a time (2-lane mode). At lower sampling rates there is a one bit per channel option (1-lane mode). Many additional fea-tures can be chosen by programming the mode control registers through a serial SPI port.
ANALOG INPUT
The analog inputs are differential CMOS sample-and-hold circuits (Figure 2). The inputs should be driven differen-tially around a common mode voltage set by the appropri-ate VCM output pins, which are nominally VDD/2. For the 2V input range, the inputs should swing from VCM – 0.5V to VCM + 0.5V. There should be 180° phase difference between the inputs.
The eight channels are simultaneously sampled by a shared encode circuit (Figure 2).
INPUT DRIVE CIRCUITS
Input Filtering
If possible, there should be an RC low pass filter right at the analog inputs. This lowpass filter isolates the drive cir-cuitry from the A/D sample-and-hold switching, and also limits wideband noise from the drive circuitry. Figure 3 shows an example of an input RC filter. The RC component values should be chosen based on the application’s input frequency.
Transformer Coupled Circuits
Figure 3 shows the analog input being driven by an RF transformer with a center-tapped secondary. The center tap is biased with VCM, setting the A/D input at its opti-mal DC level. At higher input frequencies a transmission line balun transformer (Figures 4 to 6) has better balance, resulting in lower A/D distortion.
Figure 2. Equivalent Input Circuit. Only One of the Eight Analog Channels Is Shown
CSAMPLE3.5pFRON
25Ω
RON25Ω
VDD
VDD
LTM9011-14
AIN+
9009101114 F02
CSAMPLE3.5pF
VDD
AIN–
ENC–
ENC+
1.2V
10k
1.2V
10k
CPARASITIC1.8pF
CPARASITIC1.8pF
10Ω
10ΩFigure 3. Analog Input Circuit Using a Transformer. Recommended for Input Frequencies from 5MHz to 70MHz
25Ω
25Ω25Ω
25Ω
50Ω
0.1µF
AIN+
AIN–
12pF
0.1µF
VCM
LTM9011-14ANALOG
INPUT
0.1µF T11:1
T1: MA/COM MABAES0060RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
9009101114 F03
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23Rev D
LTM9011-14/LTM9010-14/LTM9009-14
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APPLICATIONS INFORMATIONAmplifier Circuits
Figure 7 shows the analog input being driven by a high speed differential amplifier. The output of the amplifier is AC-coupled to the A/D so the amplifier’s output common mode voltage can be optimally set to minimize distortion.See back page for a DC-coupled example.
Figure 4. Recommended Front End Circuit for Input Frequencies from 70MHz to 170MHz
25Ω
25Ω
50Ω
0.1µF
AIN+
AIN–
4.7pF
0.1µF
VCM
ANALOGINPUT
0.1µF
0.1µF
T1T2
T1: MA/COM MABA-007159-000000T2: MA/COM MABAES0060 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
9009101114 F04
LTM9011-1425Ω
25Ω
50Ω
0.1µF
AIN+
AIN–
1.8pF
0.1µF
VCM
ANALOGINPUT
0.1µF
0.1µF
T1T2
T1: MA/COM MABA-007159-000000T2: COILCRAFT WBC1-1LB RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
9009101114 F05
LTM9011-14
25Ω
25Ω
50Ω
0.1µF
2.7nH
2.7nH
AIN+
AIN–
0.1µF
VCM
ANALOGINPUT
0.1µF
0.1µF
T1
T1: MA/COM ETC1-1-13RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
9009101114 F06
LTM9011-14
25Ω
25Ω
200Ω200Ω0.1µF
AIN+
AIN–
12pF
0.1µF
VCM
LTM9011-14
9009101114 F07
– –
+ +ANALOG
INPUT
HIGH SPEEDDIFFERENTIAL
AMPLIFIER
0.1µF
At very high frequencies an RF gain block will often have lower distortion than a differential amplifier. If the gain block is single-ended, then a transformer circuit (Figures 4 to 6) should convert the signal to differential before driving the A/D.
Figure 5. Recommended Front End Circuit for Input Frequencies from 170MHz to 300MHz
Figure 6. Recommended Front End Circuit for Input Frequencies Above 300MHz
Figure 7. Front End Circuit Using a High Speed Differential Amplifier
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LTM9011-14/LTM9010-14/LTM9009-14
24Rev D
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VREF1.25V
REFH
SENSETIE TO VDD FOR 2V RANGE;TIE TO GND FOR 1V RANGE;
RANGE = 1.6 • VSENSE FOR0.65V < VSENSE < 1.300V
REFL
0.1µF2.2µF
INTERNAL ADCHIGH REFERENCE
BUFFER
9009101114 F08
LTM9011-145Ω
0.8xDIFF AMP
INTERNAL ADCLOW REFERENCE
1.25V BANDGAPREFERENCE
0.625V
RANGEDETECT
ANDCONTROL
1µF
0.1µF
0.1µF
0.1µF
APPLICATIONS INFORMATION
Figure 8. Reference Circuit
Figure 9. Using an External 1.25V Reference
Reference
The LTM9011-14/LTM9010-14/LTM9009-14 has an inter-nal 1.25V voltage reference. For a 2V input range using the internal reference, connect SENSE to VDD. For a 1V input range using the internal reference, connect SENSE to ground. For a 2V input range with an external reference, apply a 1.25V reference voltage to SENSE (Figure 9).
SENSE1.25V
EXTERNALREFERENCE 1µF
9009101114 F09
LTM9011-14
The input range can be adjusted by applying a voltage to SENSE that is between 0.625V and 1.30V. The input range will then be 1.6 • VSENSE. The reference is shared by all eight ADC channels, so it is not possible to independently adjust the input range of individual channels.
The VREF , SENSE, REFH and REFL pins are internally bypassed, as shown in Figure 8.
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25Rev D
LTM9011-14/LTM9010-14/LTM9009-14
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APPLICATIONS INFORMATIONEncode Input
The signal quality of the encode inputs strongly affects the A/D noise performance. The encode inputs should be treated as analog signals—do not route them next to digital traces on the circuit board. There are two modes of operation for the encode inputs: the differential encode mode (Figure 10), and the single-ended encode mode (Figure 11).
The differential encode mode is recommended for sinu-soidal, PECL, or LVDS encode inputs (Figures 12 and 13).
Figure 13. PECL or LVDS Encode DriveFigure 12. Sinusoidal Encode Drive
50Ω100Ω
0.1µF
0.1µF
0.1µF
T1
T1 = MA/COM ETC1-1-13RESISTORS AND CAPACITORSARE 0402 PACKAGE SIZE
50Ω
LTM9011-14
9009101114 F12
ENC–
ENC+
ENC+
ENC–
PECL ORLVDS
CLOCK
0.1µF
0.1µF
9009101114 F13
LTM9011-14
VDDLTM9011-14
9009101114 F10
ENC–
ENC+
15k
VDD
DIFFERENTIALCOMPARATOR
30k
Figure 10. Equivalent Encode Input Circuit for Differential Encode Mode
30k
ENC+
ENC–
9009101114 F11
0V
1.8V TO3.3V
LTM9011-14
CMOS LOGICBUFFER
Figure 11. Equivalent Encode Input Circuit for Single-Ended Encode Mode
The encode inputs are internally biased to 1.2V through 10k equivalent resistance. The encode inputs can be taken above VDD (up to 3.6V), and the common mode range is from 1.1V to 1.6V. In the differential encode mode, ENC– should stay at least 200mV above ground to avoid falsely triggering the single-ended encode mode. For good jitter performance ENC+ should have fast rise and fall times.
The single-ended encode mode should be used with CMOS encode inputs. To select this mode, ENC– is con-nected to ground and ENC+ is driven with a square wave
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LTM9011-14/LTM9010-14/LTM9009-14
26Rev D
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APPLICATIONS INFORMATIONencode input. ENC+ can be taken above VDD (up to 3.6V) so 1.8V to 3.3V CMOS logic levels can be used. The ENC+ threshold is 0.9V. For good jitter performance ENC+ should have fast rise and fall times.
Clock PLL and Duty Cycle Stabilizer
The encode clock is multiplied by an internal phase-locked loop (PLL) to generate the serial digital output data. If the encode signal changes frequency or is turned off, the PLL requires 25µs to lock onto the input clock.
A clock duty cycle stabilizer circuit allows the duty cycle of the applied encode signal to vary from 30% to 70%. In the serial programming mode it is possible to disable the duty cycle stabilizer, but this is not recommended. In the parallel programming mode the duty cycle stabilizer is always enabled.
DIGITAL OUTPUTS
The digital outputs of the LTM9011-14/LTM9010-14/LTM9009-14 are serialized LVDS signals. Each channel outputs two bits at a time (2-lane mode). At lower sam-pling rates there is a one bit per channel option (1-lane mode). The data can be serialized with 16, 14, or 12-bit
serialization (see the Timing Diagrams section for details). Note that with 12-bit serialization the two LSBs are not available—this mode is included for compatibility with 12-bit versions of these parts.
The output data should be latched on the rising and falling edges of the data clock out (DCO). A data frame output (FR) can be used to determine when the data from a new conversion result begins. In the 2-lane, 14-bit serialization mode, the frequency of the FR output is halved.
The maximum serial data rate for the data outputs is 1Gbps, so the maximum sample rate of the ADC will de-pend on the serialization mode as well as the speed grade of the ADC (see Table 1). The minimum sample rate for all serialization modes is 5Msps.
By default the outputs are standard LVDS levels: 3.5mA output current and a 1.25V output common mode volt-age. An external 100Ω differential termination resistor is required for each LVDS output pair. The termination resistors should be located as close as possible to the LVDS receiver.
The outputs are powered by OVDD which is independent from the A/D core power.
Table 1. Maximum Sampling Frequency for All Serialization Modes. Note That These Limits Are for the LTM9011-14. The Sampling Frequency for the Slower Speed Grades Cannot Exceed 105MHz (LTM9010-14) or 80MHz (LTM9009-14).
SERIALIZATION MODEMAXIMUM SAMPLING FREQUENCY, fS (MHz) DCO FREQUENCY FR FREQUENCY SERIAL DATA RATE
2-Lane 16-Bit Serialization 125 4 • fS fS 8 • fS2-Lane 14-Bit Serialization 125 3.5 • fS 0.5 • fS 7 • fS2-Lane 12-Bit Serialization 125 3 • fS fS 6 • fS1-Lane 16-Bit Serialization 62.5 8 • fS fS 16 • fS1-Lane 14-Bit Serialization 71.4 7 • fS fS 14 • fS1-Lane 12-Bit Serialization 83.3 6 • fS fS 12 • fS
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27Rev D
LTM9011-14/LTM9010-14/LTM9009-14
For more information www.analog.com
APPLICATIONS INFORMATIONProgrammable LVDS Output Current
The default output driver current is 3.5mA. This current can be adjusted by control register A2 in the serial pro-gramming mode. Available current levels are 1.75mA, 2.1mA, 2.5mA, 3mA, 3.5mA, 4mA and 4.5mA. In the par-allel programming mode, the SCK pin can select either 3.5mA or 1.75mA.
Optional LVDS Driver Internal Termination
In most cases, using just an external 100Ω termina-tion resistor will give excellent LVDS signal integrity. In addition, an optional internal 100Ω termination resistor can be enabled by serially programming mode con-trol register A2. The internal termination helps absorb any reflections caused by imperfect termination at the receiver. When the internal termination is enabled, the output driver current is doubled to maintain the same output voltage swing. In the parallel programming mode the SDO pin enables internal termination. Internal termination should only be used with 1.75mA, 2.1mA or 2.5mA LVDS output current modes.
DATA FORMAT
Table 2 shows the relationship between the analog input voltage and the digital data output bits. By default the output data format is offset binary. The 2’s complement format can be selected by serially programming mode control register A1.
Digital Output Randomizer
Interference from the A/D digital outputs is sometimes unavoidable. Digital interference may be from capacitive or inductive coupling or coupling through the ground plane. Even a tiny coupling factor can cause unwanted tones in the ADC output spectrum. By randomizing the digital output before it is transmitted off chip, these unwanted tones can be randomized which reduces the unwanted tone amplitude.
The digital output is randomized by applying an exclusive-OR logic operation between the LSB and all other data output bits. To decode, the reverse operation is applied —an exclusive-OR operation is applied between the LSB and all other bits. The FR and DCO outputs are not affected. The output randomizer is enabled by serially programming mode control register A1.
Table 2. Output Codes vs Input VoltageAIN
+ – AIN–
(2V RANGE) D13-D0 (OFFSET BINARY)
D13-D0 (2’s COMPLEMENT)
>1.000000V+0.999878V+0.999756V
11 1111 1111 111111 1111 1111 111111 1111 1111 1110
01 1111 1111 111101 1111 1111 111101 1111 1111 1110
+0.000122V+0.000000V–0.000122V–0.000244V
10 0000 0000 000110 0000 0000 000001 1111 1111 111101 1111 1111 1110
00 0000 0000 000100 0000 0000 000011 1111 1111 111111 1111 1111 1110
–0.999878V–1.000000V<–1.000000V
00 0000 0000 000100 0000 0000 000000 0000 0000 0000
10 0000 0000 000110 0000 0000 000010 0000 0000 0000
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LTM9011-14/LTM9010-14/LTM9009-14
28Rev D
For more information www.analog.com
APPLICATIONS INFORMATIONDigital Output Test Pattern
To allow in-circuit testing of the digital interface to the A/D, there is a test mode that forces the A/D data outputs (D13-D0) of all channels to known values. The digital output test patterns are enabled by serially programming mode control registers A3 and A4. When enabled, the test patterns override all other formatting modes: 2’s comple-ment and randomizer.
Output Disable
The digital outputs may be disabled by serially program-ming mode control register A2. The current drive for all digital outputs including DCO and FR are disabled to save power or enable in-circuit testing. When disabled the com-mon mode of each output pair becomes high impedance, but the differential impedance may remain low.
Sleep and Nap Modes
The A/D may be placed in sleep or nap modes to con-serve power. In sleep mode the entire device is powered down, resulting in 2mW power consumption. Sleep mode is enabled by mode control register A1 (serial program-ming mode), or by SDI (parallel programming mode). The time required to recover from sleep mode is about 2ms.
In nap mode any combination of A/D channels can be powered down while the internal reference circuits and the PLL stay active, allowing faster wakeup than from sleep mode. Recovering from nap mode requires at least 100 clock cycles. If the application demands very accurate DC settling then an additional 50µs should be allowed so the on-chip references can settle from the slight temperature shift caused by the change in supply current as the A/D leaves nap mode. Nap mode is enabled by mode control register A1 in the serial programming mode.
DEVICE PROGRAMMING MODES
The operating modes of the LTM9011-14/LTM9010-14/LTM9009-14 can be programmed by either a parallel interface or a simple serial interface. The serial interface has more flexibility and can program all available modes. The parallel interface is more limited and can only pro-gram some of the more commonly used modes.
Parallel Programming Mode
To use the parallel programming mode, PAR/SER should be tied to VDD. The CS, SCK, SDI and SDO pins are binary logic inputs that set certain operating modes. These pins can be tied to VDD or ground, or driven by 1.8V, 2.5V, or 3.3V CMOS logic. When used as an input, SDO should be driven through a 1k series resistor. Table 3 shows the modes set by CS, SCK, SDI and SDO.
Table 3. Parallel Programming Mode Control Bits (PAR/SER = VDD)Pin DESCRIPTION
CS 2-Lane / 1-Lane Selection Bit0 = 2-Lane, 16-Bit Serialization Output Mode1 = 1-Lane, 14-Bit Serialization Output Mode
SCK LVDS Current Selection Bit0 = 3.5mA LVDS Current Mode1 = 1.75mA LVDS Current Mode
SDI Power Down Control Bit0 = Normal Operation1 = Sleep Mode
SDO Internal Termination Selection Bit0 = Internal Termination Disabled1 = Internal Termination Enabled
Serial Programming Mode
To use the serial programming mode, PAR/SER should be tied to ground. The CS, SCK, SDI and SDO pins become a serial interface that program the A/D mode control reg-isters. Data is written to a register with a 16-bit serial word. Data can also be read back from a register to verify its contents.
Serial data transfer starts when CS is taken low. The data on the SDI pin is latched at the first 16 rising
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29Rev D
LTM9011-14/LTM9010-14/LTM9009-14
For more information www.analog.com
APPLICATIONS INFORMATION
Table 4. Serial Programming Mode Register Map (PAR/SER = GND)REGISTER A0: RESET REGISTER (ADDRESS 00h)
D7 D6 D5 D4 D3 D2 D1 D0
RESET X X X X X X X
Note That CSA Controls Channels 1, 4, 5 and 8, CSB Controls Channels 2, 3, 6 and 7.
Bit 7 RESET Software Reset Bit
0 = Not Used 1 = Software Reset. All Mode Control Registers Are Reset to 00h. The ADC Is Momentarily Placed in SLEEP Mode. After the Reset SPI Write Command Is Complete, Bit D7 Is Automatically Set Back to Zero. The Reset Register Is Write Only.
Bits 6-0 Unused, Don’t Care Bits.
REGISTER A1 (CSA): FORMAT AND POWER-DOWN REGISTER (ADDRESS 01h with CSA = GND)
D7 D6 D5 D4 D3 D2 D1 D0
DCSOFF RAND TWOSCOMP SLEEP NAP_8 NAP_5 NAP_4 NAP_1
Note That CSA Controls Channels 1, 4, 5 and 8, CSB Controls Channels 2, 3, 6 and 7.
Bit 7 DCSOFF Clock Duty Cycle Stabilizer Bit 0 = Clock Duty Cycle Stabilizer On 1 = Clock Duty Cycle Stabilizer Off. This Is Not Recommended.
Bit 6 RAND Data Output Randomizer Mode Control Bit 0 = Data Output Randomizer Mode Off 1 = Data Output Randomizer Mode On
Bit 5 TWOSCOMP Two’s Complement Mode Control Bit 0 = Offset Binary Data Format 1 = Two’s Complement Data Format
Bits 4-0 SLEEP: NAP_X Sleep/Nap Mode Control Bits 00000 = Normal Operation 0XXX1 = Channel 1 in Nap Mode 0XX1X = Channel 4 in Nap Mode 0X1XX = Channel 5 in Nap Mode 01XXX = Channel 8 in Nap Mode 1XXXX = Sleep Mode. Channels 1, 4, 5 and 8 Are Disabled Note: Any Combination of Channels Can Be Placed in Nap Mode.
edges of SCK. Any SCK rising edges after the first 16 are ignored. The data transfer ends when CS is taken high again.
The first bit of the 16-bit input word is the R/W bit. The next seven bits are the address of the register (A6:A0). The final eight bits are the register data (D7:D0).
If the R/W bit is low, the serial data (D7:D0) will be writ-ten to the register set by the address bits (A6:A0). If the R/W bit is high, data in the register set by the address
bits (A6:A0) will be read back on the SDO pin (see the Timing Diagrams section). During a read back command the register is not updated and data on SDI is ignored.
The SDO pin is an open-drain output that pulls to ground with a 200Ω impedance. If register data is read back through SDO, an external 2k pull-up resistor is required. If serial data is only written and read back is not needed, then SDO can be left floating and no pull-up resistor is needed. Table 4 shows a map of the mode control registers.
![Page 30: LTM9011-14/LTM9010-14/LTM9009-14 (Rev D) · 2019-06-05 · LTM9011-14/ LTM9010-14/LTM9009-14 2 Rev D For more information ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) PIN CONFIGURATION ORDER](https://reader030.fdocuments.us/reader030/viewer/2022041012/5ec00636c7bd0c67d4621658/html5/thumbnails/30.jpg)
LTM9011-14/LTM9010-14/LTM9009-14
30Rev D
For more information www.analog.com
APPLICATIONS INFORMATIONREGISTER A1 (CSB): FORMAT AND POWER-DOWN REGISTER (ADDRESS 01h with CSB = GND)
D7 D6 D5 D4 D3 D2 D1 D0
DCSOFF RAND TWOSCOMP SLEEP NAP_7 NAP_6 NAP_3 NAP_2
Note That CSA Controls Channels 1, 4, 5 and 8, CSB Controls Channels 2, 3, 6 and 7.
Bit 7 DCSOFF Clock Duty Cycle Stabilizer Bit 0 = Clock Duty Cycle Stabilizer On 1 = Clock Duty Cycle Stabilizer Off. This Is Not Recommended.
Bit 6 RAND Data Output Randomizer Mode Control Bit 0 = Data Output Randomizer Mode Off 1 = Data Output Randomizer Mode On
Bit 5 TWOSCOMP Two’s Complement Mode Control Bit 0 = Offset Binary Data Format 1 = Two’s Complement Data Format
Bits 4-0 SLEEP: NAP_4:NAP_1 Sleep/Nap Mode Control Bits 00000 = Normal Operation 0XXX1 = Channel 2 in Nap Mode 0XX1X = Channel 3 in Nap Mode 0X1XX = Channel 6 in Nap Mode 01XXX = Channel 7 in Nap Mode 1XXXX = Sleep Mode. Channels 2, 3, 6 and 7 Are Disabled Note: Any Combination of Channels Can Be Placed in Nap Mode.
REGISTER A2: OUTPUT MODE REGISTER (ADDRESS 02h)
D7 D6 D5 D4 D3 D2 D1 D0ILVDS2 ILVDS1 ILVDS0 TERMON OUTOFF OUTMODE2 OUTMODE1 OUTMODE0
Note That CSA Controls Channels 1, 4, 5 and 8, CSB Controls Channels 2, 3, 6 and 7.Bits 7-5 ILVDS2:ILVDS0 LVDS Output Current Bits
000 = 3.5mA LVDS Output Driver Current 001 = 4.0mA LVDS Output Driver Current 010 = 4.5mA LVDS Output Driver Current 011 = Not Used 100 = 3.0mA LVDS Output Driver Current 101 = 2.5mA LVDS Output Driver Current 110 = 2.1mA LVDS Output Driver Current 111 = 1.75mA LVDS Output Driver Current
Bit 4 TERMON LVDS Internal Termination Bit 0 = Internal Termination Off 1 = Internal Termination On. LVDS Output Driver Current Is 2x the Current Set by ILVDS2:ILVDS0. Internal Termination Should Only Be Used with 1.75mA, 2.1mA or 2.5mA LVDS Output Current Modes.
Bit 3 OUTOFF Output Disable Bit 0 = Digital Outputs Are Enabled. 1 = Digital Outputs Are Disabled.
Bits 2-0 OUTMODE2:OUTMODE0 Digital Output Mode Control Bits 000 = 2-Lanes, 16-Bit Serialization 001 = 2-Lanes, 14-Bit Serialization 010 = 2-Lanes, 12-Bit Serialization 011 = Not Used 100 = Not Used 101 = 1-Lane, 14-Bit Serialization 110 = 1-Lane, 12-Bit Serialization 111 = 1-Lane, 16-Bit Serialization
![Page 31: LTM9011-14/LTM9010-14/LTM9009-14 (Rev D) · 2019-06-05 · LTM9011-14/ LTM9010-14/LTM9009-14 2 Rev D For more information ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) PIN CONFIGURATION ORDER](https://reader030.fdocuments.us/reader030/viewer/2022041012/5ec00636c7bd0c67d4621658/html5/thumbnails/31.jpg)
31Rev D
LTM9011-14/LTM9010-14/LTM9009-14
For more information www.analog.com
APPLICATIONS INFORMATIONREGISTER A3: TEST PATTERN MSB REGISTER (ADDRESS 03h)
D7 D6 D5 D4 D3 D2 D1 D0OUTTEST X TP13 TP12 TP11 TP10 TP9 TP8
Note That CSA Controls Channels 1, 4, 5 and 8, CSB Controls Channels 2, 3, 6 and 7.Bit 7 OUTTEST Digital Output Test Pattern Control Bit
0 = Digital Output Test Pattern Off 1 = Digital Output Test Pattern On
Bit 6 Unused, Don’t Care Bit.Bit 5-0 TP13:TP8 Test Pattern Data Bits (MSB)
TP13:TP8 Set the Test Pattern for Data Bit 13 (MSB) Through Data Bit 8.
REGISTER A4: TEST PATTERN LSB REGISTER (ADDRESS 04h)D7 D6 D5 D4 D3 D2 D1 D0TP7 TP6 TP5 TP4 TP3 TP2 TP1 TP0
Note That CSA Controls Channels 1, 4, 5 and 8, CSB Controls Channels 2, 3, 6 and 7.Bit 7-0 TP7:TP0 Test Pattern Data Bits (LSB)
TP7:TP0 Set the Test Pattern for Data Bit 7 Through Data Bit 0 (LSB).
Software Reset
If serial programming is used, the mode control regis-ters should be programmed as soon as possible after the power supplies turn on and are stable. The first serial command must be a software reset which will reset all register data bits to logic 0. To perform a software reset, bit D7 in the reset register is written with a logic 1. After the reset SPI write command is complete, bit D7 is auto-matically set back to zero.
GROUNDING AND BYPASSING
The LTM9011-14/LTM9010-14/LTM9009-14 requires a printed circuit board with a clean unbroken ground plane. A multilayer board with an internal ground plane in the first layer beneath the ADC is recommended. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track or underneath the ADC.
Bypass capacitors are integrated inside the package; addi-tional capacitance is optional.
The analog inputs, encode signals, and digital outputs should not be routed next to each other. Ground fill and grounded vias should be used as barriers to isolate these signals from each other.
The pin assignments of the LTM9011-14/LTM9010-14/LTM9009-14 allow a flow-through layout that makes it possible to use multiple parts in a small area when a large number of ADC channels are required. The LTM9011 module has similar layout rules to other BGA pack- ages. The layout can be implemented with 6mil blind vias and 5mil traces. The pinout has been designed to minimize the space required to route the analog and digital traces. The analog and digital traces can essen-tially be routed within the width of the package. This allows multiple packages to be located close together for high channel count applications. Trace lengths for the analog inputs and digital outputs should be matched as well as possible.
![Page 32: LTM9011-14/LTM9010-14/LTM9009-14 (Rev D) · 2019-06-05 · LTM9011-14/ LTM9010-14/LTM9009-14 2 Rev D For more information ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) PIN CONFIGURATION ORDER](https://reader030.fdocuments.us/reader030/viewer/2022041012/5ec00636c7bd0c67d4621658/html5/thumbnails/32.jpg)
LTM9011-14/LTM9010-14/LTM9009-14
32Rev D
For more information www.analog.com
APPLICATIONS INFORMATIONHEAT TRANSFER
Most of the heat generated by the LTM9011-14/LTM9010-14/ LTM9009-14 is transferred from the die through the bot-tom of the package onto the printed circuit board. The ground pins should be connected to the internal ground planes by multiple vias.
Table 5. Internal Trace Lengths
PIN NAMELENGTH
(mm) PIN NAMELENGTH
(mm) PIN NAMELENGTH
(mm) PIN NAMELENGTH
(mm)
E7 OUT1A– 1.775 K8 OUT5B– 0.379 E1 AIN3– 2.491 F10 DCOB– 1.811
E8 OUT1A+ 1.947 K7 OUT5B+ 0.528 E2 AIN3+ 2.505 F9 DCOB+ 1.812
C8 OUT1B– 1.847 K9 OUT6A– 1.866 G1 AIN4– 3.376 H7 FRA– 1.117
D8 OUT1B+ 1.850 K10 OUT6A+ 1.865 G2 AIN4+ 3.372 H8 FRA+ 1.038
B8 OUT2A– 3.233 L9 OUT6B– 2.268 H2 AIN5– 3.301 J9 FRB– 1.644
A8 OUT2A+ 3.246 L10 OUT6B+ 2.267 H1 AIN5+ 3.346 J10 FRB+ 1.643
D7 OUT2B– 0.179 M7 OUT7A– 1.089 K2 AIN6– 2.506 A7 PAR/SER 3.838
C7 OUT2B+ 1.127 L7 OUT7A+ 0.179 K1 AIN6+ 2.533 L6 SCK 0.240
D10 OUT3A– 2.126 P8 OUT7B– 3.281 M2 AIN7– 3.198 E6 SDOA 0.453
D9 OUT3A+ 2.177 N8 OUT7B+ 3.149 M1 AIN7+ 3.214 D6 SDOB 0.274
E10 OUT3B– 1.811 L8 OUT8A– 1.862 N2 AIN8– 4.726 M6 SDI 1.069
E9 OUT3B+ 1.812 M8 OUT8A+ 1.847 N1 AIN8+ 4.691 B3 VCM14 3.914
C9 OUT4A– 3.199 M10 OUT8B– 4.021 P6 ENC– 4.106 F3 VCM23 0.123
C10 OUT4A+ 3.196 M9 OUT8B+ 4.016 P5 ENC+ 4.106 J3 VCM67 0.079
F7 OUT4B– 0.706 B1 AIN1– 4.689 L5 CSA 0.919 N3 VCM58 3.915
F8 OUT4B+ 0.639 B2 AIN1+ 4.709 M5 CSB 1.162
J8 OUT5A– 0.392 C1 AIN2– 4.724 G8 DCOA– 1.157
J7 OUT5A+ 0.436 C2 AIN2+ 4.769 G7 DCOA+ 1.088
Table 5 lists the trace lengths for the analog inputs and digital outputs inside the package from the die pad to the package pad. These should be added to the PCB trace lengths for best matching.
The material used for the substrate is BT (bismaleimide-triazine), supplied by Mitsubishi Gas and Chemical. In the DC to 125MHz range, the speed for the analog input signals is 198ps/in or 7.795ps/mm. The speed for the digital outputs is 188.5ps/in or 7.417ps/mm.
![Page 33: LTM9011-14/LTM9010-14/LTM9009-14 (Rev D) · 2019-06-05 · LTM9011-14/ LTM9010-14/LTM9009-14 2 Rev D For more information ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) PIN CONFIGURATION ORDER](https://reader030.fdocuments.us/reader030/viewer/2022041012/5ec00636c7bd0c67d4621658/html5/thumbnails/33.jpg)
33Rev D
LTM9011-14/LTM9010-14/LTM9009-14
For more information www.analog.com
Top Side
TYPICAL APPLICATIONSSilkscreen Top
![Page 34: LTM9011-14/LTM9010-14/LTM9009-14 (Rev D) · 2019-06-05 · LTM9011-14/ LTM9010-14/LTM9009-14 2 Rev D For more information ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) PIN CONFIGURATION ORDER](https://reader030.fdocuments.us/reader030/viewer/2022041012/5ec00636c7bd0c67d4621658/html5/thumbnails/34.jpg)
LTM9011-14/LTM9010-14/LTM9009-14
34Rev D
For more information www.analog.com
TYPICAL APPLICATIONSInner Layer 2
Inner Layer 3
![Page 35: LTM9011-14/LTM9010-14/LTM9009-14 (Rev D) · 2019-06-05 · LTM9011-14/ LTM9010-14/LTM9009-14 2 Rev D For more information ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) PIN CONFIGURATION ORDER](https://reader030.fdocuments.us/reader030/viewer/2022041012/5ec00636c7bd0c67d4621658/html5/thumbnails/35.jpg)
35Rev D
LTM9011-14/LTM9010-14/LTM9009-14
For more information www.analog.com
Inner Layer 5
TYPICAL APPLICATIONSInner Layer 4
![Page 36: LTM9011-14/LTM9010-14/LTM9009-14 (Rev D) · 2019-06-05 · LTM9011-14/ LTM9010-14/LTM9009-14 2 Rev D For more information ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) PIN CONFIGURATION ORDER](https://reader030.fdocuments.us/reader030/viewer/2022041012/5ec00636c7bd0c67d4621658/html5/thumbnails/36.jpg)
LTM9011-14/LTM9010-14/LTM9009-14
36Rev D
For more information www.analog.com
TYPICAL APPLICATIONSBottom Side
Silkscreen Bottom
![Page 37: LTM9011-14/LTM9010-14/LTM9009-14 (Rev D) · 2019-06-05 · LTM9011-14/ LTM9010-14/LTM9009-14 2 Rev D For more information ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) PIN CONFIGURATION ORDER](https://reader030.fdocuments.us/reader030/viewer/2022041012/5ec00636c7bd0c67d4621658/html5/thumbnails/37.jpg)
37Rev D
LTM9011-14/LTM9010-14/LTM9009-14
For more information www.analog.com
TYPICAL APPLICATION
LTM
9011
-14
Sche
mat
ic
E3V+
3V T
O 6V
CLK+
CLK+
GND
TERM
SDOB3.
3 AU
X
JP6
1 2 3
R8 1kR1
110
kEN DI
S
TERM
SDOA
3.3
AUX
JP3
1 2 3
1 2 3
1 2 3
R3 1kEN DI
SR5 31
.6k
1%
R13
31.6
k1%
R4 10k
LANE
CSB
JP3
1 2 3
R1 1k1
LANE
2 LA
NE
+1.8
V+1
.8V
+1.8
V
+1.8
V
ILVD
S
SCK
JP5
R7 1k1.
7mA
3.5m
A
LANE
CSA
JP2
R2 1k1
LANE
2 LA
NE
+1.8
V
PAR/
SER
PAR/
SER
PAR/
SER
SENS
EVR
EFSC
ISC
KCS
ACS
BSD
OASD
OB
MOS
IJP
4
R6 1kPA
R
SER
R9 100Ω
E1EXT
REF R1
01k
C1 2.2µ
F, 06
03
A1A2A3A4A5A6B4B5B7C3C4C6D1D2D5E5F1F2F4F5F6G3G4G5G6H3H4H5H6J1J2J4J5J6K5K6L1L2
M3M4N4N5N6N7P1P2P3P4P7A9
A10B9
B10H9
H10N9
N10P9
P10
GNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGND
A7
C5
B6
M6
L6
L5
M5
E6
D6
LTM
9011
-14
+1.8
V
R20
100Ω
R14
(OPT
)L1
(OPT
)
1 2 3
5 4R1
8(O
PT)
R25
(OPT
)
C2 (OPT
)
R24
(OPT
)
C13
100µ
F10
V
R28
3k
9009
1011
14 T
A02
OUT1
A+
OUT1
A–
OUT1
B+
OUT1
B–
OUT1
A+
OUT1
A–
OUT1
B+
OUT1
B–
E8 E7 D8 C8
OUT2
A+
OUT2
A–
OUT2
B+
OUT2
B–
OUT2
A+
OUT2
A–
OUT2
B+
OUT2
B–
A8 B8 C7 D7
OUT3
A+
OUT3
A–
OUT3
B+
OUT3
B–
OUT3
A+
OUT3
A–
OUT3
B+
OUT3
B–
D9 D10
E9 E10
OUT4
A+
OUT4
A–
OUT4
B+
OUT4
B–
OUT4
A+
OUT4
A–
OUT4
B+
OUT4
B–
C10
C9 F8 F7
OUT5
A+
OUT5
A–
OUT5
B+
OUT5
B–
OUT5
A+
OUT5
A–
OUT5
B+
OUT5
B–
J7 J8 K7 K8
OUT6
A+
OUT6
A–
OUT6
B+
OUT6
B–
OUT6
A+
OUT6
A–
OUT6
B+
OUT6
B–
K10
K9 L10
L9
AIN1
+
AIN1
–
VCM
14
AIN1
+
AIN1
–
VCM
14
B2 B1 B3
AIN2
+
AIN2
–AI
N2+
AIN2
–C2 C1
AIN3
+
AIN3
–
VCM
23
AIN3
+
AIN3
–
VCM
23
E2 E1 F3VC
M14
AIN4
+
AIN4
–AI
N4+
AIN4
–G2 G1
AIN5
+
AIN5
–
VCM
67
AIN5
+
AIN5
–
VCM
67
H2 H1 J3
AIN6
+
AIN6
–AI
N6+
AIN6
–K1 K2
AIN8
+
AIN8
–
VCM
58
AIN8
+
AIN8
–
VCM
58
N1 N2 N3
AIN7
+
AIN7
–AI
N7+
AIN7
–M
1M
2
ENC+
ENC–
ENC+
ENC–
P5 P6OU
T7A+
OUT7
A–
OUT7
B+
OUT7
B–
OUT7
A+
OUT7
A–
OUT7
B+
OUT7
B–
M8
L8 M9
M10
FRA+
FRA–
FRB+
FRB–
FRA+
FRA–
FRB+
FRB–
H8 H7 J10
J9
DCOA
+
DCOA
–
DCOB
+
DCOB
–
DCOA
+
DCOA
–
DCOB
+
DCOB
–
G7 G8 F9 F10
+1.8
VO+1
.8VO
+1.8
VO
G9 G10
+1.8
V+1
.8V
+1.8
V+1
.8V
+1.8
V+1
.8V
+1.8
V+1
.8V
+1.8
V
D3 D4 E3 E4 K3 K4 L3 L4
C7 4.7p
F C5 4.7p
F
R23
5.1Ω
R37
100Ω
R17
5.1Ω
R22
49.9
Ω1% R2
149
.9Ω
1%
C90.
01µF
R27
(OPT
)
C6 0.01
µF(O
PT)
C3 0.01
µF
R26
(OPT
)
R16
(OPT
)R1
5(O
PT)
J2 J1
E4
T1M
ABA-
0071
59-0
0000
0
FB1
BLM
31PG
330S
N1L
FB2
BLM
31PG
330S
N1L
C40.
01µF
C80.
01µF
R19
100Ω
+1.8
V
+1.8
VO
LT30
80ED
D
C11
1µF
0603
1 2 3 9
OUT
OUT
OUT
OUT
C56
0.1µ
F
C14
0.1µ
F
C10
4.7µ
F6.
3V06
03
C12
1µF
0603
4SE
T6
NC
7 8 5
IN IN VCTR
LR2
918
0k1%
+
+1.8
V
+1.8
V
C18
(OPT
)
C23
(OPT
)
C15
(OPT
)
C19
(OPT
)C1
7(O
PT)
(SAM
E FO
R OT
HER
CHAN
NELS
)
R30
0Ω 0603
R36
0Ω 0603
R31
0Ω 0805
R37
0Ω 0805
R32
0Ω 0603
R38
0Ω 0603
IN+
IN–
R48
100Ω
![Page 38: LTM9011-14/LTM9010-14/LTM9009-14 (Rev D) · 2019-06-05 · LTM9011-14/ LTM9010-14/LTM9009-14 2 Rev D For more information ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) PIN CONFIGURATION ORDER](https://reader030.fdocuments.us/reader030/viewer/2022041012/5ec00636c7bd0c67d4621658/html5/thumbnails/38.jpg)
LTM9011-14/LTM9010-14/LTM9009-14
38Rev D
For more information www.analog.com
PACKAGE DESCRIPTION
NOTE
S:1.
DIM
ENSI
ONIN
G AN
D TO
LERA
NCIN
G PE
R AS
ME
Y14.
5M-1
994
2. A
LL D
IMEN
SION
S AR
E IN
MIL
LIM
ETER
S
BAL
L DE
SIGN
ATIO
N PE
R JE
SD M
S-02
8 AN
D JE
P95
43
DETA
ILS
OF P
IN #
1 ID
ENTI
FIER
ARE
OPT
IONA
L,BU
T M
UST
BE L
OCAT
ED W
ITHI
N TH
E ZO
NE IN
DICA
TED.
THE
PIN
#1 ID
ENTI
FIER
MAY
BE
EITH
ER A
MOL
D OR
M
ARKE
D FE
ATUR
E
PACK
AGE
TOP
VIEW
X
aaa
Z
3
SEE
NOTE
S
BGA
140
1116
REV
C
TRAY
PIN
1BE
VEL
PACK
AGE
IN T
RAY
LOAD
ING
ORIE
NTAT
ION
COM
PONE
NTPI
N “A
1”
Øb (1
40 P
LACE
S)
D
DETA
IL B
PACK
AGE
SIDE
VIE
W
MX
YZ
ddd
MZ
eee
0.4
Ø 14
0x
Y
aaa Z
E
e
A2
F
eG
LTM
XXXX
XXµM
odul
e
DETA
IL A
SUGG
ESTE
D PC
B LA
YOUT
TOP
VIEW
3.600
2.800
2.000
1.200
0.4000.000
0.400
1.200
2.000
2.800
3.600
5.20
0
4.40
0
4.40
0
5.20
0
3.60
0
2.80
0
2.00
0
1.20
0
0.40
00.
000
0.40
0
1.20
0
2.00
0
2.80
0
3.60
0
4
PIN
“A1”
CORN
ER
1
P
DETA
IL A
C D E F G H J K L M NA B
109
87
65
43
2
PIN
1
PACK
AGE
BOTT
OM V
IEW
b
b
AZ
BGA
Pack
age
140-
Lead
(11.
25m
m ×
9.0
0mm
× 2
.72m
m)
(Ref
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Please refer to http://www.linear.com/product/LTM9011-14#packaging for the most recent package drawings.
![Page 39: LTM9011-14/LTM9010-14/LTM9009-14 (Rev D) · 2019-06-05 · LTM9011-14/ LTM9010-14/LTM9009-14 2 Rev D For more information ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) PIN CONFIGURATION ORDER](https://reader030.fdocuments.us/reader030/viewer/2022041012/5ec00636c7bd0c67d4621658/html5/thumbnails/39.jpg)
39Rev D
LTM9011-14/LTM9010-14/LTM9009-14
For more information www.analog.com
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
REVISION HISTORYREV DATE DESCRIPTION PAGE NUMBER
A 9/11 Updated Functional Block Diagram. 21
B 3/15 Removed mention of OGND. 26
C 2/17 Fixed VCM channel pairs: VCM12 changed to VCM14, VCM34 changed to VCM23, VCM56 changed to VCM67, VCM78 changed to VCM58.Corrected pin names for ENC and OUTXX.
18, 20, 21, 32, 37, 40
20, 32, 37, 40
D 4/18 Corrected J3/N3 pin names. 20
![Page 40: LTM9011-14/LTM9010-14/LTM9009-14 (Rev D) · 2019-06-05 · LTM9011-14/ LTM9010-14/LTM9009-14 2 Rev D For more information ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) PIN CONFIGURATION ORDER](https://reader030.fdocuments.us/reader030/viewer/2022041012/5ec00636c7bd0c67d4621658/html5/thumbnails/40.jpg)
LTM9011-14/LTM9010-14/LTM9009-14
40Rev D
For more information www.analog.com ANALOG DEVICES, INC. 2011-2018
D16880-0-5/18(D)www.analog.com
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LTM9010-14
F3
F1
F2
C1
C2
B3
B1
B2
VCM14
AIN2+
AIN2–
AIN3+
AIN3–
VCM23
AIN4+
AIN4–
AIN8+
AIN8–
AIN1+
AIN1–
OUT1A+
OUT1A–
DCO+
DCO–
FR+
FR–
G2
G1
N1
N2
H7
H8
G8
G7
E7
E8
ENC+
ENC–
P5 P6
B6C5
1.8V1.8V
SENS
E
V DD
V REF
OVDD
33pF 100pF
150pF
180nH180nH
3.3V
180nH180nH
150pF
150Ω 474Ω37.4Ω
37.4Ω
OUT–
OUT+
VOCM
IN+V+
IN–
474Ω
75Ω
75Ω66.9Ω
66.9Ω
0.1µF
0.8pF
0.8pF
68pF
68pF0.1µF
9009101114 TA03
• • •
–
+
150Ω SHDN
GND
49.9Ω
50Ω
• • •
LTC6409