LSI/CSI LS7366R
17
(800) 882-6414 | [email protected] www.geminelec.com REQUEST QUOTE PAGE 1 OF 17 PAGES --- CLICK HERE ---- ELECTRONIC COMPONENTS 32-BIT QUADRATURE COUNTER WITH SERIAL INTERFACE GENERAL FEATURES: Operating voltage: 3V to 5.5V (VDD - VSS) 5V count frequency: 40MHz 3V count frequency: 20MHz 32-bit counter (CNTR). 32-bit data register (DTR) and comparator. 32-bit output register (OTR). Two 8-bit mode registers (MDR0, MDR1) for programmable functional modes. 8-bit instruction register (IR). 8-bit status register (STR). Latched Interrupt output on Carry or Borrow or Compare or Index. Index driven counter load, output register load or counter reset. Internal quadrature clock decoder and filter. x1, x2 or x4 mode of quadrature counting. Non-quadrature up/down counting. Modulo-N, Non-recycle, Range-limit or Free-running modes of counting 8-bit, 16-bit, 24-bit and 32-bit programmable configuration synchronous (SPI) serial interface LS7366R (DIP), LS7366R-S (SOIC), LS7366R-TS (TSSOP) - See Figure 1 - SPI/MICROWIRE (Serial Peripheral Interface): Standard 4-wire connection: MOSI, MISO, SS/ and SCK. Slave mode only. GENERAL DESCRIPTION: LS7366R is a 32-bit CMOS counter, with direct interface for quadra- ture clocks from incremental encoders. It also interfaces with the index signals from incremental encoders to perform variety of marker functions. For communications with microprocessors or microcontrollers, it provides a 4-wire SPI/MICROWIRE bus.The four standard bus I/Os are SS/, SCK, MISO and MOSI. The data transfer between a micro- controller and a slave LS7366R is synchronous. The synchroniza- tion is done by the SCK clocks supplied by the microcontroller. Each transmission is organized in blocks of 1 to 5 bytes of data. A trans- mission cycle is intitiated by a high to low transition of the SS/ input. The first byte received in a transmission cycle is always an instruc- tion byte, whereas the second through the fifth bytes are always interpreted as data bytes. A transmission cycle is terminated with the low to high transition of the SS/ input. Received bytes are shifted in at the MOSI input, MSB first, with the leading edges (high transi- tion) of the SCK clocks. Output data are shifted out on the MISO output, MSB first, with the trailing edges (low transition) of the SCK clocks. 7366R-081711-1 August 2011 PIN ASSIGNMENT TOP VIEW 14 13 12 11 10 9 8 1 2 3 4 5 6 7 V DD CNT_EN A B INDEX/ DFLAG/ LFLAG/ f CKO f CKi V SS SS/ SCK MISO MOSI FIGURE 1 Read and write commands cannot be combined. For example, when the device is shifting out read data on MISO output, it ignores the MOSI input, even though the SS/ input is active. SS/ must be terminated and reasserted before the device will accept a new command. The counter can be configured to operate as 1, 2, 3 or 4-byte counter. When configured as an n-byte counter, the CNTR, DTR and OTR are all config- ured as n-byte registers, where n = 1, 2, 3 or 4. The content of the instruction/data identity is automatically adjusted to match the n-byte configu- ration. For example, if the counter is configured as a 2-byte counter, the instruction e to expects 2 data bytes following the instruction byte. If the counter is configured as a 3-byte counter, the same instruction will expect 3 bytes of data follow- ing the instruction byte. Following the transfer of the appropriate number of bytes any further attempt of data transfer is ignored until a new instruction cycle is started by switching the SS/ input to high and then low. The counter can be programmed to operate in a number of different modes, with the operating characteristics being written into the two mode registers MDR0 and MDR1. Hardware I/Os are provided for event driven operations, such as processor interrupt and index related functions.
Transcript of LSI/CSI LS7366R
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ELECTRONIC COMPONENTSLSI/CSIUL®
LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747 (631) 271-0400 FAX (631) 271-0405A3800
32-BIT QUADRATURE COUNTER WITH SERIAL INTERFACEGENERAL FEATURES: Operating voltage: 3V to 5.5V (VDD - VSS)5V count frequency: 40MHz3V count frequency: 20MHz32-bit counter (CNTR).32-bit data register (DTR) and comparator.32-bit output register (OTR).Two 8-bit mode registers (MDR0, MDR1)for programmable functional modes.8-bit instruction register (IR).8-bit status register (STR).Latched Interrupt output on Carry or Borrow or Compare or Index.Index driven counter load, output register load or counter reset.Internal quadrature clock decoder and filter.x1, x2 or x4 mode of quadrature counting.Non-quadrature up/down counting.Modulo-N, Non-recycle, Range-limit orFree-running modes of counting8-bit, 16-bit, 24-bit and 32-bit programmable configurationsynchronous (SPI) serial interfaceLS7366R (DIP), LS7366R-S (SOIC), LS7366R-TS (TSSOP)
- See Figure 1 -
SPI/MICROWIRE (Serial Peripheral Interface):Standard 4-wire connection: MOSI, MISO, SS/ and SCK.Slave mode only.
GENERAL DESCRIPTION:LS7366R is a 32-bit CMOS counter, with direct interface for quadra-ture clocks from incremental encoders. It also interfaces with theindex signals from incremental encoders to perform variety ofmarker functions.
For communications with microprocessors or microcontrollers, itprovides a 4-wire SPI/MICROWIRE bus.The four standard bus I/Osare SS/, SCK, MISO and MOSI. The data transfer between a micro-controller and a slave LS7366R is synchronous. The synchroniza-tion is done by the SCK clocks supplied by the microcontroller. Eachtransmission is organized in blocks of 1 to 5 bytes of data. A trans-mission cycle is intitiated by a high to low transition of the SS/ input.The first byte received in a transmission cycle is always an instruc-tion byte, whereas the second through the fifth bytes are alwaysinterpreted as data bytes. A transmission cycle is terminated withthe low to high transition of the SS/ input. Received bytes are shiftedin at the MOSI input, MSB first, with the leading edges (high transi-tion) of the SCK clocks. Output data are shifted out on the MISOoutput, MSB first, with the trailing edges (low transition) of the SCKclocks.
7366R-081711-1
August 2011
PIN ASSIGNMENTTOP VIEW
LS7366R
14
13
12
11
10
9
8
1
2
3
4
5
6
7
V DD
CNT_EN
A
B
INDEX/
DFLAG/
LFLAG/
fCKO
fCKi
V SS
SS/
SCK
MISO
MOSI
FIGURE 1
Read and write commands cannot be combined.For example, when the device is shifting out readdata on MISO output, it ignores the MOSI input,even though the SS/ input is active. SS/ must beterminated and reasserted before the device willaccept a new command.
The counter can be configured to operate as 1, 2, 3or 4-byte counter. When configured as an n-bytecounter, the CNTR, DTR and OTR are all config-ured as n-byte registers, where n = 1, 2, 3 or 4.The content of the instruction/data identity isautomatically adjusted to match the n-byte configu-ration. For example, if the counter is configured as a2-byte counter, the instruction e toexpects 2 data bytes following the instruction byte.If the counter is configured as a 3-byte counter, thesame instruction will expect 3 bytes of data follow-ing the instruction byte.
Following the transfer of the appropriate number ofbytes any further attempt of data transfer is ignoreduntil a new instruction cycle is started by switchingthe SS/ input to high and then low.
The counter can be programmed to operate in anumber of different modes, with the operatingcharacteristics being written into the two moderegisters MDR0 and MDR1. Hardware I/Os areprovided for event driven operations, such asprocessor interrupt and index related functions.
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ÜÝ Û´»½¬®·½¿´ ݸ¿®¿½¬»®·¬·½ò øÌß ã óîë%Ý ¬± õèë�Ý÷ п®¿³»¬»® ͧ³¾±´ Ó·²ò ÌÇÐ Ó¿¨ò ˲·¬ λ³¿®µÍ«°°´§ ʱ´¬¿¹» ÊÜÜ íòð ó ëòë Ê óÍ«°°´§ Ý«®®»²¬ ×ÜÜ íðð ìðð ìëð kß ÊÜÜ ã íòðÊ
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п®¿³»¬»® ͧ³¾±´ Ó·²ò Ê¿´«» Ó¿¨òÊ¿´«» ˲·¬ λ³¿®µøÍ»» Ú·¹ò î÷ ÍÝÕ Ø·¹¸ Ы´» É·¼¬¸ ¬ÝØ ïîð ó ² óÍÝÕ Ô±© Ы´» É·¼¬¸ ¬ÝÔ ïîð ó ² óÍÍñ Í»¬ Ë° Ì·³» ¬ÝÍÔ ïîð ó ² óÍÍñ ر´¼ Ì·³» ¬ÝÍØ ïîð ó ² óײ¬»® ݱ³³¿²¼ ÍÍñ ¸·¹¸ ¬ÝÍ× ïîð ó ² ó
Ï«¿¼®¿¬«®» Ó±¼»øÍ»» Ú·¹ò ëô é ú è÷ºÝÕ× Ø·¹¸ Ы´» É·¼¬¸ ¬ï îì ó ² óºÝÕ× Ð«´» É·¼¬¸ ¬î îì ó ² óºÝÕ× Ú®»¯«»²½§ ºÚÝÕ ó îð Óئ óÛºº»½¬·ª» Ú·´¬»® Ý´±½µ ºÚ л®·±¼ ¬í ëð ó ² ¬í ã ¬ïõ¬îô ÓÜÎð äéâ ã ð
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MOSI
MISO
SCK
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LS7366R LS7366R LS7366R LS7366R
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Fig 15. Multiple devices sharing common SPI bus.
7366R-080211-14
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//LS7366R to 90s8515 and ATmega32 SPI interface example /********Add appropriate header les here**********/ /***MDR0 con gura on data - the con gura on byte is formed with*** ***single segments taken from each group and ORing all together.***/ //Count modes #de ne NQUAD 0x00 //non-quadrature mode #de ne QUADRX1 0x01 //X1 quadrature mode #de ne QUADRX2 0x02 //X2 quadrature mode #de ne QUADRX4 0x03 //X4 quadrature mode //Running modes #de ne FREE_RUN 0x00 #de ne SINGE_CYCLE 0x04 #de ne RANGE_LIMIT 0x08 #de ne MODULO_N 0x0C //Index modes #de ne DISABLE_INDX 0x00 //index_disabled #de ne INDX_LOADC 0x10 //index_load_CNTR #de ne INDX_RESETC 0x20 //index_rest_CNTR #de ne INDX_LOADO 0x30 //index_load_OL #de ne ASYNCH_INDX 0x00 //asynchronous index #de ne SYNCH_INDX 0x80 //synchronous index //Clock lter modes #de ne FILTER_1 0x00 // lter clock frequncy division factor 1 #de ne FILTER_2 0x80 // lter clock frequncy division factor 2 /* **MDR1 con gura on data; any of these*** ***data segments can be ORed together***/ //Flag modes #de ne NO_FLAGS 0x00 //all ags disabled #de ne IDX_FLAG 0x10; //IDX ag #de ne CMP_FLAG 0x20; //CMP ag #de ne BW_FLAG 0x40; //BW ag #de ne CY_FLAG 0x80; //CY ag //1 to 4 bytes data-width #de ne BYTE_4 0x00; //four byte mode #de ne BYTE_3 0x01; //three byte mode #de ne BYTE_2 0x02; //two byte mode #de ne BYTE_1 0x03; //one byte mode //Enable/disable counter #de ne EN_CNTR 0x00; //coun ng enabled #de ne DIS_CNTR 0x04; //coun ng disabled /* LS7366R op-code list */ #de ne CLR_MDR0 0x08 #de ne CLR_MDR1 0x10 #de ne CLR_CNTR 0x20 #de ne CLR_STR 0x30 #de ne READ_MDR0 0x48 #de ne READ_MDR1 0x50 7366R-080511-15
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ELECTRONIC COMPONENTS
#de ne READ_CNTR 0x60 #de ne READ_OTR 0x68 #de ne READ_STR 0x70 #de ne WRITE_MDR1 0x90 #de ne WRITE_MDR0 0x88 #de ne WRITE_DTR 0x98 #de ne LOAD_CNTR 0xE0 #de ne LOAD_OTR 0xE4 #de ne Slave_Select_Low PORTB &= ~(1 << PB4) #de ne Slave_Select_High PORTB |= (1 << PB4) /*Con gure and ini alize the SPI on PortB of uC*/ void init_spi_master(void) { SPCR = (0<<SPE); // Disable SPI un l PortB con gura on /* Port B (DDRB) PB7/SCK, PB5/MOSI, PB4/!SS outputs */ DDRB = (1<<DDB7)|(1<<DDB5)|(1<<DDB4); // De ne Outputs Slave_Select_High; // Disable Slave Select /*** SPCR con gura on*** *** CPOL = 0, CPHA = 0, Mode0*** *** DORD = 0, MSB rst*** *** MSTR = 1, Master*** ***SPE = 1, SPI enabled*** ***SCK frequency = fosc/4***/ SPCR = (1<<SPE)|(1<<MSTR); } void load_rst_reg(unsigned char op_code) //dataless write command { unsigned char spi_data; Slave_Select_High; // Keep SS/ High for LS7366 deselect Slave_Select_Low; // Switch SS/ low for new command SPDR = op_code; // Send command to LS7366 while (!(SPSR & (1<<SPIF))) // Wait for end of the transmission { }; spi_data = SPDR; // Reset SPIF Slave_Select_High; // Switch SS/ high for end of command } void singleByteWrite(unsigned char op_code, unsigned char data) //single byte write command { unsigned char spi_data; Slave_Select_High; // Keep SS/ High for LS7366 deselect Slave_Select_Low; // Switch SS/ low for new command SPDR = op_code; // Send command to LS7366 while (!(SPSR & (1<<SPIF))) // Wait for end of the transmission { }; spi_data = SPDR; // Reset SPIF SPDR = data; // Send data to be wri en to LS7366 register while (!(SPSR & (1<<SPIF))) // Wait for end of the transmission 7366R-080511-16
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ELECTRONIC COMPONENTS
{ }; spi_data = SPDR; // Reset SPIF /*addi onal bytes can be sent here for mul byte write, e.g., write_DTR*/ Slave_Select_High; // Switch SS/ high for end of command } void singleByteRead(unsigned char op_code) //single byte read command { unsigned char spi_data; Slave_Select_High; // deselect the the LS7366 Slave_Select_Low; // Switch SS/ low for new command SPDR = op_code; // send op_code for read to LS7366 while (!(SPSR & (1<<SPIF))) // Wait for end of transmission { }; spi_data = SPDR; // Reset SPIF SPDR = 0xFF; // Start dummy transmission to read data from LS7366 while (!(SPSR & (1<<SPIF))) // Wait for end of the transmission { }; spi_data = SPDR; // Reset SPIF /*addi onal bytes can be received here for mul byte read, e.g., read_OTR*/ Slave_Select_High; // Switch SS/ high for end of command return spi_data; } //following example instan ates all macros de ned above int main(void) { init_spi_master; load_rst_reg(CLR_CNTR); singleByteWrite(WRITE_MDR0, QUADRX4|FREE_RUN|INDX_LOADC|SYNCH_INDX|FILTER_2); singleByteWrite(WRITE_MDR1, IDX_FLAG|CMP_FLAG|BYTE_2|EN_CNTR); singleByteRead(READ_MDR0); singleByteRead(READ_MDR1); return 0; } 7366R-080511-17
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